Integrated circuit and electronic device comprising a plurality of integrated circuits electrically coupled by a synchronous signal routed through the integrated circuit

Abstract

An integrated circuit comprising: a semiconductor substrate; an electronic component integrated in the semiconductor substrate; an electrical connection structure overlying the semiconductor substrate; and an electrically conductive region having an elongated shape, the electrically conductive region having a first end and a second end. The electrically conductive region is formed in the electrical connection structure, extends over the entire length of the substrate, and is not directly electrically connected to the electronic component. A first and a second synchronous connection element are electrically coupled to the first and second end of the electrically conductive region, respectively, and each have a respective synchronous connection portion facing a coupling face.

Description

Technical Field

[0001] This disclosure relates to an integrated circuit and an electronic device, the electronic device comprising a plurality of integrated circuits electrically coupled by a synchronization signal. Background Technology

[0002] This disclosure relates to an integrated circuit and an electronic device, the electronic device comprising a plurality of integrated circuits electrically coupled by a synchronization signal.

[0003] In particular, this type of electronic equipment is used in radio frequency applications (e.g., in radar for motor vehicles (typically in the frequency range of 76 GHz to 81 GHz, where there are many transmit and / or receive channels), and / or in imaging applications such as medical applications.

[0004] In these types of multichannel applications, MMICs (monolithic microwave integrated circuits) are increasingly used due to their uniform electrical characteristics (typically, they are impedance matched to 50Ω), which makes them easy to use and allows them to be easily cascaded without any external impedance matching network.

[0005] In this manner, a device can be manufactured consisting of multiple cascaded MMICs, each configured to manage a small number of transmit / receive channels. For example, the MMICs can be connected together so that a first MMIC (referred to as the "master") generates a synchronization signal and provides these signals to all other MMICs (referred to as "slaves"). Specifically, the master generates the synchronization signal LO at a higher or lower frequency depending on the application (e.g., at 20 GHz, 40 GHz, or 80 GHz). Using this arrangement, all MMICs receive the synchronization signal LO from the master and are able to transmit and receive radio frequency signals synchronously using transmit and receive antenna connections.

[0006] For example, in this manner, high-end radar equipment can use three MMICs (one master and two slaves) to manage 12 receive channels (hereinafter referred to as "RX channels") and 9 transmit channels (hereinafter referred to as "TX channels"), with each MMIC capable of managing four RX channels and three TX channels. More generally, this type of radar equipment can use M MMICs to manage X RX channels and Y TX channels, with each MMIC capable of managing X / M RX channels and Y / M TX channels.

[0007] Furthermore, generally, MMIC-based devices for transmitting / receiving radio frequency signals include a printed circuit board (PCB) carrying the MMIC and antenna, and may have... Figure 1The layout shown in the diagram and described below.

[0008] For example, Figure 1 Device 1 is shown, which includes printed circuit boards (PCBs 2) carrying a main MMIC 3 and three subsidiary MMICs 4-6 (however, the number of MMICs can be larger or smaller). Figure 1 In the top view, MMICs 3-6 are arranged side by side on the receiving antenna structure. Figure 1 The upper RX antenna 10) and the transmitting antenna structure ( Figure 1 Between the lower TX antenna 11).

[0009] The high-frequency MMICs 3-6 are typically mounted to PCB 2 and electrically connected together via solder balls, as described in more detail below. PCB 2 has: surface electrical connections 13, which are typically formed as conductive tracks on the surface of PCB 2, for electrically connecting the MMICs 3-6 to the RX antenna 10 and the TX antenna 11; buried electrical connections 14, which are formed by conductive tracks typically extending in the inner layers of PCB 2; and connection vias for connecting different layers and surfaces of PCB 2 for exchanging signals and electrical quantities between the MMICs 3-6 in a known manner and... Figure 1 It is only shown schematically.

[0010] In radio frequency applications, due to the high operating frequency (typically above 40 GHz), solder ball connections are currently achieved through FC-BGA (Flip Chip-Ball Grid Array) technology or eWLB (embedded Wafer-Level BGA) technology.

[0011] As is well known, both technologies use a ball grid array 15 fixed to one side (e.g., the back side) of each MMIC 3-6 to be coupled to PCB 2, such as Figure 2 As shown in the example, the solder ball is specified by 15, and the general MMIC is specified by 16.

[0012] In the case of FC-BGA technology (see...) Figure 3A solder ball 15 is attached to one side of a connection substrate 7 (which is a cross-section through a typical MMIC 16), the connection substrate 7 being formed of two plates 8 containing a dielectric material 9. The dielectric material 9 is embedded with metal interconnects 18 that electrically connect the solder ball 15 to a bump 17, which is attached to the connection substrate 7 on the side opposite to the solder ball 15. Furthermore, the bump 17 is attached to a die 21 containing electronic components (generally designated by 22), and allows signals and possibly other electrical quantities (e.g., power supplies, hereinafter included in the term "signal") to pass between the electronic components 22 of each MMIC 3-6 and the connection substrate 7. A dielectric fill and matching layer (so-called underfill layer 19) extends between the die 21 and the connection substrate 7 and covers the bump 17. A cover 12 is bonded to the connection substrate 7 by an adhesive layer 23 and surrounds the die 21, the bump 17, and the underfill layer 19 to form an encapsulation with the connection substrate 7.

[0013] In the case of eWLB technology (see...) Figure 4 (This shows a cross-section through a portion of a typical MMIC 16), each solder ball 15 is typically attached to a corresponding conductive region 25. The conductive regions 25 within the dielectric layer 26 (only one shown) are typically made of copper and form one or more redistribution layers (in...) Figure 4 In the diagram, a single redistribution layer RDL 24 is shown. A dielectric layer 26 extends over a passivation layer 27, which covers the die 28 except for openings at contact pads 30 formed on the surface of the die 28 and electrically connected to electronic components integrated into the die 28 (generally designated by 31). Here, the die 28 is surrounded by a peripheral region 29. The peripheral region 29 is typically manufactured by compression molding and widens the area of ​​the die 28 so that the dielectric layer 26 (also extending over the peripheral region 29) can have a larger area than the die 28, allowing solder balls 15 to be arranged, for example, at a spacing of 500 μm over a wider area than the die 28.

[0014] eWLB technology allows for minimal interconnect lengths and excellent electrical performance up to high frequencies (with wavelengths in the millimeter domain), without requiring underfill material, enabling a large number of input / output connections at low cost.

[0015] Among the signals exchanged between MMICs 3-6, the synchronization signal LO is particularly important because it can maintain the phase coherence and amplification balance between MMICs 3-6.

[0016] Currently, using an internal additional layer of PCB 2, the synchronization signal LO (with two different inputs to enable symmetrical wiring in PCB 2) is routed through buried connection 14 because these synchronization connections cannot be formed on the top layer of PCB 2, so as not to allow surface electrical connections 13 to interact with the RX antenna 10 and TX antenna 11. Figure 1 )cross.

[0017] However, this leads to increased complexity in burying the connection 14 and higher costs in forming the internal additional layers of PCB 2. Furthermore, the increased transitions between layers result in an undesirable decrease in signal amplitude. Summary of the Invention

[0018] This disclosure provides an integrated circuit and an electronic device that overcomes the shortcomings of the prior art by using existing interconnection technologies, such as solder ball-based technologies.

[0019] According to this disclosure, an integrated circuit and an electronic device are provided.

[0020] In at least one embodiment, an integrated circuit with a coupling surface is provided. The integrated circuit includes: a semiconductor substrate; an electronic component integrated in the semiconductor substrate; an electrical connection structure covering the semiconductor substrate; and a conductive region having an elongated shape. The conductive region has a first end and a second end, and the conductive region is formed in the electrical connection structure and extends over the entire length of the substrate. The conductive region is not directly electrically connected to the electronic component. The electrical connection structure includes a plurality of connection elements, each having a corresponding connection portion facing the coupling surface, and the plurality of connection elements includes a first synchronous connection element and a second synchronous connection element. The first synchronous connection element and the second synchronous connection element are respectively electrically coupled to the first end and the second end of the conductive region, and each has a corresponding synchronous connection portion facing the coupling surface.

[0021] In at least one embodiment, an electronic device is provided, comprising: a support having a support surface; and a plurality of integrated circuits, each integrated circuit having a coupling surface coupled to the support surface. Each integrated circuit includes: a semiconductor substrate in which electronic components are integrated; an electrical connection structure covering the semiconductor substrate; and a conductive region having an elongated shape formed within the electrical connection structure. The conductive region has a first end and a second end, extends over the entire length of the substrate, and is not directly electrically connected to the electronic components. A first integrated circuit of the plurality of integrated circuits is configured to generate a synchronization signal. Each electrical connection structure includes a plurality of connection elements. The plurality of connection elements includes signal connection elements that electrically couple electronic components to a corresponding signal connection portion facing a corresponding coupling surface. The electrical connection structure of at least the first integrated circuit further includes a first synchronization connection element and a second synchronization connection element adjacent to the signal connection element, the first synchronization connection element and the second synchronization connection element being electrically coupled to the first end and the second end of the corresponding conductive region, having a corresponding synchronization connection portion facing the coupling surface, and configured to route the synchronization signal. Electronic components are bonded to the support surface, and electrical connection tracks extend on the support surface and electrically couple electronic components to the signal connection portions of the signal connection elements of each integrated circuit. The synchronous conductive track segment extends on the support surface and electrically couples at least the synchronous connection portion of the first integrated circuit to the selective signal connection portion of the integrated circuit.

[0022] In at least one embodiment, an apparatus is provided comprising a printed circuit board (PCB) having a surface, and a semiconductor device package physically coupled to the surface of the PCB. The semiconductor device package includes: a semiconductor substrate; electronic components integrated in the semiconductor substrate; an electrical connection structure covering the semiconductor substrate; and a conductive region having an elongated shape, the conductive region having a first end and a second end, the conductive region being formed in the electrical connection structure extending over the entire length of the substrate and not directly electrically connected to the electronic components. The electrical connection structure includes a plurality of connection elements, the plurality of connection elements having corresponding connection portions facing a coupling surface. The plurality of connection elements includes a first synchronous connection element and a second synchronous connection element, and the first synchronous connection element and the second synchronous connection element are respectively electrically coupled to the first end and the second end of the conductive region, and each has a corresponding synchronous connection portion facing the coupling surface. A receiving antenna is physically coupled to the surface of the PCB and electrically coupled to the semiconductor device package, and a transmitting antenna is physically coupled to the surface of the PCB and electrically coupled to the semiconductor device package. Attached Figure Description

[0023] To better understand this disclosure, some embodiments of the disclosure will now be described by way of non-limiting example, with reference to the accompanying drawings, in which:

[0024] Figure 1The layout of an electronic device with multiple integrated circuits for known types of radio frequency applications is shown;

[0025] Figure 2 This is a bottom perspective view of an integrated circuit configured to be bonded using ball grid array technology;

[0026] Figure 3 It is configured to use FC-BGA technology for bonding. Figure 2 A cross-section of a portion of an integrated circuit;

[0027] Figure 4 It is configured to use eWLB technology for bonding. Figure 2 A cross-section of a portion of an integrated circuit;

[0028] Figure 5 The layout of an electronic device having multiple integrated circuits according to one embodiment is shown;

[0029] Figure 6 yes Figure 5 A bottom view of an integrated circuit;

[0030] Figure 6A It shows Figure 6 Magnified details of the integrated circuit;

[0031] Figure 7 yes Figure 5 A cross-section of a portion of an integrated circuit;

[0032] Figure 8 A layout of an electronic device having multiple integrated circuits according to another embodiment is shown;

[0033] Figure 9 It is intercepted along the bisector IX-IX. Figure 8 A cross-section of a portion of an integrated circuit in an electronic device;

[0034] Figure 10 Is along with Figure 9 The same line intercepts Figure 9 Different embodiments of integrated circuits;

[0035] Figure 11 The layout of an electronic device having multiple integrated circuits according to different embodiments is shown;

[0036] Figure 12 It is intercepted along the transect XII-XII. Figure 11 A cross-section of a portion of an integrated circuit in an electronic device; and

[0037] Figure 13 Is along with Figure 12 The same line intercepts Figure 12Cross-sections of different embodiments of the integrated circuit. Detailed Implementation

[0038] Figure 5 An electronic device 50 is shown, which includes a printed circuit board 52 that carries four microcontrollers (MMICs), for example, one master MMIC 53 and three slave MMICs 54-56 (but the number of slave MMICs can vary). Figure 5 In the top-down plan view, MMIC 53-56 are arranged side by side on the receiving antenna structure ( Figure 5 The upper RX antenna 60) and the transmitting antenna structure ( Figure 5 Between the lower TX antenna 61).

[0039] refer to Figure 7 MMICs 53-56 include a semiconductor device package 57 (which may be referred to as a die 57 in some embodiments) housing electronic components (schematically represented and specified by 58 in general). A connection region 59 extends over the die 57. In the case of eWLB bonding technology, this connection region is formed by a dielectric layer housing metal interconnects, as referenced above. Figure 4 As described. In the case of FC-BGA bonding technology, the connection region 59 is composed of a structure similar to... Figure 3 The bonding support 7 is formed. In the case of eWLB bonding technology, the possible passivation layer is... Figure 7 The possible peripheral area surrounding chip 57 is not visible in the middle. Figure 7 It is also not visible in the middle, or in the case of FC-BGA bonding technology, the bottom filler layer and bumps are in Figure 7 They are invisible, but they can exist, such as in... Figure 4 and Figure 3 As shown in the image.

[0040] Refer again Figure 5 MMICs 53-56 are connected to the RX antenna 60 and TX antenna 61 via surface electrical connections 63, which are formed as conductive tracks on the surface of the PCB 52 carrying the MMICs 53-56 in a known manner. Additionally, the MMICs 53-56 are interconnected via buried connections formed in the PCB 52 (described below) and also via a synchronization line 64 (described in detail below), which routes the synchronization signal LO generated by the main MMIC 53 through the electronic component 74. The synchronization signal LO is provided from the MMICs 54-56 in a manner known per se for their synchronization and amplitude balancing.

[0041] In the following text, for better understanding, MMICs 54-56 are also referred to as the first, second, and third MMICs 54, 55, and 56. In the illustrated embodiments (specifically, see...), Figure 5 The master MMIC 53 is positioned between the first slave MMIC 54 (located on the left) and the second slave MMIC 55 (located on the right). Therefore, the synchronization signal LO crosses the master MMIC 53 and the second slave MMIC 55.

[0042] MMIC 53-56 (see also MMIC 53-56) Figure 6 and 7 The solder balls 65 are used to secure and electrically connect to PCB 52. This can be achieved using the techniques described above and... Figure 3 and Figure 4 The FC-BGA or eWLB technology shown is used to bond solder balls 65. It should be noted that the term "ball" will be used below; however, after bonding, they are typically deformed and have a shape different from that of a sphere.

[0043] As in Figure 6 It can be noted that the solder balls are arranged in rows and columns of 65. Figure 6 The rows are identified by the letters AY, and the columns are identified by the numbers 1-18, but there is no solder ball 65 in row J.

[0044] In this way, line J defines a blank or missing line, that is, it is placed in an adjacent line ( Figure 6 The solder balls 65 on rows K and H are arranged at a distance greater than the distance between other adjacent rows. Specifically, refer to... Figure 6A The magnified details, if p The distance between adjacent rows in the array (i.e., the distance between the center points of solder balls 65 belonging to adjacent rows) is then the distance in an empty row. d It is the spacing p twice ( d =2 p ).

[0045] like Figure 6 The dashed line in the diagram indicates that synchronization line 64 is in a blank line (on PCB 52) at a distance of... d The two rows of solder balls extend between each other at 65.

[0046] refer to Figure 7PCB 52 includes a dielectric material body 67 in a known manner. Body 67 has a first side 67A and a second side 67B, and embedded conductive regions 68. The conductive regions 68 are connected together and connected to the first side 67A via metal vias 69 for electrical connection between MMICs 53-56. Possible vias (not shown) may also connect the conductive regions 68 to the second side 67B of PCB 52. Furthermore, the first side 67A of PCB 52 carries surface electrical connections 63 (not visible here) and synchronization lines 64.

[0047] In particular (see also) Figure 5 Synchronization line 64 is formed here by synchronization track 66, which includes a straight portion 66A and a branch portion 66B. The branch portion 66B extends from the straight portion 66A to a corresponding solder ball 65 disposed at a terminal of MMIC 53-56. The corresponding solder ball 65 is designed to receive / transmit synchronization signal LO (in Figure 5 In this context, the synchronization signal LO is represented by LOin for the input terminal and LOout for the output terminal. For example, it is connected to solder ball 65A (which is coupled to...). Figure 5 The branch section 66B of the main MMIC 53 (input terminal LOin and output terminal LOout) is located in... Figure 6 The middle part is represented by a dashed line.

[0048] In fact, Figure 5 In the illustrated embodiment, even though all MMICs 53-56 have empty lines, and branch portion 66B is connected to two solder balls 65 for the main MMIC 53 ( Figure 6 The solder balls 65A and 65B in the MMIC 54-56 and the single solder ball 65 for the MMIC 54-56, but the straight portion 66A of the sync line 64 also extends only below the main MMIC 53 and the second from the MMIC 55.

[0049] However, the straight section 66A is not necessarily formed by a single segment that crosses the main MMIC 53 and the second secondary MMIC 55, but can be formed by an interrupted line, only the portion that crosses the single MMIC 53 and 55 is preferably linear.

[0050] Synchronization track 66 can be formed in the same manner as surface electrical connections 63 formed on the first side 67A of PCB 52, for example, formed as a copper track, and typically has a much smaller thickness than solder balls 65, even when these solder balls are slightly deformed after soldering, such as Figure 7 It is visible in the text.

[0051] Figures 8-10Electronic device 70 is shown, illustrating different solutions for routing the synchronization signal LO. Here, the MMIC comprises a microstrip (with a ground region disposed below) or a coplanar waveguide (with a ground region in the same plane as the waveguide). The microstrip or coplanar waveguide is formed above the die and extends virtually through the width of each MMIC to connect opposite sides of each MMIC. Connections to terminals LOin and LOout are obtained by conductive tracks formed on the PCB and connected to the microstrip or coplanar waveguide via solder balls. Figure 8 and Figure 9 The solution shown for bonding MMICs using eWLB technology can also be used when bonding MMICs using FC-BGA technology, as described below.

[0052] exist Figure 8 and Figure 9 In this context, the MMIC (as specified here by 83-86) has a coupling surface 81, such as... Figure 4 As shown, each MMIC includes a die 73 that integrates electronic components (generally designated by 74), a peripheral region 76, and a dielectric layer 72. (Refer to the above...) Figure 4 The schematically illustrated metal interconnect 75 extends within the dielectric layer 72 and connects to solder balls 95. Furthermore, for clarity, MMICs 84-86 are also referred to herein as the first, second, and third MMICs. It should be noted that, here, although not shown, but in a manner known per se, each die 73 is obtained from dicing a processed semiconductor wafer and includes a semiconductor substrate (not shown) covered by one or more insulating layers (not shown) that house the metal interconnects (also not shown).

[0053] In addition, with Figure 5 Just like in the middle, in Figure 8 In the middle, MMICs 83-86 are arranged side by side between the receiving antenna structure RX antenna 90 and the transmitting antenna structure TX antenna 91, and are coupled to the RX antenna 90 and TX antenna 91 by surface electrical connections 93 formed on the PCB (specified by 92). The PCB includes a dielectric material body 97 in a known manner, the body 97 being embedded in conductive regions 98, the conductive regions 98 being connected together and connected to the first surface 97A through metal vias 99.

[0054] Specifically, regarding Figure 8 and Figure 9 In one embodiment, each MMIC 83-86 has a dielectric layer 72 formed in the main MMIC 83 and a conductive strip 71 in the dielectric layer 72 of the MMIC 84-86.

[0055] Here, a redistribution layer RDL is used to form a conductive strip 71.

[0056] Figure 10 It shows Figure 9 A variant in which MMIC 83-86 uses FC-BGA technology for bonding.

[0057] Here, the electronic device specified by 70' is similar to Figure 3 The connecting substrate 89 of the connecting substrate 7 has a conductive strip 71' formed in a metal layer, which is connected to the metal connecting line 88 (which is similar to...). Figure 3 The metal layer of the metal connecting wire 18) is similar. Figure 10 In the diagram, plate 8 is not shown, and the bottom fill layer, bumps, and cover are specified by 77, 79, and 80, respectively.

[0058] exist Figure 9 and Figure 10 In both cases, the conductive strips 71 and 71' extend approximately the width of the MMIC 83-86 (and therefore the width of the dielectric layer 72 or the width of the connecting substrate 89), terminating only at a short distance from the edge of the MMIC 83-86.

[0059] It should be noted that, in this context, the width of the term MMIC 53-56 indicates the size of MMIC 53-56 in the adjacent direction.

[0060] like Figure 8 As shown, electronic devices 70, 70' have a synchronization line 96, which is formed by conductive strips 71, 71' of some of the MMICs 83-86 (those MMICs crossed by the synchronization line 96) and track portions 94 formed on PCB 92. The conductive strips 71, 71' and track portions 94 forming the synchronization line 96 are connected together by solder balls 95.

[0061] In detail, synchronization line 96 here consists of the main MMIC 83 and the second slave MMIC 85 (in Figure 9 and Figure 10 Conductive strips 71 and 71' are formed in the middle (arranged on the right side of the main MMIC 83). Conductive strips 71 and 71' are not electrically coupled to any component in the assembly 74, and are only connected to the corresponding solder balls 95 of the main MMIC 83 and the second slave MMIC 85. Therefore, the first slave MMIC 84 (in Figure 8 The middle is located on the far left, and in Figure 9 and Figure 10 (Partially visible) and the third from MMIC 86 (in Figure 8 The middle is located on the far right, and in Figure 9 and Figure 10 The conductive bands 71 ​​and 71' (not visible in the middle) float (or are connected to an appropriate fixed potential, such as ground).

[0062] As an alternative to the above, the conductive strips 71, 71' of the first MMIC 84 and the third MMIC 86 can be connected to the corresponding solder balls 95, but these conductive strips 71, 71' are not connected to any metal wire, or may be connected only to the common ground wire if necessary.

[0063] The track portion 94 formed on PCB 92 allows the synchronization line 96 to be connected to the input terminal LOin of MMIC 83-86 and the output terminal LOout of the main MMIC 83. For details, refer to... Figure 9 and Figure 10 By utilizing the 95A designation, the solder ball is coupled to the first input terminal LOin of the MMIC 84 in a manner not shown. Figure 9 and Figure 10 (Indicated by dashed lines because it is not traversed by the cross-sectional plane); the first ends of the conductive strips 71, 71', which are coupled to the main MMIC 83 via the 95B identifier (in) Figure 9 and Figure 10 The solder ball on the left side; the second end of the conductive strip 71, 71' of the main MMIC 83 is coupled to the conductive strip 71, 71' of the main MMIC 83 via the 95C marking (in Figure 9 and 10 The solder ball on the right side; and coupled to the first end of the second conductive strip 71, 71' from the MMIC 85 via the 95D marking (in the right side); Figure 9 and Figure 10 The solder balls on the left side of the MMIC 84 are connected to the solder balls 95A of the main MMIC 83 via the first track portion 94A, and then to the solder balls 95B of the main MMIC 83 via the second track portion 94A, which are coupled to the input terminal LOin of the main MMIC 83 in a manner not shown (not visible); the solder balls 95C of the main MMIC 83 are connected to the solder balls 95D of the second slave MMIC 85, and then to the solder balls 95D of the output terminal LOout of the main MMIC 83 via the third track portion 94C (only on the left side of the MMIC 84). Figure 8 (As shown in the diagram) The second end of the conductive strip 71 of the second MMIC 85 is connected to a solder ball (not visible) that is coupled to the input terminal LOin of the second MMIC 85 and the input terminal LOin of the third MMIC 86.

[0064] It should be noted that, as will be apparent to those skilled in the art, this solution can also be applied in the case of wire bonding / solder ball hybrid technology.

[0065] Figures 11-13An electronic device 100 is shown that implements different solutions for routing synchronization signals LO. Here, the MMIC has a microstrip or coplanar waveguide integrated within the die, and the microstrip or coplanar waveguide extends across the width of each chip to connect opposite sides of each chip. Connections to terminals LOin and LOout are made via metal interconnects, wires within the MMIC, and conductive tracks formed on the PCB. Figure 11 and Figure 12 The solution shown for bonding MMIC 83-86 using eWLB technology can also be used when coupling MMIC 83-86 using FC-BGA technology or wire bonding technology, as referenced below. Figure 13 The subject of discussion.

[0066] In detail, such as Figure 11 and Figure 12 As shown, where Figure 8 and Figure 9 The same parts of the electronic device 70 are designated by the same reference numerals and will not be described further. The die 73 is shown as being formed from a semiconductor substrate 104 covered by an insulating layer 105. Each MMIC 83-86 has a metallic conductive strip 101, which is formed here by a metallization layer extending within the insulating layer 105 of each die 73. Here, each conductive strip 101 is formed directly below the surface 73A of the corresponding die 73. In the case of the main MMIC 83 and the second slave MMIC 85, each conductive strip 101, at its own end, is connected to a corresponding solder ball 95 arranged on the edge of each MMIC 83, 85 via vias formed in the insulating layer 105 and connecting pads 103, as well as a corresponding metallic interconnect 102 (formed in the dielectric layer 72 and similar to a metallic interconnect). In the first and third cases from MMIC 84, 86, conductive strip 101 is not electrically connected to electronic component 74 of electronic device 100, as discussed above for conductive strips 71, 71'.

[0067] In fact, in this case, the conductive strip 101, which is manufactured together with component 74 at the wafer level to form a microstrip or coplanar waveguide, is already present when the wafer is cut into individual dies 73.

[0068] Furthermore, this solution can also be applied to bonding using FC-BGA bonding technology (in which case the conductive strip 101 is electrically coupled to the solder ball 95 via bumps and bonding supports, as shown in the image). Figure 10 As shown in the figure, it can also be applied to electronic devices that are configured to operate at low frequencies and have a package (wire bonded package) that is coupled to the PCB via wire bonding.

[0069] For example, Figure 13It shows having Figure 11 The electronic device 110 uses a connection scheme, but the MMIC is connected via wire bonding. Therefore, with Figure 11 and Figure 12 The same parts of the electronic device 100 are designated by the same reference numerals and will not be described further.

[0070] In particular, Figure 13 In the example shown, each MMIC 83-86 includes a bonding wire 115 connecting a corresponding contact pad 103 to a pin 116. Similarly, here, the contact pads 103 are arranged at opposite ends of conductive strips 101; each conductive strip 101 is formed within the insulating layer 105 of each die 73 and extends substantially throughout the width of each die 73. Figure 13 For simplicity, the insulating layer 105 is shown as a single layer that covers the semiconductor substrate 104 of each die 72 and is exposed only at the contact pads 103. However, the insulating layer 105 can be formed in a known manner by different layers disposed on top of each other.

[0071] The die 73 and bonding wire 115 are covered by an encapsulation layer 117 or a layer containing a dielectric material (e.g., molding resin) (however, the encapsulation layer can be formed according to any known encapsulation technique, as will be apparent to those skilled in the art). The encapsulation layer 117 also has pins 116 embedded on all sides except the back side, on which the pins 116 are in direct electrical contact with the track portion 94 of the synchronization line 96.

[0072] and Figure 12 Just like in the middle, in Figure 13 In this configuration, only the conductive strip 101 of the main MMIC 83 and the conductive strip 101 of the second slave MMIC 85 are connected by bonding wire 115. Therefore, the conductive strips 101 of the first and third MMICs 84 and 86 are floating (or connected to a suitable fixed potential, such as ground). Figure 13 The bond wire 115 is shown in dashed lines (because it is arranged in a plane parallel to the cross-sectional plane). The bond wire 115 connects the first input terminal LOin of the MMIC 84 to the first track portion 94A, which is electrically connected to one end of the conductive strip 101 of the main MMIC 83, as shown in the reference above. Figure 11 As described.

[0073] The MMICs and electronic devices described in this article have many advantages.

[0074] In particular, the described solution allows the synchronization signal generated by the master MMIC to be carried to the slave MMIC without requiring additional connection layers in the PCB design, thus reducing costs.

[0075] The described packaging structure allows the use (at least partially) of the same conductive layer as the radio frequency signals exchanged with antenna structures 60, 61, 90, 91 to carry the synchronization signal LO.

[0076] The path of the synchronization signal LO is simplified and can be minimized, thereby reducing loss phenomena or layout complexity.

[0077] Finally, it is clear that modifications and variations can be made to the integrated circuits and electronic devices described and illustrated herein without departing from the scope of this disclosure. For example, the different embodiments described can be combined to provide alternative solutions.

[0078] For example, MMICs can also be arranged without being aligned with each other, but simply placed side by side between the RX and TX antenna structures. In this case, the synchronization track may include a broken line.

[0079] Electronic devices can include different types of integrated circuits, which can even operate at frequencies different from radio frequencies.

[0080] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments based on the detailed description above. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents to these claims. Therefore, the claims are not limited by the disclosure.

Claims

1. An electronic device, comprising: Support component, having a support surface, A master integrated circuit, a first slave integrated circuit, a second slave integrated circuit, and a third slave integrated circuit are arranged in a line, each integrated circuit having a coupling surface coupled to the support surface and including: Semiconductor substrate; Electronic components are integrated into the semiconductor substrate; Connecting substrate, covering the semiconductor substrate; Multiple conductive strips, having an elongated shape and having a first end and a second end, are formed in the connection substrate and are not directly electrically connected to the electronic component; Multiple solder balls are coupled to the support surface and the integrated circuit; and Multiple track sections are respectively coupled to the multiple solder balls. The connecting substrate includes multiple connecting lines, and The main integrated circuit among the plurality of said integrated circuits is configured to generate a synchronization signal, and Each integrated circuit includes an input terminal electrically coupled to one of the plurality of track portions, and The main integrated circuit among the plurality of integrated circuits includes an output terminal electrically coupled to one of the plurality of track portions, and The synchronization line, comprising the plurality of conductive strips, is electrically coupled to the track section, and The solder balls coupled to the master integrated circuit and the second slave integrated circuit are coupled to the synchronization line, while the solder balls coupled to the first slave integrated circuit and the third slave integrated circuit are not coupled to the synchronization line.

2. The electronic device according to claim 1, wherein, Each integrated circuit includes a die having an insulating layer extending over the semiconductor substrate. The connecting substrate includes a dielectric region of a certain length, and the plurality of conductive strips extend through the dielectric region along the length.

3. The electronic device according to claim 2, wherein the plurality of solder balls are a ball grid array bonding structure.

4. The electronic device of claim 3, wherein the dielectric region accommodates at least one redistribution layer coupled to an embedded wafer-level BGA.

5. The electronic device according to claim 4, wherein the solder balls belong to a ball grid array connection structure, and the ball grid array connection structure forms a flip chip-ball grid array coupling or an embedded wafer-level BGA coupling.

6. The electronic device of claim 4, wherein the dielectric region includes an encapsulation layer.

7. The electronic device of claim 1, wherein the plurality of conductive strips are coupled to at least one integrated circuit.

8. The electronic device according to claim 1, wherein the integrated circuit is a monolithic microwave integrated circuit.

9. The electronic device of claim 1, wherein the plurality of conductive strips are formed in a metal layer.

10. An electronic device, comprising: Support component, having a supporting surface; Multiple integrated circuits, each having a coupling surface coupled to the support surface, and each integrated circuit comprising: Semiconductor substrate, with integrated electronic components; A dielectric layer coupled to the semiconductor substrate; Multiple solder balls are coupled between the support surface and the coupling surface; Multiple track sections are coupled to the support surface and the multiple solder balls; A conductive strip, having an elongated shape, is located in the dielectric layer. The conductive strip has a first end and a second end, wherein a plurality of solder balls are coupled to the support surface and the integrated circuit; and the plurality of track portions are respectively coupled to the plurality of solder balls; and A synchronization line includes a conductive strip of each integrated circuit, wherein the synchronization line of the conductive strip is electrically coupled to the track portion, and solder balls coupled to the third and second integrated circuits are coupled to the synchronization line, while solder balls coupled to the first integrated circuit are not coupled to the synchronization line.

11. The electronic device of claim 10, wherein the support has a first side and a second side opposite to the first side.

12. The electronic device according to claim 11, wherein the solder balls belong to a ball grid array connection structure.

13. The electronic device of claim 10, wherein the plurality of solder balls extend in the dielectric layer.

14. The electronic device of claim 13, wherein the plurality of solder balls belong to a ball grid array connection structure, and the ball grid array connection structure forms a flip chip-ball grid array coupling or an embedded wafer-level BGA coupling.

15. The electronic device of claim 13, wherein the electronic device includes a dielectric region coupled to the die and the dielectric layer.

16. The electronic device according to claim 10, wherein: The third integrated circuit forms the main integrated circuit. The first integrated circuit and the second integrated circuit include a first slave circuit and a second slave circuit arranged on opposite sides of the main integrated circuit.

17. An apparatus comprising: Printed circuit boards have a surface; A first semiconductor device package and a second semiconductor device package are coupled together by a line, wherein the first semiconductor device package and the second semiconductor device package include: Semiconductor substrate; Electronic components are integrated into the semiconductor substrate; An insulating layer extends over the semiconductor substrate and together forms a bare die. Slender conductive strips are located within the insulating layer, each conductive strip having a first end and a second end. Multiple solder balls are coupled to the surface of the printed circuit board and the first semiconductor device package and the second semiconductor device package, and A metal connecting wire is coupled from the conductive strip to the solder ball; The first semiconductor device package is configured to generate a synchronization signal, the solder balls coupled to the first semiconductor device package are coupled to the conductive strip, and the solder balls coupled to the second semiconductor device package are not coupled to the conductive strip; A receiving antenna is coupled to the printed circuit board and the first semiconductor device package and the second semiconductor device package; and A transmitting antenna is coupled to the printed circuit board and the first semiconductor device package and the second semiconductor device package.

18. The device of claim 17, wherein the first semiconductor device package and the second semiconductor device package are disposed between the receiving antenna and the transmitting antenna.

19. The device of claim 17, wherein the first semiconductor device package and the second semiconductor device package are monolithic microwave integrated circuit packages.

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