A doped-free semiconductor device for an SoC and a manufacturing method thereof

Abstract

The present invention discloses a doped semiconductor device for a system-on-chip (SoC) and a manufacturing method thereof, which integrates single or multiple planar field effect transistors (FETs) or their arrays and single or multiple planar storage devices or their arrays, wherein the planar field effect transistors and the planar storage devices are single or multiple field effect transistor units and single or multiple storage units having a doped semiconductor channel material layer. By utilizing the characteristics that the doped semiconductor channel material layer does not need to undergo high-temperature annealing and high-temperature ion implantation, the present invention can realize the integration of field effect transistor devices and storage devices on the same chip simultaneously, including two-dimensional integration or three-dimensional integration structures, thereby forming an integrated circuit composed of two-dimensional field effect transistors integrated with an embedded memory SoC, or an integration of any combination of two-dimensional or three-dimensional SoC and two-dimensional or three-dimensional storage.

Description

Technical Field

[0001] The present invention relates to a carbon nanotube CMOS integrated circuit process, and particularly to a doping-free semiconductor device for an SoC and a manufacturing method thereof. Background Art

[0002] When the integrated circuit technology node reaches 16 nm after two generations downward, it will reach the limit of silicon materials and physical quantum mechanics. For the continuous development of electronics, it is urgent to find new advantageous materials to replace silicon materials and break through the limit of Moore's Law. Carbon nanotubes (CNTs) have ultra-high carrier mobility and mean free path, and a nanoscale tube diameter, and can be used to construct nanoscale field effect transistors with faster speed, lower power consumption, and smaller size. Therefore, carbon nanotube (CNTs) electronics is considered to be one of the future information technologies most likely to replace silicon-based CMOS devices and continue Moore's Law. According to relevant research, although the performance of carbon nanotube hole devices is far superior to that of silicon-based devices of the corresponding scale, the performance of electron devices prepared by chemical doping methods is far inferior to that of silicon-based devices, and the mainstream semiconductor CMOS technology cannot be realized through carbon nanotube materials.

[0003] By controlling the source-drain contact metal materials scandium (Sc) or palladium (Pd), electrons or holes can be selectively injected into the carbon nanotubes, and high-performance n-type and p-type carbon nanotube field effect transistors can be effectively regulated and fabricated. Specifically, using Pd as the source-drain contact can form a high-performance P-type carbon nanotube FET, and using Sc or Y as the source-drain contact can form a high-performance N-type carbon nanotube FET, thereby realizing the control of the transistor polarity. The entire manufacturing process does not require any doping. Therefore, it is called the "doping-free" carbon nanotube CMOS process. This manufacturing method of the "doping-free" carbon nanotube CMOS device is different from the current mainstream silicon-based integrated circuits. The ion implantation process is not introduced. When Pd electrodes and Sc electrodes are sputtered on the same carbon nanotube respectively, the device between two Pd electrodes is P-type, and the device between two Sc electrodes is N-type. This method can directly realize the regulation of the transistor device type, greatly saving the process steps and reducing the production cost.

[0004] Currently, it is already possible to fabricate CNTFETs with good performance and low power consumption in the laboratory. A self-aligned gate structure nanoscale field-effect transistor and its fabrication method are disclosed in Chinese Patent ZL200810223905.X, which uses one-dimensional semiconductor nanomaterials as the conductive channel, with source and drain electrodes at both ends. The gate dielectric layer is grown by atomic layer deposition, covering between the source and drain electrodes, as well as the sidewalls of the opposite faces of the source and drain electrodes and part of the source and drain electrodes, and a self-aligned process is implemented to fabricate CNTFETs and can fabricate CNTFETs through a self-aligned approach. However, the current self-aligned process still has some deficiencies. A sufficiently large distance and spacing are required to fabricate S / D contacts, and larger device sizes result in a larger gate coverage area and a larger coverage capacitance, affecting the AC performance of the device. Therefore, there is a need for a device with a smaller device area and a smaller coverage capacitance. In traditional CMOS processes, high-temperature doping and annealing processes are usually required. When performing three-dimensional device integration, the upper high-temperature process will damage the completed lower-layer devices, resulting in the inability to continuously perform three-dimensional integration.

[0005] Based on this, the present invention proposes a planar memory device that can two-dimensionally integrate one or more memory device units with a non-doped semiconductor channel material layer, and a semiconductor device structure that further three-dimensionally integrates the above planar memory device with a planar field-effect transistor. Utilizing the excellent device performance of carbon nanotube devices and the advantage that non-doped semiconductor devices do not require high-temperature doping and annealing processes, it is possible to provide a larger storage capacity and a higher integration density. Summary of the Invention

[0006] The object of the present invention is to improve the SoC integration density. The present invention proposes a field-effect transistor device with a smaller device area and a smaller coverage capacitance. At the same time, it proposes a planar memory device and a fabrication method for two-dimensionally integrating one or more memory device units with a non-doped semiconductor channel material layer, as well as a method for integrating a planar or three-dimensional high-density SoC integrated circuit with a planar or three-dimensional NAND or NOR memory array. The specific content is as follows.

[0007] On the one hand, the present invention provides a non-doped semiconductor device for an SoC, which includes a planar memory device that two-dimensionally integrates one or more memory device units with a non-doped semiconductor channel material layer, where the planar memory device is all of the above memory device units or includes some of the above memory device units.

[0008] Preferably, the SoC further includes non-memory units, and the non-memory units include digital, logic, analog, mixed-signal, or radio frequency devices.

[0009] Preferably, the above memory device units are NAND or NOR memory units.

[0010] Preferably, the undoped semiconductor channel material layer is selected from carbon nanotubes or two-dimensional materials, where the two-dimensional materials are selected from MoS2, MoSe2, BN, WSe2, graphene, or black phosphorus.

[0011] Preferably, the above planar memory device has a substrate containing a buffer layer or a transition layer, an undoped semiconductor channel material layer, a gate insulating layer, and a patterned source-drain contact metal layer located in the gate insulating layer. One or more planar memory devices or arrays composed of memory device units are provided in the above patterned source-drain contact metal layer.

[0012] Preferably, the above memory device unit includes a gate structure located on the above gate insulating layer. The gate structure is composed of a sidewall and a stack of a charge storage layer, an insulating layer, a gate metal, and a gate capping layer between the sidewalls.

[0013] On the other hand, the present invention provides a method for an undoped semiconductor device for an SoC, and the specific steps are as follows:

[0014] Provide a semiconductor substrate containing a buffer layer or a transition layer. Form an undoped semiconductor channel material layer, a gate insulating layer, and an insulating layer on the semiconductor substrate. Pattern the above gate insulating layer and insulating layer to form source-drain vias. Deposit source-drain contact metal in the above source-drain vias and cover the insulating layer. Chemically mechanically polish the deposited source-drain contact metal layer using the insulating layer as a stop layer, and then remove the insulating layer to form a source-drain contact metal pattern; form a conformal insulating layer on the above source-drain contact metal pattern, and anisotropically etch the conformal silicon dioxide layer covering the top insulating layer of the source-drain contact metal and the bottom gate insulating layer to form sidewalls on the sides of the above patterned source-drain contact metal layer;

[0015] Deposit a charge storage layer, an insulating layer, a gate metal, and a gate capping layer between the above sidewalls to form a single memory device unit, and then further form memory device units in other areas to form a planar memory device.

[0016] Preferably, the above memory device is fabricated using a dummy gate process, and the specific steps are as follows:

[0017] Form an undoped semiconductor channel material layer and a gate insulating layer on the semiconductor substrate, and form sidewalls and a dummy gate structure thereon. The above sidewalls are gate sidewalls formed by ALD. Remove the gate insulating layer between the sidewalls, and deposit source-drain electrodes.

[0018] Preferably, a interlayer dielectric layer is covered on the above planar memory device and patterned, and then a metal interconnect layer is formed thereon.

[0019] On the other hand, the present invention provides a doped-free semiconductor device for an SoC, which integrates one or more planar field effect transistors and one or more planar memory devices to form a three-dimensional device, and the above-mentioned planar memory device has a doped-free semiconductor channel material layer.

[0020] Preferably, all of the above-mentioned planar memory devices are memory device units, or include partial memory device units.

[0021] Preferably, the above-mentioned memory device unit is a memory cell of NAND or NOR.

[0022] Preferably, the lowermost layer of the above-mentioned three-dimensional device is a silicon-based planar field effect transistor, a planar field effect transistor with a doped-free semiconductor channel material layer, or the above-mentioned planar memory device with a doped-free semiconductor channel material layer.

[0023] Preferably, one or more of the above-mentioned planar field effect transistors, one or more of the above-mentioned planar memory devices, and a hybrid integration of one or more of the above-mentioned planar field effect transistors and the above-mentioned planar memory devices are integrated on the above-mentioned lowermost layer of the three-dimensional device.

[0024] Preferably, all of the above-mentioned planar field effect transistors are field effect transistor units, or include partial field effect transistor units, and the above-mentioned field effect transistor unit is preferably a digital, logic, analog, digital-analog hybrid, or radio frequency device.

[0025] Preferably, the above-mentioned doped-free semiconductor channel material layer is selected from carbon nanotubes or two-dimensional materials, and the two-dimensional materials are selected from MoS2, MoSe2, BN, WSe2, graphene, or black phosphorus.

[0026] Preferably, the above-mentioned planar field effect transistor has a substrate containing a buffer layer or other transition layer, a doped-free semiconductor channel material layer located on the above-mentioned substrate, a gate insulating layer, and a patterned source-drain contact metal layer located in the gate insulating layer, and the above-mentioned patterned source-drain contact metal layer has the above-mentioned planar single field effect transistor or its array composed of field effect transistor units.

[0027] Preferably, the above-mentioned field effect transistor unit includes a gate structure located on the above-mentioned gate insulating layer, and the gate structure is composed of a sidewall and a stack of a gate metal layer and a gate capping layer between the sidewalls.

[0028] Preferably, an interlayer dielectric layer and a metal interconnection layer connected to the source and drain electrodes of the above-mentioned planar field effect transistor are provided on the above-mentioned planar field effect transistor.

[0029] Preferably, the above-mentioned planar storage device has a substrate containing a buffer layer or a transition layer, an undoped semiconductor channel material layer, a gate insulating layer, and a patterned source-drain contact metal layer located in the gate insulating layer. One or more planar storage devices or arrays composed of storage device units are provided in the above-mentioned patterned source-drain contact metal layer.

[0030] Preferably, the above-mentioned storage device unit includes a gate structure located on the above-mentioned gate insulating layer. The gate structure is composed of a sidewall and a stack of a charge storage layer, an insulating layer, a gate metal, and a gate capping layer between the sidewalls.

[0031] Preferably, an interlayer dielectric layer and a metal interconnect layer connected to the source and drain electrodes of the above-mentioned planar storage device are covered on the above-mentioned planar storage device.

[0032] Preferably, the above-mentioned gate insulating layer material is selected from Y2O3, Hf2O3, Al2O3, or ZrO2.

[0033] Preferably, the above-mentioned source-drain contact metal layer is selected from TiN, TaN, Co, Mo, W, Pd, Pt, Sc, Y, Er, or a laminated combination of different types of the above-mentioned metals.

[0034] Another aspect of the present invention proposes a method for manufacturing the above-mentioned undoped semiconductor device for SoC. The specific steps are as follows: providing a semiconductor substrate or a silicon-based planar field-effect transistor, forming a planar storage device or a planar field-effect transistor with an undoped semiconductor channel material layer on it, forming an interlayer dielectric layer on it, and then forming another planar field-effect transistor or planar storage device with an undoped semiconductor channel material layer on the above-mentioned interlayer dielectric layer. A three-dimensional chip with periodic integration or hybrid integration of multiple planar storage devices and planar field-effect transistors is formed according to the above steps.

[0035] Preferably, the manufacturing steps of the above-mentioned planar field-effect transistor include:

[0036] Providing a semiconductor substrate, the semiconductor substrate includes single-crystalline silicon covered with silicon oxide including a flat surface or a recessed surface formed by etching; sequentially forming an undoped semiconductor channel material layer, a gate insulating layer, and an insulating layer on the semiconductor substrate, patterning the above-mentioned gate insulating layer and insulating layer to form source-drain vias, depositing source-drain contact metal in the above-mentioned source-drain vias and covering a certain height on the above-mentioned insulating layer, performing chemical mechanical polishing (CMP) on the above-mentioned source-drain contact metal layer with the insulating layer as a stop layer, then removing the above-mentioned insulating layer to form a source-drain contact metal pattern, forming a conformal insulating layer on the above-mentioned source-drain contact metal pattern, and removing the conformal insulating layer covering the top insulating layer of the source-drain contact metal and the bottom gate insulating layer by an anisotropic etching method to form sidewalls on the sides of the above-mentioned patterned source-drain contact metal layer.

[0037] A gate metal layer and a gate capping layer are deposited between the above sidewalls to form a field effect transistor unit. If there is no insulating isolation between the in-plane field effect transistor units, a planar field effect transistor is formed.

[0038] Preferably, a dummy gate process can also be used to fabricate the above-mentioned field effect transistor device. The specific steps are as follows:

[0039] An undoped semiconductor channel material layer and a gate insulating layer are formed on a semiconductor substrate, and sidewalls and a dummy gate structure are formed thereon. The above sidewalls are gate sidewalls formed by ALD. The gate insulating layer between the sidewalls is removed, and source and drain electrodes are deposited.

[0040] Preferably, an interlayer dielectric layer is covered on the above planar field effect transistor and patterned, and then a metal interconnect layer is formed thereon.

[0041] Preferably, the manufacturing steps of the above planar memory device are as follows:

[0042] A semiconductor substrate containing a buffer layer or a transition layer is provided. An undoped semiconductor channel material layer, a gate insulating layer, and an insulating layer are formed on the semiconductor substrate. The above gate insulating layer and insulating layer are patterned to form source and drain vias. Source and drain contact metals are deposited in the above source and drain vias and cover the insulating layer. Chemical mechanical polishing (CMP) is performed on the deposited source and drain contact metal layer using the insulating layer as a stop layer, and then the insulating layer is removed to form a source and drain contact metal pattern; A conformal insulating layer is formed on the above source and drain contact metal pattern, and the conformal silicon dioxide layer covering the top insulating layer of the source and drain contact metal and the bottom gate insulating layer is removed by an anisotropic etching method, and sidewalls are formed on the sides of the patterned source and drain contact metal layer;

[0043] A charge storage layer, an insulating layer, a gate metal, and a gate capping layer are deposited between the above sidewalls to form a single memory device unit, and then memory device units are further formed in other regions to form a planar memory device.

[0044] Preferably, a dummy gate process is used to fabricate the above memory device. The specific steps are as follows:

[0045] An undoped semiconductor channel material layer and a gate insulating layer (203’) are formed on a semiconductor substrate, and sidewalls and a dummy gate structure are formed thereon. The above sidewalls are gate sidewalls formed by ALD. The gate insulating layer between the sidewalls is removed, and source and drain electrodes are deposited.

[0046] Preferably, an interlayer dielectric layer is covered on the above planar memory device and patterned, and then a metal interconnect layer is formed thereon.

[0047] The present invention provides a field effect transistor with a smaller device area and smaller overlap capacitance and a self-aligned manufacturing method thereof, which can integrate the field effect transistor and the memory device on the same chip. Further, the Flash memory device and the field effect transistor (FET) can be integrated into a 3D NAND flash memory array for a larger volume. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The above and other objects, features and advantages of the present invention will become more apparent from the following description of the undoped semiconductor device structure and its manufacturing method for SoC with reference to the accompanying drawings, in which:

[0049] Figure 1 A channel layer and an insulating layer are formed on a substrate having a buffer layer.

[0050] Figure 2 Source-drain contact holes are formed.

[0051] Figure 3 Source-drain contact metal is deposited.

[0052] Figure 4 The source-drain contact metal is planarized.

[0053] Figure 5 A conformal insulating layer is formed.

[0054] Figure 6 The conformal insulating layer is anisotropically etched.

[0055] Figure 7 A gate metal layer is deposited.

[0056] Figure 8 A gate capping layer is formed.

[0057] Figure 9 A field effect transistor integrated device is formed.

[0058] Figure 10 An ILD is formed and planarized.

[0059] Figure 11 Through holes are formed on the source-drain electrodes.

[0060] Figure 12 A metal interconnect layer is formed.

[0061] Figure 13 A charge storage layer, a charge isolation insulating layer, and a gate metal layer are deposited.

[0062] Figure 14 A gate capping layer is formed.

[0063] Figure 15 A memory device integrated device is formed.

[0064] Figure 16 Form the ILD and planarize it.

[0065] Figure 17 Form vias on the source and drain electrodes.

[0066] Figure 18 Form the metal interconnect layer.

[0067] Figure 19 Form the 3D structure device.

[0068] Figure 20 Form the dummy gate structure.

[0069] Figure 21 Deposit to form the source and drain.

[0070] Figure 22 Remove the dummy gate.

[0071] Figure 23 Deposit the charge storage layer.

[0072] Figure 24 Deposit the charge isolation insulating layer.

[0073] Figure 25 Deposit the gate metal layer.

[0074] Figure 26 Deposit the gate capping layer. Detailed implementation manners

[0075] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In the drawings, the same elements are denoted by the same reference numerals, and the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, a semiconductor structure obtained after several steps may be described in one figure.

[0076] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "above" or "on top of" another layer or another region, it may mean directly above the other layer or another region, or there may be other layers or regions between it and the other layer or another region. And if the device is flipped, this layer or region will be "below" or "beneath" the other layer or another region.

[0077] If it is for describing the case of being directly above another layer or another region, the expression "A is directly on top of B" or "A is on top of B and adjacent thereto" will be used in this article. In this application, "A is directly located in B" means that A is located in B and A is directly adjacent to B, rather than A being located in a doped region formed in B.

[0078] The present invention proposes a non-doped semiconductor device for an SoC, such as Figure 20As shown, it includes a planar field-effect transistor and a planar memory device stacked structure separated by an interlayer dielectric layer. The above-mentioned planar field-effect transistor and planar memory device integrate one or more field-effect transistor or memory device units with an undoped semiconductor channel material layer. Preferably, the undoped semiconductor channel material layer is selected from carbon nanotubes or two-dimensional materials such as MoS2, MoSe2, BN, WSe2, graphene, black phosphorus, etc. The above-mentioned field-effect transistor unit is a digital, logic, analog, or radio frequency device, and the above-mentioned memory device unit is a NAND device or an embedded NOR device. In one embodiment, the above-mentioned stacked structure further has a plurality of planar field-effect transistors separated by an interlayer dielectric layer. In another embodiment, the above-mentioned stacked structure can also have a plurality of planar memory device stacks separated by an interlayer dielectric layer. In other embodiments, there can also be a stacked structure in which planar field-effect transistors and planar memory devices are periodically alternated and separated by an interlayer dielectric layer.

[0079] Among them, the planar field-effect transistor can not only be entirely composed of field-effect transistor units, but can also be an array including a single field-effect transistor unit or multiple field-effect transistors, or can also integrate some field-effect transistor units and some memory device units at the same time; similarly, the planar memory device can be entirely composed of memory device units, or can be an array including a single memory device or multiple memory devices, or can also integrate some memory device units and field-effect transistor units at the same time. In another embodiment, the above-mentioned planar field-effect transistor and planar memory device can be integrated on a traditional CMOS chip.

[0080] In one embodiment, the undoped semiconductor device for SoC can include a layer of planar memory device and one or more non-memory units. The planar memory device two-dimensionally integrates one or more memory device units with an undoped semiconductor channel material layer. The above-mentioned memory device unit can be a NAND device or an embedded NOR device, but is not limited thereto. The non-memory unit can be selected from digital, logic, analog, mixed-signal, or radio frequency devices. Similarly, the above-mentioned undoped semiconductor channel material layer is selected from carbon nanotubes or two-dimensional materials such as MoS2, MoSe2, BN, WSe2, graphene, black phosphorus, etc. The structure and manufacturing process of the above-mentioned memory device unit are the same as those of the memory device unit in the above-mentioned three-dimensional integrated device, and specific details can be seen in the subsequent description.

[0081] In summary, those skilled in the art can set the stacking order and quantity of the planar field-effect transistor and planar memory device as needed, so as to obtain a 3D device structure in which the planar field-effect transistor and planar memory device are formed on a single chip at the same time.

[0082] Furthermore, the planar field-effect transistor has a substrate 101, an undoped semiconductor channel material layer 102 located on the substrate 101, a gate insulating layer 103, and a patterned source-drain contact metal layer located in the gate insulating layer 103. The planar field-effect transistor composed of field-effect transistor cells is provided in the patterned source-drain contact metal layer. The field-effect transistor cell includes a gate structure located on the gate insulating layer 103. The gate structure has sidewalls, and a stack of a gate metal layer 107 and a gate capping layer 108 is provided between the sidewalls. An interlayer dielectric layer 109 and a metal interconnect layer connected to the source and drain electrodes of the planar field-effect transistor are further provided on the planar field-effect transistor.

[0083] Furthermore, the planar memory device has a substrate 201, an undoped semiconductor channel material layer 202, a gate insulating layer 203, and a patterned source-drain contact metal layer located in the gate insulating layer 203. Multiple planar memory devices composed of memory device cells are provided in the patterned source-drain contact metal layer. The memory device cell includes a gate structure located on the gate insulating layer 203. The gate structure has sidewalls, and a stack composed of a charge storage layer 207, a charge isolation insulating layer 208, a gate metal 209, and a gate capping layer 210 is provided between the sidewalls. Meanwhile, an interlayer dielectric layer (ILD) 211 and a metal interconnect layer connected to the source and drain electrodes of the planar memory device are further covered on the planar memory device.

[0084] The material of the above-mentioned gate insulating layer 103 or gate insulating layer 203 is selected from Y2O3, Hf2O3, Al2O3, or ZrO2. The source-drain contact metal layer can be selected from TiN, TaN, Co, Mo, W, Pd, Pt, Sc, Y, Er, or a laminated combination of different types of the above metals.

[0085] In addition, the present invention provides a method for manufacturing an undoped semiconductor device of the above-mentioned SoC. First, a semiconductor substrate is provided, and a planar memory device or a planar field-effect transistor having an undoped semiconductor channel material layer is formed thereon. An interlayer dielectric layer is formed thereon, and then another planar field-effect transistor or planar memory device having an undoped semiconductor channel material layer is formed on the above-mentioned interlayer dielectric layer. A three-dimensional device integrated with multiple planar memory devices and planar field-effect transistors is formed periodically according to the above steps. In one embodiment, a planar field-effect transistor is first formed on the semiconductor substrate, then an interlayer dielectric layer is formed thereon, and then a planar memory device is formed. Subsequently, a three-dimensional device structure is formed periodically. In another embodiment, a planar memory device is first formed on the semiconductor substrate, then an interlayer dielectric layer is formed, and then a planar field-effect transistor is formed. Subsequently, a three-dimensional device structure is formed periodically. When integrating multiple planar memory devices and planar field-effect transistors, the integration arrangement order is not limited, and those skilled in the art can combine them according to the needs of manufacturing the three-dimensional device.

[0086] The following will Figures 1 to 20 describe this manufacturing method in detail. As Figure 1 shown, a semiconductor substrate 101 is provided, and an undoped semiconductor channel material layer 102, a gate insulating layer 103, and an insulating layer 104 are respectively formed thereon. The gate insulating layer 103 is deposited by atomic layer deposition (ALD), and the insulating layer 104 can be formed by including physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or any combination thereof.

[0087] In this embodiment, the semiconductor substrate 101 is a planar Si with SiO2, the above-mentioned undoped semiconductor channel layer 102 uses carbon nanotubes (CNT), the gate insulating layer 103 uses Y2O3, and the insulating layer 104 is SiO2. In other embodiments, the substrate 101 can also be selected from Si with etching grooves. Those skilled in the art should be familiar that a buffer layer (not shown in the figure) is usually grown on the semiconductor substrate 101 to make the lattice matching between the grown undoped semiconductor channel material and the substrate. The undoped semiconductor channel material layer 102 can also be selected from carbon nanotubes or two-dimensional materials such as MoS2, MoSe2, BN, WSe2, graphene, black phosphorus, etc. The gate insulating layer 103 can be Hf2O3, Al2O3, or ZrO2. The insulating layer 104 can be selected from Si3N4 or Hf2O3. Those skilled in the art can combine the materials of each layer according to the art.

[0088] Furthermore, as Figure 2 shown, source / drain patterns are formed on the insulating layer 104 through a conventional lithography process, and the SiO2 substrate is etched using this as a mask to form source / drain through-holes. Then, the gate insulating layer 103 is etched using the SiO2 pattern as a mask.

[0089] Furthermore, as Figure 3 shown, a contact metal layer 105 is deposited in the through-holes formed in the above steps. The source / drain contact metal layer 105 can be selected from metals such as TiN, TaN, Co, Mo, W, Pd, Pt, Sc, Y, Er, or different types of laminated combinations of the above metals. The above source / drain contact metal is grown by magnetron sputtering or electron beam evaporation. The source / drain contact metal layer 105 contacts the undoped semiconductor channel material layer 102 and covers a certain thickness on the insulating layer 104, and then is planarized by chemical mechanical polishing (CMP) with the insulating layer 104 as the stop layer to form a structure as Figure 4 shown. After further removing the insulating layer 104, a conformal silicon dioxide insulating layer 106 is formed on the source / drain contact metal pattern, as Figure 5As shown. Then, anisotropic etching is performed on the insulating layer 106 by reactive ion etching (RIE) to remove the conformal silicon dioxide layer covering the source / drain contact metal top insulating layer and the bottom gate insulating layer 103, and sidewalls 106 are formed on the sides of the source / drain contact metal layer 105 by ALD or PE-ALD, as Figure 6 shown.

[0090] In one embodiment, as Figure 7 shown, first, a gate metal layer 107 is deposited between the sidewalls by ALD respectively, and the gate metal layer 107 can be selected from metals such as TiN, TaN, Co, Mo, W, Pd, Pt, Sc, Y, Er, or a laminated combination of different types of the above metals. Then, a gate capping layer 108 is deposited by PECVD, as Figure 8 shown, and the gate capping layer 108 can be selected from SiO2 or Si3N4. A planar field-effect transistor is formed by planarizing the gate capping layer with the source / drain contact metal layer as the stop layer, as Figure 9 shown. Then, an interlayer dielectric layer (ILD) 109 is continuously deposited on the field-effect transistor, and source / drain level metal contact hole patterns are formed thereon, and a metal interconnect layer 110 is deposited thereon to form a field-effect transistor, where each field-effect transistor unit can be connected in series or in parallel, as Figures 10 - 12 shown. The field-effect transistor units include NMOS units and PMOS units.

[0091] In this embodiment, on the planar field-effect transistor formed above, a semiconductor substrate 201, an undoped semiconductor channel material layer 202, a gate insulating layer 203, and a patterned source / drain contact metal layer located in the gate insulating layer are further deposited, and then a planar storage device is further integrated, as Figure 13 shown, a charge storage layer 207, an insulating layer 208, and a gate metal 209 are deposited between the sidewalls by atomic layer deposition (ALD) respectively, where the charge storage layer 207 is a nitride or polysilicon, the insulating layer 208 can be a high-k dielectric material or an oxide, and the gate metal 209 can be selected from TiN, TaN, Co, Mo, W, Pd, Pt, Sc, Y, Er, etc. Then, a gate capping layer 210 is deposited by PECVD, and the gate capping layer 210 is selected from SiO2 or Si3N4, as Figure 14 shown. A planar storage device unit is formed by planarizing the gate capping layer with the source / drain contact metal layer as the stop layer, as Figure 15 shown. Further, as Figure 16 and Figure 17 shown, an interlayer dielectric layer (ILD) 211 is continuously deposited on the planar storage device, and then source / drain level metal contact hole patterns are formed thereon, and then as Figure 18As shown, a metal interconnection layer 212 is deposited thereon to form a planar memory device, wherein each memory device unit can be connected in series or in parallel. Based on the structure formed by the above process, multiple planar memory device structures can be further integrated, such as Figure 19 shown.

[0092] The above field effect transistor device or memory device can also be manufactured by using a dummy gate process. In one embodiment, the memory device is manufactured by using a dummy gate process, specifically as follows Figures 20 - 26 First, an undoped semiconductor channel material layer 202' and a gate insulating layer 203' are formed on a semiconductor substrate 201', and a sidewall and a dummy gate structure are formed thereon. The sidewall is a gate sidewall formed by atomic layer deposition (ALD), preferably PE-ALD, as shown in FIG. Figure 20 Then the gate insulating layer between the sidewalls is removed, and the source and drain electrodes 205' are deposited, as shown in FIG. Figure 21 Then, the dummy gate between the sidewalls is removed to form a groove, and then the gate metal layer 207', the charge isolation insulating layer 208', the gate metal layer 209', and the gate cap layer 210' are deposited in the groove using conventional deposition processes in the art. Figure 10 and Figure 12 An intermediate insulating layer and a metal interconnect layer are formed to form a field effect transistor device.

[0093] In another embodiment, a field effect transistor device is formed by using a dummy gate process. Figures 20 - 22 The process is the same. After removing the dummy gate structure, the gate metal and the cap layer are deposited to form the gate structure, and then the intermediate dielectric layer and the metal interconnection layer are formed to form the memory device. The memory device finally formed has the same structure as that formed by the conventional process, such as Figure 15 shown.

[0094] In another embodiment, the above-mentioned planar field effect transistor and planar memory device can be integrated on a conventional CMOS chip. Since the conventional CMOS process will go through ion implantation and high temperature annealing process steps, the use of an undoped semiconductor channel layer does not require a high temperature ion implantation process, and the process temperature is generally low, below 600°C, so it will not damage the devices already formed in the underlying layer, thereby enabling the integration of 3D devices.

[0095] In another embodiment, one or more memory device units having an undoped semiconductor channel material layer are two-dimensionally integrated on a planar memory device, wherein the manufacturing process of the memory device unit is the same as the manufacturing process of the aforementioned memory device unit. Similarly, the aforementioned dummy gate process can also be used to manufacture the memory device unit, thereby forming a two-dimensional planar memory device.

[0096] Based on the above process, the present invention realizes a semiconductor device structure that can three-dimensionally integrate a field-effect transistor and a memory structure device by using an undoped semiconductor channel material layer. Since the undoped semiconductor device does not require a high-temperature doping annealing process, it can provide a larger storage capacity and a higher integration degree.

[0097] Although the present invention has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to it based on the present invention, which are obvious to those skilled in the art. Therefore, these modifications or improvements made without departing from the spirit of the present invention all fall within the scope of protection required by the present invention.

Claims

1. A method for fabricating a doped semiconductor device for an SoC, characterized in that: A silicon-based planar field-effect transistor is provided, on which a planar memory device with an undoped semiconductor channel material layer or a planar field-effect transistor with an undoped semiconductor channel material layer is formed at a temperature below 600 °C. An interlayer dielectric layer is formed thereon, and then another planar field-effect transistor or planar memory device with an undoped semiconductor channel material layer is formed on the interlayer dielectric layer. The undoped semiconductor channel material layer is selected from carbon nanotubes, MoS2, MoSe2, BN, WSe2, graphene, or black phosphorus; A three-dimensional chip with periodic integration or hybrid integration of multiple planar memory devices and planar field-effect transistors is formed according to the above steps; The manufacturing steps of the planar field-effect transistor with the undoped semiconductor channel material layer include: Providing a semiconductor substrate (101), the semiconductor substrate includes single-crystalline silicon covered with silicon oxide and includes a flat surface or a recessed surface formed by etching; An undoped semiconductor channel material layer (102), a gate insulating layer (103), and an insulating layer (104) are sequentially formed on the semiconductor substrate (101). The gate insulating layer (103) and the insulating layer (104) are patterned to form source-drain vias. Source-drain contact metal is deposited in the source-drain vias and covers a certain height on the insulating layer (104). The source-drain contact metal layer is chemically mechanically polished with the insulating layer (104) as the stop layer, and then the insulating layer (104) is removed to form a source-drain contact metal pattern. A conformal insulating layer (106) is formed on the source-drain contact metal pattern, and the conformal insulating layer covering the top insulating layer of the source-drain contact metal and the bottom gate insulating layer (103) is removed by an anisotropic etching method to form sidewalls on the sides of the patterned source-drain contact metal layer (105); A gate metal layer (107) and a gate capping layer (108) are deposited between the sidewalls to form a field-effect transistor unit. If there is no insulating isolation between the planar field-effect transistor units in the plane, a planar field-effect transistor is formed.

2. The manufacturing method of the undoped semiconductor device for SoC according to claim 1, characterized in that, The planar field-effect transistor is fabricated using a dummy gate process. The specific steps are as follows: An undoped semiconductor channel material layer and a gate insulating layer are formed on the semiconductor substrate, and sidewalls and a dummy gate structure are formed thereon. The sidewalls are gate sidewalls formed by ALD. The gate insulating layer between the sidewalls is removed, and source-drain electrodes are deposited.

3. The manufacturing method of the undoped semiconductor device for the SoC according to claim 1 or 2, characterized in that, An interlayer dielectric layer (109) is covered on the planar field-effect transistor and patterned, and then a metal interconnect layer (110) is formed thereon.

4. The manufacturing method of the undoped semiconductor device for SoC according to claim 1, characterized in that, The material of the gate insulating layer (103) is selected from Y2O3, Hf2O3, Al2O3, or ZrO2.

5. The manufacturing method of the undoped semiconductor device for the SoC according to claim 1, characterized in that, The insulating layer (104) is selected from Si3N4 or Hf2O3.

6. The manufacturing method of the undoped semiconductor device for SoC according to claim 1, characterized in that The patterned source-drain contact metal layer (105) is selected from TiN, TaN, Co, Mo, W, Pd, Pt, Sc, Y, Er, or a laminated combination of different types of the above metals.

7. The manufacturing method of the undoped semiconductor device for SoC according to claim 1, characterized in that, The gate metal layer (107) is selected from TiN, TaN, Co, Mo, W, Pd, Pt, Sc, Y, Er, or a laminated combination of different types of the above metals.

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