Semiconductor device and method of forming a semiconductor device

Abstract

Disclosed are methods for performing a pre-cleaning process to remove oxide from a semiconductor device and a semiconductor device formed by the same. In one embodiment, the method includes: forming a shallow trench isolation region above a semiconductor substrate; forming a gate stack above the shallow trench isolation region; etching the shallow trench isolation region adjacent to the gate stack using an anisotropic etching process; and after etching the shallow trench isolation region using the anisotropic etching process, etching the shallow trench isolation region using an isotropic etching process, wherein the process gas used for the isotropic etching process includes hydrogen fluoride (HF) and ammonia (NH3). Embodiments of the present application also relate to semiconductor devices and methods of forming semiconductor devices.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming semiconductor devices. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Typically, semiconductor devices are manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of individual electronic components (eg, transistors, diodes, resistors, capacitors, etc.) by continually reducing minimum feature size, which allows more components to be integrated into a given area. Summary of the Invention

[0004] Some embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a shallow trench isolation region above a semiconductor substrate; forming a gate stack above the shallow trench isolation region; etching the shallow trench isolation region adjacent to the gate stack using an anisotropic etching process; and after etching the shallow trench isolation region using the anisotropic etching process, etching the shallow trench isolation region using an isotropic etching process, wherein the process gas used for the isotropic etching process includes hydrogen fluoride (HF) and ammonia (NH3).

[0005] Other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a gate stack above a semiconductor fin, the semiconductor fin extending from a semiconductor substrate; anisotropically etching the semiconductor fin to form a first recess; and isotropically etching the semiconductor fin using a plasma-free dry etching process to remove oxide from the semiconductor fin.

[0006] Still other embodiments of the present application provide a semiconductor device comprising: a shallow trench isolation (STI) region located above a semiconductor substrate; a gate electrode located above the shallow trench isolation region; and a first dielectric located above the shallow trench isolation region and surrounding the gate electrode, the first dielectric having a first circular profile extending a first distance of 5nm to 25nm below a top surface of the shallow trench isolation region, the first dielectric having a second circular profile extending a second distance of 10nm to 30nm from the first circular profile below the top surface of the shallow trench isolation region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 An example of a semiconductor device including a fin field effect transistor (FinFET) in a three-dimensional view is shown in accordance with some embodiments.

[0009] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6A 、 Figure 6B 、 Figure 7A 、 Figure 7B 、 Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figure 9C 、 Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 11A 、 Figure 11B 、 Figure 11C 、 Figure 12A 、 Figure 12B 、 Figure 12C 、 Figure 12D 、 Figure 13A 、 Figure 13B 、 Figure 14A 、 Figure 14B 、 Figure 15A 、 Figure 15B 、 Figure 15C 、 Figure 16A 、 Figure 16B 、 Figure 17A 、 Figure 17B 、 Figure 17C and Figure 17D is a cross-sectional view of an intermediate stage in the fabrication of a semiconductor device according to some embodiments.

[0010] Figure 18A 、 Figure 18B 、 Figure 19A 、 Figure 19B 、 Figure 20A 、 Figure 20B 、 Figure 21A and Figure 21B are various 3D and cross-sectional views of intermediate stages in the fabrication of a fin including a superlattice for a finFET, according to some embodiments. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another (or more) elements or components as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0013] Various embodiments provide methods for implementing an improved pre-cleaning process to remove a native oxide layer in a semiconductor device and a semiconductor device formed by the above method. The pre-cleaning process can be a plasma-free dry etching process. In some embodiments, the pre-cleaning process can remove oxide (e.g., native oxide) from grooves formed in the fins using an etchant (such as hydrogen fluoride (HF) and ammonia (NH3)) before forming epitaxial source / drain regions in the fins. Implementing the pre-cleaning process using a plasma-free dry etching process can reduce the removal of material from shallow trench isolation (STI) regions and provide a better STI region profile. This may result in a semiconductor device formed by a method including a pre-cleaning process having an increased breakdown voltage, better performance, and reduced device defects.

[0014] Figure 1An example of a FinFET according to some embodiments is shown. The FinFET includes a fin 55 located on a substrate 50 (e.g., a semiconductor substrate). STI regions 58 are provided in the substrate 50, and the fin 55 protrudes above and from adjacent STI regions 58. Although the STI regions 58 are described / illustrated as being separated from the substrate 50, as used herein, the term "substrate" may be used to refer only to the semiconductor substrate or the semiconductor substrate including the STI regions. In addition, although the fin 55 and the substrate 50 are shown together as a single, continuous material, the fin 55 and / or the substrate 50 may include a single material or multiple materials. In this document, the fin 55 refers to the portion extending between adjacent STI regions 58.

[0015] Gate dielectric layer 100 is located along the sidewalls of fin 55 and over the top surface of fin 55, and gate electrode 102 is located over gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on opposite sides of fin 55, gate dielectric layer 100, and gate electrode 102. Figure 1 Reference cross sections used in subsequent figures are also shown. Cross section AA' is along the longitudinal axis of gate electrode 102 and is, for example, perpendicular to the direction of current flow between epitaxial source / drain regions 92 of the FinFET. Cross section BB' is perpendicular to cross section AA' and is along the longitudinal axis of fin 55 and is, for example, in the direction of current flow between epitaxial source / drain regions 92 of the FinFET. Cross section CC' is parallel to cross section AA' and extends through epitaxial source / drain regions 92 of the FinFET. Cross section DD' is parallel to cross section BB' and extends through the fin 55 of the FinFET. For clarity, subsequent figures refer to these reference cross sections.

[0016] Some embodiments discussed herein are discussed in the context of fin field-effect transistors (FinFETs) formed using a gate-last process. In some embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate aspects for use in planar devices such as planar FETs, nanostructure (e.g., nanosheets, nanowires, gate-all-around, etc.) field-effect transistors (NSFETs), and the like.

[0017] Figures 2 to 17D is a cross-sectional view of an intermediate stage in the fabrication of a FinFET, according to some embodiments. Figures 2 to 5 Shown in Figure 1 The reference section AA' is shown in FIG. Figure 1 The reference section AA' shown in FIG. Figure 6A 、 Figure 12A 、 Figure 13A 、 Figure 14A 、 Figure 15A 、 Figure 16A and Figure 17A Along Figure 1 A similar cross section BB' is shown showing Figure 6B 、 Figure 7B 、 Figure 8B 、 Figure 9B 、 Figure 10B 、 Figure 11B 、 Figure 12B 、 Figure 13B 、 Figure 14B 、 Figure 15B 、 Figure 15C 、 Figure 16B and Figure 17B Along Figure 1 The reference section CC' shown in FIG. Figure 7A 、 Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 11C and Figure 12C Along Figure 1 The reference section D-D' shown in FIG. Figure 9C 、 Figure 10C 、 Figure 12D 、 Figure 17C and Figure 17D .

[0018] exist Figure 2 In the embodiment of the present invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, which is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0019] Substrate 50 has region 50N and region 50P. Region 50N can be used to form n-type devices, such as NMOS transistors, for example, n-type FinFETs. Region 50P can be used to form p-type devices, such as PMOS transistors, for example, p-type FinFETs. Region 50N can be physically separated from region 50P (as shown by separation line 51), and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between region 50N and region 50P.

[0020] exist Figure 3 In the embodiment of the present invention, fins 55 are formed in substrate 50. Fins 55 are semiconductor strips. In some embodiments, fins 55 can be formed in substrate 50 by etching trenches in substrate 50. The etching process can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching process can be anisotropic.

[0021] The fins 55 may be patterned by any suitable method. For example, the fins 55 may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography and self-aligned processes, thereby allowing the creation of patterns having, for example, a pitch that is smaller than that obtainable using a single direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over the substrate and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins 55. In some embodiments, the mask (or other layer) may remain on the fins 55.

[0022] exist Figure 4 In the embodiment shown, shallow trench isolation (STI) regions 58 are formed adjacent to the fins 55. The STI regions 58 can be formed by forming an insulating material (not shown separately) over the substrate 50 and between adjacent fins 55. The insulating material can be an oxide, such as silicon oxide, nitride, or the like, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system with post-curing to convert the deposited material into another material, such as an oxide), or the like, or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the embodiment shown, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In some embodiments, the insulating material is formed so that excess insulating material covers the fins 55. The insulating material can include a single layer or multiple layers can be utilized. For example, in some embodiments, a liner (not shown separately) can be first formed along the surface of the substrate 50 and the fins 55. Thereafter, a filler material, such as those discussed above, can be formed over the liner.

[0023] Then, a removal process is applied to the insulating material to remove excess insulating material located above the fin 55. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. may be utilized. The planarization process may planarize the insulating material and the fin 55. The planarization process exposes the fin 55 so that after the planarization process is completed, the top surface of the fin 55 and the insulating material are flush.

[0024] The insulating material is then recessed to form a Figure 4 The STI regions 58 shown are shown. The insulating material is recessed so that the upper portions of the fins 55 and substrate 50 protrude from between adjacent STI regions 58. In addition, the top surfaces of the STI regions 58 can have a flat surface, a convex surface, a concave surface (such as a depression), or a combination thereof as shown. The top surfaces of the STI regions 58 can be formed to be flat, convex, and / or concave by appropriate etching. The STI regions 58 can be recessed using an acceptable etching process, such as one that is selective to the material of the insulating material (e.g., a material that etches the insulating material at a faster rate than the material of the fins 55 and substrate 50). For example, oxide removal can be used (using, for example, diluted hydrofluoric acid (dHF)).

[0025] about Figures 2 to 4 The process described is only one example of how the fin 55 may be formed. In some embodiments, the fin 55 may be formed by an epitaxial growth process. For example, a dielectric layer may be formed above the top surface of the substrate 50, and a trench may be etched through the dielectric layer to expose the substrate 50 below. A homoepitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form the fin. Additionally, in some embodiments, a heteroepitaxial structure may be used as the fin 55. For example, a heteroepitaxial structure may be used. Figure 4 The fins 55 in the substrate 50 are recessed, and a material different from the fins 55 can be epitaxially grown over the recessed fins 55. In such an embodiment, the fins 55 include the recessed material and the epitaxially grown material disposed over the recessed material. In some embodiments, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer. A heteroepitaxial structure can then be epitaxially grown in the trench using a material different from the substrate 50, and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fins 55. In some embodiments of epitaxially grown homoepitaxial or heteroepitaxial structures, the epitaxially grown material can be doped in situ during growth, which can eliminate previous and subsequent implants, but in situ and implant doping can be used together.

[0026] Furthermore, it may be advantageous to epitaxially grow a different material in region 50N (eg, NMOS region) than in region 50P (eg, PMOS region). In some embodiments, the upper portion of fin 55 may be made of silicon germanium (SiGe). x Ge 1-x, where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0027] Further in Figure 4 In the embodiment of the present invention, appropriate wells (not separately shown) may be formed in the fin 55 and / or the substrate 50. In some embodiments, a P-well may be formed in the region 50N, and an N-well may be formed in the region 50P. In some embodiments, either a P-well or an N-well may be formed in both the region 50N and the region 50P.

[0028] In embodiments with different well types, different implantation steps for regions 50N and 50P may be implemented using a photoresist or other mask (not separately shown). For example, a photoresist may be formed over the fin 55 and STI region 58 located in region 50N. The photoresist is patterned to expose a region 50P of substrate 50, such as a PMOS region. The photoresist may be formed using a spin coating technique, and the photoresist may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, an n-type impurity implantation is performed in region 50P, and the photoresist may be used as a mask to substantially prevent n-type impurities from being implanted into region 50N (such as an NMOS region). The n-type impurity may be equal to or less than 1×10 18 atoms / cm 3 The concentration (such as about 1×10 16 atoms / cm 3 and about 1×10 18 atoms / cm 3 Phosphorus, arsenic, antimony, etc. between the electrodes. After implantation, the photoresist is removed, such as by an acceptable ashing process.

[0029] After the implantation of region 50P, a photoresist is formed over fin 55 and STI region 58 located in region 50P. The photoresist is patterned to expose region 50N of substrate 50, such as an NMOS region. The photoresist can be formed using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implant can be performed in region 50N, and the photoresist can be used as a mask to substantially prevent the p-type impurity from being implanted into region 50P (such as a PMOS region). The p-type impurity can be equal to or less than 1×10 18 atoms / cm 3 The concentration (such as about 1×10 16 atoms / cm 3 and about 1x1018 atoms / cm 3 Boron, boron fluoride, indium, etc. between the electrodes. After implantation, the photoresist can be removed, such as by an acceptable ashing process.

[0030] After implantation of regions 50N and 50P, an anneal may be performed to repair implant damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the grown material of the epitaxial fins may be in-situ doped during growth, which may eliminate implantation, but in-situ and implantation doping may be used together.

[0031] exist Figure 5 In the embodiment of the present invention, a dummy dielectric layer 60 is formed on the fin 55 and the substrate 50. The dummy dielectric layer 60 can be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown according to an acceptable technique. A dummy gate layer 62 is formed above the dummy dielectric layer 60, and a mask layer 64 is formed above the dummy gate layer 62. The dummy gate layer 62 can be deposited above the dummy dielectric layer 60 and then planarized by a process such as CMP. The mask layer 64 can be deposited above the dummy gate layer 62. The dummy gate layer 62 can be a conductive or non-conductive material and can be selected from a group including amorphous silicon, polycrystalline silicon (poly-silicon), polycrystalline silicon germanium (poly-silicon germanium), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known in the art and used to deposit the selected material. The dummy gate layer 62 can be made of other materials with high etch selectivity relative to the material of the STI region 58. Mask layer 64 may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across region 50N and region 50P. It should be noted that, for illustrative purposes only, dummy dielectric layer 60 is shown covering only fin 55 and substrate 50. In some embodiments, dummy dielectric layer 60 may be deposited such that dummy dielectric layer 60 covers STI region 58, extending between dummy gate layer 62 and STI region 58.

[0032] 6A to 17D Various additional steps in the fabrication of example devices are shown. Figures 6A to 17D Components located in either region 50N or region 50P are shown. For example, 6A to 17D The structure shown may apply to both region 50N and region 50P. Differences in structure, if any, between region 50N and region 50P are described in the text accompanying each figure.

[0033] exist Figure 6A and Figure 6B In the embodiment, the mask layer 64 may be patterned using acceptable photolithography and etching techniques (see Figure 5) to form a mask 74. The pattern of the mask 74 can be transferred to the dummy gate layer 62 using an acceptable etching technique to form the dummy gate 72. In some embodiments, the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60. The dummy gates 72 cover the corresponding channel regions 68 of the fins 55. The pattern of the mask 74 can be used to physically separate each of the dummy gates 72 from the adjacent dummy gates. The dummy gates 72 can also have a length direction that is substantially perpendicular to the length direction of the corresponding epitaxial fin 55. The dummy dielectric layer 60, the dummy gates 72, and the mask 74 can be collectively referred to as a "dummy gate stack."

[0034] exist Figure 7A and Figure 7B in Figure 6A and Figure 6B A first spacer layer 80 and a second spacer layer 82 are formed over the structure shown. Figure 7A and Figure 7B In the embodiment of the present invention, a first spacer layer 80 is formed on the top surface of the STI region 58, on the top surface and sidewalls of the fin 55 and the mask 74, and on the sidewalls of the dummy gate 72 and the dummy dielectric layer 60. A second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 can be formed by thermal oxidation or deposited by CVD, ALD, etc. The first spacer layer 80 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc. The second spacer layer 82 can be deposited by CVD, ALD, etc. The second spacer layer 82 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc.

[0035] exist Figure 8A and Figure 8B , the first spacer layer 80 and the second spacer layer 82 are etched to form the first spacer 81 and the second spacer 83. The first spacer layer 80 and the second spacer layer 82 may be etched using a suitable etching process, such as an anisotropic etching process (e.g., a dry etching process). The first spacer 81 and the second spacer 83 may be disposed on the sidewalls of the fin 55, the dummy dielectric layer 60, the dummy gate 72, and the mask 74. Due to the etching process used to etch the first spacer layer 80 and the second spacer layer 82, the first spacer 81 and the second spacer 83 may have different heights from the adjacent fin 55 and the dummy gate stack, as well as different heights between the fin 55 and the dummy gate stack. Specifically, as Figure 8A and Figure 8B As shown, in some embodiments, the first spacer 81 and the second spacer 83 may partially extend upward along the sidewalls of the fin 55 and the dummy gate stack. In some embodiments, the first spacer 81 and the second spacer 83 may extend to the top surface of the dummy gate stack.

[0036] After forming the first spacer 81 and the second spacer 83, an implantation for a lightly doped source / drain (LDD) region (not shown separately) may be performed. In embodiments with different device types, similar to the above, Figure 4 50P, and an appropriate type of impurity (e.g., p-type) can be implanted into the exposed fins 55 and substrate 50 in the region 50P. The mask can then be removed. Subsequently, a mask, such as a photoresist, can be formed over the region 50P, while exposing the region 50N, and an appropriate type of impurity (e.g., n-type) can be implanted into the exposed fins 55 and substrate 50 in the region 50N. The mask can then be removed. The n-type impurity can be any of the n-type impurities previously discussed, and the p-type impurity can be any of the p-type impurities previously discussed. The lightly doped source / drain regions can have a density ranging from about 1×10 15 atoms / cm 3 to about 1×10 19 atoms / cm 3 Annealing can be used to repair implant damage and activate the implanted impurities.

[0037] It should be noted that the above disclosure generally describes a process for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, and a different sequence of steps may be used (e.g., the first spacer 81 may be formed before the second spacer 83 is formed, other spacers may be formed and removed, and / or the like). Furthermore, different structures and steps may be used to form n-type and p-type devices.

[0038] exist Figures 9A to 9C In the embodiment, a first recess 86 is formed in the fin 55, and a second recess 88 is formed in the substrate 50 in the STI region 58. Figure 9A As shown, the top surface of the STI region 58 can be flush with the top surface of the substrate 50. The substrate 50 can be etched so that the bottom surface of the first recess 86 is disposed above or below the top surface of the STI region 58. The fin 55 can be etched to form the first recess 86 so that epitaxial source / drain regions (such as those described below with respect to the embodiment of the present invention) can be subsequently formed in the first recess 86. Figures 11A to 11C The epitaxial source / drain regions 92 discussed above are shown in FIG. 1 . The etch process used to form first recess 86 may be selective to the material of fin 55 and substrate 50 (e.g., an etch process that etches the material of fin 55 and substrate 50 at a faster rate than the material of STI region 58). However, some material from STI region 58 may be removed by the etch process used to form first recess 86, thereby forming second recess 88.

[0039] The first recess 86 and the second recess 88 can be formed by etching the fin 55, the substrate 50, and the STI region 58 using an anisotropic etching process (such as RIE, NBE, etc.). In some embodiments, the process gases used in etching the fin 55, the substrate 50, and the STI region 58 may include hydrogen bromide (HBr), methane (CH4), and helium (He), but any suitable process gas may be used to etch the fin 55, the substrate 50, and the STI region 58. During the etching process used to form the first recess 86 and the second recess 88, the first spacer 81, the second spacer 83, and the mask 74 mask portions of the fin 55, the substrate 50, and the STI region 58. A single etching process or multiple etching processes can be used to form the first recess 86 and the second recess 88. After the first recess 86 reaches a desired depth, a timed etching process can be used to stop the etching of the first recess 86 and the second recess 88.

[0040] like Figure 9A As shown, the second groove 88 formed between adjacent fins 55 may have a width W1 from about 3 nm to about 5 nm or from about 3 nm to about 10 nm and a depth D1 from about 3 nm to about 8 nm or from about 3 nm to about 20 nm. The second groove 88 disposed outside the adjacent fins 55 may have a depth D2 from about 5 nm to about 25 nm or from about 10 nm to about 20 nm. Figure 9B As shown, the first recess 86 formed in the fin 55 and the substrate 50 may have a depth D3 from about 40 nm to about 60 nm or from about 45 nm to about 55 nm. Figure 9C As shown, the second recess formed adjacent to the dummy gate stack may have a width W2 from about 20 nm to about 28 nm or from about 22 nm to about 26 nm and a depth D4 from about 5 nm to about 25 nm or from about 10 nm to about 20 nm.

[0041] exist Figures 10A to 10CIn the embodiment of the present invention, a pre-cleaning process is performed to remove oxide (e.g., native oxide) from the surfaces of the fin 55 and the substrate 50 adjacent to the first recess 86. The pre-cleaning process may also remove material from the STI region 58, thereby extending the second recess 88. The pre-cleaning process may be performed by an isotropic dry etching process, etc. In some embodiments, the pre-cleaning process may use a plasma-free gaseous etching process. The pre-cleaning process may use a first process gas, such as hydrogen fluoride (HF), and a second process gas, such as ammonia (NH3), argon (Ar), helium (He), hydrogen (H2), or a combination thereof. During the pre-cleaning process, the flow rate of the first process gas may be from about 2 sccm to about 7 sccm or from about 3 sccm to about 5 sccm, and the flow rate of the second process gas may be from about 6 sccm to about 20 sccm or from about 10 sccm to about 16 sccm. The ratio of the flow rates of the first process gas to the second process gas may be from about 1:10 to about 1:1 or from about 1:5 to about 1:2. The pre-cleaning process may be performed for a duration ranging from about 70 seconds to about 80 seconds at a temperature ranging from about 5° C. to about 15° C. and a pressure ranging from about 1 Torr to about 3 Torr. The pre-cleaning process may remove an oxide layer having a thickness of less than about 4 nm or from about 3 nm to about 5 nm from surfaces of the fin 55 and the substrate 50 adjacent to the first recess 86.

[0042] A conventional pre-cleaning process may use a plasma-based dry etching process that includes free radicals, such as fluorine (F) radicals. Compared to a plasma-free gas cleaning process, the conventional pre-cleaning process may be performed at a higher temperature and a higher pressure in a shorter time. Compared to a conventional pre-cleaning process that may use a plasma-based process or a wet etching process, the use of a plasma-free gas cleaning process reduces the undercut of the STI region 58 located below the first spacer 81 and the second spacer 83. This increases the breakdown voltage and results in a device with better performance and reduced device defects.

[0043] like Figure 10AAs shown, second recess 88 outside fin 55 may have a profile having a first circular profile extending to a depth D5 from about 5 nm to about 25 nm, or from about 10 nm to about 20 nm, and a second circular profile extending from the bottom of the first circular profile to a depth D6 from about 10 nm to about 30 nm, or from about 15 nm to about 25 nm. The ratio of depth D5 to depth D6 may be from about 5:6 to about 2:3, or from about 4:5 to about 7:10. Second recess 88 may undercut first spacer 81 and second spacer by a lateral distance LD1 of less than about 3 nm, or from about 3 nm to about 5 nm. Second recess 88 located between adjacent fins 55 may have a maximum width W3 of from about 3 nm to about 5 nm, from about 5 nm to about 7 nm, or from about 5 nm to about 12 nm, and a depth D7 of from about 5 nm to about 10 nm, or from about 5 nm to about 22 nm.

[0044] like Figure 10C As shown, a second recess 88 adjacent to the dummy gate stack may also have a profile having a first circular profile extending to a depth D8 from about 5 nm to about 25 nm, from about 7 nm to about 27 nm, or from about 10 nm to about 20 nm, and a second circular profile extending from the bottom of the first circular profile to a depth D9 from about 10 nm to about 30 nm, or from about 15 nm to about 25 nm. The ratio of depth D8 to depth D9 may be from about 5:6 to about 2:3, or from about 4:5 to about 7:10. The second recess 88 may undercut the first spacer 81 and the second spacer by a lateral distance LD2 of less than about 3 nm, or from about 3 nm to about 5 nm. The first circular profile may have a maximum width W4 of from about 25 nm to about 30 nm, or from about 26 nm to about 29 nm, and the second circular profile may have a maximum width W5 of from about 5 nm to about 10 nm, or from about 6 nm to about 9 nm. The ratio of width W4 to width W5 may be from about 6:1 to about 5:1. The width W6 of the STI region 58 separating adjacent second recesses 88 may be greater than about 24 nm or from about 20 nm to about 28 nm. After forming the first recess 86 and the second recess 88, the first spacer 81 and the second spacer 83 may have a thickness T1 adjacent to the top of the dummy gate stack and a thickness T2 adjacent to the bottom of the dummy gate stack. The ratio of thickness T2 to thickness T1 may be from about 1 to about 1.2 or from about 1.05 to about 1.15.

[0045] Performing the pre-clean process using the first process gas and the second process gas allows for removal of the oxide layer from the surfaces of the fin 55 and substrate 50 adjacent to the first recess 86 while minimizing the amount of material removed from the STI region 58. In some embodiments, the pre-clean process can result in less lateral etching than other methods of removing the oxide layer and can produce STI regions 58 and second recesses 88 with better profiles. For example, fewer kinks can be formed adjacent to the interface of the dummy gate stack and the top of the STI region 58. Using the pre-clean process allows devices formed by methods including the pre-clean process to have increased breakdown voltage, better performance, and reduced device defects.

[0046] After the pre-cleaning process is performed, the STI region 58 may be implanted. Implantation may be used to increase the resistance of the STI region 58, which may further increase the breakdown voltage, improve performance, and reduce device defects. Impurities such as phosphorus ions, boron ions, or combinations thereof may be implanted into the STI region 58. The STI region 58 may have a density greater than about 1×10 15 atoms / cm 3 or from about 1×10 15 atoms / cm 3 to about 1×10 16 atoms / cm 3 The impurities may be implanted at a temperature of from about 50° C. to about 70° C. or from about 55° C. to about 65° C. Annealing may be used to repair implantation damage and activate the implanted impurities.

[0047] exist Figures 11A to 11C In the embodiment, epitaxial source / drain regions 92 are formed in the first recess 86 to apply stress on the channel region 68 of the fin 55, thereby improving performance. Figure 10B As shown, epitaxial source / drain regions 92 are formed in first recesses 86 such that each dummy gate 72 is disposed between a corresponding adjacent pair of epitaxial source / drain regions 92. In some embodiments, first spacers 81 are used to separate the epitaxial source / drain regions 92 from the dummy gates 72 by an appropriate lateral distance so that the epitaxial source / drain regions 92 do not short-circuit a subsequently formed gate of the resulting FinFET.

[0048] Epitaxial source / drain regions 92 located in regions 50N (e.g., NMOS regions) can be formed by masking regions 50P (e.g., PMOS regions). Epitaxial source / drain regions 92 are then epitaxially grown in first recesses 86. Epitaxial source / drain regions 92 can include any acceptable material, such as suitable for n-type FinFETs. For example, if fins 55 are silicon, epitaxial source / drain regions 92 can include a material that applies tensile strain to fins 55, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain regions 92 can have surfaces that are raised from the corresponding surfaces of the fins 55 and can have small facets.

[0049] Epitaxial source / drain regions 92 may be formed in regions 50P (e.g., PMOS regions) by masking regions 50N (e.g., NMOS regions). Epitaxial source / drain regions 92 are then epitaxially grown in first recesses 86. Epitaxial source / drain regions 92 may include any acceptable material, such as suitable for p-type NSFETs. For example, if fins 55 are silicon, epitaxial source / drain regions 92 may include a material that applies compressive strain to fins 55, such as silicon germanium, boron-doped silicon germanium, germanium, germanium-tin, etc. Epitaxial source / drain regions 92 may also have surfaces that are raised from the corresponding surfaces of fins 55 and may have facets.

[0050] The epitaxial source / drain regions 92, fins 55, and / or substrate 50 may be implanted with dopant species to form source / drain regions, similar to the previously discussed method for forming lightly doped source / drain regions, followed by annealing. The source / drain regions may have a density of about 1×10 19 atoms / cm 3 and about 1×10 21 atoms / cm 3 The n-type and / or p-type impurities used for the source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0051] Due to the epitaxial process used to form epitaxial source / drain regions 92 in regions 50N and 50P, the upper surfaces of epitaxial source / drain regions 92 have facets that extend laterally outward beyond the sidewalls of fin 55. In some embodiments, these facets allow adjacent epitaxial source / drain regions 92 of the same FinFET to merge, e.g., Figure 11A In some embodiments, after the epitaxial process is completed, adjacent epitaxial source / drain regions 92 remain separated, as shown in FIG. Figure 10C As shown. Figure 11A and Figure 11CIn the embodiment shown, first spacers 81 can be formed to cover portions of the sidewalls of fins 55 extending above STI regions 58, thereby preventing epitaxial growth. In some embodiments, the spacer etch used to form first spacers 81 can be tailored to remove spacer material, thereby allowing the epitaxial growth region to extend to the surface of STI regions 58.

[0052] exist 12A to 12D In the embodiment, the first interlayer dielectric (ILD) 96 is deposited on Figure 6A 、 Figure 11A 、 Figure 11B and Figure 10C ( 7A to 10C The process has not changed Figure 6A The cross section shown, Figure 6A The dummy gate 72 and the multilayer stack 56 protected by the dummy gate 72 are shown, and Figures 11A to 11C The process has not changed Figure 10C The cross section shown, Figure 10C 88 formed in the STI region 58). The first ILD 96 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain regions 92, the mask 74, the first spacer 81, the second spacer 83, and the STI region 58. The CESL 94 may include a dielectric material having a different etch rate than the material of the first ILD 96 above, such as silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0053] exist Figure 13A and Figure 13B In the process, a planarization process (such as CMP) can be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 72 or the mask 74. The planarization process can also remove the mask 74 located on the dummy gate 72 and the portion of the first spacer 81 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, the first spacer 81, and the first ILD 96 are flush. Therefore, the top surface of the dummy gate 72 is exposed through the first ILD 96. In some embodiments, the mask 74 can be retained, wherein the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 74 and the first spacer 81.

[0054] exist Figure 14A and Figure 14BIn the etching step, the dummy gate 72 and mask 74 (if present) are removed, thereby forming second recesses 98. Portions of the dummy dielectric layer 60 located in the second recesses 98 may also be removed. In some embodiments, only the dummy gate 72 is removed, and the dummy dielectric layer 60 remains and is exposed by the second recesses 98. In some embodiments, the dummy dielectric layer 60 is removed from the second recesses 98 in a first region of the die (e.g., the core logic region) and remains in the second recesses 98 in a second region of the die (e.g., the input / output region). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 72 at a faster rate than the first ILD 96 or the first spacers 81. Each second recess 98 exposes and / or is located above the channel region 68 of a corresponding fin 55. Each channel region 68 is disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy dielectric layer 60 may serve as an etch stop layer when etching the dummy gate 72. The dummy dielectric layer 60 may then be optionally removed after removal of the dummy gate 72.

[0055] exist Figure 15A and Figure 15B In the process, a gate dielectric layer 100 and a gate electrode 102 for replacing a gate are formed. Figure 15C Shown Figure 15B Detailed view of region 101 of the fin 55 is provided. A gate dielectric layer 100 is conformally deposited in second recess 98, such as on the top surfaces and sidewalls of fin 55 and first spacer 81, and on the top surfaces of STI region 58, first ILD 96, second spacer 83, and CESL 94. In some embodiments, gate dielectric layer 100 comprises silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, gate dielectric layer 100 comprises a high-k dielectric material, and in these embodiments, gate dielectric layer 100 may have a k value greater than approximately 7.0 and may comprise a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Methods of forming gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, and the like. In embodiments where a portion of dummy dielectric layer 60 remains in second recess 98, gate dielectric layer 100 comprises the material of dummy dielectric layer 60 (e.g., SiO2).

[0056] A gate electrode 102 is deposited over the gate dielectric layer 100 and fills the remaining portion of the second recess 98. The gate electrode 102 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, a combination thereof, or a multilayer thereof. Figure 15B A single-layer gate electrode 102 is shown in FIG. 1 , but the gate electrode 102 may include Figure 15C96 . A plurality of liner layers 102A, work function adjustment layers 102B, and filler material 102C are shown. After filling the second recess 98, a planarization process (such as CMP) may be performed to remove excess portions of the gate dielectric layer 100 and the gate electrode 102 material that are located above the top surface of the first ILD 96. The gate electrode 102 and the remaining portions of the gate dielectric layer 100 material thus form a replacement gate for the resulting FinFET. The gate electrode 102 and the gate dielectric layer 100 may be collectively referred to as a "gate stack." The gate and the gate stack may extend along the sidewalls of the channel region 68 of the fin 55.

[0057] The formation of the gate dielectric layer 100 in the region 50N and the region 50P can occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 can occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region can be formed by a different process, such that the gate dielectric layer 100 can be a different material, and / or the gate electrode 102 in each region can be formed by a different process, such that the gate electrode 102 can be a different material. When different processes are used, various masking steps can be used to mask and expose the appropriate regions.

[0058] exist Figure 16A and Figure 16B In some embodiments, a second ILD 106 is deposited over the first ILD 96. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material (such as PSG, BSG, BPSG, USG, etc.) and can be deposited by any suitable method (such as CVD, PECVD, etc.). In some embodiments, prior to the formation of the second ILD 106, the gate stack (including the gate dielectric layer 100 and the corresponding upper gate electrode 102) is recessed so that a groove is formed directly above the gate stack and between the opposing portions of the first spacer 81. A gate mask 104 including one or more layers of dielectric material (such as silicon nitride, silicon oxynitride, etc.) is filled in the groove, followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD 96. A gate contact (such as the one described below with reference to FIG. 1 ) is subsequently formed. Figure 17A and Figure 17B The gate contact 112 discussed herein penetrates the gate mask 104 to contact the top surface of the recessed gate electrode 102 .

[0059] exist 17A to 17DIn the embodiment of the present invention, a gate contact 112 and a source / drain contact 114 are formed through the second ILD 106 and the first ILD 96. An opening for the source / drain contact 114 is formed through the first ILD 96 and the second ILD 106, and an opening for the gate contact 112 is formed through the second ILD 106 and the gate mask 104. The openings can be formed using acceptable photolithography and etching techniques. A liner (such as a diffusion barrier layer, an adhesion layer, etc.) and a conductive material are formed in the openings. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process (such as CMP) can be performed to remove excess material from the surface of the second ILD 106. The remaining liner and conductive material form the source / drain contacts 114 and the gate contact 112 in the openings. An annealing process may be performed to form silicide at the interface between the epitaxial source / drain regions 92 and the source / drain contacts 114. The source / drain contacts 114 are physically and electrically coupled to the epitaxial source / drain regions 92, and the gate contact 112 is physically and electrically coupled to the gate electrode 102. The source / drain contacts 114 and the gate contact 112 may be formed in different processes or may be formed in the same process. Although shown as being formed in the same cross-section, it should be understood that each of the source / drain contacts 114 and the gate contact 112 may be formed in different cross-sections, which may avoid shorting of the contacts.

[0060] like Figure 17C As shown, the source / drain contacts 114 may extend below the top surface of the STI regions 58 by a distance D of about 5 nm to about 10 nm or about 6 nm to about 9 nm. 10 The width W7 of the first ILD 96 extending from the sidewall of the CESL 94 to the sidewall of the source / drain contact 114 may be from about 5 nm to about 10 nm, and the width W8 of the source / drain contact 114 may be from about 15 nm to about 20 nm. The ratio of the width W8 to the width W7 may be from about 3:1 to about 4:1. Figure 17D As shown, in some embodiments, the bottom surface of the source / drain contact 114 can be disposed above the top surface of the STI region 58. For example, the bottom surface of the source / drain contact 114 can be disposed above the top surface of the STI region 58 by a distance D from about 2 nm to about 8 nm or from about 3 nm to about 6 nm. 11 The source / drain contacts 114 may be connected to two or more epitaxial source / drain regions 92, and Figure 17C and Figure 17DA source / drain contact 114 is shown located between the epitaxial source / drain regions 92. The source / drain contact 114 can be separated from the gate stack by a lateral distance of at least 6 nm or from about 4 nm to about 10 nm. Separating the source / drain contact 114 from the gate stack by at least a lateral distance helps increase breakdown voltage, improve device performance, and reduce device defects.

[0061] like Figure 17C and Figure 17D As shown, the second ILD 96 may have substantially straight, vertical sidewalls extending from a point flush with the top surfaces of the gate mask 104, the first spacer 81, and the second spacer 83 to a point flush with the bottom surfaces of the gate dielectric layer 100, the first spacer 81, and the second spacer 83. The sidewalls of the second ILD 96 may have a first circular profile extending from a point flush with the bottom surfaces of the gate dielectric layer 100, the first spacer 81, and the second spacer 83 to a first depth below the top surface of the STI region. The first circular profile may have a first diameter. The sidewalls of the second ILD 96 may have a second circular profile extending from the first depth to a second depth below the top surface of the STI region 58. The second circular profile may have a second diameter that is smaller than the first diameter. The ratio of the second diameter to the first diameter may be from about 5:6 to about 2:3 or from about 4:5 to about 7:10, and the ratio of the first depth to the second depth may be from about 4:1 to about 7:1 or from about 5:1 to about 6:1. As shown Figure 17C and Figure 17D As further shown, the sidewalls of the upper portion of the source / drain contacts 114 may be substantially straight and vertical, and the sidewalls of the lower portion of the source / drain contacts 114 may have a rounded profile.

[0062] As previously discussed, using the above-described pre-clean process and the above-described implant process on STI regions 58 respectively reduces material loss from STI regions 58 and improves the resistance of STI regions 58. This helps to increase breakdown voltage, improve device performance, and reduce device defects in semiconductor devices formed according to the above-described processes.

[0063] The disclosed FinFET embodiments may also be applied to nanostructured devices, such as nanostructured (e.g., nanosheets, nanowires, all-around gate, etc.) field effect transistors (NSFETs). In NSFET embodiments, the fins are replaced by nanostructures formed by stacks of alternating layers of patterned channel layers and sacrificial layers. A dummy gate stack and source / drain regions are formed in a manner similar to the above-described embodiments. After removing the dummy gate stack, the sacrificial layer in the channel region may be partially or completely removed. A replacement gate structure is formed in a manner similar to the above-described embodiments, the replacement gate structure may partially or completely fill the opening left by removing the sacrificial layer, and the replacement gate structure may partially or completely surround the channel layer in the channel region of the NSFET device. An ILD and contacts to the replacement gate structure and source / drain regions may be formed in a manner similar to the above-described embodiments. The nanostructured device may be formed as disclosed in U.S. Patent Application No. 2016 / 0365414, the entire contents of which are incorporated herein by reference.

[0064] The formation of a nanostructured device is described below using the method disclosed in U.S. Patent Application No. 2016 / 0365414 as an example.

[0065] exist Figure 18A and Figure 18B In the embodiment, a substrate 20 is provided. Figure 19A and Figure 19B , a buffer layer 22 is formed on a substrate 20. In this embodiment, the buffer layer 22 has a lower portion that will remain as part of the fin and additionally includes an upper portion that will serve as a sacrificial fin, as will be described later. The upper portion of the buffer layer 22 can be of any material composition, such as the same composition as the surface of the lower portion that will be formed later away from the substrate 20. Although not specifically shown, suitable wells can be formed in the buffer layer 22 and / or the substrate 20, such as by implantation as previously discussed or in-situ implantation during growth.

[0066] exist Figure 20A 、 Figure 20B In the embodiment of the present invention, a trench is formed in the buffer layer 22 to form a sacrificial fin from the buffer layer 22. In some embodiments, the sacrificial fin can be formed by etching a trench in the buffer layer 22 but not completely through the buffer layer 22. In some embodiments, the trench can extend through the buffer layer 22 but not into the substrate 20. In some embodiments, the trench can extend through the buffer layer 22 and into the substrate 20. The etching process can be any acceptable etching process such as RIE, NBE, etc., or a combination thereof. The etching process can be anisotropic.

[0067] In addition, Figure 20A 、 Figure 20BIn the embodiment shown, the trench is filled with an insulating material 30. The insulating material 30 can be an oxide such as silicon oxide, a nitride, or the like, or a combination thereof, and can be formed by HDP-CVD, FCVD, or the like, or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the embodiment shown, the insulating material 30 is silicon oxide formed by an FCVD process. Once the insulating material 30 is formed, an annealing process can be performed. In addition, a planarization process such as CMP can remove any excess insulating material and form a coplanar top surface of the insulating material 30 and the top surface of the sacrificial fin.

[0068] In addition, Figure 20A 、 Figure 20B The sacrificial fin is recessed to form a groove between the insulating material 30. The recess can be made using an acceptable etching process, such as an etching process that is selective to the sacrificial fin. The etching process can be a wet process or a dry process and can be isotropic. The recessing of the sacrificial fin results in the lower portion of the buffer layer 22 remaining between the insulating material 30 as shown. This recess forms the surface of the buffer layer 22 away from the substrate 20 as previously discussed.

[0069] exist Figure 21A 、 Figure 21B In the embodiment of the present invention, a superlattice 24 is formed in the grooves between the insulating material 30 and on the buffer layer 22. The superlattice 24 includes alternating first layers 26 and second layers 28. The superlattice 24 can include any number of first layers 26 and any number of second layers 28. As shown, the superlattice 24 has four first layers 26 and four second layers 28. The first layers 26 and second layers 28 can be strained or relaxed. By forming the superlattice 24 in the grooves between the insulating material 30, a fin including the superlattice 24 is formed. A planarization process such as CMP can form the top surfaces of the insulating material 30 and the fin to be coplanar.

[0070] According to an embodiment, a method includes: forming a shallow trench isolation region above a semiconductor substrate; forming a gate stack above the shallow trench isolation region; etching the shallow trench isolation region adjacent to the gate stack using an anisotropic etching process; and etching the shallow trench isolation region using an isotropic etching process after etching the shallow trench isolation region using the anisotropic etching process, wherein the process gas used for the isotropic etching process includes hydrogen fluoride (HF) and ammonia (NH3). In an embodiment, during the isotropic etching process, the flow rate of hydrogen fluoride is from 2 sccm to 7 sccm, and during the isotropic etching process, the flow rate of ammonia is from 6 sccm to 20 sccm. In an embodiment, during the isotropic etching process, the ratio of the flow rate of ammonia to the flow rate of hydrogen fluoride is 3:1. In an embodiment, the anisotropic etching process etches the shallow trench isolation region to a depth of 5 nm to 25 nm below the top surface of the shallow trench isolation region, and the isotropic etching process etches the shallow trench isolation region to a depth of 10 nm to 30 nm below the top surface of the shallow trench isolation region. In an embodiment, after etching the shallow trench isolation region using the isotropic etching process, impurities are implanted into the shallow trench isolation region. In an embodiment, the impurities include phosphorus, and the shallow trench isolation region is doped to at least 1×10 15 atoms / cm 3 Phosphorus concentration. In an embodiment, the shallow trench isolation region is etched using an isotropic etching process for 70 seconds to 80 seconds. In an embodiment, the shallow trench isolation region is etched using an anisotropic etching process to form a first circular profile in the shallow trench isolation region to a depth of 5 nm to 25 nm below the top surface of the shallow trench isolation region, and the shallow trench isolation region is etched using an isotropic etching process to form a second circular profile in the shallow trench isolation region to a depth of 5 nm to 25 nm below the top surface of the shallow trench isolation region, and a third circular profile is formed in the shallow trench isolation region extending from the second circular profile to a depth of 10 nm to 30 nm below the top surface of the shallow trench isolation region.

[0071] According to another embodiment, a method includes: forming a gate stack above a semiconductor fin, the semiconductor fin extending from a semiconductor substrate; anisotropically etching the semiconductor fin to form a first recess; and isotropically etching the semiconductor fin using a plasma-free dry etching process to remove oxide from the semiconductor fin. In an embodiment, isotropically etching the semiconductor fin includes exposing the semiconductor fin to a process gas including hydrogen fluoride (HF) and ammonia (NH3). In an embodiment, the ratio of the flow rate of ammonia in the process gas to the flow rate of hydrogen fluoride in the process gas is 3:1. In an embodiment, the flow rate of ammonia in the process gas is from 6 sccm to 20 sccm, and the flow rate of hydrogen fluoride in the process gas is from 2 sccm to 7 sccm. In an embodiment, the method further includes epitaxially growing a source / drain region in the first recess after isotropically etching the semiconductor fin.

[0072] According to yet another embodiment, a semiconductor device includes: a shallow trench isolation (STI) region located above a semiconductor substrate; a gate electrode located above the STI region; and a first dielectric located above the shallow trench isolation region and surrounding the gate electrode, the first dielectric having a first circular profile extending a first distance of 5 nm to 25 nm below a top surface of the shallow trench isolation region, the first dielectric having a second circular profile extending a second distance of 10 nm to 30 nm from the first circular profile below the top surface of the shallow trench isolation region. In an embodiment, the semiconductor device further includes: a gate spacer adjacent to the gate electrode, the first dielectric extending a lateral distance of 3 nm to 5 nm below the gate spacer. In an embodiment, the STI region is doped with phosphorus. In an embodiment, the STI region is doped with phosphorus to at least 1×10 15 atoms / cm 3 In an embodiment, the first circular profile has a maximum width of 25 nm to 30 nm, and the second circular profile has a maximum width of 5 nm to 10 nm. In an embodiment, the first dielectric includes a contact etch stop layer (CESL) and an interlayer dielectric (ILD) located above the CESL. In an embodiment, the semiconductor device further includes: source / drain contacts extending at least partially through the first dielectric, with a bottom surface of the source / drain contacts disposed below a top surface of the STI region.

[0073] The features of several embodiments have been summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor device, comprising: forming a shallow trench isolation region above the semiconductor substrate; forming a gate stack above the shallow trench isolation region; Etching the shallow trench isolation region adjacent to the gate stack using an anisotropic etching process, wherein etching the shallow trench isolation region using the anisotropic etching process forms a first circular profile in the shallow trench isolation region, the first circular profile extending to a first depth below a top surface of the shallow trench isolation region; and After etching the shallow trench isolation region using the anisotropic etching process, etching the shallow trench isolation region using an isotropic etching process, wherein the process gas used for the isotropic etching process includes hydrogen fluoride (HF) and ammonia (NH3), wherein the shallow trench isolation region is etched using the isotropic etching process to form a second circular profile and a third circular profile in the shallow trench isolation region, the second circular profile to the first depth below the top surface of the shallow trench isolation region, and the third circular profile extends from the second circular profile to the second depth below the top surface of the shallow trench isolation region.

2. The method according to claim 1, wherein During the isotropic etching process, a flow rate of hydrogen fluoride is from 2 sccm to 7 sccm, and during the isotropic etching process, a flow rate of ammonia is from 6 sccm to 20 sccm.

3. The method according to claim 1, wherein During the isotropic etching process, the ratio of the flow rate of ammonia to the flow rate of hydrogen fluoride is 3:

1.

4. The method according to claim 1, wherein The first depth is 5 nm to 25 nm, and wherein the second depth is 10 nm to 30 nm.

5. The method according to claim 1, further comprising: After etching the shallow trench isolation region using the isotropic etching process, impurities are implanted into the shallow trench isolation region.

6. The method according to claim 5, wherein: The impurities include phosphorus, and wherein the shallow trench isolation region is doped to at least 1×10 15 atoms / cm 3 phosphorus concentration.

7. The method according to claim 1, wherein The shallow trench isolation region is etched for 70 seconds to 80 seconds using the isotropic etching process.

8. The method according to claim 1, wherein The second circular profile has a maximum width from 25 nm to 30 nm, and wherein the third circular profile has a maximum width from 5 nm to 10 nm.

9. A method of forming a semiconductor device, comprising: forming an isolation region above a semiconductor substrate and adjacent to a semiconductor fin, the semiconductor fin extending from the semiconductor substrate; forming a gate stack over the semiconductor fin and the isolation region, the semiconductor fin extending from a semiconductor substrate; Anisotropically etching the semiconductor fin and the isolation region, wherein anisotropically etching the semiconductor fin removes material of the semiconductor fin and forms a first recess in the semiconductor fin; The semiconductor fin and the isolation region are isotropically etched using a plasma-free dry etching process, wherein isotropically etching the semiconductor fin removes native oxide from an inner surface of the first recess.

10. The method according to claim 9, wherein: Isotropically etching the semiconductor fin includes exposing the semiconductor fin to a process gas including hydrogen fluoride (HF) and ammonia (NH 3 ).

11. The method according to claim 10, wherein: The ratio of the flow rate of ammonia in the process gas to the flow rate of hydrogen fluoride in the process gas is 3:

1.

12. The method according to claim 10, wherein: The flow rate of ammonia in the process gas is from 6 sccm to 20 sccm, and the flow rate of hydrogen fluoride in the process gas is from 2 sccm to 7 sccm.

13. The method according to claim 9, further comprising: After isotropically etching the semiconductor fin, source / drain regions are epitaxially grown in the first recess.

14. A semiconductor device comprising: a shallow trench isolation (STI) region located above the semiconductor substrate; a gate electrode located above the shallow trench isolation region; as well as A first dielectric is located above the shallow trench isolation region and surrounds the gate electrode, the first dielectric having a first circular profile extending a first distance of 5 nm to 25 nm below a top surface of the shallow trench isolation region, and the first dielectric having a second circular profile extending a second distance of 10 nm to 30 nm from the first circular profile below the top surface of the shallow trench isolation region.

15. The semiconductor device according to claim 14, further comprising: A gate spacer is adjacent to the gate electrode, and the first dielectric extends a lateral distance of 3 nm to 5 nm below the gate spacer.

16. The semiconductor device according to claim 14, wherein The shallow trench isolation region is doped with phosphorus.

17. The semiconductor device according to claim 16, wherein The shallow trench isolation region is doped with phosphorus to at least 1×10 15 atoms / cm 3 dopant concentration.

18. The semiconductor device according to claim 14, wherein The first circular profile has a maximum width from 25 nm to 30 nm, and wherein the second circular profile has a maximum width from 5 nm to 10 nm.

19. The semiconductor device according to claim 14, wherein The first dielectric includes a contact etch stop layer (CESL) and an interlayer dielectric (ILD) over the CESL.

20. The semiconductor device according to claim 14, further comprising: A source / drain contact extends at least partially through the first dielectric, wherein a bottom surface of the source / drain contact is disposed below a top surface of the shallow trench isolation region.

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