Semiconductor structure and method for forming the same

Abstract

The semiconductor structure includes a first dielectric layer located above a first conductive line and a second conductive line, a high resistance layer located above a portion of the first dielectric layer, a low-k dielectric layer located above the second dielectric layer, a second dielectric layer located on the high resistance layer, a first conductive via extending through the low-k dielectric layer and the second dielectric layer, and a second conductive via extending through the low-k dielectric layer and the first dielectric layer to the first conductive line. The first conductive via extends into the high resistance layer. Embodiments of the present invention also relate to a method for forming a semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor structures and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. Over the course of IC evolution, functional density (e.g., the number of interconnected devices per chip area) has generally increased, while geometry size (e.g., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] As devices scale down, manufacturers have begun using new and different materials and / or combinations of materials to facilitate device scaling. Scaling down, alone and in combination with new and different materials, also raises challenges that may not have been encountered in previous generations of larger geometries. Summary of the invention

[0004] An embodiment of the present invention provides a semiconductor structure, comprising: a first dielectric layer, located above a first conductive line and a second conductive line; a high resistance layer, located above a first portion of the first dielectric layer, the second portion of the first dielectric layer does not have the high resistance layer, the first portion of the first dielectric layer has a first thickness, and the second portion of the first dielectric layer has a second thickness less than the first thickness; a second dielectric layer, located on the high resistance layer; a low-k dielectric layer, located above the second dielectric layer and the second portion of the first dielectric layer, the low-k dielectric layer extending along the side walls of the high resistance layer and the second dielectric layer; a first conductive via, extending through the low-k dielectric layer and the second dielectric layer, the first conductive via extending into the high resistance layer; and a second conductive via, extending through the low-k dielectric layer and the first dielectric layer to the first conductive line.

[0005] Another embodiment of the present invention provides a semiconductor structure, comprising: a logic region, comprising: a first conductive line; a first portion of a first dielectric layer, located above the first conductive line, the first portion having a first thickness; a first portion of a low-k dielectric layer, located above the first dielectric layer; and a first conductive via, extending through the first portion of the low-k dielectric layer and the first dielectric layer, the first conductive via being in physical contact with the first conductive line; and a high resistance region, the high resistance region comprising: a second portion of the first dielectric layer; a high resistance layer, located on the second portion of the first dielectric layer; a second dielectric layer, located on the high resistance layer, the second dielectric layer having a second thickness, wherein the second dielectric layer has the same material structure as the first portion of the first dielectric layer above the first conductive line; the second portion of the low-k dielectric layer, located on the second dielectric layer; and a second conductive via, extending through the second portion of the low-k dielectric layer and the second dielectric layer, the second conductive via extending below the top surface of the high resistance layer.

[0006] Another embodiment of the present invention provides a method for forming a semiconductor structure, the method comprising: forming a first dielectric layer above an interconnect layer, the interconnect layer comprising a conductive line; forming a high resistance layer on the first dielectric layer; forming a second dielectric layer on the high resistance layer; patterning the second dielectric layer and the high resistance layer, wherein the patterning causes the first dielectric layer above the conductive line to be recessed, wherein, after the patterning, the first dielectric layer above the conductive line has a first thickness, wherein the first dielectric layer below the high resistance layer has a second thickness greater than the first thickness; forming a low-k dielectric layer above the second dielectric layer and the first dielectric layer, the low-k dielectric layer extending above the top surface and sidewalls of the first dielectric layer; forming a first opening through the low-k dielectric layer and the second dielectric layer, the first opening extending into the high resistance layer; forming a conductive material in the first opening; and planarizing the low-k dielectric layer and the conductive material. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 A cross-sectional view of a semiconductor substrate and a multi-level interconnect structure of an integrated circuit according to some embodiments is shown.

[0009] Figures 2 to 10B Cross-sectional views and plan views of semiconductor devices at various intermediate stages of fabrication are illustrated in accordance with some embodiments. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0011] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or during operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0012] The present invention includes a high resistance layer and a method of forming the same between metallization layers in a back-end of line (BEOL) region, for example, located above a semiconductor device. Placing the high resistance layer in the BEOL region between the metallization layers, for example, can save up to 5% of the analog circuit design area and about 5% of the analog die area relative to a design where the high resistance layer is located below the metallization layer, such as in a middle of line (MEOL) or front-end of line (FEOL) region. A uniform contact resistance for a conductive via can be produced by using a dielectric layer of substantially similar thickness and material as an etch stop above the conductive line and the high resistance layer to control the bottom surface area of ​​the conductive via to be substantially similar. This uniformity of the conductive via contact resistance can be useful for device performance. Although the present invention discusses aspects of a method of forming a high resistance layer in the context of a BEOL process performed after, for example, a FinFET formation process, other embodiments may use aspects of the present invention with other semiconductor manufacturing processes.

[0013] Figure 1 A cross-sectional view of a semiconductor structure 100 is shown according to some embodiments, the semiconductor structure 100 including a semiconductor substrate 50 in which various electronic devices may be formed and portions of a multi-level interconnect system (e.g., layers 100A and 100B) formed above the substrate 50. In general, as will be discussed in more detail below, Figure 1 A FinFET device 60 is shown formed on a substrate 50 with multiple interconnect layers formed above the substrate 50 .

[0014] generally, Figure 1 The substrate 50 shown may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer located below a thin semiconductor layer, which is the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor generally include a crystalline semiconductor material, silicon, but may include one or more other semiconductor materials, such as germanium, a silicon-germanium alloy, a compound semiconductor (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.), or alloys thereof (e.g., Ga x Al 1-x As、Ga x Al 1-x N、In x Ga 1-x As, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.

[0015] Figure 1 The illustrated FinFET device 60 is a three-dimensional MOSFET structure formed in a fin-like strip of semiconductor protrusions 58 called fins. Figure 1 The cross section shown in is taken along the longitudinal axis of the fin in a direction parallel to the direction of current flow between the source region and the drain region 54. The fin 58 can be formed by patterning the substrate using photolithography and etching techniques. For example, a spacer image transfer (SIT) patterning technique can be used. In this method, a sacrificial layer is formed over the substrate using a suitable photolithography and etching process and the sacrificial layer is patterned to form a mandrel. Spacers are formed next to the mandrel using a self-aligned process. The sacrificial layer is then removed by an appropriate selective etching process. Each remaining spacer can then be used as a hard mask to pattern the corresponding fin 58 by etching a trench in the substrate 50 using, for example, reactive ion etching (RIE). Figure 1 A single fin 58 is shown, but substrate 50 may include any number of fins.

[0016] Figure 158 , a shallow trench isolation (STI) region 62 is shown formed along the opposite sidewalls of the fin 58. The STI region 62 can be formed by depositing one or more dielectric materials (e.g., silicon oxide) to completely fill the trench around the fin, and then recessing the top surface of the dielectric material. The dielectric material of the STI region 62 can be deposited using high density plasma chemical vapor deposition (HDP-CVD), low pressure CVD (LPCVD), sub-atmospheric pressure CVD (SACVD), flowable CVD (FCVD), spin coating, etc., or a combination thereof. After deposition, an annealing process or a curing process can be performed. In some cases, the STI region 62 may include a liner (not shown), such as a thermal oxide liner grown by oxidizing the silicon surface, for example. The recessing process can use, for example, a planarization process (e.g., chemical mechanical polishing (CMP)), and a subsequent selective etching process (e.g., wet etching, dry etching, or a combination thereof) that can recess the top surface of the dielectric material in the STI region 62, so that the upper portion of the fin 58 protrudes from the surrounding insulating STI region 62. In some cases, the patterned hard mask used to form fins 58 may also be removed by the planarization process.

[0017] In some embodiments, Figure 1 The gate structure 68 of the FinFET device 60 shown is a high-k metal gate (HKMG) gate structure that can be formed using a gate-last process flow. In the gate-last process flow, a sacrificial dummy gate structure (not shown) is formed after the STI region 62 is formed. The dummy gate structure may include a dummy gate dielectric, a dummy gate electrode, and a hard mask. First, a dummy gate dielectric material (e.g., silicon oxide, silicon nitride, etc.) can be deposited. Next, a dummy gate material (e.g., amorphous silicon, polycrystalline silicon, etc.) can be deposited over the dummy gate dielectric, and then the dummy gate material is planarized (e.g., by CMP). A hard mask layer (e.g., silicon nitride, silicon carbide, etc.) can be formed over the dummy gate material. Then, a dummy gate structure is formed by patterning the hard mask and transferring the pattern to the dummy gate dielectric and dummy gate material using suitable lithography and etching techniques. The dummy gate structure can extend along multiple sides of the protruding fin and extend between the fins above the surface of the STI region 62. As described in more detail below, the dummy gate structure can be formed by Figure 1 A high-k metal gate (HKMG) gate structure 68 is shown instead. Figure 1 The HKMG gate structure 68 shown on the right (visible on top of the fin 58) is an example of an active HKMG gate structure that, for example, extends along the sidewalls of the fin 58 and over the portion of the fin 58 that protrudes above the STI 62, and Figure 1The HKMG gate structure 68 on the left in the middle is an example gate structure extending over the STI region 62, such as between adjacent fins. The materials used to form the dummy gate structure and the hard mask may be deposited using any suitable method, such as CVD, plasma enhanced CVD (PECVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD), etc. or by thermal oxidation of the semiconductor surface or a combination thereof.

[0018] For example, Figure 1 The source and drain regions 54 and spacers 72 of the FinFET 60 are shown to be formed to be self-aligned with the dummy gate structure. The spacers 72 can be formed by deposition and anisotropic etching of a spacer dielectric layer performed after the dummy gate patterning is completed. The spacer dielectric layer can include one or more dielectrics such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, etc. or a combination thereof. The anisotropic etching process removes the spacer dielectric layer from above the top of the dummy gate structure, leaving a spacer dielectric layer on the surface of the fin (such as the sidewalls of the dummy gate structure) along the sidewalls of the dummy gate structure. Figure 1 ) or the surface of the STI dielectric (as shown on the right side of Figure 1 A spacer 72 extending laterally on the portion of the housing 100 (shown on the left side of the housing 100).

[0019] The source and drain regions 54 are semiconductor regions that are in contact with the semiconductor fins 58. In some embodiments, the source and drain regions 54 may include heavily doped regions and relatively lightly doped drain extensions or LDD regions. Typically, the heavily doped regions are spaced apart from the dummy gate structure using spacers 72, while the LDD regions may be formed before forming the spacers 72, thus extending under the spacers 72, and in some embodiments, further extending to the portion of the semiconductor under the dummy gate structure. The LDD regions may be formed by, for example, implanting dopants (e.g., As, P, B, In, etc.) using an ion implantation process.

[0020] The source and drain regions 54 may include epitaxially grown regions. For example, after forming the LDD regions, the spacers 72 may be formed, and subsequently, heavily doped source and drain regions may be formed self-aligned with the spacers 72 by first etching the fins to form recesses and then depositing crystalline semiconductor material in the recesses by a selective epitaxial growth (SEG) process, which may fill the recesses and generally extend beyond the initial surface of the fins to form a raised source-drain structure, such as Figure 1 The crystalline semiconductor material can be an element (e.g., Si or Ge, etc.), or an alloy (e.g., Si 1-x C x or Si 1-x Ge xThe SEG process may use any suitable epitaxial growth method, such as vapor phase / solid phase / liquid phase epitaxy (VPE, SPE, LPE) or metal organic CVD (MOCVD) or molecular beam epitaxy (MBE), etc. An ion implantation process or a combination thereof may be performed in situ during SEG or after SEG to implant a high dose (e.g., about 10 14 cm -2 Up to 10 16 cm -2 ) dopants are introduced into the heavily doped source and drain regions 54.

[0021] The first interlayer dielectric (ILD) 76 (in Figure 1 ) is deposited over the structure. In some embodiments, a contact etch stop layer (CESL) (not shown) of a suitable dielectric (e.g., silicon nitride, silicon carbide, etc., or a combination thereof) may be deposited prior to depositing the ILD material. A planarization process (e.g., CMP) may be performed to remove excess ILD material and any remaining hard mask material from over the dummy gate to form a top surface, wherein the top surface of the dummy gate material is exposed and may be substantially coplanar with the top surface of the first ILD 76. The spacers 72 may then be formed by first removing the dummy gate structure using one or more etching techniques to create recesses between the corresponding spacers 72. Figure 1 The HKMG gate structure 68 is shown.

[0022] Next, a replacement gate dielectric layer 66 comprising another dielectric is deposited, followed by a replacement conductive gate layer 64 comprising one or more conductive materials to completely fill the recess. The gate dielectric layer 66 comprises, for example, a high-k dielectric material, such as an oxide and / or silicate of a metal (e.g., an oxide and / or silicate of Hf, Al, Zr, La, Mg, Ba, Ti and other metals), silicon nitride, silicon oxide, etc., or a combination thereof or a multilayer thereof. In some embodiments, the conductive gate layer 64 may be a multilayer metal gate stack comprising a barrier layer, a work function layer, and a gate fill layer formed continuously on top of the gate dielectric layer 66. Example materials for the barrier layer include TiN, TaN, Ti, Ta, etc., or a multilayer combination thereof. For p-type FETs, the work function layer may include TiN, TaN, Ru, Mo, Al, and for n-type FETs, the work function layer may include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr. Other suitable work function materials, combinations thereof, or multilayers thereof may be used. The gate filling layer filling the remaining portion of the groove may include a metal such as Cu, Al, W, Co, Ru, etc., or a combination thereof or a multilayer thereof. The material used to form the gate structure may be deposited by any suitable method, for example, CVD, PECVD, PVD, ALD, PEALD, electrochemical plating (ECP), chemical plating, etc. Excess portions of the gate structure layers 64 and 66 may be removed from above the top surface of the first ILD 76 using, for example, a CMP process. Figure 1 As shown, the resulting structure may be a substantially coplanar surface including exposed top surfaces of the first ILD 76 , the spacer layers 72 , and the remaining portions of the HKMG gate layers 66 and 64 embedded between the respective spacer layers 72 .

[0023] like Figure 1 As shown, the second ILD layer 78 may be deposited over the first ILD layer 76. In some embodiments, the insulating material forming the first ILD layer 76 and the second ILD layer 78 may include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), a low dielectric constant (low-k) dielectric, such as fluorosilicate glass (FSG), silicon oxycarbide (SiOCH), carbon-doped oxide (CDO), flowable oxide or porous oxide (e.g., xerogel / aerogel), etc., or a combination thereof. The dielectric material used to form the first ILD layer 76 and the second ILD layer 78 may be deposited using any suitable method, such as CVD, physical vapor deposition (PVD), ALD, PEALD, PECVD, SACVD, FCVD, spin coating, etc., or a combination thereof.

[0024] like Figure 1 As shown, the electrodes of the electronic devices formed in the substrate 50 can be electrically connected to the conductive features of the first interconnect level 100A using conductive connections (e.g., contacts 74) formed through the intermediate dielectric layer. Figure 1 In the example shown, contacts 74 are electrically connected to the source and drain regions 54 of FinFET 60. Typically, contacts 74 to the gate electrode are formed over STI regions 62. A separate gate electrode 64 (in Figure 1 ) shows such a contact. Photolithography techniques may be used to form the contact. For example, a patterned mask may be formed over the second ILD 78, and used to etch an opening extending through the second ILD 78 to expose a portion of the gate electrode above the STI region 62, and an opening further extending through the first ILD 76 and the CESL (not shown) liner below the first ILD 76 may be etched over the fin 58 to expose portions of the source and drain regions 54. In some embodiments, an anisotropic dry etching process may be used, in which etching is performed in two consecutive steps. The etchant used in the first step of the etching process has a higher etching rate for the materials of the first ILD layer 76 and the second ILD layer 78 relative to the etching rate of the materials used in the gate electrode 64 and the CESL, and the CESL may be lined with the top surface of the heavily doped regions of the source and drain regions 54. Once the first step of the etching process exposes the CESL, the second step of the etching process may be performed, in which the etchant may be switched to selectively remove the CESL.

[0025] In some embodiments, a conductive liner may be formed in the openings in the first ILD layer 76 and the second ILD layer 78. Subsequently, the openings are filled with a conductive filling material. The liner includes a barrier metal that is used to reduce the diffusion of conductive material from the contact 74 into the surrounding dielectric material. In some embodiments, the liner may include two barrier metal layers. The first barrier metal contacts the semiconductor material in the source region and the drain region 54, and may then chemically react with the heavily doped semiconductor in the source region and the drain region 54 to form a low resistance ohmic contact, after which the unreacted metal may be removed. For example, if the heavily doped semiconductor in the source region and the drain region 54 is silicon or a silicon germanium alloy semiconductor, the first barrier metal may include Ti, Ni, Pt, Co, other suitable metals, or alloys thereof. The second barrier metal layer of the conductive liner may additionally include other metals (e.g., TiN, TaN, Ta, or other suitable metals or alloys thereof). A conductive fill material (e.g., W, Al, Cu, Ru, Ni, Co, alloys thereof, combinations thereof, etc.) may be deposited over the conductive liner layer using any acceptable deposition technique (e.g., CVD, ALD, PEALD, PECVD, PVD, ECP, electroless plating, etc., or any combination thereof) to fill the contact opening. Next, a planarization process (e.g., CMP) may be used to remove any excess conductive material from over the surface of the second ILD 78. The resulting conductive plug extends into the first ILD layer 76 and the second ILD layer 78 and forms a conductive contact with the first ILD layer 76 and the second ILD layer 78. Figure 1 Contacts 74 are shown for physical and electrical connection of the electrodes of the illustrated tri-gate FinFET 60 electronic device. In this example, contacts to the electrodes over STI 62 and the electrodes over fin 58 are formed simultaneously using the same processing steps. However, in other embodiments, these two types of contacts may be formed separately.

[0026] like Figure 1 As shown, according to the back-end-of-line (BEOL) scheme adopted by the integrated circuit design, multiple interconnection levels can be formed, vertically stacked on the contacts 74 formed in the first ILD layer 76 and the second ILD layer 78. Figure 1 In the BEOL scheme shown, each interconnect level has similar components. However, it should be understood that other embodiments may utilize alternative integration schemes in which each interconnect level may use different components. For example, the contact 74 shown as a vertical connector may be extended to form a conductor that transmits current laterally.

[0027] The interconnect levels (e.g., interconnect levels 100A-100N) include conductive vias and lines embedded in an intermetal dielectric (IMD) layer. In addition to providing insulation between individual conductive elements, the IMD layer may also include one or more dielectric etch stop layers to control the etching process that forms the openings in the IMD layer. Typically, vias conduct current vertically and are used to electrically connect two conductive components located in vertically adjacent levels, while lines conduct current laterally and are used to distribute electrical signals and power within a level. Figure 1 In the BEOL scheme shown, conductive via 104A connects contact 74 to wire 108A, and at a subsequent level, the via connects the line on the level below the via to the line above the via (e.g., a pair of lines 108A and 108B can be connected through via 104B). Other embodiments may adopt different schemes. For example, via 104A can be omitted from the 100A level, and contact 74 can be configured to connect directly to M1 line 108A.

[0028] Still reference Figure 1 , the first interconnect level 100A can be formed using, for example, a dual damascene process flow. First, a dielectric stack for forming the IMD layer 110A can be deposited using one or more layers of the dielectric materials listed in the description of the first ILD layer 76 and the second ILD layer 78. In some embodiments, the IMD layer 110A includes an etch stop layer (not shown) located at the bottom of the dielectric stack. The etch stop layer includes one or more insulator layers (e.g., SiN, SiC, SiCN, SiCO, CN, combinations thereof, etc.) having an etch rate different from that of the material above. The techniques for depositing the dielectric stack of the IMD can be the same as those used to form the first ILD layer 76 and the second ILD layer 78.

[0029] The IMD layer 110A may be patterned using appropriate photolithography and etching techniques (e.g., anisotropic RIE using fluorocarbon chemistries) to form openings for vias and lines. The openings for vias may be vertical holes extending through the IMD layer 110A to expose the top conductive surface of the contact 74, and the openings for lines may be longitudinal grooves formed in the upper portion of the IMD layer. In some embodiments, the method for patterning holes and grooves in the IMD 110A utilizes a via-first scheme, wherein a first photolithography and etching process forms holes for vias, and a second photolithography and etching process forms grooves for lines. Other embodiments may use different methods, such as a trench-first scheme, or an incomplete via-first scheme, or a buried etch stop layer scheme. The etching technique may utilize multiple steps. For example, a first main etching step may remove portions of the dielectric material of the IMD layer 110A and stop on an etch stop dielectric layer. Then, an etchant may be switched to remove the etch stop layer dielectric material. The parameters of the various etching steps (eg, chemical composition, flow and pressure of gases, reactor power, etc.) can be adjusted to produce a tapered sidewall profile with a desired internal taper angle.

[0030] Several conductive materials may be deposited to fill the holes and trenches, forming the conductive vias 104A and lines 108A of the first interconnect level 100A. The openings may first be lined with a conductive diffusion barrier material and then completely filled with a conductive fill material deposited over the conductive diffusion barrier liner. In some embodiments, a thin conductive seed layer may be deposited over the conductive diffusion barrier liner to help initiate the ECP deposition step of completely filling the openings with the conductive fill material.

[0031] The diffusion barrier conductive liner in the via 104A and the line 108A may include one or more layers of TaN, Ta, TiN, Ti, Co, etc., or combinations thereof. The conductive fill layer in the via 104A and the line 108A may include a metal such as Cu, Al, W, Co, Ru, etc., or combinations thereof or multiple layers thereof. The conductive material used to form the conductive via 104A and the line 108A may be deposited by any suitable method, for example, CVD, PECVD, PVD, ALD, PEALD, electrochemical plating (ECP), electroless plating, etc. In some embodiments, the conductive seed layer may have the same conductive material as the conductive fill layer and be deposited using a suitable deposition technique (for example, CVD, PECVD, ALD, PEALD, PVD, etc.).

[0032] Any excess conductive material above IMD 110A outside of the opening may be removed by a planarization process (e.g., CMP) to form a top surface including a dielectric region of IMD 110A that is substantially coplanar with the conductive region of line 108A. The planarization step completes the fabrication of first interconnect level 100A including conductive vias 104A and conductive lines 108A embedded in IMD 110A, as shown in FIG. Figure 1 shown.

[0033] exist Figure 1 The interconnect level located vertically above the first interconnect level 100A is the second interconnect level 100B. In some embodiments, the structures of the respective interconnect levels (eg, the first interconnect level 100A and the second interconnect level 100B) may be similar. Figure 1 In the example shown, second interconnect level 100B includes conductive vias 104B and wires 108B embedded in insulating film IMD 110B having a flat top surface. The materials and processing techniques described above in the context of first interconnect level 100A may be used to form second interconnect level 100B and subsequent interconnect levels.

[0034] Subsequent interconnect levels may be formed above the first interconnect level 100A and the second interconnect level 100B, up to the Nth interconnect level 100N. In this example, the Nth interconnect level 100N may be formed using the same materials and methods as those used to form the first interconnect level 100A and the second interconnect level 100B. Figure 1 The ellipsis in indicates one or more additional interconnect levels that may be used to electrically connect between the second interconnect level 100B and the Nth interconnect level 100N.

[0035] The example electronic device (FinFET 60 ) and the example interconnect structure establishing connections to the electronic device are provided for illustrative purposes only, only to further explain the application of the present invention, and are not meant to limit the present invention in any way.

[0036] Figure 2 Shows Figure 1 A detailed cross-sectional view of region 101 of FIG. 1 shows the top of the Nth interconnect level 100N. Figure 2 , according to some embodiments, the Nth interconnect level 100N has been illustrated as an interconnect level over which a high resistance layer is formed, as discussed in more detail below. The conductive lines 108N and IMD 110N are illustrated for exemplary purposes only; it should be understood that the conductive lines 108N and IMD 110N may be placed at any metallization layer suitable for a particular design, for example, the fifth metallization layer.

[0037] Figure 3A first dielectric layer 202 including a first silicide barrier layer (SBL) 204 and a first dielectric sublayer 208, a high resistance layer 210, and a second dielectric layer 212 including a second SBL 214 and a second dielectric sublayer 218 are shown located above the conductive line 108N and the IMD 110N. The first silicide barrier layer (SBL) 204 and the second silicide barrier layer (SBL) 214 may be formed to reduce the formation of excess silicide during the subsequent formation of the conductive contact, which may be used to reduce leakage current through the path provided by the excess silicide, improve device performance, and serve as an etch stop layer. The first SBL 204 includes SiC, SiN, oxynitride, SiON, SiCN, SiOCN, SiOC, oxide, combinations thereof, and the like, and may be formed on the conductive line 108N and the IMD 110N by methods for forming such layers, such as chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), sputtering, and other methods known in the art. The first SBL 204 may be formed to a thickness in a range of about 80 angstroms to about 150 angstroms.

[0038] The first dielectric sublayer 208 and the second dielectric sublayer 218 may be formed as an etch stop for a subsequent etching process (e.g., to form a contact to the conductive line 108N and / or the high resistance layer 210). The first dielectric sublayer 208 and the second dielectric sublayer 218 include a dielectric material having an etch selectivity to a material of a subsequently formed dielectric layer (e.g., as described below with reference to Figure 5A The low-k dielectric layer 124 of the first dielectric layer 208 is formed by etching the first dielectric layer 208 and the second dielectric layer 218 at a faster rate than the material of the first dielectric layer 208 and the second dielectric layer 218. In some embodiments, the first dielectric layer 208 and the second dielectric layer 218 can be formed using precursors such as tetraethyl orthosilicate (TEOS) by methods for forming such layers, such as chemical vapor deposition (CVD), plasma enhanced CVD, sputtering, and other methods known in the art. The first dielectric layer 208 can be formed to a thickness in the range of about 150 angstroms to about 250 angstroms.

[0039] Further references Figure 3, the high resistance layer 210 includes TaN or TiN, a combination thereof, etc., and can be formed on the first dielectric sublayer 208 by methods such as CVD, PECVD, PVD, etc. The high resistance layer 210 can be formed to a thickness in the range of about 30 angstroms to about 60 angstroms. As discussed below, the high resistance layer 210 will be patterned to form a resistor (e.g., a high resistance path) in the circuit. Relative to designs where the resistor is located below the metallization layer (such as in the MEOL or FEOL region), the high resistance layer 210 formed in the BEOL region between the metallization layers can save, for example, up to 5% of the analog circuit design area and occupy about 5% of the analog die area. The second SBL 214 includes a material similar to the first SBL 204 and can be formed on the high resistance layer 210 by methods similar to the first SBL 214 described above. The second SBL 214 can be formed to a thickness in the range of about 80 angstroms to about 150 angstroms. The second dielectric sublayer 218 includes similar materials as the first dielectric sublayer 208 and can be formed on the high resistance layer 210 by similar methods as described above for the first dielectric sublayer 208. The second dielectric sublayer 218 can be formed to a thickness in a range of about 200 angstroms to about 400 angstroms.

[0040] Continue Figure 3 after, Figure 4A A patterned layer 300 is shown, and the patterned layer 300 includes a patterned first dielectric sublayer 308, a patterned high resistance layer 310, a patterned second SBL 314, and a patterned second dielectric sublayer 318 on the first SBL 204 in the logic area 500A / 500B and the high resistance area 600. In the logic area 500A and 500B, which can be used for the manufacture of metal lines, for example, the patterning process can remove the high resistance layer 210, the second SBL 214, and the second dielectric sublayer 218. The high resistance area 600 can be used for the manufacture of transistors, for example. The patterned high resistance layer 310, the patterned second SBL 314, and the patterned second dielectric sublayer 318 can remain after the patterning process. The patterned layer 300 can have a width W1 measured between the opposite sidewalls of the patterned second dielectric sublayer 318 in the range of about 1000 angstroms to about 20000 angstroms. For illustration purposes, the logic regions 500A / 500B are shown immediately adjacent to and on opposite sides of the high resistance region 600. In some embodiments, the high resistance region 600 may be spaced apart from the logic regions 500A / 500B as shown.

[0041] In some embodiments, the patterned layer 300 is patterned using a photolithography and etching process. For example, the photolithography and etching process may include forming and patterning a photoresist layer, which is formed and patterned on the second dielectric sublayer 218, optionally using one or more mask layers. The photoresist may be formed by spin coating, etc., and the photoresist may be exposed to light for patterning. The pattern of the photoresist corresponds to the patterned layer 300. One or more exposure steps may be applied to the photoresist to define the patterned layer 300. After one or more exposures, the photoresist is developed to form an opening through the photoresist to expose a portion of the underlying layer (such as the second dielectric sublayer 218 or the mask layer). The photoresist is then removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Once the photoresist is removed, the exposed portions of the first dielectric sublayer 208, the high resistance layer 210, the second SBL 214, and the second dielectric sublayer 218 are removed, such as by using one or more etching processes, such as by wet or dry etching with a two-step etching process. In the first etching step, the second SBL 214 and the second dielectric sub-layer 218 are etched, for example, for a duration of about 20 seconds to about 40 seconds, stopping on the high resistance layer 210. Then, in the second etching step, the high resistance layer 210 is etched for a duration in the range of about 20 seconds to about 40 seconds, stopping on the first dielectric sub-layer 208. In some embodiments, a portion of the first dielectric sub-layer 208 is recessed during the second etching step.

[0042] The etching may be followed by an acceptable stripping process, such as a wet stripping using NaOH and / or a cleaning process using HF, to remove the remaining photoresist / masking material and residues of the etched portions of the first dielectric sub-layer 208, the high-resistance layer 210, the second SBL 214, and the second dielectric sub-layer 218. The remaining portions of the first dielectric sub-layer 208, the high-resistance layer 210, the second SBL 214, and the second dielectric sub-layer 218 form the patterned layer 300.

[0043] Figure 4B Shows Figure 4A Detailed view of region 101 of FIG. 1, showing high resistance region 600. The thickness of patterned second dielectric sublayer 318 may be in the range of about 80 angstroms to about 150 angstroms. By the patterning process used to form patterned layer 300, for example, as described above with respect to Figure 4A The etching process described above can reduce the thickness of the patterned second dielectric sublayer 318 from the initial thickness of the second dielectric sublayer 218. Before the patterning process, the patterned second SBL 314 and the patterned high resistance layer 310 can have the same thickness as described above. Figure 3The second SBL 214 and the high-resistance layer 210 are depicted as having substantially similar thicknesses. Portions of the patterned first dielectric sublayer 308 not covered by the patterned high-resistance layer 310 may be recessed to a thickness in a range of about 80 angstroms to about 120 angstroms. Portions of the patterned first dielectric sublayer 308 covered by the patterned high-resistance layer 310 may remain at their original thickness in a range of about 150 angstroms to about 250 angstroms.

[0044] The patterned first dielectric layer 302 including the first SBL 204 and the portion of the patterned first dielectric sublayer 308 not covered by the patterned high resistance layer 310 may have a thickness T1 in the range of about 150 angstroms to about 250 angstroms. The patterned second dielectric layer 312 including the patterned second SBL 314 and the patterned second dielectric sublayer 318 may have a thickness T2 in the range of about 150 angstroms to about 250 angstroms. The ratio of thickness T1 to thickness T2 may be in the range of about 1:1. Thickness T1 being substantially the same as thickness T2, and being formed of the same or similar material, may allow for simultaneous formation of openings through a low-k dielectric layer subsequently formed over the patterned first dielectric layer 302 and the patterned second dielectric layer 312, which may be used to form conductive vias having substantially similar bottom surface areas and contact resistance uniformity.

[0045] The sidewall of the patterned high-resistance layer 310 forms an angle α with the bottom surface of the patterned high-resistance layer 310, and the angle α may be in the range of about 70° to about 90°, or in the range of about 87° to about 90°, such as about 90°. An angle α in the range of about 70° to about 90° may provide better uniformity of the patterned high-resistance layer 310. An angle α less than about 70° may cause poor uniformity in the patterned high-resistance layer 310. An angle α greater than about 90° may cause etching residues that may be located under the patterned high-resistance layer 310.

[0046] Figure 5A and Figure 5B Follow Figure 4A and Figure 4B , a low-k dielectric layer 124 is shown formed over the patterned layer 300. The low-k dielectric layer 124 may be an extremely low-k (ELK) dielectric layer. For example, the low-k dielectric layer 124 may have a k value in the range of about 2.4 to about 3.2. In some examples, the low-k dielectric layer 124 is or includes silicon, carbon, fluorine, oxygen, etc., or a combination thereof. The low-k dielectric layer 124 may be deposited using CVD, PECVD, ALD, PEALD, PVD, spin coating, etc., or a combination thereof. The thickness of the low-k dielectric layer 124 may be in the range of from about 1310 angstroms to about 1510 angstroms.

[0047] Figure 5AAlso shown is a mask over the low-k dielectric layer 124. In some embodiments, the mask includes a bottom mask 328 and a top mask 332. The bottom mask 328 may be an anti-reflective coating (ARC) located over the low-k dielectric layer 124. The anti-reflective coating improves optical resolution by reducing optical distortion associated with specular reflections, thin film interference, and / or standing waves, which may inhibit sharp feature definition during imaging of the photoresist material. In the example shown, the bottom mask or ARC 328 may include a nitrogen-free ARC (NFARC) (e.g., an organic ARC such as C x H x O x , or an inorganic ARC, such as SiC), to further improve feature definition during patterning of a subsequently formed photoresist layer. In some embodiments, the thickness of the bottom mask 328 can be in the range of about 290 angstroms to about 310 angstroms, such as about 300 angstroms. The bottom mask 328 can be formed by any suitable deposition technique, for example, CVD, PECVD, ALD, PEALD, PVD, spin coating, etc., or a combination thereof.

[0048] Further references Figure 5A , the top mask 332 may be a hard mask including materials such as TiN, TaN, etc., or combinations thereof. In some embodiments, the thickness of the top mask 332 may be in the range of about 370 angstroms to about 390 angstroms. The top mask 332 may be formed by any suitable deposition technique, for example, CVD, PECVD, ALD, PEALD, PVD, spin coating, etc., or combinations thereof.

[0049] In some embodiments, bottom mask 208 and top mask 332 are formed before planarizing the top surface of low-k dielectric layer 124 by a process such as CMP. Forming bottom mask 328 and top mask 332 over the top surface of low-k dielectric layer 124 before planarization can be used to subsequently form via openings (see below). Fig. 6A ), the via opening has substantially similar bottom profiles in the logic regions 500A and 500B and the high resistance region 600. When the via opening is subsequently formed due to planarization performed after forming the via opening, the thickness of the low-k dielectric layer 124 in the logic regions 500A and 500B will be substantially similar to the thickness of the low-k dielectric layer 124 in the high resistance region 600.

[0050] Additionally, the materials located above the patterned high-resistance layer 310 and above the conductive line 108N are similar and have similar thicknesses, thereby allowing the formation of an opening through the low-k dielectric layer 124 to the conductive line 108N and the patterned high-resistance layer while achieving substantially equal sized via openings. For example, as discussed above, the patterned second dielectric sub-layer 318 located above the patterned high-resistance layer 310 has a similar thickness and is formed of similar materials as the patterned first dielectric sub-layer 308 located above the conductive line 108N. The first dielectric sub-layer 208 is initially formed to be thicker than the second dielectric sub-layer 218. The above reference Figure 4A and Figure 4B The described patterning process thins the first dielectric sublayer 208 more than the second dielectric sublayer 218, so that the thickness of the patterned first dielectric sublayer 308 over the conductive line 108N is substantially similar to the thickness of the patterned second dielectric sublayer 318 over the patterned high-resistance layer 310. In some embodiments, the difference between the thickness of the patterned first dielectric sublayer 308 and the thickness of the patterned second dielectric sublayer 318 can be less than about 10 angstroms, and the ratio of the thickness of the patterned first dielectric sublayer 308 to the thickness of the patterned second dielectric sublayer 318 can be in a range of about 0.9 to about 1.1.

[0051] Fig. 6A Trench openings 140 and 240 are shown extending through the top mask 332, the bottom mask 328, and the low-k dielectric layer 124 in accordance with some embodiments. The terms "trench" and "via" as used herein may broadly cover any topographical features suitable for providing a conductive or contact path extending horizontally and / or vertically within a semiconductor device, such as an "opening," "hole," "recess," "plug," and the like. The trench opening 140 may be formed in the high-resistance region 600 above the patterned high-resistance layer 310, and the trench opening 240 may be formed in the logic regions 500A and 500B above the conductive line 108N. The low-k dielectric layer 124 may be patterned using a photoresist (not shown) over the top mask 332 as an etch mask to etch the trench openings 140 and 240. Any acceptable etching technique may be used, for example, as previously described with reference to FIG. Figure 1 An RIE process for forming vias and lines, such as via 104B and conductive line 108B, is described.

[0052] The etching process may include one or more etching steps. For example, a first etching step may be performed using an etchant to remove exposed portions of the top mask 332 and the bottom mask 328, and a second etching step may be performed using an etchant that removes portions of the low-k dielectric layer 124. In some embodiments, the first etching step and the second etching step may be the same step.

[0053] Fig. 6A Also shown are via openings 144 and 244 in the bottom surfaces of the trench openings 140 and 240 , respectively. Figure 6B Shows Fig. 6A Detailed view of region 102 of FIG. 100 is shown, showing a via opening 144 in high resistance region 600. Via openings 144 and 244 may be formed in logic regions 500A and 500B and high resistance region 600 using a patterned mask (e.g., a patterned photoresist layer and / or one or more patterned mask layers) that defines a via pattern that is substantially aligned with a trench pattern, but has a narrower lateral width than the trench pattern used as a mask, followed by an appropriate etching process. Via opening 144 extends through patterned first dielectric sublayer 308 and first SBL 204 to a top surface of patterned high resistance layer 310, and via opening 244 extends through patterned first dielectric sublayer 308 and first SBL 204 to a top surface of conductive line 108N. Via openings 144 and 244 may be formed by an etching process using an etchant gas mixture such as CH4, O2, N2, or the like, or a combination thereof, and a plasma power source power in a range of about 100 to about 500 Watts. The via opening 244 can be formed using the patterned first dielectric sublayer 308 and the first SBL 204 as an etch stop, and the via opening 144 can be formed using the patterned second dielectric sublayer 318 and the patterned second SBL 314 as an etch stop, which may be useful for controlling the depth of the subsequently formed conductive vias into the wire 108N and the patterned high resistance layer 310, respectively. The etching process can be an etching with a duration in the range of about 30 seconds to about 50 seconds. In some embodiments, the via openings 144 and 244 are formed simultaneously with the same etching process. The patterned mask is then removed using any suitable stripping process. It should be understood that although the trench first and via last (TFVL) method is discussed herein, the concepts of the present invention may also be applied to the via first and trench last (VFTL) method.

[0054] In some embodiments, the first SBL 204 in the logic regions 500A and 500B has substantially the same thickness as the patterned second SBL 314 in the high resistance region 600, the patterned first dielectric sublayer 308 of the logic regions 500A and 500B has substantially the same thickness as the patterned second dielectric sublayer 318 in the high resistance region 600, and the same etching process is performed to etch the via opening 144 and the via opening 244. The via opening 144 and the via opening 244 can be controlled to have substantially similar bottom surface areas by using similar materials, similar thicknesses, and the same etching process. Because the via openings 144 and 244 are formed to have substantially similar bottom surface areas, the conductive vias subsequently formed in the via openings 144 and 244 can have substantially similar resistances, which can be useful for uniformity of contact resistance and device performance.

[0055] The via opening 144 may extend into the patterned high-resistance layer 310 at a depth D1 in a range of about 10 angstroms to about 40 angstroms, which may provide a subsequently formed conductive via with a lower contact resistance, resulting in improved device performance. A depth D1 of less than about 10 angstroms may result in poor connection between a subsequently formed via and the patterned high-resistance layer 310. A depth D1 of greater than about 40 angstroms may result in the via opening 144 passing through the lower surface of the patterned high-resistance layer 310, which may result in poor device function.

[0056] Fig. 7A and Figure 7B Follow Fig. 6A and Figure 6B , and a seed layer or barrier layer 348 is shown formed on the exposed surfaces of the via openings 144 and 244, the trench openings 140 and 240, the bottom mask 328, and the top mask 332. The barrier layer 348 can be a conductive diffusion barrier liner including Ti or TiN, and can have a thickness in the range of about 30 angstroms to about 50 angstroms. The material used to form the barrier layer 348 can be deposited by any suitable method, for example, CVD, PECVD, PVD, ALD, PEALD, electrochemical plating (ECP), electroless plating, etc.

[0057] Fig. 8A and Figure 8B Follow Fig. 7A and Figure 7B, showing the conductive fill material 400 located above the barrier layer 348. In the logic regions 500A and 500B, the conductive fill material 400 combines with the barrier layer 348 to form the conductive line 440 in the trench opening 240 and the conductive via 444 in the via opening 244. The conductive via 444 can contact the top surface of the conductive line 108N. In the high resistance region 600, the conductive fill material 400 combines with the barrier layer 348 to form the conductive line 340 in the trench opening 140 and the conductive via 344 in the via opening 144. In some embodiments, the materials and processing techniques used to form the conductive vias 344 and 444 and the conductive lines 340 and 440 can be the same as those used to form vias and lines at the above-described interconnect levels (e.g., 104A and 108A). Because via openings 144 and 244 are formed to have substantially similar bottom surface areas, conductive vias 344 and 444 may have substantially similar resistances due to being formed in via openings 144 and 244, respectively, which may have the same resistances as described above with respect to Fig. 6A and Figure 6B The substantially similar bottom surface area described above. This uniformity of contact resistance of conductive vias 344 and 444 may be useful for device performance. In addition, as described below with respect to Fig.9A As described, the via openings 144 and 244 are formed before the top surface of the low-k dielectric layer 124 is planarized by a process such as CMP. During the formation of the via openings 144 and 244, the thickness of the low-k dielectric layer 124 in the logic regions 500A and 500B will be substantially similar to the thickness of the low-k dielectric layer 124 in the high resistance region 600, which may be useful in obtaining substantially similar bottom surface areas of the via openings 144 and 244.

[0058] Fig.9A The top of the conductive fill material 400, the top of the low-k dielectric layer 124, the top of the barrier layer 348, the bottom mask 328, and the top mask 332 are shown removed. A planarization process such as CMP may be performed to form a substantially planar top surface of the low-k dielectric layer 124 and the conductive lines 340 and 440. Subsequent interconnect levels may be formed on the top surfaces of the low-k dielectric layer 124 and the conductive lines 340 and 440.

[0059] Fig. 9B Shows Fig.9ADetailed view of region 102 of the high resistance region 600. The high resistance region 600 includes two conductive vias 344 that extend into the patterned high resistance layer 310. The two conductive vias 344 can be separated by a width W2 in the range of about 1000 angstroms to 10,000 angstroms. The electrical connection between the two conductive vias 344 through the patterned high resistance layer 310 can have a resistance in the range of about 500 ohm / sq to about 900 ohm / sq. Forming a connection through the patterned high resistance layer 310 in the high resistance region 600 can save up to 5% of the analog circuit design area compared to a design in which an equivalent connection through a resistor is formed below the metallization layer.

[0060] Fig. 10A follow Fig.9A , showing the N+1th interconnect level 100N+1 located above the low-k dielectric layer 124 and the conductive lines 340 and 440. In some embodiments, the structure of the N+1th interconnect level 100N+1 can be similar to other interconnect levels (e.g., the first interconnect level 100A and the second interconnect level 100B). Fig. 10A In the example shown, the N+1th interconnect level 100N+1 includes a conductive via 104N+1 and a conductive line 108N+1 embedded in an insulating film IMD 110N+1 having a flat top surface. The materials and processing techniques described above in the context of the first interconnect level 100A and subsequent interconnect levels can be used to form the N+1th interconnect level 100N+1.

[0061] In some embodiments, Fig. 10A As shown, the conductive via 104N+1 and the conductive line 108N+1 form an electrical connection between the conductive lines 108N in the Nth interconnect level through the patterned high resistance layer 310. The electrical connection can be further extended to electrically couple the patterned high resistance layer 310 to gate electrodes, source / drain regions, capacitors, other resistors, other circuits, etc. For example, in some embodiments, the electrical connection can be connected to a device such as a FinFET 60 (see Figure 1 ) of the transistor gate electrode 64 (eg, Figure 1 The replacement conductive gate layer shown) is electrically connected to a voltage source (not shown). Forming an electrical connection between the gate electrode 64 of the transistor and the voltage source of the second transistor may be useful for current limiting to reduce potential damage to the transistor. An electrical connection may also be formed through the patterned high resistance layer 310, which can be used to form, for example, a voltage divider. A voltage divider is a circuit that converts a large voltage into a smaller voltage. Using two series resistors and an input voltage, an output voltage can be created that is a fraction of the input voltage.

[0062] Fig. 10BThe conductive vias 344 and 444 are shown to be physically and electrically connected by the conductive line 342 according to some embodiments. Fig.9A Conductor 342 is formed by a similar process to conductors 340 and 440 shown in FIG. 1 , wherein trench openings 240 and 140 (see FIG. 1 ) are formed by a similar process to conductors 340 and 440 shown in FIG. Fig. 7A ) is formed to connect the through-hole openings 144 and 244 (see Fig. 7A ). Conductor 342 forms an electrical connection between conductors 108N in the Nth interconnect level through patterned high resistance layer 310. Similar to the above discussion, the electrical connection can be further extended, for example, to electrically connect gate electrodes, source / drain regions, capacitors, other circuits, etc.

[0063] The above disclosure may provide advantages. By placing electrical connections in the BEOL region between metallization layers above circuits such as transistors and / or resistors through the patterned high resistance layer 310, up to 5% of the analog circuit design area may be saved, for example, relative to designs where the high resistance layer is located below the metallization layer (such as the middle-end of line (MEOL) region or the front-end of line (FEOL) region), and about 5% of the analog die area. Although the present invention is Fig. 10A Forming electrical connections through patterned high resistance layer 310 is discussed in the context of the illustrated example of electrical connections between conductive lines 108N+1 in the Nth interconnect level, but other embodiments may utilize aspects of the present invention for other configurations of electrical connections.

[0064] Furthermore, using similar dielectric layers above and below the high resistance layer can be used to control the bottom surface area of ​​the conductive vias to be substantially similar, resulting in uniform contact resistance in the conductive vias, which can be useful for device performance.

[0065] According to an embodiment, a semiconductor structure includes: a first dielectric layer located above a first conductive line and a second conductive line; a high resistance layer located above a first portion of the first dielectric layer, a second portion of the first dielectric layer having no high resistance layer, the first portion of the first dielectric layer having a first thickness, and the second portion of the first dielectric layer having a second thickness less than the first thickness; a second dielectric layer located on the high resistance layer; a low-k dielectric layer located above the second dielectric layer and the second portion of the first dielectric layer, the low-k dielectric layer extending along the sidewalls of the high resistance layer and the second dielectric layer; a first conductive via extending through the low-k dielectric layer and the second dielectric layer, the first conductive via extending into the high resistance layer; and a second conductive via extending through the low-k dielectric layer and the first dielectric layer to the first conductive line. In an embodiment, the thickness of the second dielectric layer is substantially similar to the second thickness of the first dielectric layer. In an embodiment, the depth of the first conductive via extending into the high resistance layer is in the range of 10 angstroms to 40 angstroms. In an embodiment, the high resistance layer includes TiN or TaN. In an embodiment, the structure further includes a third conductive line, wherein the third conductive line is electrically inserted between the first conductive via and the second conductive via. In an embodiment, the second dielectric layer includes a silicide barrier layer (SBL) and a dielectric sublayer located above the SBL. In an embodiment, the dielectric sublayer includes SiO2, and the SBL includes SiC. In an embodiment, the dielectric sublayer has a thickness in a range of 80 angstroms to 150 angstroms, and the SBL has a thickness in a range of 80 angstroms to 150 angstroms.

[0066] According to another embodiment, a semiconductor structure includes: a logic region, including a first conductive line, a first portion of a first dielectric layer located above the first conductive line, a first portion of a low-k dielectric layer located above the first dielectric layer, and a first conductive via extending through the first portion of the low-k dielectric layer and the first dielectric layer, the first portion of the first dielectric layer having a first thickness, and the first conductive via being in physical contact with the first conductive line; and a high resistance region, the high resistance region including a second portion of the first dielectric layer; a high resistance layer located on the second portion of the first dielectric layer; a second dielectric layer located on the high resistance layer, the second dielectric layer having a second thickness, wherein the second dielectric layer has the same material structure as the first portion of the first dielectric layer above the first conductive line; a second portion of the low-k dielectric layer located on the second dielectric layer; and a second conductive via extending through the second portion of the low-k dielectric layer and the second dielectric layer, the second conductive via extending below a top surface of the high resistance layer. In an embodiment, the first portion of the first dielectric layer includes a first silicide barrier layer (SBL) and a first dielectric sublayer located above the first SBL, and the second dielectric layer includes a second SBL and a second dielectric sublayer located above the second SBL. In an embodiment, the first SBL and the second SBL include a first same material, wherein the first dielectric sublayer and the second dielectric sublayer include a second same material. In an embodiment, the first dielectric sublayer and the second dielectric sublayer have a third thickness, wherein the first SBL and the second SBL have a fourth thickness. In an embodiment, the third thickness is in a range of 150 angstroms to 250 angstroms, and the fourth thickness is in a range of 150 angstroms to 250 angstroms. In an embodiment, a ratio of the first thickness to the second thickness is in a range of 0.9 to 1.1.

[0067] According to yet another embodiment, a method of forming a semiconductor structure includes: forming a first dielectric layer over an interconnect layer, the interconnect layer including a conductive line; forming a high-resistance layer on the first dielectric layer; forming a second dielectric layer on the high-resistance layer; patterning the second dielectric layer and the high-resistance layer, wherein the patterning recesses the first dielectric layer over the conductive line, wherein after the patterning, the first dielectric layer over the conductive line has a first thickness, wherein the first dielectric layer under the high-resistance layer has a second thickness greater than the first thickness; forming a low-k dielectric layer over the second dielectric layer and the first dielectric layer, the low-k dielectric layer extending over a top surface and sidewalls of the first dielectric layer; forming a first opening through the low-k dielectric layer and the second dielectric layer, the first opening extending into the high-resistance layer; forming a conductive material in the first opening; and planarizing the low-k dielectric layer and the conductive material. In an embodiment, the ratio of the second thickness to the first thickness is in the range of 0.9 to 1.1. In an embodiment, forming the first dielectric layer includes forming a first dielectric sublayer and a second dielectric sublayer above the first dielectric sublayer, wherein forming the second dielectric layer includes forming a third dielectric sublayer and a fourth dielectric sublayer above the third dielectric sublayer, wherein the first dielectric sublayer has substantially the same thickness as the third dielectric sublayer, wherein the second dielectric sublayer is thicker than the fourth dielectric sublayer. In an embodiment, the method further includes forming a second opening through the low-k dielectric layer and the first dielectric layer, the first dielectric layer being in physical contact with the low-k dielectric layer, wherein forming the conductive material includes forming the conductive material in the second opening. In an embodiment, forming the first opening and forming the second opening are performed simultaneously. In an embodiment, the method further includes forming a trench in the low-k dielectric layer, wherein the trench extends from the first opening to the second opening, wherein forming the conductive material includes forming the conductive material in the trench.

[0068] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that this equivalent configuration does not deviate from the spirit and scope of the present invention, and that they can make multiple changes, substitutions and changes herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure comprising: a first interconnect layer, located above the transistors; a second interconnect layer, located above the first interconnect layer, the second interconnect layer comprising a first conductive line and a second conductive line; a first dielectric layer, located above the first conductive line and the second conductive line; a high resistance layer located above a first portion of the first dielectric layer, a second portion of the first dielectric layer being free of the high resistance layer, the first portion of the first dielectric layer having a first thickness, and the second portion of the first dielectric layer having a second thickness less than the first thickness; a second dielectric layer, located on the high resistance layer; a low-k dielectric layer located over the second dielectric layer and the second portion of the first dielectric layer, the low-k dielectric layer extending along sidewalls of the high-resistance layer and the second dielectric layer; a first conductive via extending through the low-k dielectric layer and the second dielectric layer, the first conductive via extending into the high resistance layer; as well as A second conductive via extends through the low-k dielectric layer and the first dielectric layer to the first conductive line.

2. The semiconductor structure according to claim 1, wherein: The thickness of the second dielectric layer is the same as the second thickness of the first dielectric layer.

3. The semiconductor structure according to claim 1, wherein: The first conductive via extends into the high resistance layer to a depth ranging from 10 angstroms to 40 angstroms.

4. The semiconductor structure according to claim 1, wherein: The high resistance layer includes TiN or TaN.

5. The semiconductor structure according to claim 1, further comprising: A third conductive line is disposed in the low-k dielectric layer, wherein the third conductive line is electrically inserted between the first conductive via and the second conductive via.

6. The semiconductor structure according to claim 1, wherein: The second dielectric layer includes a silicide barrier layer and a dielectric sublayer located above the silicide barrier layer.

7. The semiconductor structure according to claim 6, wherein: The dielectric sublayer includes SiO2, and the silicidation barrier layer includes SiC.

8. The semiconductor structure according to claim 6, wherein: The dielectric sublayer has a thickness in a range of 80 angstroms to 150 angstroms, and the silicide barrier layer has a thickness in a range of 80 angstroms to 150 angstroms.

9. A semiconductor structure comprising: a first interconnect layer, located above the transistors; A second interconnect layer, located above the first interconnect layer, the second interconnect layer includes a first conductive line, and the first interconnect layer and the second interconnect layer span across the logic area and the storage area; Logical area, including: the first conductive wire; a first portion of a first dielectric layer, located above the first conductive line, the first portion having a first thickness; a first portion of a low-k dielectric layer overlying the first dielectric layer; and a first conductive via extending through the first portion of the low-k dielectric layer and the first dielectric layer, the first conductive via being in physical contact with the first conductive line; and A high resistance region, the high resistance region comprising: a second portion of the first dielectric layer; a high resistance layer disposed on the second portion of the first dielectric layer; a second dielectric layer, located on the high resistance layer, the second dielectric layer having a second thickness, wherein the second dielectric layer has the same material structure as the first portion of the first dielectric layer above the first conductive line; a second portion of the low-k dielectric layer located on the second dielectric layer; and A second conductive via extends through the second portion of the low-k dielectric layer and the second dielectric layer, the second conductive via extending below a top surface of the high-resistance layer.

10. The semiconductor structure according to claim 9, wherein: The first portion of the first dielectric layer includes a first silicide barrier layer and a first dielectric sublayer over the first silicide barrier layer, and the second dielectric layer includes a second silicide barrier layer and a second dielectric sublayer over the second silicide barrier layer.

11. The semiconductor structure according to claim 10, wherein: The first silicide blocking layer and the second silicide blocking layer include a first same material, wherein the first dielectric sublayer and the second dielectric sublayer include a second same material.

12. The semiconductor structure according to claim 10, wherein: The first dielectric sublayer and the second dielectric sublayer have a third thickness, and wherein the first silicide barrier layer and the second silicide barrier layer have a fourth thickness.

13. The semiconductor structure according to claim 12, wherein: The third thickness is in a range of 80 angstroms to 150 angstroms, and the fourth thickness is in a range of 80 angstroms to 150 angstroms.

14. The semiconductor structure according to claim 9, wherein: A ratio of the first thickness to the second thickness is in a range of 0.9 to 1.

1.

15. A method of forming a semiconductor structure, the method comprising: forming a first interconnect layer over the transistor; forming a second interconnect layer over the first interconnect layer; forming a first dielectric layer over the second interconnect layer, the second interconnect layer comprising conductive lines; forming a high resistance layer on the first dielectric layer; forming a second dielectric layer on the high resistance layer; patterning the second dielectric layer and the high resistance layer, wherein the patterning recesses the first dielectric layer above the conductive line, wherein after the patterning, the first dielectric layer above the conductive line has a first thickness, and wherein the first dielectric layer below the high resistance layer has a second thickness greater than the first thickness; forming a low-k dielectric layer over the second dielectric layer and the first dielectric layer, the low-k dielectric layer extending over a top surface and sidewalls of the first dielectric layer; forming a first opening through the low-k dielectric layer and the second dielectric layer, the first opening extending into the high resistance layer; forming a conductive material in the first opening; and The low-k dielectric layer and the conductive material are planarized.

16. The method according to claim 15, wherein: A ratio of the second thickness to the first thickness is in a range of 0.9 to 1.

1.

17. The method according to claim 15, wherein: Forming the first dielectric layer includes forming a first dielectric sublayer and a second dielectric sublayer over the first dielectric sublayer, wherein forming the second dielectric layer includes forming a third dielectric sublayer and a fourth dielectric sublayer over the third dielectric sublayer, wherein the first dielectric sublayer has the same thickness as the third dielectric sublayer, and wherein the second dielectric sublayer is thicker than the fourth dielectric sublayer.

18. The method according to claim 15, further comprising: A second opening is formed through the low-k dielectric layer and the first dielectric layer, the first dielectric layer being in physical contact with the low-k dielectric layer, wherein forming the conductive material includes forming the conductive material in the second opening.

19. The method according to claim 18, wherein: The forming of the first opening and the forming of the second opening are performed simultaneously.

20. The method of claim 18, further comprising: A trench is formed in the low-k dielectric layer, wherein the trench extends from the first opening to the second opening, wherein forming the conductive material includes forming the conductive material in the trench.

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