Non-volatile memory device and manufacturing method thereof

Abstract

The present invention discloses a non-volatile memory device and a method for manufacturing the same, wherein the non-volatile memory device includes a substrate, a stacked structure, an anti-fuse gate, a gate dielectric layer, a first doped region, and a second doped region. The stacked structure is formed on the substrate and includes a floating gate, a select logic gate, a logic gate dielectric layer, and an interpolysilicon dielectric layer, wherein the select logic gate is disposed on the floating gate, the logic gate dielectric layer is disposed between the floating gate and the substrate, and the interpolysilicon dielectric layer is disposed between the floating gate and the select logic gate. The anti-fuse gate is also disposed on the substrate, and the gate dielectric layer is disposed between the anti-fuse gate and the substrate. A first doped region is formed in the substrate on one side of the floating gate. A second doped region is formed in the substrate between the floating gate and the anti-fuse gate, and a channel region is formed between the second doped region and the first doped region.

Description

Technical Field

[0001] The present invention relates to a memory element, and more particularly to a non-volatile memory element and a manufacturing method thereof. Background Art

[0002] Non-volatile memory devices have become a widely used memory device in personal computers and electronic devices due to their advantages of being able to store, read, and erase data multiple times and not losing the stored data even after a power outage.

[0003] Non-volatile memory devices can generally be categorized into erasable programmable read-only memory (EPROM), one-time programmable (OTP) read-only memory, and multiple-time programmable (MTP) memory devices. STP is more convenient because it allows for noise erasure and data writing after the memory leaves the factory, meaning that data can be written to the memory by the user according to the memory's configuration environment.

[0004] To meet the trend toward smaller devices and higher integration, current single-time programmable read-only memories (STPROMs) employ a two-transistor (2T) structure, with a write transistor connected in series to one side of an antifuse (AF) transistor. During programming, a high voltage is applied to the antifuse transistor, breaking down the gate dielectric layer and turning the antifuse "on." Conversely, when no voltage is applied, the antifuse is "off," achieving the desired programming behavior.

[0005] To comply with standard logic low-voltage manufacturing processes and design guidelines, conventional transistors and anti-fuse transistors are manufactured using the same logic low-voltage process, with the same gate dielectric thickness. However, the transistors used for writing typically need to withstand high voltages, so external circuitry is required to reduce the voltage to prevent breakdown. This increases the overall device area, hindering the development of high-density integration. Summary of the Invention

[0006] The present invention provides a non-volatile memory element which does not require an external circuit for voltage reduction, thereby increasing the element integration and improving the performance of the non-volatile memory element.

[0007] The present invention further provides a non-volatile memory device that can shut down the entire device to ensure normal device performance when the anti-fuse gate is miswritten or has excessive leakage due to a defect.

[0008] The present invention further provides a method for manufacturing a non-volatile memory element, which can be manufactured using a standard logic low voltage manufacturing process to produce a non-volatile memory element having the above-mentioned function.

[0009] A non-volatile memory device according to the present invention includes a substrate, a stacked structure, an antifuse gate, a gate dielectric layer, a first doped region, and a second doped region. The stacked structure is formed on the substrate and includes a floating gate, a select logic gate, a logic gate dielectric layer, and an interpolysilicon dielectric layer. The select logic gate is disposed on the floating gate, the logic gate dielectric layer is disposed between the floating gate and the substrate, and the interpolysilicon dielectric layer is disposed between the floating gate and the select logic gate. The antifuse gate is also disposed on the substrate, and the gate dielectric layer is disposed between the antifuse gate and the substrate. A first doped region is formed in the substrate on one side of the floating gate. A second doped region is formed in the substrate between the floating gate and the antifuse gate, and a channel region is formed between the second doped region and the first doped region.

[0010] Another non-volatile memory device of the present invention includes a substrate, at least one first doped region formed within the substrate, a plurality of stacked structures, a plurality of second doped regions, a plurality of antifuse gates, and a gate dielectric layer. The stacked structures are formed on the substrate and connected in series via the first doped region. Each stacked structure includes a floating gate, a select logic gate, a logic gate dielectric layer, and an interpolysilicon dielectric layer. The select logic gate is disposed on the floating gate, the logic gate dielectric layer is disposed between the floating gate and the substrate, and the interpolysilicon dielectric layer is disposed between the floating gate and the select logic gate. A second doped region is formed within the substrate on one side of each floating gate, and a channel region is formed between one of the second doped regions and the first doped region. An antifuse gate is disposed on the substrate and connected in series with one of the stacked structures via a second doped region. The gate dielectric layer is disposed between each antifuse gate and the substrate.

[0011] In the above embodiment of the present invention, the floating gate includes a polysilicon or metal gate.

[0012] In the above embodiment of the present invention, the selection logic gate includes a polysilicon gate.

[0013] In the above embodiment of the present invention, the material of the logic gate dielectric layer and the material of the gate dielectric layer may be the same, and the thickness of the logic gate dielectric layer and the thickness of the gate dielectric layer may also be the same.

[0014] In the above embodiment of the present invention, the non-volatile memory device may further include offset spacers located on sidewalls of the floating gate and sidewalls of the anti-fuse gate.

[0015] In the above embodiment of the present invention, the non-volatile memory device may further include a main spacer located on a sidewall of the stack structure.

[0016] In the above embodiment of the present invention, the non-volatile memory device may further include a metal silicide layer formed on top surfaces of the first doped region, the second doped region, the anti-fuse gate, and the select logic gate.

[0017] In the above embodiment of the present invention, the first doped region may be coupled to a bit line.

[0018] A method for manufacturing a non-volatile memory device according to the present invention includes forming a logic gate dielectric layer on a substrate; forming a first conductor layer on the logic gate dielectric layer; patterning the first conductor layer and the logic gate dielectric layer to form at least one floating gate and at least one anti-fuse gate; forming a first doped region and a second doped region in the substrate on either side of the floating gate, wherein the second doped region is located between the floating gate and the anti-fuse gate to connect the floating gate and the anti-fuse gate in series; then forming an interpolysilicon dielectric layer entirely on the substrate to cover the floating gate and the anti-fuse gate, and then forming a second conductor layer on the interpolysilicon dielectric layer; and patterning the second conductor layer and the interpolysilicon dielectric layer to form a select logic gate located above the floating gate. The select logic gate, the interpolysilicon dielectric layer, the floating gate, and the logic gate dielectric layer form a stacked structure.

[0019] In yet another embodiment of the present invention, the material of the first conductive layer includes polysilicon or metal.

[0020] In yet another embodiment of the present invention, the material of the second conductive layer includes polysilicon.

[0021] In yet another embodiment of the present invention, after patterning the first conductive layer and the logic gate dielectric layer, offset spacers may be formed on sidewalls of the floating gate and the anti-fuse gate.

[0022] In yet another embodiment of the present invention, after patterning the second conductive layer and the inter-polysilicon dielectric layer, main spacers may be formed on the sidewalls of the stacked structure.

[0023] In another embodiment of the present invention, after patterning the second conductor layer and the polysilicon interlayer dielectric layer, a silicide metal layer can be formed on the top surface of the first doped region, the top surface of the second doped region, the top surface of the anti-fuse gate and the top surface of the selection logic gate.

[0024] In the above embodiment of the present invention, the materials of the logic gate dielectric layer and the gate dielectric layer independently include silicon oxide or high-k dielectric material.

[0025] In the above embodiment of the present invention, the material of the inter-polysilicon dielectric layer includes oxide or nitride.

[0026] Based on the above, the present invention stacks materials with different dielectric constants to increase parasitic capacitance, making the stacked structure capable of withstanding high voltages. By connecting this high-voltage-resistant structure in series with the antifuse gate, device programming can be achieved without the need for external voltage-stepping circuitry, thereby increasing device integration. Furthermore, if the antifuse gate is accidentally written or if a defect causes excessive leakage, the stacked structure can shut down the entire device, ensuring normal device performance.

[0027] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a cross-sectional schematic diagram of a non-volatile memory device according to a first embodiment of the present invention;

[0029] Figure 2 is a cross-sectional schematic diagram of a non-volatile memory device according to a second embodiment of the present invention;

[0030] Figures 3A to 3G FIG. 4 is a schematic diagram of a manufacturing process of a non-volatile memory device according to a third embodiment of the present invention.

[0031] Explanation of symbols

[0032] 100, 300: base

[0033] 102, 322: stacked structure

[0034] 104, 310: anti-fuse gate

[0035] 106: gate dielectric layer

[0036] 108, 314a: first doped region

[0037] 110, 314b: second doped region

[0038] 112, 308: floating gate

[0039] 114, 320: Select logic gate

[0040] 116, 302: logic gate dielectric layer

[0041] 118, 316: inter-polysilicon dielectric layer

[0042] 120: Channel area

[0043] 122, 312: offset spacer

[0044] 124, 324: Main spacer

[0045] 126, 326: silicide metal layer

[0046] 128: bit line

[0047] 200, 306: Isolation structure

[0048] 304: first conductor layer

[0049] 318: Second conductor layer DETAILED DESCRIPTION

[0050] Some embodiments are listed below and described in detail with reference to the accompanying drawings, but the embodiments provided are not intended to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn to their original size. For ease of understanding, the same elements in the following description will be indicated by the same symbols. In addition, the terms "include", "including", "have", etc. used in the text are all open terms; that is, they mean including but not limited to. Moreover, the directional terms mentioned in the text, such as "up", "down", etc., are only used to refer to the directions of the drawings. Therefore, the directional terms used are used for illustration, not for limiting the present invention.

[0051] Figure 1 is a cross-sectional schematic diagram of a non-volatile memory device according to a first embodiment of the present invention.

[0052] Please refer to Figure 1The non-volatile memory device of the first embodiment includes a substrate 100, a stacked structure 102, an anti-fuse gate 104, a gate dielectric layer 106, a first doped region 108, and a second doped region 110. The stacked structure 102 and the anti-fuse gate 104 are both formed on the substrate 100 and connected in series via the second doped region 110. The stacked structure 102 includes a floating gate 112, a select logic gate 114, a logic gate dielectric layer 116, and an inter-polysilicon dielectric layer 118. The select logic gate 114 is disposed above the floating gate 112, the logic gate dielectric layer 116 is disposed between the floating gate 112 and the substrate 100, and the inter-polysilicon dielectric layer 118 is disposed between the floating gate 112 and the select logic gate 114. Because the substrate 100, logic gate dielectric layer 116, floating gate 112, interpolysilicon dielectric layer 118, and select logic gate 114 each have different dielectric constants, similar to a SONOS device, which increases parasitic capacitance, the stacked structure 102 itself is capable of withstanding high voltages. In one embodiment for logic consumer electronics applications, the stacked structure 102 can withstand a maximum high voltage of 11V; in another embodiment, the stacked structure 102 can withstand a maximum high voltage of 8V.

[0053] The anti-fuse gate 104 can be a polysilicon or metal (such as tungsten, titanium, cobalt, etc.) gate, and can be used with silicon oxide or high-k dielectric materials as the gate dielectric layer 106, wherein high-k dielectric materials include hafnium oxide (HfO2), hafnium silicon oxynitride (HfSiON), aluminum nitride (AlN), or aluminum oxide (Al2O3). The floating gate 112 can also be a polysilicon or metal gate, and can be used with silicon oxide or high-k dielectric materials as the logic gate dielectric layer 116. The material selection can refer to the anti-fuse gate 104 and the gate dielectric layer 106, and will not be repeated here. As for the selection logic gate 114, it is preferably a polysilicon gate, and from Figure 1From a cross-sectional view, the width of the selection logic gate 114 is greater than that of the floating gate 112. The material of the inter-polysilicon dielectric layer 118 is, for example, oxide or nitride, preferably silicon oxide formed using tetraethylorthosilicate glass (TEOS). From the perspective of manufacturing process integration, the logic gate dielectric layer 116 and the gate dielectric layer 106 in this embodiment can be formed simultaneously using the same manufacturing process, and the anti-fuse gate 104 and the floating gate 112 can also be formed simultaneously using the same manufacturing process; in other words, the material of the above-mentioned logic gate dielectric layer 116 and the material of the above-mentioned gate dielectric layer 106 can be the same, and the thickness of the logic gate dielectric layer 116 and the thickness of the gate dielectric layer 106 can also be the same. Similarly, the material and thickness of the anti-fuse gate 104 and the floating gate 112 can also be the same. However, the present invention is not limited to this. In another embodiment, the above-mentioned structures can also be manufactured using different manufacturing processes. Based on an 80nm manufacturing process, the thickness of the above-mentioned logic gate dielectric layer 116 is approximately tens of angstroms. like The thickness of the polysilicon of the floating gate 112 is about 40nm to 200nm; the thickness of the inter-polysilicon dielectric layer 118 is about 5nm to 30nm; the thickness of the selection logic gate 114 is about tens of nanometers.

[0054] Please continue to refer to Figure 1A second doped region 110 is provided in the substrate 100 between the anti-fuse gate 104 and the floating gate 112. A first doped region 108 is provided in the substrate 100 on the other side of the floating gate 112. A channel region (not shown) is formed between the second doped region 110 and the first doped region 108. If the substrate 100 is a P-type silicon substrate, the first doped region 108 and the second doped region 110 can be N+ regions. Vice versa, if the substrate 100 is an N-type silicon substrate, the first doped region 108 and the second doped region 110 can be P+ regions. In this embodiment, offset spacers 122 may be formed on the sidewalls of the floating gate 112 and the antifuse gate 104, and main spacers 124 may be formed on the sidewalls of the stacked structure 102 and outside the offset spacers 122 to protect the internal conductive structures, such as the select logic gate 114, the floating gate 112, and the antifuse gate 104. However, the present invention is not limited thereto, and the offset spacers 122 and / or the main spacers 124 may be omitted. Furthermore, to improve conductivity, a metal silicide layer 126 may be formed on the top surfaces of the first doped region 108, the second doped region 110, the antifuse gate 104, and the select logic gate 114 using a self-aligned method. The metal silicide layer 126 may be made of, for example, tungsten silicide, titanium silicide, cobalt silicide, tantalum silicide, nickel silicide, platinum silicide, or palladium silicide. However, the present invention is not limited thereto, and the metal silicide layer 126 may also be omitted.

[0055] Before programming, because the select logic gate 114 is slightly wider than the floating gate 112, the offset spacers 122 on the sidewalls of the floating gate 112 create capacitance with the select logic gate 114, thereby reducing program disturb. Therefore, after programming, the original anti-fuse gate 104 is transformed into a resistor, and the floating gate 112 and the select logic gate 114 can be used as a read unit, thereby reducing the read disturb experienced by a single gate. Because the programming voltage of the non-volatile memory device described above is approximately 5V to 8V, the overall device design can follow a low-voltage device design, significantly reducing the device size compared to similar existing devices.

[0056] Figure 2 is a cross-sectional view of a non-volatile memory device according to a second embodiment of the present invention, wherein Figure 1 The same or similar components are represented by the same reference numerals, and the description of the same components can refer to Figure 1 The relevant content will not be repeated here.

[0057] Please refer to Figure 2The non-volatile memory device of the second embodiment also includes a substrate 100, and an isolation structure 200, such as a shallow trench isolation (STI), is typically provided within the substrate 100 to define the active region of the memory device. The second embodiment differs from the first embodiment in that there are two stacked structures 102 and two antifuse gates 104, respectively. Two channel regions 120 are formed within the substrate 100 between the second doped region 110 and the first doped region 108. The two stacked structures 102 share a common first doped region 108, while two second doped regions 110 are located between each antifuse gate 104 and each stacked structure 102, thereby connecting one antifuse gate 104 and one stacked structure 102 in series via the second doped region 110. The designs of the antifuse gate 104, select logic gate 114, and floating gate 112 of the non-volatile memory device of the second embodiment are similar to those of the first embodiment in terms of mitigating program disturb or read disturb, and therefore will not be further described.

[0058] Figures 3A to 3G FIG. 1 is a schematic diagram of a manufacturing process of a non-volatile memory device according to a third embodiment of the present invention.

[0059] Please refer to Figure 3A A logic gate dielectric layer 302 is formed on a substrate 300, and a first conductive layer 304 is formed on the logic gate dielectric layer 302. An isolation structure 306, such as a shallow trench isolation (STI) structure, is provided within the substrate 100 to define the active region of the memory device. The first conductive layer 304 is made of polysilicon or metal and is formed by a chemical vapor deposition process. In one embodiment, if the first conductive layer 304 is made of polysilicon, it can be formed by first depositing an undoped polysilicon layer and then implanting dopants into the polysilicon layer using ion implantation. Alternatively, a gas containing the desired dopants can be added in situ while the polysilicon is being deposited, resulting in a doped polysilicon layer. The logic gate dielectric layer 302 is made of silicon oxide or a high-k dielectric material and is formed by a thermal oxidation process or a chemical vapor deposition process.

[0060] Then, please refer to Figure 3BThe first conductive layer 304 and the logic gate dielectric layer 302 are patterned to form a floating gate 308 and an anti-fuse gate 310. The logic gate dielectric layer below the anti-fuse gate can serve as a gate dielectric layer. The patterning step involves, for example, forming a patterned photoresist (not shown) or a patterned hard mask (not shown) on the first conductive layer 304. This hard mask is then used as an etching mask to remove the unmasked first conductive layer 304 and the underlying logic gate dielectric layer 302. Because the floating gate 308 and the anti-fuse gate 310 can be fabricated using the same process and integrated into existing fabrication processes, the fabrication process can be simplified and costs reduced.

[0061] Afterwards, please refer to Figure 3C , an offset spacer 312 can be formed on the sidewalls of the floating gate 308 and the sidewalls of the anti-fuse gate 310. The material of the offset spacer 312 is, for example, silicon oxide, silicon nitride or silicon oxynitride, and its formation method includes first performing a chemical vapor deposition process and then performing an anisotropic etching process. Then, a first doped region 314a and a second doped region 314b are formed in the substrate 300 on both sides of the floating gate 308, and its formation method includes performing an ion implantation process, wherein the second doped region 314b is located between the floating gate 308 and the anti-fuse gate 310 to connect the floating gate 308 and the anti-fuse gate 310 in series. Figure 3C The first and second doped regions 314a and 314b may also be formed by LDD processes (not shown) before forming the offset spacers 312, and heavily doped regions (such as 314a and 314b) may be formed by conventional ion implantation processes after forming the offset spacers 312.

[0062] Then, please refer to Figure 3D An interpoly dielectric layer 316 is formed entirely on the substrate 300, covering the floating gate 308 and the antifuse gate 310. A second conductive layer 318 is then formed on the interpoly dielectric layer 316. The interpoly dielectric layer 316 may be made of an oxide or a nitride, and may be formed by a chemical vapor deposition process. For example, the interpoly dielectric layer 316 may be silicon oxide formed using tetraethyl orthosilicate glass (TEOS). The second conductive layer 318 may be made of polysilicon, and may be formed by a chemical vapor deposition process.

[0063] Next, please refer to Figure 3EThe second conductive layer 318 and the interpoly dielectric layer 316 are patterned to form a select logic gate 320 located above the floating gate 308. The patterning step involves, for example, forming a patterned photoresist (not shown) or a patterned hard mask (not shown) on the second conductive layer 318. This layer is then used as an etching mask to remove the unmasked second conductive layer 318 and the underlying interpoly dielectric layer 316. The select logic gate 320, the interpoly dielectric layer 316, the floating gate 308, and the logic gate dielectric layer 302 form a stacked structure 322.

[0064] Afterwards, please refer to Figure 3F After the non-volatile memory device of the third embodiment is fabricated, main spacers 324 may be formed on the sidewalls of the stacked structure 322. The main spacers 324 may be formed by, for example, first depositing a dielectric layer or an insulating layer entirely on the substrate 300 and then removing the dielectric layer or insulating layer on a horizontal surface using anisotropic etching or etch-back. As a result, the main spacers 324 are also formed outside the offset spacers 312 on the sidewalls of the anti-fuse gate 310.

[0065] Then, please refer to Figure 3G To improve conductivity, a metal silicide layer 326 may be formed on the top surfaces of the first doped region 314a, the second doped region 314b, the antifuse gate 310, and the select logic gate 320 using a self-aligned method. The metal silicide layer 326 may be made of, for example, tungsten silicide, titanium silicide, cobalt silicide, tantalum silicide, nickel silicide, platinum silicide, or palladium silicide. The metal silicide layer 326 may be formed by, for example, first depositing a metal layer (not shown) over the entire surface of the substrate 300. Then, at high temperature, the metal layer reacts with the underlying silicon (e.g., the silicon substrate of the first doped region 314a and the second doped region 314b and the polysilicon of the antifuse gate 310 and the select logic gate 320) to form a metal silicide. The remaining unreacted metal is then removed. If the antifuse gate 310 is a metal gate, no metal silicide will form on its top surface.

[0066] In summary, the present invention achieves device programming in a one-time programmable (OTP) read-only memory (ROM) with an antifuse gate by stacking structures made of materials with different dielectric constants in series. Because this stacked structure is capable of withstanding high voltages, it eliminates the need for external voltage-reducing circuitry, thereby increasing device integration. Furthermore, if the antifuse gate is accidentally written or if a defect causes excessive leakage, the stacked structure can shut down the entire device, ensuring normal device performance.

[0067] Although the present invention is disclosed in conjunction with the above embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the definition of the attached claims.

Claims

1. A non-volatile memory device, wherein the non-volatile memory device is a one-time programmable read-only memory, characterized in that: include: substrate; A high-pressure-resistant stacking structure is formed on the substrate, and the stacking structure includes: floating gate; A selection logic gate is disposed on the floating gate; a logic gate dielectric layer disposed between the floating gate and the substrate; and an inter-polysilicon dielectric layer, disposed between the floating gate and the selection logic gate; an anti-fuse gate, disposed on the substrate; a gate dielectric layer disposed between the antifuse gate and the substrate; a first doped region formed in the substrate on one side of the floating gate; and A second doping region is formed in the substrate between the floating gate and the anti-fuse gate, and a channel region is formed between the second doping region and the first doping region.

2. A non-volatile memory device, wherein the non-volatile memory device is a one-time programmable read-only memory, characterized in that: include: substrate; at least one first doped region formed in the substrate; A plurality of high-voltage-resistant stacked structures are formed on the substrate and connected in series via the at least one first doped region, wherein each stacked structure comprises: floating gate; A selection logic gate is provided on the floating gate; a logic gate dielectric layer disposed between the floating gate and the substrate; and an inter-polysilicon dielectric layer, disposed between the floating gate and the selection logic gate; a plurality of second doped regions formed in the substrate on one side of the floating gate, and a channel region formed between one of the second doped regions and the at least one first doped region; a plurality of anti-fuse gates disposed on the substrate and connected in series with one of the stack structures via one of the second doped regions; and A gate dielectric layer is disposed between each of the anti-fuse gates and the substrate. 3 . The non-volatile memory device as claimed in claim 1 , wherein the floating gate comprises a polysilicon or metal gate. 4 . The non-volatile memory device as claimed in claim 1 , wherein the select logic gate comprises a polysilicon gate. 5 . The non-volatile memory device as claimed in claim 1 , wherein a material of the inter-poly dielectric layer comprises oxide or nitride. 6 . The non-volatile memory device as claimed in claim 1 , wherein a material of the logic gate dielectric layer is the same as a material of the gate dielectric layer, and a thickness of the logic gate dielectric layer is the same as a thickness of the gate dielectric layer. 7 . The non-volatile memory device as claimed in claim 1 , wherein the logic gate dielectric layer and the gate dielectric layer are each independently made of silicon oxide or a high-k dielectric material. 8 . The non-volatile memory device as claimed in claim 1 , further comprising offset spacers located on sidewalls of the floating gate and sidewalls of the anti-fuse gate. 9 . The non-volatile memory device as claimed in claim 1 , further comprising a main spacer located on a sidewall of the stack structure.

10. The non-volatile memory device as claimed in claim 1 or 2, further comprising a metal silicide layer formed on top surfaces of the first doped region, the second doped region, the anti-fuse gate, and the select logic gate.

11. The non-volatile memory device as claimed in claim 1 or 2, wherein the first doped region is coupled to a bit line.

12. A method for manufacturing a non-volatile memory device, wherein the non-volatile memory device is a one-time programmable read-only memory, the method comprising: forming a logic gate dielectric layer on the substrate; forming a first conductor layer on the logic gate dielectric layer; patterning the first conductive layer and the logic gate dielectric layer to form at least one floating gate and at least one anti-fuse gate; forming a first doping region and a second doping region in the substrate on both sides of the floating gate, wherein the second doping region is located between the floating gate and the anti-fuse gate to connect the floating gate and the anti-fuse gate in series; forming an interpolysilicon dielectric layer on the substrate to cover the floating gate and the anti-fuse gate; forming a second conductor layer on the inter-polysilicon dielectric layer; as well as The second conductive layer and the interpolysilicon dielectric layer are patterned to form a selection logic gate located on the floating gate, and the selection logic gate, the interpolysilicon dielectric layer, the floating gate and the logic gate dielectric layer form a high-voltage resistant stacked structure. 13 . The method for manufacturing a non-volatile memory device as claimed in claim 12 , wherein a material of the logic gate dielectric layer comprises silicon oxide or a high-k dielectric material. 14 . The method for manufacturing a non-volatile memory device as claimed in claim 12 , wherein a material of the first conductive layer comprises polysilicon or metal. 15 . The method for manufacturing a non-volatile memory device as claimed in claim 12 , wherein a material of the inter-polysilicon dielectric layer comprises oxide or nitride. 16 . The method for manufacturing a non-volatile memory device as claimed in claim 12 , wherein a material of the second conductive layer comprises polysilicon. 17 . The method for manufacturing a non-volatile memory device as claimed in claim 12 , wherein after patterning the first conductive layer and the logic gate dielectric layer, the method further comprises forming offset spacers on sidewalls of the floating gate and the anti-fuse gate. 18 . The method for manufacturing a non-volatile memory device as claimed in claim 12 , further comprising forming main spacers on sidewalls of the stacked structure after patterning the second conductive layer and the inter-polysilicon dielectric layer.

19. The method for manufacturing a non-volatile memory device as claimed in claim 12, wherein after patterning the second conductive layer and the inter-polysilicon dielectric layer, the method further comprises forming a silicide layer on a top surface of the first doped region, a top surface of the second doped region, a top surface of the anti-fuse gate, and a top surface of the select logic gate.

Images