Multiple precision memory system

Abstract

Space in the memory is allocated based on the highest precision used. When the maximum precision used is not used, the bits required for that particular precision level (e.g., floating point format) are transferred between the processor and the memory, while the rest are not. A given floating point number is distributed over discontinuous addresses. Each portion of a given floating point number is located at the same offset within an access unit, group, and / or memory array. This allows a sequencer in a memory device to access a precision-related number of access units, groups, and / or memory arrays in succession without receiving additional requests through a memory channel.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0001] Figures 1A to 1D is a diagram illustrating example storage formats for floating point numbers with different precisions.

[0002] Figure 2 is a block diagram illustrating a system that handles multiple floating point number formats.

[0003] Figure 3 is a flow chart illustrating a method of accessing floating point numbers with different precisions.

[0004] Figure 4 is a flow chart illustrating a method of storing and retrieving floating point numbers with different precisions in a memory device.

[0005] Figure 5 is a flow chart illustrating a method of retrieving floating point numbers from a memory device, and storing floating point numbers to a memory device.

[0006] 6A to 6F is a diagram illustrating the use of column offsets to efficiently access floating point numbers with different precisions.

[0007] 7A to 7E The configuration of the memory device is illustrated.

[0008] FIG. 8A to FIG. 8C is a diagram illustrating a hierarchy of functions for storing / retrieving floating point numbers with different precisions.

[0009] Fig. 9 is a flow chart illustrating a method for configuring access to floating point numbers with different precisions.

[0010] Fig.10 is a block diagram of a processing system that uses a stack of memory devices to store floating-point numbers with varying precision.

[0011] Fig.11 is a block diagram of a processing system that uses memory modules to store floating-point numbers with varying precision.

[0012] Fig.12 is a block diagram of a processing system that uses directly attached memory devices to store floating point numbers with varying precision.

[0013] Fig.13 It is a block diagram of the processing system. DETAILED DESCRIPTION

[0014] Different steps and / or operations during machine learning can use different levels of precision. As used herein, precision is the number of digits in a number (e.g., the number of bits in a binary number - fixed point or floating point). Various number formats can have various bit numbers. Examples of the precision of a number include: a single bit (e.g., only a sign bit), five or six bits (e.g., only an exponent or an exponent with a sign bit), 32 bits (e.g., 23 significant bits, a sign bit, and 8 exponent bits (IEEE 754 standard single precision)), 64 bits (e.g., 52 significant bits, a sign bit, and 11 exponent bits (IEEE 754 standard double precision)) and others (e.g., any number of signs, exponents, and / or significant bits or combinations thereof).

[0015] In one example, training a neural network can use higher precision numbers (integer or floating point) during training calculations for the network than the precision used to perform inference calculations using the trained network. Similarly, matrix multiplication calculations can create higher precision outputs, for example, after thresholding lower precision inputs. Finally, for example, higher precision numbers can be used for backpropagation calculations than for forward propagation calculations.

[0016] In one embodiment, space in memory is allocated based on the highest used precision. When the maximum used precision is not used, the bits required for that particular precision level (e.g., floating point format) are transferred between the processor and memory, while the remaining bits are not transferred. This saves memory bandwidth, power, and processor resources.

[0017] In one embodiment, the storage format for various precision levels is selected to be efficiently stored and retrieved from the memory device. Specifically, a given floating point number and its components are distributed on discontinuous addresses. The discontinuous addresses for a given floating point number are located in more than one memory access unit, group and / or memory array. In one embodiment, each part of a given floating point number is located at the same offset in an access unit, group and / or memory array. This allows a sequencer in a memory device to successively (or simultaneously) access the access units, groups and / or memory arrays of a precision-related number without receiving additional requests through a memory channel. In one embodiment, the most significant bit (MSB) of a floating point number is stored so that the MSB is accessed before a less significant bit.

[0018] Figures 1A to 1D is a diagram illustrating example storage formats for floating point numbers with different precisions. Figure 1AIn FIG. 1 , an example format for a 32-bit floating point number is shown. The example format is labeled FLOAT32*110. A 32-bit floating point number includes 32 bits stored in 4 bytes. The most significant byte includes a bit S for the exponent sign. E , 6 bits for the exponent (E5-E0) and one bit for the mantissa sign S M The next most significant byte contains the most significant 8 bits of the mantissa (excluding the sign) (M 23 -M 16 ). The next most significant byte includes the M of the mantissa. 15 Finally, the least significant byte of the 32-bit floating point number includes bits M7-M0 of the mantissa.

[0019] It should be understood that the selection and placement of the sign bit, exponent bit, and mantissa bit are examples only, and other numbers of bits and placements of these bits can be envisioned. For example, the most significant byte can include fewer (e.g., 4) exponent bits and include more (e.g., 2) mantissa bits.

[0020] In one embodiment, each byte of the FLOAT32* format floating point number 110 is stored in a different access unit of the memory 120. Figure 1A As shown by arrow 150, arrow 151, arrow 152 and arrow 153, arrow 150 extends from the most significant byte of floating point number 110 to position A1 in group P of memory 120; arrow 151 extends from the second most significant byte of number 110 to position A1 of group P+1 of memory 120; arrow 152 extends from the third most significant byte of number 110 to position A1 of group P+2 of memory 120; and arrow 153 extends from the least significant byte of number 110 to position A1 of group P+3 of memory 120.

[0021] The access units (groups) of the memory 120 may, for example, be selected for efficiently transferring FLOAT32* formatted numbers and / or their constituent subbytes. For example, if the memory 120 has a burst size of 64 bytes, then positioning each of the corresponding bytes of the 64 FLOAT32* formatted floating point numbers 110 in a different 64-byte group will allow the corresponding bytes to be retrieved / stored by different bursts. This allows the 64 most significant bytes of the 32-bit floating point number (i.e., the sign of the exponent and mantissa) to be retrieved by the first burst for processing. The M of the mantissa 23 -M 16 The bits are retrieved / stored by the second burst, etc. If the remaining bytes of the mantissa of the 64 floating point numbers are not needed (e.g., only the most significant bytes are needed to determine if a number is positive, negative, or not a number - NaN), then subsequent bursts need not be performed.

[0022] Other group sizes (e.g., 2 k -1) may be selected according to the architecture of the memory 120. For example, the access unit group may be selected to correspond to the column access width or page size of the array of the memory 120, or to multiply or divide it by a power of 2. For example, for a page size of 2kB, the selected access unit (group) size may be 2kB / 32=64B, whereby the exponent portion of the first group of 64 floating point numbers is stored in the first 64 bytes of the page, the next most significant byte is stored in the second 64 bytes, and so on, where the second group of 64 floating point numbers starts at byte 64*4=256 of the page, and so on for the 8 groups of 64 floating point numbers 120 stored per page of the memory 120.

[0023] exist Figure 1B , an example format of a 24-bit floating point number is shown. The example number is labeled FLOAT24*111. A 24-bit floating point number consists of 3 bytes. The most significant byte includes one bit SE for the exponent sign, 6 bits of the exponent (E5-E0), and one bit SM for the mantissa sign. The next most significant byte includes the most significant 8 bits of the mantissa (excluding the sign) (M 23 -M 16 ). Finally, the least significant byte includes the M of the mantissa. 15 Thus, it should be understood that the FLOAT24* format is equivalent to the FLOAT32* format in which the least significant byte (M7-M0) of the mantissa is truncated (eg, set to 0x00h).

[0024] In one embodiment, each of the bytes of the FLOAT24* format floating point number 111 is stored in a different access unit of the memory 120. These bytes / bits are stored in the same access group and location as their (untruncated) counterparts in the FLOAT32* number would be stored. This Figure 1B 1 is illustrated by arrow 150, arrow 151, and arrow 152, with arrow 150 extending from the most significant byte of floating point number 111 to position A1 in group P of memory 120; arrow 151 extending from the second most significant byte of number 111 to position A1 in group P+1 of memory 120; and arrow 152 extending from the third most significant byte of number 111 to position A1 in group P+2 of memory 120. Position A1 in group P+3, where the least significant byte of the FLOAT32* number is to be stored, may optionally be set to 0x00h. This is illustrated in FIG. Figure 1B This is illustrated by the "0" in position A1 of group P+3.

[0025] Placing each byte of a FLOAT24* number in the same location and access group as a FLOAT32* number allows the same access pattern to be used for FLOAT32* numbers and lower precision FLOAT24* numbers - except that the last access / burst (i.e., to retrieve / store the least significant byte) does not need to be performed. This allows FLOAT24* numbers to be retrieved using 3 bursts instead of the 4 bursts required for float32* numbers. Thus, the 64 most significant bytes of a 24-bit floating point number can be retrieved / stored by the first burst; the M of the mantissa 23 -M 16 bits are retrieved / stored by the second burst; and, M 15 -M8 bits are retrieved / stored by the third burst. The fourth burst does not need to be performed for FLOAT24* format numbers - thus saving memory channel bandwidth / cycles.

[0026] exist Figure 1C , an example format for a 16-bit floating point number is shown. The example number is labeled FLOAT16*112. A 16-bit floating point number consists of 2 bytes. Similar to the FLOAT32* and FLOAT24* formats, the most significant byte includes 1 bit SE for the exponent sign, 6 bits (E5-E0) of the exponent, and one bit S for the mantissa sign. M The other byte in FLOAT16* format contains the most significant 8 bits of the mantissa (excluding the sign) (M 23 -M 16 ). Therefore, it should be understood that the FLOAT16* format is equivalent to the following: where the 2 least significant bytes of the mantissa (i.e., M 15 -M0) is truncated (e.g., set to 0x00h), and the least significant byte of the mantissa (i.e., M 15 -M8) truncated (e.g., set to 0x00h) FLOAT24* format.

[0027] In one embodiment, each of the bytes of the FLOAT16* format floating point number 112 is stored in a different access unit of the memory 120. These bytes / bits are stored in the same access group and location as their (untruncated) counterparts in a FLOAT32* or FLOAT24* number would be stored. Figure 1C1 and 151, arrow 150 extending from the most significant byte of floating point number 112 to position A1 in group P of memory 120; and arrow 151 extending from the second most significant byte of number 112 to position A1 in group P+1 of memory 120; position A1 in group P+2, where the least significant two bytes of the FLOAT32* number may be stored, and position A1 in group P+3 may optionally be set to 0x00h. This is shown in FIG. Figure 1C This is illustrated by the "0" in position A1 of groups P+2 and P+3.

[0028] Placing each byte of a FLOAT16* number in the same location and access group as FLOAT32* and FLOAT24* numbers allows the same access pattern to be used for FLOAT32* numbers, FLOAT24* numbers, and lower precision FLOAT16* numbers - except that the last one or two accesses / bursts (i.e., to retrieve or store 1 or 2 least significant bytes, as needed) do not need to be performed. This allows FLOAT16* numbers to be retrieved using 2 bursts instead of the 4 bursts required for FLOAT32* numbers. Thus, the 64 most significant bytes of a 16-bit floating point number can be retrieved / stored with the first burst, while the remaining 4 bits of the mantissa are retrieved / stored. 23 -M 16 Retrieve / store via the second burst. A third or fourth burst does not need to be performed for FLOAT16* format numbers - thus saving memory channel bandwidth / cycles.

[0029] exist Figure 1D , an example format of an 8-bit floating point number is shown. The example number is labeled FLOAT8*113. An 8-bit floating point number consists of 1 byte. Similar to the FLOAT32*, FLOAT24*, and FLOAT16* formats, one byte of the FLOAT8* format includes one bit SE for the exponent sign, 6 bits (E5-E0) of the exponent, and one bit S for the mantissa sign. M Therefore, it should be understood that the FLOAT8* format is equivalent to the following: 23 -M0) is truncated (e.g., set to 0x00h) in FLOAT32* format; where the 2 least significant bytes of the mantissa (i.e., M 23 -M8) is truncated (e.g., set to 0x00h) FLOAT24* format; and the least significant byte of the mantissa (i.e., M 23 -M 16 ) in FLOAT16* format that is truncated (for example, set to 0x00h).

[0030] In one embodiment, the bytes of a floating point number 113 in FLOAT8* format are stored in the same access group and location where their (untruncated) counterparts in FLOAT32*, FLOAT24*, and / or FLOAT16* numbers would be stored. Figure 1D This is illustrated by arrow 150 extending from the most significant byte of floating point number 113 to position A1 in bank P of memory 120. Position A1 in bank P+1, position A1 in bank P+2, and position A1 in bank P+3, where the 3 least significant bytes of the FLOAT32* number will be stored, may optionally be set to 0x00h. Figure 1D This is illustrated by the "0" in position A1 of group P+1, group P+2, and group P+3.

[0031] The byte of FLOAT8* number is placed in the same position and access group as FLOAT32*, FLOAT24* and FLOAT16* number, allowing the same access mode to be used for FLOAT32* number, FLOAT24* number, FLOAT16* number and FLOAT8* number of lower precision---except the last, two or three access / bursts (that is, as required, in order to retrieve / store one, two or three least significant bytes) do not need to be executed. This allows FLOAT8* number to use 1 burst, rather than to retrieve for the required 4 bursts of FLOAT32* number. Therefore, the 64 most significant bytes of 8-bit floating-point numbers can be retrieved / stored by a single burst. The second, third or fourth burst need not be executed for the FLOAT8* format number---thus saving memory channel bandwidth / cycle.

[0032] Figure 2 is a block diagram illustrating a system for processing multiple floating point number formats. Figure 2 , the processing system 200 includes a processor 210 and a memory device 220. The processor 210 includes one or more processor cores 211, a floating point format processing device 215, a controller 212, a command address interface 213, and a data interface 214. The memory device 220 includes one or more memory cores 221, a command address interface 223, a data interface 224, a control circuit device 222, and a data path circuit device 226. The control circuit device 222 includes a column sequencer 225.

[0033] The processor core 211 is operably coupled to the floating point format processing device 215 and the controller 212. The floating point format processing device 215 is operably coupled to the processor core 211 and the controller 212. The controller 212 is operably coupled to the processor core 211, the floating point format processing device 215, the command address interface 213 and the data interface 214.

[0034] The command interface 223 of the memory device 220 is operably coupled to the control circuitry 222. The control circuitry 222 is operably coupled to the memory core 221. The memory core 221 is operably coupled to the data path circuitry 226. The data path circuitry 226 is operably coupled to the data interface 224. The command address interface 213 of the processor 210 is operably coupled to the command address interface 223 of the memory device 220. The data interface 224 of the memory device 220 is operably coupled to the data interface 214 of the processor 210.

[0035] Processor 210 and memory device 220 may be or include an integrated circuit type device, such as what is commonly referred to as a "chip". A memory controller, such as controller 212, manages the flow of data to and from the memory device and / or memory module. Memory device 220 may be a standalone device, or may be a memory module or a component thereof. For example, the memory controller may be a north bridge chip, an application specific integrated circuit (ASIC) device, a graphics processor unit (GPU), a system on chip (SoC), or an integrated circuit device including many circuit blocks (such as, selected from a graphics core, a processor core, and an MPEG encoder / decoder, etc.). For example, as Figure 2 As depicted, memory controller 212 may be included on a single die with one or more processor cores 211, or may be included as part of a more complex integrated circuit system, such as a block of a system on a chip (SOC). Memory devices 220 may include dynamic random access memory (DRAM) cores or other types of memory cores, such as static random access memory (SRAM) cores or non-volatile memory cores such as flash memory.

[0036] The controller 212 is operably coupled to the memory 220 via at least one command address interface 213. The controller 212 is operably coupled to the memory 220 to send commands to the memory 220. The memory 220 receives commands (and addresses) via corresponding command address interfaces 223. The memory 220 communicates data with the processor 210 via at least one data interface 224. The processor 210 (and in particular, the controller 212) communicates data with the memory 220 via corresponding data interfaces 214.

[0037] The floating point format processing device 215 receives floating point numbers from the processor core 211. These floating point numbers may have different formats and / or different precisions. The floating point format processing device processes (e.g., disassembles, disassembly) these floating point numbers according to their precision. For example, the floating point format processing can process floating point numbers with a first precision (e.g., 32 bits) so that these numbers can be stored (e.g., by the controller 212) in a plurality of bit blocks in non-continuous addressing locations. For example, the most significant byte of these floating point numbers with a first precision is stored in a first address range in the memory 220; the second most significant byte is stored in a second address range, and so on. Similarly, the floating point format processing device can process floating point numbers with a second precision (e.g., 16 bits) so that these numbers can be stored (e.g., by the controller 212) in a subset of the bit blocks for storing numbers with the first precision in non-continuous addressing locations. Therefore, the subset of the blocks for storing a given second precision number corresponds to the second precision version of the corresponding first precision floating point number. Multiple non-contiguously addressed locations corresponding to a set of floating point numbers with a selected precision can be assembled into contiguously addressed data blocks (e.g., bursts, pages, etc.) by a floating point format processing device for storage in a memory device 220 via a data (DQ) interface 214 and a DQ interface 224 by a controller 212 (using a command address (CA) interface 213 and a CA interface 223).

[0038] For example, each byte of the bytes of a floating point number in FLOAT32* format may be stored in a different access unit (e.g., a group and / or a memory address range) of memory 220. A collection of multiple FLOAT32* numbers may be assembled such that a first transaction (e.g., a burst) stores all of the corresponding most significant bytes of the collection of FLOAT32* numbers to a first access unit in a single transaction. A second transaction may then store the corresponding second most significant byte to a second access unit, and so on.

[0039] In one embodiment, the memory device 220 (and in particular, the column sequencer 225) is configured (and / or commanded) to receive a first transaction and then generate internal accesses for subsequent less significant bytes without receiving additional transactions. For example, the controller 212 may configure the memory device 220 (and / or send a command to the memory device) with an indicator of the precision (e.g., the number of bytes) that each floating point number consists of. The indicator may determine the number of access units that the memory device 220 is to store in the memory core 221 before a new transaction address is required. In other words, the memory device 220 may be configured (and / or commanded) to store a set of FLOAT32* numbers, where each byte of a separate FLOAT32* number is stored in a different access unit. Therefore, the controller 212 may transmit a first address to the memory device 220, thereby indicating the location (e.g., group P) where the first byte (e.g., the most significant) of each floating point number in the set of FLOAT32* floating point numbers is to be stored. Subsequently, the (e.g., next most significant) second byte of each floating point number in the set of floating point numbers can be sent via DQ interface 214 and stored without requiring a new address to be specified via CA interface 223 because memory device 220 has been configured (and / or commanded) with both the size of the access unit (e.g., burst size) and the number of bytes in the FLOAT32* number (4). Column sequencer 225 serves to generate internal addressing to memory core 221, which stores the individual bytes of the FLOAT32* format number in the appropriate access unit (e.g., P, P+1, etc.) without receiving a new address for each burst. In some embodiments, the sequencer is also capable of performing address modifications where portions of the memory array receive unique addresses simultaneously, or performing address offsets associated with the data format requested by the controller.

[0040] Similarly, the memory device 220 can be configured (and / or commanded) to store a set of FLOAT16* numbers, wherein each byte of a separate FLOAT16* number is stored in a different access unit. Thus, the controller 212 can transmit a first address to the memory device 220, thereby indicating that the (e.g., most significant) first byte of each floating point number in the set of FLOAT16* floating point numbers is to be stored at location (e.g., group P). Subsequently, the (e.g., least significant) second byte of each floating point number in the set of floating point numbers can be sent and stored via the DQ interface 214 without requiring a new address to be specified via the CA interface 223, because the memory device 220 has been configured (and / or commanded) with both the size of the access unit (e.g., burst size) and the number of bytes (2) in the FLOAT16* number. Column sequencer 225 is used to generate internal addressing to memory core 221, which stores each byte of the FLOAT16* format number in the appropriate access unit (e.g., P, P+1, etc.) without receiving a new address for each burst of the group. A similar process can be used to store FLOAT8* and FLOAT24* numbers.

[0041] The controller 212 may configure the memory device 220 with an indicator (e.g., number of bytes) of the precision to be retrieved (regardless of the precision of the number and / or set of numbers). The indicator may determine the number of access units that the memory device 220 will retrieve from the memory core 221 before a new transaction address is required. In other words, the memory device 220 may be configured (and / or commanded) to retrieve a set of FLOAT24* numbers that were originally stored as FLOAT32* numbers. In the case where each byte of the individual numbers is stored in a different access unit, the retrieval of numbers with lower precision than originally stored may be accomplished by transferring fewer bursts.

[0042] For example, the controller 212 may transmit a first address to the memory device 220, indicating the location (e.g., group P) from which the first byte (e.g., most significant byte) of each floating point number in the set of FLOAT32*, FLOAT24*, FLOAT16*, or FLOAT8* floating point numbers will be retrieved. Subsequently, the (e.g., next most significant) second byte (if applicable) of each floating point number in the set of floating point numbers may be retrieved and sent via the DQ interface 214 without requiring a new address to be specified via the CA interface 223, because the memory device 220 has been configured (and / or commanded) with both the size of the access unit (e.g., burst size) and the number of bytes in the maximum precision floating point number (e.g., if FLOAT32* is the highest precision, the maximum burst number is 4). The column sequencer 225 serves to generate internal addressing to the memory core 221, which retrieves each byte of the configured (and / or commanded) format in the appropriate access unit (e.g., P, P+1, etc.) without receiving a new address for each burst.

[0043] For example, the controller 212 may transmit a first address to the memory device 220, indicating the location of the (e.g., most significant) first byte of each floating point number in the set of, for example, FLOAT24* floating point numbers to be retrieved (e.g., group P). Subsequently, the (e.g., next most significant) second byte of each floating point number in the set of FLOAT24* floating point numbers may be retrieved and sent via the DQ interface 224 without requiring a new address to be specified via the CA interface 223, because the memory device 220 has been configured (and / or commanded) with both the size of the access unit (e.g., the burst size) and the number of bytes in the maximum precision floating point number (e.g., 3 for FLOAT24*). The column sequencer 225 serves to generate internal addressing to the memory core 221, which retrieves individual bytes in the FLOAT24* format in the appropriate access unit (e.g., P, P+1, etc.) without receiving a new address for each burst.

[0044] Similarly, the memory device 220 can be configured (and / or commanded) to retrieve a set of FLOAT16* numbers, where each byte of a separate FLOAT16* number is retrieved from a different access unit. Thus, the controller 212 can transmit a first address to the memory device 220, thereby indicating the location (e.g., group P) where the (e.g., most significant) first byte of each floating point number in the set of FLOAT16* floating point numbers is stored. Subsequently, the (e.g., least significant) second byte of each floating point number in the set of floating point numbers can be retrieved and sent via the DQ interface 224 without requiring a new address specified via the CA interface 223, because the memory device 220 has been configured (and / or commanded) with the size of the access unit (e.g., burst size) and the number of bytes in the FLOAT16* number (2). The column sequencer 225 is used to generate internal addressing for the memory core 221, which retrieves each byte of the FLOAT16* format number in the appropriate access unit (e.g., P, P+1, etc.). A similar process can be used to retrieve numbers of other sizes / precisions.

[0045] Once retrieved, the floating point format processing device 215 receives a data burst from the controller 212, which includes the various parts of the set of floating point numbers. The floating point format processing device 215 processes (e.g., reassembles) the floating point numbers according to the precision of the floating point numbers. For example, the floating point format processing device 215 can reorganize the floating point numbers from multiple (e.g., 4) bytes (which were previously stored in non-contiguous memory 220 locations) with a first precision (e.g., 32 bits) so that these numbers can be processed by the processor core 211. For example, the most significant part (e.g., byte) of these floating point numbers with a first precision may have been stored in a first address range in the memory 220; the second most significant part is stored in a second address range, and so on. Therefore, at least two parts will arrive from the memory 220, and other data intervenes between these parts (e.g., other parts of other floating point numbers). Multiple non-contiguous addressing parts of the floating point number can be assembled into a complete floating point number by the floating point format processing device 215, and the complete floating point number is provided to the processor core 211.

[0046] In one embodiment, to deassemble the floating point numbers of multiple precisions, the floating point processing device 215 may read the portions of the floating point registers or the portions of the floating point cache lines in the first order when storing the floating point numbers to the memory device 220. To reassemble the floating point numbers of multiple precisions, the floating point processing device 215 may write the portions of the floating point registers or the portions of the floating point cache lines in the first order when retrieving the floating point numbers to the memory device 220.

[0047] Figure 3is a flow chart illustrating a method of accessing floating point numbers with different precisions. Figure 3 The steps shown in , for example, may be performed by one or more elements of the system 200. A first access command is received (302), the first access command including information indicating a first number of consecutive transactions to be executed in response to the first access command, the first number of consecutive transactions corresponding to a first precision number format. For example, the memory device 220 may receive an access command via the CA interface 223, the access command including information (e.g., bits) indicating a first number (e.g., 4) of transactions to be executed in response to the command without requiring a new address to be specified. In another example, the memory device 220 may be pre-configured (and / or commanded) by the controller 212 (e.g., in a register) with a first number (e.g., 4) of transactions to be executed in response to the command without requiring a new address to be specified. Then, when an access command of a variable precision type is received, the pre-configured (and / or commanded) number of transactions is executed without requiring a new address to be specified.

[0048] A second access command is received (304), the second access command including information indicating a second number of consecutive transactions to be executed in response to the second access command, the second number of consecutive transactions corresponding to the second precision number format. For example, the memory device 220 can receive an access command via the CA interface 223, the access command including information (e.g., bits) indicating a second number (e.g., 2) of transactions, the second number of transactions being executed in response to the command without specifying a new address. In another example, the memory device 220 can be pre-configured (and / or commanded) by the controller 212 (e.g., in a register) with a second number (e.g., 2) of transactions, the second number of transactions being executed in response to the command without specifying a new address. Then, when an access command of a variable precision type is received, the pre-configured (and / or commanded) second number of transactions is executed without specifying a new address.

[0049] Figure 4 is a flow chart illustrating a method of storing and retrieving floating point numbers with different precisions in a memory device. Figure 4 The steps shown in can be performed, for example, by one or more elements of system 200. A first floating point number is stored with a first precision by storing a first plurality of bit blocks in first non-contiguously addressed locations, wherein the first plurality of bit blocks includes a first subset of the first plurality of bit blocks, the first subset of the first plurality of bit blocks corresponding to a second precision version of the first floating point number (402). For example, after the burst is formatted by floating point format processing device 215, controller 212 can store the first floating point number (as part of a set) in, for example, a FLOAT32* format. As referred to herein Figures 1A to 1DAs discussed, the FLOAT32* format includes various subsets of bits that correspond to the FLOAT24*, FLOAT16*, and FLOAT8* formats, respectively.

[0050] A second floating point number is retrieved from the second non-contiguously addressed locations by retrieving the first subset of the first plurality of blocks of bits, the second floating point number being a second precision version of the first floating point number (404). For example, the controller 212 may retrieve the second floating point number, e.g., in FLOAT24* format (as part of a set), from the subset of non-contiguously addressed locations in which the FLOAT32* format number is stored.

[0051] Figure 5 is a flow chart illustrating a method of retrieving a floating point number from a memory device and storing a floating point number to a memory device. Figure 5 The steps shown may be performed by one or more elements of the system 200. A first set of floating point numbers is received via a first coherent memory transaction, wherein first portions of the first set of floating point numbers are received from non-contiguously addressed locations in a memory device, wherein each of the first portions is received in response to a different transaction in the first coherent memory transaction (502). For example, the processor 210 (and in particular, the floating point (FP) format processor 215) may receive a set of floating point numbers dispersed over a plurality of bursts of data received from the memory device 220. These bursts of data may be received from the memory device 220 in response to a single command sent via the CA interface 213, wherein addresses of subsequent bursts of data are calculated by a column sequencer 225 in the memory device 220.

[0052] The first portion of the first set of floating point numbers is arranged into the first set of floating point numbers (504). For example, the floating point format processor 215 may receive a burst of data sent by the memory device 220 in response to a "multi-precision" memory access command. The floating point format processor 215 may arrange the portions of the floating point numbers into a complete floating point number.

[0053] A second set of floating point numbers is received from the processor 506. For example, the floating point format processing device 215 may receive a set of floating point numbers from the processor core 211. The number of floating point numbers in the set may correspond to an access unit and / or a data burst size.

[0054] Through the second coherent memory transaction, second portions of the second set of floating point numbers are transmitted to be stored in non-contiguous address locations in the memory device, wherein each portion of the second portion is transmitted as part of a different transaction in the second coherent memory transaction (508). For example, the controller 212 may use separate transactions with the memory device 220 to transmit separate portions of the floating point numbers in the set received from the processor core 211. In other words, for example, a set of multiple floating point numbers may be assembled such that a first transaction (e.g., a burst) stores all corresponding most significant bytes of the set of floating point numbers to a first address range in a single transaction. The second transaction may then store the corresponding second most significant bytes to a second (different) address range, and so on.

[0055] 6A to 6F is a diagram illustrating the use of column offsets to efficiently access floating point numbers with different precisions. Column offsets (also known as granular memory column access) are described in U.S. Patent No. 6,825,841 to Hampel et al., entitled “GRANULARITYMEMORY COLUMN ACCESS” (hereinafter “Hampel”), which is incorporated herein by reference in its entirety for all purposes.

[0056] One aspect described in Hampel is a memory device (e.g., memory device 220) that accesses different memory arrays simultaneously, where different columns can be addressed for each memory array. Thus, for example, for 32-bit access, the first byte of the 32 bits can be stored in / retrieved from the first array, the second byte is stored in / retrieved from the second array, the third byte is stored in / retrieved from the third array, and the fourth byte is stored in / retrieved from the fourth array. However, each of these first, second, third, and fourth bytes can be stored in a different column address. This aspect can be used to efficiently store / retrieve portions of floating point numbers having different precisions.

[0057] Fig. 6A The arrangement of portions of an example floating point format in a memory device that can access multiple arrays using different column addresses (e.g., as described in Hampel) is illustrated. FIG. 6A to FIG. 6D In Figure 1, five 32-bit floating point numbers A, B, C, D, and E are shown. These are FIG. 6A to FIG. 6D The parts (e.g., bytes) of each of these numbers are represented as follows: Xare the sign and exponent bytes (ie, the most significant byte), M X2 is the most significant byte of the mantissa, M X1 is the third most significant byte of the mantissa, and M X0 is the least significant byte of the mantissa, where X is the floating point flag (e.g., S B are the sign and exponent bytes in the illustration of a floating point number "B").

[0058] Floating point numbers A, B, C, D, and E are stored, for example, in individual rows of four memory arrays W 651, X 652, Y 653, and Z 654. Byte-wide groups of column sense amplifiers (or other memory elements associated with reading / writing rows into memory arrays 651-654) are labeled with an array tag (W, X, Y, or Z, as appropriate) and a number representing the column address of the byte-wide group (e.g., X0 is the tag for the first byte of a column group addressed in a row of array X 652, X1 is the tag for the second byte of a column group addressed in a row of array X 652, and so on).

[0059] Each array 651 to 654 provides (or receives) the same 8-bit byte to (or from) interface 660 for each transaction. FIG. 6A to FIG. 6D In FIG. 6 , the bytes of interface 660 are marked as W-BYTE I / F (W byte interface) 661 , X-BYTE I / F (X byte interface) 662 , Y-BYTE I / F (Y byte interface) 663 , and Z-BYTE I / F (Z byte interface) 664 .

[0060] exist FIG. 6A to FIG. 6D In , the parts (e.g., bytes) of the floating point number A are stored as follows: A is stored in byte group W0, M A2 is stored in X0, M A1 is stored in Y0, and M A0 is stored in Z0. The floating point number B is stored as follows: B is stored in byte group Y1, M B2 is stored in Z1, M B1 is stored in W1 and M B0 is stored in X1. The floating point number C is stored as follows: S C is stored in byte group X2, M C2 is stored in W2, M C1 is stored in Z2, M C0 is stored in Y2. The floating point number D is stored as follows: D is stored in byte group Z3, M D2 is stored in Y3, MD1 is stored in X3, M D0 is stored in W3. The pattern then repeats, and floating point number E is stored using the same part-to-rank assignment as floating point number A: S E is stored in byte group W0, M E2 is stored in X0, M E1 is stored in Y0 and M E0 is stored in Z0. This mode is for additional floating point numbers (e.g., F, G, H, etc., for simplicity, in FIG. 6A to FIG. 6D ) continue.

[0061] Figure 6B The diagram illustrates the storage and access of a first FLOAT32* formatted number. This first number (FLOAT32*-A) is stored at a column group address of zero (0). Therefore, in order to access (read or write) FLOAT32*-A, the W0, X0, Y0, and Z0 column groups need to be accessed. Therefore, in Figure 6B In, S A Stored in the W0 column group of array W 651; M A2 Stored in the X0 column group of array X 652; M A1 is stored in the Y0 column group of array Y 653; and M A0 is stored in the Z0 column group of array Y 654. When the first FLOAT32* format number is read, array W 651 stores the retrieved S via column group W0. A The value is provided to the W byte interface 661; the array X 652 retrieves the M bytes via the column group X0. A2 The value is provided to the X byte interface 662; the array Y 653 retrieves the M through the column group Y0. A1 The value is provided to the Y byte interface 663; and the array Z 654 sends the retrieved M through the column group Z0. A0 The value is provided to the Z byte interface 664.

[0062] Figure 6C The storage and access of a second FLOAT32* format number is illustrated. This second number (FLOAT32*-B) is stored at a column group address of one (1). Therefore, to access (read or write) FLOAT32*-B, the W1, X1, Y1, and Z1 column groups are accessed. Therefore, in Figure 6C In, S B Stored in the Y1 column group of array Y 653; M B2 Stored in the Z1 column group of array Z 654; M B1 is stored in the W1 column group of the array W 651; and M B0is stored in the X1 column group of array X 652. When the second FLOAT32* format number is read, array W 651 stores the retrieved M through column group W1. B1 The value is provided to the W byte interface 661; the array X652 retrieves the M bytes via the column group X1. B0 The value is provided to the X byte interface 662; the array Y 653 passes the retrieved S through the column group Y1 B The value is provided to the Y byte interface 663; and the array Z 654 sends the retrieved M through the column group Z1. B2 The value is provided to the Z-byte interface 664. Thus, it will be appreciated that the bytes of the 32-bit value received via the interface 660 may need to be rearranged (eg, by the FP format handler 115) before being used by the processor.

[0063] Fig.6D The use of column offsets to store and access the first two FLOAT16* formatted numbers is illustrated. The first of the two FLOAT16* numbers (FLOAT16*-A) is stored at a column group address of zero (0). The second of the two FLOAT16* numbers (FLOAT16*-B) is stored at a column group address of one (1). Therefore, to access (read or write) the first number (FLOAT16*-A), the W0 and X0 column groups are accessed. To access the second number (FLOAT16*-B), the Y1 and Z1 column groups are accessed. Therefore, when the two FLOAT16* formatted numbers are accessed, arrays W 651 and X 652 are configured (and / or commanded) using a column offset of zero (0). Arrays Y 653 and Z 654 are configured (and / or commanded) using a column offset of one (1). As a result, when accessed, array W 651 sends the retrieved S A The value is provided to the W byte interface 661; the array X 652 retrieves the M bytes via the column group X0. A2 The value is provided to the X-byte interface 662; the array Y 653 retrieves the S B The value is provided to the Y byte interface 663; and the array Z 654 sends the retrieved M through the column group Z1. B2 The value is provided to the Z byte interface 664. Thus, by selecting an offset of 1 for the Y 653 and Z 654 arrays, two different FLOAT16* numbers (eg, FLOAT16*-A and FLOAT16*-B) can be accessed using the same address / transaction.

[0064] Fig. 6EThe use of column offsets to store and access two second FLOAT16* formatted numbers is illustrated. The first of the two second FLOAT16* numbers (FLOAT16*-C) is stored in a column group address of two (2). The second of the two second FLOAT16* numbers (FLOAT16*-D) is stored in a column group address of three (3). Therefore, to access (read or write) the first number (FLOAT16*-C), the W2 and X2 column groups are accessed. To access the second number (FLOAT16*-D), the Y3 and Z3 column groups are accessed. Therefore, when the two second FLOAT16* formatted numbers are read, arrays W 651 and X 652 are configured (and / or commanded) with a column offset of zero (0), and the column address provided to the memory device is set to two (2) (i.e., COL_ADDR=2 - the address of FLOAT16*-C). Arrays Y 653 and Z 654 are configured (and / or commanded) with a column offset of one (1). Thus, when accessed, array W 651 retrieves M via column group W2. C2 The value is provided to the W byte interface 661; the array X 652 retrieves the S C The value is provided to the X byte interface 662; the array Y 653 retrieves the M through the column group Y3. D2 The value is provided to the Y byte interface 663; and the array Z 654 passes the retrieved S D The value is provided to the Z byte interface 664. Thus, by selecting an offset for the X and Y 653 and Z 654 arrays, two different FLOAT16* numbers (e.g., FLOAT16*-C and FLOAT16*-D) can be accessed using the same address / transaction. However, it should be understood that the bytes of the two 16-bit values ​​received via the interface 660 will need to be rearranged (e.g., by the FP format handling device 215) before being used by the processor.

[0065] Fig. 6FThe use of column offsets to store and access four FLOAT8* format numbers is illustrated. The first of the four FLOAT8* numbers (FLOAT8*-A) is stored at a column group address of zero (0). The second of the four FLOAT8* numbers (FLOAT8*-B) is stored at a column group address of one (1). The third of the four FLOAT8* numbers (FLOAT8*-C) is stored at a column group address of two (2). The fourth of the four FLOAT8* numbers (FLOAT8*-D) is stored at a column group address of three (3). Therefore, to access (read or write) the first number (FLOAT8*-A), the W0 column group is accessed. To access the second number (FLOAT16*-B), the Y1 column group is accessed. To access the third number (FLOAT8*-C), the X2 column group is accessed. To access the fourth number (FLOAT8*-D), the Z3 column group is accessed. Thus, when the four FLOAT8* format numbers are accessed, array W 651 is configured (and / or commanded) with a column offset of zero (0); array X 652 is configured (and / or commanded) with a column offset of two (2); array Y 653 is configured (and / or commanded) with a column offset of one (1); and array Z is configured (and / or commanded) with a column offset of three (3). Thus, when accessed, array W 651 retrieves S via column group W0. A The value is provided to the W byte interface 661; the array X 652 retrieves the S C The value is provided to the X byte interface 662; the array Y 653 passes the retrieved S through the column group Y1 B The value is provided to the Y byte interface 663; and the array Z 654 passes the retrieved S D The value is provided to the Z-byte interface 664. Thus, by selecting the appropriate offsets into the W 651, X 652, Y 653, and Z 654 arrays, four different FLOAT8* numbers can be accessed using the same address / transaction.

[0066] Table 1 shows an example byte arrangement for 8 consecutive FLOAT32* accesses.

[0067]

[0068] Table 2 shows an example byte arrangement for 4 consecutive FLOAT16* accesses.

[0069]

[0070] Table 3 shows an example byte arrangement for 2 consecutive FLOAT8* accesses.

[0071]

[0072]

[0073] 7A to 7E The diagram shows the configuration of the memory devices. 7A to 7E , the memory device 700 includes a row decoder 765; memory arrays W 751, X 752, Y 753, and Z 754; precision configuration circuitry 727; column logic 728; W array column access block 755; X array column access block 756; Y array column access block 757; Z array column access block; W array byte 761; X array byte 762; Y array byte 763; Z array byte 764, swizzle circuitry 777; byte zero (0) interface 770; byte one (1) interface 761; byte two (2) interface 772 and byte three (3) interface 773. The column logic 728 may include column sequence logic 729. The column access blocks 755 to 758 may include column decoder logic / circuitry. Column access blocks 755 - 758 may include data path logic / circuitry to access / select / write, etc., columns of corresponding memory arrays 751 - 754 .

[0074] The row address (ROW_ADDR) is supplied to the row decoder 765. The row decoder selects a row in each of the memory arrays 751 to 754. The contents of the selected row in the memory arrays 751 to 754 are supplied to the column decoders 755 to 758, respectively.

[0075] The precision configuration 727 is operably coupled to the column logic 728. As described in Hampel, cited herein, the precision configuration can be utilized to configure the column logic 728, with the offset affecting the selection of the column decoders 755 to 758. The precision configuration 727 can also provide the column logic with precision information that configures (and / or commands) the column logic 727 to receive a first transaction and then generate internal accesses for subsequent bytes without receiving additional transactions. For example, see the discussion of system 200, which will not be repeated here for the sake of brevity.

[0076] The column address (COL_ADDR) is provided to the column logic 728. The column logic provides the column address to the column decoders 755 to 758. These column addresses may be the same or may include one or more offsets. For reading of the memory arrays 751 to 754, the output from the column decoders 755 to 758 is bytes 761 to 764. Bytes 761 to 764 are provided to a hybrid circuit device 777. The output of the hybrid circuit device 777 is provided to the byte interface 770 to 773. For writing to the memory arrays 751 to 754, the value received via the byte interface 770 to 773 is provided to the hybrid circuit device 777. The output of the hybrid circuit device 777 is provided to the column decoders 755 to 758. It should be understood that the use of four (4) 8-bit bytes as the width of the access and interface 760 of the memory device 700 is only an example. Other numbers (e.g., 4, 16, etc.) of bits per interface group and array access width may be selected and may not match each other.

[0077] As reference Figure 6B and Fig.6D As mentioned above, some FLOAT32* and FLOAT16* accesses do not need to be relocated. Figure 7B , where the mixing circuit device 777 is configured (and / or commanded) not to rearrange the bytes received from / transmitted to the column decoders 755 to 758. Therefore, the precision configuration circuit device 727 configures (and / or commands) the mixing circuit device 777 as follows: the byte 0 interface 770 receives bytes from / transmits bytes to the W column decoder 755; the byte 1 interface 771 receives bytes from / transmits bytes to the X column decoder 756; the byte 2 interface 772 receives bytes from / transmits bytes to the Y column decoder 757; and the byte 3 interface 773 receives bytes from / transmits bytes to the Z column decoder 758.

[0078] As reference Figure 6C As mentioned above, some FLOAT32* accesses need to be re-arranged. This is Figure 7C , where the mixing circuit device 777 is configured (and / or commanded) to rearrange the bytes received from the column decoders 755 to 758. Therefore, the precision configuration circuit device 727 configures (and / or commands) the mixing circuit device 777 as follows: the byte 0 interface 770 receives bytes from / transmits bytes to the Y column decoder 757; the byte 1 interface 771 receives bytes from / transmits bytes to the Z column decoder 758; the byte 2 interface 772 receives bytes from / transmits bytes to the W column decoder 755; and the byte 3 interface 773 receives bytes from / transmits bytes to the X column decoder 756.

[0079] As reference Fig. 6E As mentioned above, some FLOAT16* accesses need to be re-arranged. This is Fig.7D , where the mixing circuit device 777 is configured (and / or commanded) to rearrange the bytes received from the column decoders 755 to 758. Therefore, the precision configuration circuit device 727 configures (and / or commands) the mixing circuit device 777 as follows: the byte 0 interface 770 receives bytes from / transmits bytes to the X column decoder 756; the byte 1 interface 771 receives bytes from / transmits bytes to the W column decoder 755; the byte 2 interface 772 receives bytes from / transmits bytes to the Z column decoder 758; and the byte 3 interface 773 receives bytes from / transmits bytes to the Y column decoder 757.

[0080] As reference Fig. 6F As mentioned above, some FLOAT8* accesses need to be re-arranged. This is Fig.7D , where the mixing circuit device 777 is configured (and / or commanded) to rearrange the bytes received from the column decoders 755 to 758. Therefore, the precision configuration circuit device 727 configures (and / or commands) the mixing circuit device 777 as follows: the byte 0 interface 770 receives bytes from / transmits bytes to the W column decoder 755; the byte 1 interface 771 receives bytes from / transmits bytes to the Y column decoder 757; the byte 2 interface 772 receives bytes from / transmits bytes to the Y column decoder 757; and the byte 3 interface 773 receives bytes from / transmits bytes to the Z column decoder 758.

[0081] It should be understood that the configuration of the hybrid circuit device 777 is an example, which is related to the format of the floating point numbers stored in the memory arrays 751-754 (e.g., FLOAT32*, FLOAT16*, etc.) and the arrangement of those numbers in the arrays (e.g., non-contiguous stride, MSB first vs. not first or last, etc.). Other configurations of the hybrid circuit device 777 are contemplated.

[0082] In one embodiment, the memory device 700 may transmit / receive unmixed W bytes, X bytes, Y bytes, and Z bytes. In such an embodiment, the functionality of the mixing circuitry 777 may be implemented in the host system (eg, in the FP format processing block 215 or in software).

[0083] Fig. 8A804a and / or memory column circuitry 805 (e.g., using an offset) to operate with the specified precision. In one embodiment, the memory controller 803a or the processor ( Fig. 8A ) may include a floating point format processor that is dynamically configured (and / or commanded) by the operating system 802a to operate using the specified precision.

[0084] Figure 8B 801 is a diagram illustrating a second example functional hierarchy for storing / retrieving floating point numbers with different precisions. Application software 801 selects the precision (e.g., FLOAT32*, FLOAT16*, etc.) for its calculations and passes the precision configuration information to an operating system 802b. Operating system 802b dynamically configures (and / or commands) a memory controller 803b to operate using the specified precision. Operating system 802b dynamically configures (and / or commands) a memory controller 803b to operate using the specified precision based on the association 803b between memory allocations / apertures (e.g., memory pages, address ranges, etc.) and the associated precision to be used when storing / retrieving data from those corresponding allocations / apertures (e.g., tables). Based on the precision information received from the operating system 802b, the memory controller 803b dynamically configures (and / or commands) the precision control device 804b and / or the memory column circuit device 805 (e.g., using an offset) to operate using the specified precision (e.g., until reconfigured and / or commanded to use other precision).

[0085] Figure 8C801 selects the precision (e.g., FLOAT32*, FLOAT16*, etc.) for its calculations and passes the precision configuration information to the operating system 802c. The operating system 802c dynamically configures (and / or commands) the memory controller 803c to operate using the specified precision. The memory controller 803c dynamically configures (and / or commands) the precision control device 804c and / or the memory column circuit 805 (e.g., using an offset) to operate using the specified precision (e.g., until reconfigured and / or commanded to use a different precision). The memory controller 803c dynamically configures (and / or commands) the precision control device 804c to operate using the specified precision based on the association between memory allocations / wells (e.g., memory pages, address ranges, etc.) and the associated precision used when storing / retrieving data from those corresponding allocations / wells (e.g., tables).

[0086] Fig. 9 is a flow chart illustrating a method of configuring access to floating point numbers with different precisions. Fig. 9 The steps shown may be performed by one or more elements of system 200, system 800a, system 800b, and / or system 800c. Software selects precision for an upcoming operation (902). For example, application software 801 may select precision for an operation to be performed. The operating system communicates the precision to a memory controller (904). For example, operating system 802a may dynamically configure (and / or command) memory controller 803a using information related to precision associated with memory allocation.

[0087] The memory controller sets the current precision in the precision control block (906). For example, the memory controller 803a can use the precision information to dynamically configure (and / or command) the precision control device 804a. The memory controller creates a request for a physical address (908). For example, the memory controller 803a can create a request for: retrieving one or more floating point numbers from an allocation / hole / range of memory associated with a given precision. The precision control block determines the column address and column offset based on the precision configuration (910). For example, the precision control device 804a can determine the column address and offset based on the precision configured (and / or commanded) according to Table 1, Table 2, or Table 3. The memory device executes the request (912). Once the request is executed, the memory controller determines whether the precision and / or precision configuration has changed (914). If not, the process proceeds to box 908. If the precision has been changed by the operating system, the process proceeds to box 906.

[0088] Fig.10is a block diagram of a processing system that uses a stack of memory devices to store floating-point numbers with varying degrees of precision. Fig.10 , system 1000 includes a processor 1010, a memory controller 1012, and a memory 1020. The memory 1020 includes a base layer 1026 and a memory layer 1027. The base layer 1026 includes a precision control block 1029. The processor 1010 is operably coupled to the memory controller 1012. The memory controller 1012 is operably coupled to the memory 1020. Specifically, the memory controller 1012 is operably coupled to the memory layer 1027 and the precision control block 1029. The precision control block 1029 is also operably coupled to the memory layer 1027. The precision control block 1029 can be configured (and / or commanded) by the memory controller 1012 using precision information (e.g., offset and address span). The precision control block 1029 can configure the memory layer 1027 using offset or other precision configuration information. The precision control block 1029 can generate an address sent to the memory layer 1027 based on the precision configuration information.

[0089] Fig.11 is a block diagram of a processing system that uses memory modules to store floating-point numbers with varying degrees of precision. Fig.11 , system 1100 includes a processor 1110, a memory controller 1112, and a memory module 1120. The memory module 1120 includes a memory device 1121 and a buffer 1126. The buffer 1126 includes a precision control block 1129. The processor 1110 is operably coupled to the memory controller 1112. The memory controller 1112 is operably coupled to the module 1120. Specifically, the memory controller 1112 is operably coupled to the memory device 1121 and the buffer 1126. The buffer 1126 distributes commands and addresses to the memory device 1121. The precision control block 1129 can be configured (and / or commanded) by the memory controller 1112 using precision information (e.g., offset and address span). The precision control block 1129 can configure the memory device 1121 using the offset or other precision configuration information. The precision control block 1129 can generate an address sent to the memory device 1121 based on the precision configuration information.

[0090] Fig.12 is a block diagram of a processing system that uses directly attached memory devices to store floating-point numbers with varying degrees of precision. Fig.12, system 1200 includes a processor 1210, a memory controller 1212, and a memory device 1220. The memory device 1220 includes a precision control block 1229 and a memory core 1221. The processor 1210 is operably coupled to the memory controller 1212. The memory controller 1212 is operably coupled to the memory device 1220. The precision control block 1229 can be configured (and / or commanded) by the memory controller 1212 using precision information (e.g., offset and address span). The offset or other precision configuration information can be used by the precision control block 1229, and a column address sent to the memory core 1221 can be generated based on the precision configuration information.

[0091] The above methods, systems and devices can be implemented in a computer system or stored by a computer system. The above methods can also be stored on a non-transitory computer-readable medium. The devices, circuits and systems described herein can be implemented using computer-aided design tools available in the art and embodied by computer-readable files containing software descriptions of such circuits. This includes but is not limited to one or more elements of system 200, device 700, system 800a, system 800b, system 800c, system 1000, system 1100 and / or system 1200 and components thereof. These software descriptions may be: descriptions of behavior, register transfer, logic components, transistors and layout geometry levels. In addition, the software description can be stored on a storage medium or communicated via a carrier wave.

[0092] Data formats that can implement such descriptions include, but are not limited to, formats that support behavioral languages ​​(e.g., C), formats that support register transfer level (RTL) languages ​​(e.g., Verilog and VHDL), formats that support geometric description languages ​​(e.g., GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfer of such files on machine-readable media can be electronically performed on various media on the Internet or electronically, for example, via email. Please note that the physical file can be implemented on a machine-readable medium (such as, 4 mm tape, 8 mm tape, 3-1 / 2 inch floppy disk media, CD, DVD, etc.).

[0093] Fig.13 13 is a block diagram illustrating one embodiment of a processing system 1300 for including, processing, or generating representations of circuit components 1320. Processing system 1300 includes one or more processors 1302, memory 1304, and one or more communication devices 1306. Processor 1302, memory 1304, and communication devices 1306 communicate using any suitable type, number, and / or configuration of wired and / or wireless connections 1308.

[0094] Processor 1302 executes instructions of one or more processes 1312 stored in memory 1304 to process and / or generate circuit components 1320 in response to user input 1314 and parameters 1316. Process 1312 can be any suitable electronic design automation (EDA) tool or part thereof used to design, simulate, analyze and / or verify electronic circuit devices and / or generate photomasks for electronic circuit devices. As shown, representation 1320 includes data describing all or part of system 200, device 700, system 800a, system 800b, system 800c, system 1000, system 1100, and / or system 1200 and components thereof.

[0095] The representation 1320 may include one or more of behavioral, register transfer, logic component, transistor, and layout geometry level descriptions. Furthermore, the representation 1320 may be stored on a storage medium or communicated via a carrier wave.

[0096] The data formats in which representation 1320 may be implemented include, but are not limited to, formats supporting behavioral languages ​​(e.g., C), formats supporting register transfer level (RTL) languages ​​(e.g., Verilog and VHDL), formats supporting geometric description languages ​​(e.g., GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data delivery of such files on machine-readable media may be performed electronically over various media on the Internet, or, for example, via email.

[0097] User input 1314 may include input parameters from a keyboard, mouse, voice recognition interface, microphone and speaker, graphical display, touch screen, or other type of user interface device. The user interface may be distributed among multiple interface devices. Parameters 1316 may include specifications and / or characteristics entered to help define representation 1320. For example, parameters 1316 may include information defining device type (e.g., NFET, PFET, etc.), topology (e.g., block diagram, circuit description, schematic), and / or device description (e.g., device properties, device size, supply voltage, simulation temperature, simulation model, etc.).

[0098] Memory 1304 includes non-transitory computer-readable storage media that stores any suitable type, number, and / or configuration of processes 1312 , user inputs 1314 , parameters 1316 , and circuit components 1320 .

[0099] The communication device 1306 includes any suitable type, number, and / or configuration of wired and / or wireless devices, and the communication device 1306 transmits information from the processing system 1300 to another processing or storage system (not shown) and / or receives information from another processing or storage system (not shown). For example, the communication device 1306 can transmit the circuit component 1320 to another system. The communication device 1306 can receive the process 1312, the user input 1314, the parameter 1316, and / or the circuit component 1320, and cause the process 1312, the user input 1314, the parameter 1316, and / or the circuit component 1320 to be stored in the memory 1304.

[0100] The implementation methods discussed in this article include but are not limited to the following examples:

[0101] Example 1: A memory device comprises: a command interface for receiving an access command, the access command comprising information indicating the number of consecutive transactions to be executed in response to the corresponding access command; and the number of consecutive transactions is configurable to correspond to at least a first precision number format and a second precision number format.

[0102] Example 2: The memory device of example 1, wherein the number of consecutive transactions executed is higher for the first precision number format as compared to the second precision number format.

[0103] Example 3: The memory device of Example 1, wherein the access command comprises a read command and a write command.

[0104] Example 4: The memory device of Example 3, wherein the write command includes information indicating a number of memory locations to be set to a selected value.

[0105] Example 5: The memory device of example 4, wherein the selected value is configurable in response to information received via the command interface.

[0106] Example 6: The memory device of Example 5, wherein the selected value is stored in at least one register internal to the memory device.

[0107] Example 7: The memory device of example 4, wherein the selected value corresponds to zero.

[0108] Example 8: A method of accessing floating point numbers in a memory device, comprising: storing a first floating point number with a first precision by storing a first plurality of bit blocks in a first non-contiguously addressed location, the first plurality of bit blocks comprising a first subset of the first plurality of bit blocks, the first subset of the first plurality of bit blocks corresponding to a second precision version of the first floating point number; and retrieving a second floating point number from a second non-contiguously addressed location by retrieving the first subset of the first plurality of bit blocks, the second floating point number being the second precision version of the first floating point number.

[0109] Example 9: The method of Example 8, wherein the second precision is less than the first precision.

[0110] Example 10: The method according to Example 8 also includes: storing a third floating point number with the first precision by storing a second plurality of bit blocks in a second non-contiguously addressed location, the second plurality of bit blocks including a second subset of the second plurality of bit blocks, the second subset of the second plurality of bit blocks corresponding to the second precision version of the third floating point number; and retrieving a fourth floating point number from the third non-contiguously addressed location by retrieving the second subset of the second plurality of bit blocks, the fourth floating point number being the second precision version of the second floating point number.

[0111] Example 11: The method of Example 10, wherein the second non-contiguously addressed locations are respectively addressed contiguously with the first non-contiguously addressed locations.

[0112] Example 12: The method of Example 8, wherein the first plurality of bit blocks includes a second subset of the first plurality of bit blocks, the second subset of the first plurality of bit blocks being set to a selected value.

[0113] Example 13: The method of Example 12, wherein the selected value is configurable in response to information received via a command interface.

[0114] Example 14: The method of Example 12, wherein the selected value corresponds to zero.

[0115] Example 15: A controller comprising: access circuit means for receiving a first plurality of floating point numbers from at least one memory device and via a first plurality of consecutive memory transactions, a first plurality of portions of the first plurality of floating point numbers being received from non-consecutively addressed locations, wherein each portion of the first plurality of portions is received in response to a different memory transaction in the first plurality of consecutive memory transactions; and floating point number assembly circuit means for receiving the first portions of the first plurality of floating point numbers and arranging the first portions of the first plurality of floating point numbers into the first plurality of floating point numbers.

[0116] Example 16: The controller of Example 15, wherein the floating point number assembly circuit device is configurable to arrange at least floating point numbers having a first precision, and floating point numbers having a second precision different from the first precision.

[0117] Example 17: The controller according to Example 15 also includes: a floating point number deassembling circuit device, which is used to receive a second plurality of floating point numbers and to transmit a second plurality of parts of the corresponding second plurality of floating point numbers through a second plurality of consecutive memory transactions, wherein the second plurality of parts of the corresponding second plurality of floating point numbers will each be stored in non-contiguously addressed locations, and each of the second plurality of parts will be transmitted as part of a different memory transaction in the second plurality of consecutive memory transactions.

[0118] Example 18: The controller of Example 17, further comprising: floating point number rounding circuitry to set a subset of the second plurality of portions of the corresponding second plurality of floating point numbers to a selected value.

[0119] Example 19: The controller of Example 18, wherein the selected value is configurable in response to information received via a command interface.

[0120] Example 20: The controller of Example 18, wherein the selected value corresponds to zero.

[0121] The foregoing description of the invention has been given for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations are possible in light of the above teachings. The embodiments are selected and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to best utilize the invention in various embodiments and various modifications suitable for the specific use contemplated. Unless limited by the prior art, the appended claims are intended to be interpreted as including other alternative embodiments of the invention.

Claims

1. A memory device, comprising: a command interface to receive an access command, the access command comprising information indicating a number of consecutive transactions to be performed in response to the corresponding access command, the access command comprising a read command and a write command, and the write command comprising information indicating a number of memory locations at which the selected value is to be set; and The number of consecutive transactions may be configured to correspond to at least a first precision number format and a second precision number format. 2 . The memory device of claim 1 , wherein the number of consecutive transactions executed for the first precision number format is higher than for the second precision number format.

3. The memory device of claim 1, wherein the number of consecutive transactions is further configurable to correspond to at least a third precision number format.

4. The memory device of claim 1, wherein the selected value is configurable in response to information received via the command interface.

5. The memory device of claim 4, wherein the selected value is stored in at least one register internal to the memory device. The memory device of claim 1 , wherein the selected value corresponds to zero.

7. A method for accessing floating point numbers in a memory device, comprising: storing a first floating point number with a first precision by storing a first plurality of blocks of bits in first non-contiguously addressed locations, the first plurality of blocks of bits comprising a first subset of the first plurality of blocks of bits, the first subset of the first plurality of blocks of bits corresponding to a second precision version of the first floating point number; as well as A second floating point number is retrieved from a second non-contiguously addressed location by retrieving the first subset of the first plurality of blocks of bits, the second floating point number being the second precision version of the first floating point number. The method of claim 7 , wherein the second precision is less than the first precision.

9. The method according to claim 7, further comprising: storing a third floating point number at the first precision by storing a second plurality of blocks of bits in second non-contiguously addressed locations, the second plurality of blocks of bits comprising a second subset of the second plurality of blocks of bits, the second subset of the second plurality of blocks of bits corresponding to the second precision version of the third floating point number; as well as A fourth floating point number is retrieved from a third non-contiguously addressed location by retrieving the second subset of the second plurality of blocks of bits, the fourth floating point number being the second precision version of the second floating point number.

10. The method of claim 9, wherein the second non-contiguously addressed locations are addressed contiguously with respect to the first non-contiguously addressed locations.

11. The method of claim 7, wherein the first plurality of blocks of bits comprises a second subset of the first plurality of blocks of bits, the second subset of the first plurality of blocks of bits being set to a selected value.

12. The method of claim 11, wherein the selected value is configurable in response to information received via a command interface. The method of claim 11 , wherein the selected value corresponds to zero.

14. A controller comprising: access circuitry to receive a first plurality of floating point numbers from at least one memory device and via a first plurality of consecutive memory transactions, a first plurality of portions of the first plurality of floating point numbers being received from non-consecutively addressed locations, wherein each portion of the first plurality of portions is received in response to a different memory transaction of the first plurality of consecutive memory transactions; as well as The floating point number assembly circuitry is configured to receive the first plurality of portions of the first plurality of floating point numbers and to arrange the first plurality of portions of the first plurality of floating point numbers into the first plurality of floating point numbers.

15. The controller of claim 14, wherein the floating point number assembly circuitry is configurable to arrange at least floating point numbers having a first precision, and floating point numbers having a second precision different from the first precision.

16. The controller according to claim 14, further comprising: and floating point number deassembling circuitry to receive a second plurality of floating point numbers and to transmit a second plurality of portions of the second plurality of floating point numbers via a second plurality of consecutive memory transactions, the second plurality of portions of the second plurality of floating point numbers being each to be stored in non-consecutive addressed locations, wherein each portion of the second plurality of portions is transmitted as part of a different memory transaction in the second plurality of consecutive memory transactions.

17. The controller according to claim 16, further comprising: Floating point number rounding circuitry is provided for setting a subset of the second plurality of portions of the corresponding second plurality of floating point numbers to selected values.

18. The controller of claim 17, wherein the selected value is configurable in response to information received via a command interface.

19. The controller of claim 17, wherein the selected value corresponds to zero.

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