High voltage semiconductor device with improved electric field suppression

Abstract

A semiconductor device (16) is provided. The semiconductor device (16) includes an electric field (E-field) suppression layer (36) formed on a termination region. The E-field suppression layer (36) is patterned to form an opening on a metal contact region (66). The thickness of the E-field suppression layer (36) is such that when the semiconductor device (16) is operated at or below a maximum voltage, the electric field strength above the E-field suppression layer (36) is lower than the dielectric strength of adjacent materials.

Description

Technical Field

[0001] The subject matter disclosed herein relates to semiconductor devices and, more particularly, to semiconductor devices with improved electric field suppression. Background Art

[0002] Power electronic systems, such as power conversion systems, are widely used in modern electrical systems to convert power from one form to another for consumption by a load. In this power conversion process, many power electronic systems use various semiconductor devices and components, such as thyristors, diodes, and various types of transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs), junction gate field effect transistors (JFETs), insulated gate bipolar transistors (IGBTs), and other suitable transistors. Various semiconductor devices can be included in power electronic systems to control the flow of current in a circuit. In particular, semiconductor devices, such as transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs)) can be utilized. However, while specific types of transistors or other semiconductor devices may be used in high power applications due to certain benefits provided by selecting such transistors, there may be many design considerations and challenges for each type of transistor to ensure reliable operation.

[0003] A semiconductor device often used in power electronic systems is the silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET). The potential performance advantages of SiC MOSFET in high power, high frequency power switching applications have been recognized. For example, SiC allows for high critical electric field strengths (2-3MV / cm), which is about 10 times higher than that achievable using semiconductor devices (e.g., transistors) manufactured on silicon (Si) substrates. Therefore, the use of SiC substrates provides devices with high voltage, high frequency, and high efficiency performance, because SiC unipolar devices (JFET, MOSFET) provide low losses in voltage levels that Si unipolar devices cannot. However, the high electric fields associated with SiC materials under blocking conditions (and the interaction of the electric fields with the dielectric system above the SiC surface) complicate the design, manufacture, and testing of SiC MOSFET devices.

[0004] In particular, the use of SiC as a material for high-voltage power devices presents challenges during manufacturing and high-voltage testing in wafer and die form in power modules. In wafer and die form, the high-voltage termination region is typically covered with a material of low dielectric strength, such as air when the device is in wafer form, and silicone when the device is in module form. When the device is tested under certain conditions (e.g., high-voltage reverse bias conditions), the electric field can extend beyond the semiconductor substrate and through the insulating layer, which is fabricated as a passivation layer on the termination region. The electric field strength may exceed the capability of the material on the passivation layer, causing reliability risks or dielectric failures (arcing).

[0005] Embodiments described herein may address one or more of the above challenges. Summary of the invention

[0006] In one embodiment, a semiconductor device is provided. The semiconductor device includes an electric field (E-field) suppression layer formed on a termination region. The E-field suppression layer is patterned to have an opening on a metal contact region. The thickness of the E-field suppression layer is such that when the semiconductor device is operated at or below a maximum voltage, the electric field strength above the E-field suppression layer is lower than the dielectric strength of an adjacent material.

[0007] In another embodiment, a semiconductor device including a metal oxide semiconductor field effect transistor (MOSFET) element is provided. The semiconductor device also includes one or more isolation layers formed on the surface of the MOSFET element. Further, the semiconductor device includes a patterned electric field (E field) suppression layer formed on the one or more isolation layers, wherein the E field suppression layer is configured to suppress the electric field strength generated by the MOSFET element, so that when the semiconductor device is operated at a maximum voltage or below the maximum voltage, the electric field strength above the E field suppression layer is lower than the dielectric strength of the adjacent material.

[0008] In a further embodiment, a semiconductor device is provided. The semiconductor device includes a silicon carbide (SiC) substrate, a termination region formed on the SiC substrate, and a metal contact region formed on the SiC substrate. The semiconductor device also includes an electric field (E-field) suppression layer formed on the termination region, wherein the E-field suppression layer is patterned to have an opening on the metal contact region, and wherein the E-field suppression layer includes a thickness such that when the semiconductor device is operated at or below a maximum voltage, an electric field strength above the E-field suppression layer is lower than a dielectric strength of an adjacent material. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] These and other features, aspects and advantages of the present invention will be better understood when the following detailed description is read with reference to the accompanying drawings, wherein like characters represent like parts throughout the drawings, and wherein:

[0010] Figure 1 is a block diagram of a power electronic system including a semiconductor device according to an embodiment of the present disclosure;

[0011] Figure 2 is a cross-sectional view of a termination region of a silicon carbide (SiC) semiconductor device that may be used in a power electronics system;

[0012] Figure 3 is a cross-sectional view of a termination region of a silicon carbide (SiC) semiconductor device that can be used in a power electronic system according to an embodiment of the present disclosure;

[0013] Figure 4 The effect of various materials and temperatures on Figure 3 Modeling results of the electric field intensity above the surface of the SiC semiconductor device;

[0014] Figure 5 A wafer having an E-field suppression layer manufactured thereon according to an embodiment of the present invention is shown;

[0015] Fig. 6A and 6B A top view and a side view respectively show a portion of a SiC semiconductor device manufactured according to an embodiment of the present invention;

[0016] Fig. 7A and 7B A top view and a side view respectively show a portion of a SiC semiconductor device manufactured according to another embodiment of the present invention; and

[0017] Fig. 8A and 8B A top view and a side view respectively show a portion of a SiC semiconductor device manufactured according to another embodiment of the present invention. DETAILED DESCRIPTION

[0018] One or more specific embodiments are described below. In order to provide a concise description of these embodiments, not all features of the actual implementation are described in the specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, many implementation-specific decisions must be made to achieve the developer's specific goals, such as complying with system-related and business-related constraints, which may vary from implementation to implementation. In addition, it should be understood that such development work may be complex and time-consuming, but it is still a routine task of design, manufacture, and preparation for ordinary technicians who benefit from this disclosure.

[0019] Unless otherwise defined, the technical and scientific terms used herein have the same meanings as those of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second", etc. used herein do not represent any order, quantity or importance, but are used to distinguish one element from another. In addition, when introducing the elements of the various embodiments of the present disclosure, the articles "one", "a kind of" and "the" are intended to represent the presence of one or more elements. The terms "include", "comprise" and "have" are intended to be inclusive, and mean that there may be other elements in addition to the listed elements. If a range is disclosed, the endpoints of all ranges for the same parts or properties are included and can be independently combined. The modifier "approximately" related to quantity includes the value and has the meaning of contextual provisions (for example, including the degree of process variation or error associated with the measurement of a specific quantity).

[0020] As used herein, the term "layer" refers to a material arranged on at least a portion of the lower surface in a continuous or discontinuous manner. In addition, unless otherwise specified, the term "layer" does not necessarily mean a uniform thickness of the arranged material, and the arranged material can have a uniform or variable thickness. In addition, unless the context clearly specifies otherwise, the term "layer" used herein refers to a single layer or multiple layers. In addition, as used herein, unless otherwise specifically specified, the phrases "arranged on", "sputtered on" or "deposited on" refer to layers being arranged in direct contact with each other or indirectly arranged by having an intermediate layer therebetween. As used herein, the term "adjacent" refers to two layers being arranged continuously and in direct contact with each other. In addition, the term "on..." describes the relative position of the layers / regions to each other and does not necessarily mean "on the top...", because the relative position above or below depends on the orientation of the device to the observer. In addition, the use of "top", "bottom", "above", "below", "on" and variations of these terms is for convenience, and unless otherwise specified, any specific orientation of the components is not required. With this in mind, as used herein, the terms "lower," "middle," or "bottom" refer to features that are relatively closer to the substrate layer, while the terms "top" or "upper" refer to a particular feature that is relatively farthest from the substrate layer.

[0021] Various semiconductor devices may be included in the power conversion system. In particular, semiconductor devices such as transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs), junction field effect transistors (JFETs), or insulated gate bipolar transistors (IGBTs)) and power diodes may be utilized. It should be understood that although the present embodiment is described herein in the context of metal oxide semiconductor field effect transistors (MOSFETs), some of the present technology may be applicable to other types of semiconductor device structures, such as other types of transistors or other semiconductor devices for high voltage systems. In addition, although the presently described embodiments have been tested to provide particular benefits to semiconductor devices based on silicon carbide (e.g., SiC MOSFETs), for example, the present embodiment may also provide benefits to semiconductor devices using other substrate materials, such as silicon (Si), silicon carbide (SiC), germanium (Ge), aluminum nitride (AlN), gallium nitride (GaN), gallium arsenide (GaAs), diamond (C).

[0022] The technical effect of an embodiment of the present invention is to provide a durable semiconductor device that can be used in high voltage systems and can be tested in wafer form at full voltage and rated temperature without the need for special probing techniques for arc suppression (e.g., probing with a removable liquid dielectric layer or using a high voltage probing chamber) and can be tested in wafer form at full voltage and rated temperature. The present embodiment provides a semiconductor device, such as a SiC MOSFET device, having certain areas, such as termination areas, covered with a strong, compliant, thick dielectric electric field (E-field) suppression layer that is compatible with commercial manufacturing and sufficient to reduce the edge field strength to below the strength required for reliable module use (where the device is encapsulated in silicone) or below the dielectric strength of air to avoid arcing when probing in wafer form or wafer form, even at rated temperature.

[0023] More specifically, the E-field suppression layer can be patterned and arranged on the device termination area to avoid any arcing under high voltage testing, such as reverse bias at full voltage and rated high temperature. In one embodiment, the E-field suppression layer is a dielectric polyimide that can be provided and patterned in roll or sheet form. The metal contact areas on the upper surface of the SiC MOSFET are kept exposed by the patterned thick E-field suppression layer for wire bonding or other contact schemes. The E-field suppression layer can be separated from the wafer during the wafer sawing process and retained as part of the unpackaged wafer for discrete packaging or for power modules, where the E-field suppression layer prevents reliability failures associated with high electric fields. The thickness of the E-field suppression layer is sufficient to suppress or contain electric field arcing that may occur above the surface of the SiC MOSFET during high voltage testing.

[0024] The technical effect of this embodiment allows semiconductor devices to be tested at full rated voltage and temperature without using special test equipment and reducing the risk of damaging the semiconductor device or the test equipment. Confidence in the yield of "known good wafers" for wafer detection is improved and reliability risks are reduced. Quality problems caused by insufficient dielectric strength (i.e., air gaps at terminations due to filling problems or bubbles) can be determined at the wafer level before the wafers are assembled into high-value components, thereby reducing the costs associated with scrapped devices after assembly.

[0025] In addition, the disclosed embodiments mitigate failures that may be associated with defects that may only be detectable by visual inspection, but visual inspection is difficult or impossible during device manufacturing. For example, at certain points in the semiconductor device manufacturing process, it may not be possible to visually inspect quality defects in or through a transparent gel or component used to manufacture the device. Such visual inspection is often required to locate debris generated by soldering or welding operations associated with the manufacture of semiconductor devices (e.g., SiC MOSFETs), or to identify other undesirable particles that may affect device operation or reliability. The inability to perform visual inspection at certain points may be due to a lack of visual ability (no line of sight) to see the wafer being assembled, or because there may be no non-destructive testing methods to inspect through surrounding materials (e.g., gel). Advantageously, the semiconductor device currently described with a thick E-field suppression layer on the termination area will mitigate failures that may be associated with bubbles or particles in previous designs, thereby eliminating the need for visual inspections that may be beneficial in previous designs to prevent device failures. Therefore, the present embodiments provide wafer-level full voltage ratings that provide higher quality and more reliable parts. Furthermore, in module construction, the E-field in the gel can be kept below the material rated dielectric strength rating, thereby avoiding reliability issues that may be associated with particles and bubbles.

[0026] Further, according to the embodiments provided herein, a power overlay (POL) structure can be advantageously employed to bond to a SiC MOSFET. As the device current density increases, the total current of the device may be limited by the current carrying capacity (e.g., limited cross-sectional area) of the wire connection to the source bond. This is particularly true for smaller wafers with a relatively large area of ​​the wafer for termination. As provided herein, an E-field suppression layer formed on the termination area can be used as a POL dielectric layer, which is combined with a POL metallization layer to form a POL structure that redistributes the bonding area to be larger than the original pad size. The disclosed POL structure, including an E-field suppression layer disposed on the termination area, can also provide re-metallization to be compatible with various metal types and various bonding techniques.

[0027] As a further technical effect according to the presently described embodiments, because the wafer termination region of a semiconductor device typically produces the highest field in the design, implementing an E-field suppression layer at the termination region can reduce electrical requirements in subsequent device packaging, broadening the allowable material properties. This can allow higher voltage wafers to be integrated with lower voltage module design features. In addition, the E-field suppression layer provides stress buffering (which may damage the device if such a layer is not provided), which can allow the use of rigid packaging materials, thereby providing larger volume device sizes or more complex 3D module shapes.

[0028] Considering the foregoing, Figure 1 A block diagram of an embodiment of a power electronics system 10 (e.g., a power conversion system, a switching system, etc.) is illustrated. The power electronics system 10 may include a power supply 12, an electrical load 14, at least one semiconductor device 16 (e.g., a switching device), and a controller 18 (e.g., an electronic control unit). The power supply 12 may include an alternating current (AC) power supply or a direct current (DC) power supply. In some embodiments, the power supply 12 may include a power grid, a generator, a battery, etc. The power supply 12 may be electrically connected to the semiconductor device 16 and may provide current (e.g., AC current or DC current) to the semiconductor device 16. In addition, at least one semiconductor device 16 may be electrically connected to the electrical load 14 and may supply current (e.g., AC current or DC current) to the electrical load 14. The electrical load 14 may include a DC load or an AC load. In some embodiments, the electrical load 14 may be configured to store power and / or use power to perform operations. For example, the electrical load 14 may include a battery, a computer, a motor, etc.

[0029] The semiconductor device 16 may be communicatively coupled to the controller 18 via one or more wired and / or wireless connections. In some embodiments, the controller 18 may include one or more processors and one or more memory devices (e.g., tangible, non-transitory, computer-readable media) storing instructions executable by the one or more processors. In certain embodiments, the controller 18 may include a logic array and / or a control circuit. The controller 18 may be configured to switch the semiconductor device 16 between a conductive state (e.g., an on state) and a non-conductive state (e.g., an off state). In addition, the semiconductor device 16 may be configured to control the flow of current from the power source 12 to the electrical load 14. In particular, when the semiconductor device 16 is in the conductive state, the semiconductor device 16 may allow or enable current to flow from the power source 12 to the electrical load 14. In addition, when the semiconductor device 16 is in the non-conductive state, the semiconductor device 16 may prevent current from flowing from the power source to the electrical load 14. According to one embodiment, semiconductor device 16 includes a silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET) fabricated to include a thick dielectric layer patterned on a termination region, as summarized above and described in further detail below. In some embodiments, controller 18 may be configured to control semiconductor device 16 to convert AC current from power source 12 into DC current.

[0030] Figure 2 Yes, you can Figure 1 1 is a cross-sectional view of an embodiment of a portion of a semiconductor device 16 used in a power electronic system 10. In particular, Figure 2 The semiconductor device 16 shown is a portion of a planar n-channel silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET), hereinafter referred to as a SiC MOSFET device 20. As previously described, during operation and testing of the device, the termination region of the SiC MOSFET device 20 may exhibit high electric fields, particularly under certain operating conditions, as discussed in detail below. Therefore, the illustrated SiC MOSFET device 20 is described in conjunction with the provided experimental data and simulation results to demonstrate certain reliability issues that have been identified and may be associated with testing SiC MOSFET devices in wafer form and die form. In particular, only the termination region of the SiC MOSFET device 20 is illustrated to more clearly describe the experimental / modeling data and the challenges that may be associated with testing SiC MOSFET devices (and other high voltage devices) at full voltage and temperature ratings.

[0031] Figure 2The SiC MOSFET device 20 shown includes a semiconductor substrate layer 22, a semiconductor drift layer 24, a blocking junction 26, and a junction termination region 28. In the above-described embodiments, the semiconductor substrate layer 22 and the semiconductor drift layer 24 may include silicon carbide (SiC). The semiconductor drift layer 24 may be of a first conductivity type (e.g., an n-type drift layer) and may directly interface with (i.e., be arranged in direct contact with) the underlying SiC substrate layer 22. In some embodiments, the semiconductor substrate layer 22 may have a first conductivity type and may be more heavily doped than the semiconductor drift layer 24 (e.g., an n+ substrate layer). The blocking junction 26 may be formed in or on an upper portion of the semiconductor drift layer 24 and may be heavily doped with a second conductivity type (e.g., a p+ blocking junction) to provide a PN junction at the interface with the n-type portion of the semiconductor drift layer 24. A junction termination (JTE) region 28 is provided as a termination of a PN junction between the blocking junction 26 and the semiconductor drift layer 24. The JTE region 28 is a region having a gradient doping profile relative to proximity to the blocking junction 26. That is, the JTE region 28 may be most heavily doped with the second conductivity type (e.g., p+) at the interface with the blocking junction 26. The JTE region 28 becomes progressively more lightly doped as the JTE region 28 extends laterally farther from the interface with the blocking junction 26. This heavy-to-light gradual doping across the JTE region 28 creates a gradient distribution of charge and extends the electric field throughout the region.

[0032] The JTE region 28 described herein provides an illustrative example of a junction termination, and more specifically, the JTE region 28 described herein depicts an illustrative example of a gradient region JTE. However, in some embodiments, an implant region having a second conductivity type (e.g., p-type), such as a floating region, may be additionally or alternatively implemented to have one or more characteristics corresponding to another termination and / or junction termination structure. For example, the implant region may be implemented as a single-region JTE, which may include a single implant region in contact with an intermediate well region, and / or as a multi-region JTE, which may include two or more connected implant regions. In some embodiments, the two or more connected implant regions may have the same or different characteristics, and at least one of the two or more connected implant regions may contact the intermediate well region. In addition, in some embodiments, the implant region may be implemented to form a multi-floating region JTE. In such an embodiment, a first implant region may contact the intermediate well region, and a set of additional implant regions having different spacings and / or widths, such as a floating region, may be disconnected from the first implant region and implanted disconnected from each other. Furthermore, in some embodiments, implant regions (e.g., floating regions) may be implemented to form floating field ring (FFR) terminations. In such embodiments, the floating regions may be implanted disconnected from each other and disconnected from the intermediate well region. Additionally or alternatively, the implant regions may be implemented to form a spatially modulated JTE, which may include a first implant region in contact with the intermediate well region and disconnected from a set of additional implant regions, the first implant region being implanted to form the FFR. Thus, it will be appreciated that the techniques described herein may be applied to any suitable junction termination, such as a single-region JTE, a multi-region JTE, a gradient JTE, a multi-floating region JTE, an FFR, a spatially modulated JTE, and / or the like, and that the embodiments described herein are intended to be illustrative and not limiting.

[0033] As used herein, the terms "semiconductor elements", "transistor elements", "active elements", "active device elements", "MOSFET elements", etc. refer to the layers and materials that make up the portion of the device formed on, in, over, or around the semiconductor material. These terms do not include any dielectric material disposed on the surface of the device. For example, in the illustrated example, the semiconductor elements (transistor elements, active elements, active device elements) of the SiCMOSFET device 20 include a semiconductor substrate layer 22, a semiconductor drift layer 24, a blocking junction 26, and a junction termination region 28. However, the term does not include overlying dielectric or insulating isolation materials described further below.

[0034] As will be appreciated, the SiC MOSFET device 20 may also be coated with multiple dielectric films and insulating layers to provide physical and electrical isolation of the underlying device. For example, the SiC MOSFET device 20 may include a passivation layer 30 and a dielectric layer 32. As further described below, the SiC MOSFET device 20 may be tested in a post-manufacturing material or environment 34 while the SiC MOSFET device 20 is in wafer form or die form before the device is fully packaged. That is, when the SiC MOSFET 20 is still in wafer or die form, element 34 is used herein to designate a test environment.

[0035] The passivation layer 30 may include one or more thin layers of insulating materials (e.g., oxides and nitrides) for forming the passivation layer during typical wafer processing. For example, one or more thin layers forming the passivation layer 30 may be deposited by standard deposition techniques to form the passivation layer 30 with a thickness in the range of about 1-10 microns (μm). In one embodiment of the MOSFET device 20 described in detail below with respect to simulated testing, the passivation layer 30 has a thickness of about 1.8 μm. By way of example, Table 1 provides a list of glass films with various film types, dielectric properties, and possible thicknesses under standard processing, which may be used alone or in combination with each other (or in combination with similar materials) to form the passivation layer 30.

[0036]

[0037] Table 1

[0038] As shown in Table 1, while the dielectric strength of oxide and nitride materials is excellent (e.g., in the range of 3.0E6-10.0E6 V / cm), the thickness of the material in the passivation layer 30 is typically limited to less than 10 μm using standard deposition techniques. Therefore, the passivation layer 30 provides some electrical isolation for the termination region of the SiC MOSFET device 20. However, as described below, this electrical isolation may not be sufficient to completely isolate the active material during high voltage operation.

[0039] To further provide electrical isolation of the underlying termination region of the SiC MOSFET device 20, a dielectric layer 32 may be formed on the passivation layer 30. Polyimides (or similar materials) may be deposited alone or in combination with one another to form the dielectric layer 32, according to standard deposition techniques employed in wafer processing. By way of example, Table 2 provides a list of various polyimides that may be considered for on-wafer termination region coverage and may be deposited by standard techniques used in wafer processing.

[0040]

[0041] Table 2

[0042] It is apparent from Table 2 that while the dielectric strength of polyimide materials is good (e.g., in the range of 2.75E6–4.70E6 V / cm), the thickness of the material in dielectric layer 32 is typically limited to less than 15 μm using standard deposition techniques. While dielectric layer 32 may further isolate the termination region of SiC MOSFET device 20, this layer in combination with passivation layer 30 may not be sufficient to completely isolate the device during high voltage operation.

[0043] When the SiC MOSFET device 20 has been manufactured but is still in wafer form, the device can be electrically probed at the termination area for reliability and functional testing. That is, it is beneficial to test the SiC MOSFET device 20 in wafer form to identify known good chips before the wafer is separated and packaged. The earlier the defect is identified, the less time and material will be wasted on the further processing equipment that will eventually be scrapped. By testing the SiC MOSFET device 20 in wafer form (and again in wafer form, before further packaging), known good wafers can be identified early. Therefore, when the SiC MOSFET device 20 is in wafer form, it is usually probed in the post-manufacturing material (environment) 34 (such as air or gel). It is worth noting that in order to make the electrical test have the best meaning, the SiC MOSFET device 20 should be tested within all possible operating temperatures and electrical limits that the SiC MOSFET device 20 is rated to perform. However, based on the high E field generated in the termination area at high voltage, the electrical probing of the SiC MOSFET device 20 in wafer form may be problematic at full rated power and temperature. For example, it is contemplated that the post-manufacturing material 34 may include one of the materials provided in Table 3.

[0044]

[0045] Table 3

[0046] It is worth noting that at standard temperature and pressure (STP), the dielectric strength of dry air is the lowest among the post-manufacturing materials or test environment 34. Therefore, when testing the SiC MOSFET device 20 in wafer form, the SiC MOSFET device 20 should be able to be tested to its highest rated voltage operation in dry air while maintaining the E field strength measurable at the surface of the SiC MOSFET device 20 to a level equal to or lower than 3.0E4 V / cm. The test results of various embodiments of the above-mentioned SiC MOSFET device 20 having a glass film passivation layer 30 with a thickness of less than 10 μm and a polyimide dielectric layer 32 with a thickness of less than 15 μm show that, without additional materials, Figure 2The design shown is not sufficient to provide complete electrical isolation in typical post-manufacturing materials 34. Specifically, simulation results for testing SiC MOSFET device 20 under reverse bias conditions (1700V) in air indicate that the measurable magnitude of the electric field strength is approximately 2.7E5 V / cm, which is well above the target maximum E-field strength of 3.0E4 V / cm at the surface in air. That is, the described combination of passivation layer 30 and dielectric layer 32 does not provide the necessary protection to avoid arcing during testing of MOSFET device 20 at its high temperature rating limit (e.g., 175°C-200°C) and MOSFET device 20 at its high voltage rating limit (e.g., 1700V under full reverse bias conditions) in gel or air in wafer or die form without dedicated test equipment.

[0047] To mitigate the possibility of arcing over materials formed on the termination regions of the SiC MOSFET devices 20 during wafer testing and die testing, but prior to completed packaging of the SiC MOSFET devices 20, an E-field suppression layer (illustrated and described below) is provided in accordance with an embodiment of the present invention. Figure 3-7B The E-field suppression layer provides further electrical isolation of the termination region of the SiC MOSFET device 20 so that the device can be reliably tested in wafer and die form at all rated temperatures and voltages.

[0048] Certain design considerations were made when selecting materials for the E-field suppression layer that may be deposited, disposed, or generally formed on top of the illustrated dielectric layer 32. Since the material of the dielectric layer 32 has favorable properties, including high dielectric strength, similar dielectric materials were investigated for use in the E-field suppression layer. Simulations were therefore run to simulate the results of a SiC MOSFET device 20 having additional dielectric material on the passivation layer 30 and the dielectric layer 32 to determine the appropriate thickness of a dielectric material having an E-field strength in the range of 2.0E6–5.0E6 V / cm and a dielectric constant in the range of 2.9-3.6 to form the E-field suppression layer to reliably test the SiC MOSFET device 20.

[0049] Figure 3 3 shows a SiC MOSFET device 20 having an E-field suppression layer 36 formed on a dielectric layer 32. According to the embodiments described herein, the E-field suppression layer 36 provides sufficient isolation of the electric field generated on the termination area of ​​the SiC MOSFET device 20 in wafer form or die form at full temperature and rated voltage. Figure 4As described by the simulation test results shown in , depending on the thickness and materials selected for the underlying passivation layer 30 and dielectric layer 32, when using materials with E field strengths in the range of 2.0E6–5.0E6 V / cm and dielectric constants in the range of 2.9-3.6, a sufficient thickness T of the E-field suppression layer 36 was found to be in the range of about 80 μm–100 μm. This range of thickness T of the E-field suppression layer 36 also provides sufficient electrical isolation in a “worst case” test environment of air. As will be appreciated, if the dielectric strength and / or thickness of the passivation layer 30 or dielectric layer 32 is increased, the thickness T of the E-field suppression layer 36 can be reduced to below the range of about 80 μm-100 μm. In certain embodiments, the thickness T can be greater. For example, in other embodiments, the thickness T can be in the range of about 50 μm–200 μm. However, the selection of these materials and deposition techniques typically available in typical manufacturing facilities may limit material selection and thickness capabilities to materials and thicknesses similar to those described with respect to Tables 1 and 2. Furthermore, if the test environment (i.e., post-manufacturing material 34) is known to be something other than air (e.g., silicone), the thickness of E-field suppression layer 36 may also be reduced, as described below with respect to Figure 4 Further described.

[0050] As will also be described, many conventional techniques are unable to deposit materials (such as those described in Table 2 above) to an appropriate thickness range, based on simulation test results, which indicate that for materials having an E field strength in the range of 2.0E6–5.0E6 V / cm and a dielectric constant in the range of 2.9–3.6, the thickness T of the E field suppression layer 36 is in the range of about 80 μm-100 μm. Therefore, other forms of materials are disclosed herein as optional materials for the E field suppression layer 36. For example, polyimide, polybenzoxazole (PBO), or a mixture of the two may be used as the E field suppression layer 36. These materials may be applied to the chip surface as a liquid dielectric that is dispensed, cured, and patterned. The material may be spun cast, dip coated, sprayed, or screen printed. Liquid resin materials may also be additionally applied using additive techniques that may include screen printing, aerosol jet printing, gravure printing, or syringe dispensing. In one embodiment, the thick dielectric for the E-field suppression layer 36 can be provided as a sheet or roll of dry film of polyimide (e.g., Kapton brand). Although polyimide in sheet form is generally described below as a material candidate for the E-field suppression layer 36 and has been demonstrated for its experimental verification, other high temperature dielectric materials are available in sheet form. For example, polyetherimide (Ultem), polyimide, polyetherimide, liquid crystal polymer (LCP) polysulfone, polyetheretherketone (PEEK), polyaryletherketone, epoxy resin, and polybenzoxazole and fluoropolymer or epoxy resin can also provide 100 to 500 micron thick sheets and are also considered.

[0051] refer to Figure 4 , model results 40 are shown. Specifically, a SiC MOSFET device 20 is modeled having a passivation layer 30 and a dielectric layer 32 having properties similar to those described above with respect to Tables 1 and 2 and having an E-field suppression layer (e.g., a polyimide material) 36 formed thereon. Simulated measurements of the E-field strength of the simulated polyimide (along the y-axis 42) are plotted as a function of the distance from the surface of the semiconductor SiC MOSFET device 20 (along the x-axis 44) to determine the thickness of the polyimide E-field suppression layer 36 to adequately suppress the electric field generated in the gel or air under the most extreme operating conditions (e.g., 1700V under full reverse bias conditions). That is, the selection of the thickness of the polyimide E-field suppression layer 36 can be determined so that the electric field strength of the E-field suppression layer 36 is greater than or equal to the dielectric strength of the test environment (i.e., the material 34 after manufacturing). Further considerations can be provided if the dielectric strength of the material 34 after manufacturing varies with temperature (e.g., silicone).

[0052] Referring again to Table 3, if silicone is the post-manufacturing material 34, the dielectric strength of silicone at room temperature (25°C) is about 1.75E5 V / cm and about 1.0E5 V / cm at 175°C. The dielectric strength of air is about 3.0E4 within the standard operating range of the SiC MOSFET device 20. Therefore, the thickness of the E-field suppression layer 36 should be selected to reliably suppress any E-field that may be generated over the termination region of the SiC MOSFET device 20. Returning again to Figure 4 The simulation test results under these three conditions indicate the minimum thickness of the E-field suppression layer 36 to ensure reliable testing over the entire voltage and temperature range of the SiC MOSFET device 20 .

[0053] Specifically, curve 46 models the electric field strength through the thickness of the polyimide and thus provides a threshold thickness for the E-field suppression layer 36 to provide sufficient suppression of the electric field at 1700 V. If the post-fabrication material 34 of the device to be tested is silicone and the SiC MOSFET device 20 is operated at room temperature, a threshold thickness of the E-field suppression layer of about 25 μm will reduce the electric field strength to less than 1.75E5 V / cm, which is sufficient to suppress the maximum E-field that may be generated over the termination region, as shown by point 48 on curve 46. If the post-fabrication material 34 is silicone and the MOSFET device 20 is operated at a temperature of 175° C., a threshold thickness of the E-field suppression layer 36 of about 44 μm will reduce the electric field strength to less than 1.0E5 V / cm, which is sufficient to suppress the maximum E-field that may be generated over the termination region, as shown by point 50 on curve 46. If the post-fabrication material 34 is air and the MOSFET device 20 is operated at any temperature, the threshold thickness of the E-field suppression layer 36 of about 94 μm will reduce the electric field strength above the layer to less than 3.0E4 V / cm, which is sufficient to suppress the maximum E-field that may be generated above the termination area, as shown by point 52 of curve 46. Therefore, in order to allow for a "worst case" test scenario in which the test environment (i.e., the post-fabrication material 34) is air, a total dielectric thickness of about 94 μm should be selected to mitigate reliability risks and / or dielectric failures (i.e., arcing) during testing at the rated voltage and temperature of the MOSFET device 20. That is, the combined thickness of the passivation layer 30, the dielectric layer 32, and the E-field suppression layer 36 should be about 94 μm (or greater) to ensure reliable testing. Therefore, in an embodiment in which the thickness of the passivation layer 30 is about 1.8 μm and the thickness of the dielectric layer 32 is about 12 μm, the thickness of the E-field suppression layer 36 should be greater than or equal to about 82.2 μm.

[0054] Figure 5A test wafer 60 including a plurality of SiC MOSFET devices 20 is shown, which are manufactured and tested according to the present embodiment to provide experimental verification. An enlarged view of a portion 62 of the wafer 60 is provided to better illustrate the SiC MOSFET wafer 20. According to the present embodiment, each wafer includes an E-field suppression layer 36. For testing and verification purposes in wafer form, the passivation layer 30 (not visible) is deposited to a thickness of approximately 1.8 μm. A polyimide Kapton film provided in roll form is adhered to the wafer and provides the E-field suppression layer 36. The combined thickness of the E-field suppression layer 36 and the underlying dielectric layer 32 is approximately 87 μm. Before the film (E-field suppression layer 36) is aligned and adhered to the wafer, the E-field suppression layer 36 is patterned via laser ablation to expose the gate metal 64 and the source pad 66 for detection. The SiC MOSFET device 20 is a 1200 volt rated SiC device that is probed at full breakdown voltage at test temperatures from room temperature to 200°C, and no arcing is observed. In fact, using these materials and thicknesses, the E-field suppression layer 36 was found to reliably contain arcing when operated up to approximately 1800 volts. Notably, the E-field suppression layer 36 may be any material that can be patterned (either before or after deposition or placement on a wafer) to expose underlying contact structures and provide adequate suppression of any electric fields that may be generated by the semiconductor elements of the SiC MOSFET device 20 during normal rated operating conditions (e.g., voltage and temperature).

[0055] Reference now Fig. 6A and 6B , describes other features and benefits of embodiments of the present invention. Specifically, Fig. 6A A top view of a single SiC MOSFET 20 is shown, and Figure 6BA side view of a SiC MOSFET device 20 is illustrated. As shown, the SiC MOSFET 20 includes an E-field suppression layer 36 that is patterned to expose a source metal pad 66. As previously described, the thickness T of the E-field suppression layer 36 (e.g., 80 μm-100 μm) is sufficient to contain any electric field 70 that may be generated in the termination region when the SiC MOSFET device 20 is operated at its highest rated voltage (e.g., 1700 V). In addition to the benefits of the thick E-field suppression layer 36 described previously, because the electric field 70 is reduced to below the level of concern within the E-field suppression layer 36, any particles, debris, or bubbles that may be present on the top surface of the E-field suppression layer 36 will not affect the operation of the device. Therefore, when the SiC MOSFET device 20 is later packaged, thereby eliminating the ability to visually inspect the surface of the device 20 for the presence of such debris, the deleterious effects of any particles, debris, or bubbles (in the packaging material) will be mitigated because within the E-field suppression layer 36, any particles will not react with the residual electric field due to the reduction of the electric field 70. In addition, Fig. 6A and 6B 6 shows a bonding element 72 electrically coupled to the source metal pad 66 to provide an electrical connection to the SiC MOSFET device 20. In one embodiment, the bonding element 72 is an aluminum wedge bonding element that can electrically couple the SiC MOSFET device 20 to an external element, device, or system. It should be understood that other types of bonding elements (e.g., wire bonds, ribbons, etc.) and other conductive metals (e.g., copper, gold, etc.) may be used in certain embodiments.

[0056] Fig. 7A and 7BA top view and a side view of an alternative embodiment of a SiC MOSFET device 20 are shown, respectively, having an improved bonding structure utilizing an electric field suppression layer 36. In order to increase the number of bonding elements 72 and provide better current density for the SiC MOSFET device 20, an additional metallization layer 74 is provided over the entire SiC MOSFET device 20. Advantageously, in addition to the above advantages, the E-field suppression layer 36 can also provide a dielectric layer as an insulating barrier between the metallization layer 74 and the underlying active region of the SiC MOSFET device 20. In this embodiment, the E-field suppression layer 36 and the metallization layer 74 combine to provide a power overlay (POL) structure. The POL structure can be advantageously used to bond to the SiC MOSFET device 20. As the device current density increases, the total current of the device may be limited by the current carrying capacity (e.g., limited cross-sectional area) of the wire connected to the source junction. This is particularly true for smaller wafers with a relatively large area of ​​the wafer for termination. As provided herein, the E-field suppression layer 36 formed on the termination area can be used as a POL dielectric layer, which is combined with the POL metallization layer 74 to form a POL structure that redistributes the bonding area to be larger than the original pad size (i.e., the source metal pad 66) while maintaining electrical isolation from the underlying active area of ​​the SiC MOSFET device 20. The disclosed POL structure, in combination with the E-field suppression layer 36 disposed on the termination area, can also provide re-metallization to be compatible with various metal types and various bonding techniques. For example, the metallization layer 74 can be copper (Cu) and nickel gold (NiAu) for better bonding. Because the size of the metallization layer 74 is larger than the underlying source metal pad 66, the number of bonding elements 72 can be increased. In one embodiment, the bonding element 72 is an aluminum wedge bonding element. In another embodiment, the bonding element 72 is a copper wedge bonding element. It should be understood that other types of bonding elements (e.g., wire bonds, ribbons, etc.) and other conductive metals can be used in certain embodiments.

[0057] Fig. 8A and 8B 1 and 2 show a top view and a side view, respectively, of an alternative embodiment of a SiC MOSFET device 20 having an improved bonding structure utilizing an E-field suppression layer 36 and bonding elements 72 that can reduce the on-resistance of the package during operation. Fig. 7A and 7BAs with the embodiments shown in the drawings, the presently shown embodiments include a POL structure for redistributing the bonding area over a larger area. The POL structure includes an E-field suppression layer 36 (POL dielectric) and a metallization layer 74. The metallization layer 74 can be copper (Cu) and nickel gold (NiAu) for better bonding. In the embodiment shown, the bonding element 72 can be a copper ribbon or copper clip bonding element, which can be electrically and physically connected to the underlying metallization layer 74 using, for example, solder 76. It should be understood that other conductive adhesives can be used instead of solder 76. Advantageously, the use of copper clip bonding can reduce the on-resistance of the package during operation.

[0058] This written description uses examples to disclose the invention, including the best mode, and also to enable those skilled in the art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal language of the claims.

Claims

1. A semiconductor device having a corresponding maximum operating voltage, characterized in that: The semiconductor device comprises: an electric field (E-field) suppression layer formed on a termination region, wherein the E-field suppression layer comprises a film of an isolation layer bonded to the termination region, wherein the E-field suppression layer is patterned to have an opening on a metal contact region, and wherein the E-field suppression layer comprises a thickness such that when the semiconductor device is operated at the maximum voltage, an electric field strength over the E-field suppression layer is lower than a dielectric strength of an adjacent material; The isolation layer includes a passivation layer formed below the E-field suppression layer and a dielectric layer formed of a different material on the passivation layer and below the E-field suppression layer; and A metallization layer is formed at least partially over the E-field suppression layer to form a power overlay (POL) structure configured to expand an underlying bonding area, wherein the POL structure includes the E-field suppression layer, the E-field suppression layer having a thickness in the range of 50 μm-200 μm.

2. The semiconductor device according to claim 1, wherein: The device comprises a transistor, a diode or a thyristor.

3. The semiconductor device according to claim 1, wherein: Further including: substrate; A semiconductor drift layer, wherein the semiconductor drift layer is formed on the substrate; a blocking junction formed in the drift layer; and A junction termination region is formed in the semiconductor drift layer and is laterally adjacent to the blocking junction.

4. The semiconductor device according to claim 3, characterized in that At least one of the substrate or the drift layer comprises silicon carbide (SiC).

5. The semiconductor device according to claim 1, wherein: The maximum voltage is 900 volts to 10KV.

6. The semiconductor device according to claim 1, wherein: The E-field suppression layer includes polyimide, polybenzoxazole (PBO), epoxy resin, bisbenzocyclobutene (BCB), polyetherimide (Ultem), polyetherimide, liquid crystal polymer (LCP), polysulfone, polyetheretherketone (PEEK), polyaryletherketone, fluorine-containing polymer or a combination thereof.

7. The semiconductor device according to claim 1, wherein: The metallization layer is a re-metallization layer.

8. The semiconductor device according to claim 1, wherein: Wherein the metallization layer extends into the opening, and wherein the metallization layer is electrically coupled to the metal contact region through the opening.

9. The semiconductor device according to claim 1, wherein: The E-field suppression layer comprises a material suitable for dry film form.

10. The semiconductor device according to claim 2, wherein: The transistor comprises one of a MOSFET, a JFET or an IGBT.

11. A semiconductor device having a corresponding maximum operating voltage, characterized in that: The semiconductor device comprises: Metal oxide semiconductor field effect transistor (MOSFET) components; one or more isolation layers, the one or more isolation layers formed on a surface of the MOSFET element; a patterned electric field (E-field) suppression layer formed on the one or more isolation layers, wherein the E-field suppression layer comprises a film of an isolation layer of the one or more isolation layers bonded to a termination region of the MOSFET element, wherein the E-field suppression layer is configured to suppress an electric field strength generated by the MOSFET element such that when the semiconductor device is operated at the maximum voltage, an electric field strength above the E-field suppression layer is lower than a dielectric strength of an adjacent material; and a metallization layer formed at least partially over the E-field suppression layer to form a power overlay (POL) structure configured to expand an underlying bonding area, wherein the POL structure includes the E-field suppression layer, the E-field suppression layer having a thickness in the range of 50 μm-200 μm; The one or more isolation layers include a passivation layer formed below the E-field suppression layer and a dielectric layer formed of a different material on the passivation layer and below the E-field suppression layer.

12. The semiconductor device according to claim 11, characterized in that The E-field suppression layer includes polyimide, polybenzoxazole (PBO), epoxy resin, bisbenzocyclobutene (BCB), polyetherimide (Ultem), polyetherimide, liquid crystal polymer (LCP), polysulfone, polyetheretherketone (PEEK), polyaryletherketone, fluorine-containing polymer or a combination thereof.

13. The semiconductor device according to claim 11, characterized in that The E-field suppression layer covers a termination region of the MOSFET element, and the E-field suppression layer is patterned to expose an underlying gate pad, a source pad, or both of the MOSFET element.

14. The semiconductor device according to claim 13, characterized in that Further included is a metallization layer at least partially disposed over the E-field suppression layer and extending into openings of the patterned E-field suppression layer such that the metallization layer is electrically coupled to the underlying gate pad, the source pad, or both of the MOSFET element.

15. The semiconductor device according to claim 14, characterized in that Wherein the metallization layer comprises an area that is larger than an area of ​​the underlying gate pad, the source pad, or both of the MOSFET element.

16. The semiconductor device according to claim 11, wherein The MOSFET element comprises silicon carbide (SiC).

17. A semiconductor device having a corresponding maximum operating voltage, characterized in that: The semiconductor device comprises: Silicon carbide (SiC) substrate; a termination region, the termination region being formed on the SiC substrate; a metal contact region formed on the SiC substrate; an electric field (E-field) suppression layer formed on the termination region, wherein the E-field suppression layer comprises a film of an isolation layer bonded to the termination region, wherein the E-field suppression layer is patterned to have an opening on a metal contact region, and wherein the E-field suppression layer comprises a thickness such that when the semiconductor device is operated at the maximum voltage, an electric field strength over the E-field suppression layer is lower than a dielectric strength of an adjacent material; The isolation layer includes a passivation layer formed below the E-field suppression layer and a dielectric layer formed of a different material on the passivation layer and below the E-field suppression layer; and A metallization layer is formed at least partially over the E-field suppression layer to form a power overlay (POL) structure configured to expand an underlying bonding area, wherein the POL structure includes the E-field suppression layer, the E-field suppression layer having a thickness in the range of 50 μm-200 μm.

18. The semiconductor device according to claim 17, wherein: Wherein the E-field suppression layer comprises a thickness in the range of about 80 μm-100 μm.

19. The semiconductor device according to claim 17, wherein: Wherein the metallization layer extends into the opening, and wherein the metallization layer is electrically coupled to the metal contact region through the opening.

20. The semiconductor device according to claim 17, wherein The E-field suppression layer includes polyimide, polybenzoxazole (PBO), epoxy resin, bisbenzocyclobutene (BCB), polyetherimide (Ultem), polyetherimide, liquid crystal polymer (LCP), polysulfone, polyetheretherketone (PEEK), polyaryletherketone, fluorine-containing polymer or a combination thereof.

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