Analog-to-digital converter stage

Abstract

A stage suitable for use in an analog-to-digital converter or a digital-to-analog converter, where the stage comprises multiple segments that can be operated together to form a composite output, reducing thermal noise, while each segment itself has a sufficiently small capacitance to respond quickly to changes in the digital code applied to that segment. This allows for fast conversions without sacrificing noise performance.

Description

Technical Field

[0001] The present disclosure relates to techniques and structures for providing improved analog-to-digital converters, and in particular to increasing speed and resolution without sacrificing noise performance. Background Art

[0002] Analog-to-digital converters are judged based on parameters such as sampling rate, noise, linearity, power consumption, and resolution.

[0003] Each of these parameters affects the choice of analog-to-digital converter (ADC) technology selected for the task. For example, a "flash converter" may provide a high throughput rate, but because each possible output result is evaluated by a corresponding comparator, the comparator input reference offset limits the minimum bit size that can be resolved. In addition, providing a large number of comparators can be relatively power-hungry.

[0004] In situations where noise performance is a priority, the noise shaping properties of Σ-Δ (ΣΔ) converters may make them attractive. ΣΔ converters use a low-resolution quantizer, typically only 1 or 2 bits, to greatly oversample the input signal. This provides good linearity. Such circuits also offer the possibility of making the noise transfer function different from the signal transfer function. This gives the designer the option of moving the quantization noise away from the signal bandwidth. Conversion rates tend to be lower than other ADC technologies.

[0005] Successive approximation register (SAR) analog-to-digital converters can be used to provide good resolution, good power consumption, and reasonable noise performance at reasonable sampling rates. However, there is a constant need to improve ADC performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] To provide a more complete understanding of the present disclosure and its features and advantages, reference is made to the following description taken in conjunction with the accompanying drawings, wherein like reference numerals represent like parts, and wherein:

[0007] Figure 1 A schematic diagram of a switched capacitor sampling digital-to-analog converter (DAC) and the reference voltage generator that supplies it. The purpose is to illustrate that parasitic components in the reference voltage path cause ringing, so settling time needs to be allowed during bit testing.

[0008] Figure 2 A two-stage DAC is schematically shown, where the first stage processes the more significant bits of the digital word presented to the DAC and may also be used to sample the input signal, and the second stage processes the least significant bits of the digital word.

[0009] Figure 3 A circuit diagram of a simplified sample (or track) and hold circuit is shown so that the difficulties of building a high speed analog-to-digital converter can be discussed.

[0010] Figure 4 is a graph showing the exponential change of the sampled voltage toward a target value over time.

[0011] Figure 5 is a schematic diagram of a pipeline converter with two stages and a residual amplifier.

[0012] Figure 6 Yes Figure 5 A modification of the arrangement shown to add a micro ADC to the first stage of the pipeline.

[0013] Figure 7 is a schematic diagram of a multi-layer conversion stage in accordance with the teachings of the present disclosure.

[0014] Figure 8 shows the structure of a unit cell according to an embodiment of the present disclosure;

[0015] Fig. 9 Shows Figure 7 Variations of the arrangement shown.

[0016] Fig.10 Yes Figure 7 Schematic diagram of a further modification of the shown arrangement, in which the residual amplifier is omitted.

[0017] Fig.11 is a schematic diagram showing another variation, in which the second stage ADC is arranged to control the DAC segment of the first stage.

[0018] Fig.12 is shown in more detail Figure 7 A circuit diagram of a detail of an embodiment of the stage is shown.

[0019] Fig.13 yes Fig.12 Circuit diagram of a variation of the circuit shown.

[0020] Fig.14 is a circuit diagram of another embodiment of the present disclosure, illustrating the use of individual buffer amplifiers and shared bandwidth limiting resistors;

[0021] Fig.15 is a schematic diagram of a two-stage pipeline ADC according to the teachings of the present disclosure.

[0022] Fig.16 is a schematic diagram of a two-stage pipeline time-interleaved ADC in accordance with the teachings of the present disclosure.

[0023] Fig.17 yes Fig.16 The timing diagram of the time-interleaved ADC is shown.

[0024] Fig.18is a plan view of a DAC layout plan on a semiconductor die.

[0025] Fig.19 is a schematic diagram of a dual-ended (differential) ADC according to the teachings of the present disclosure;

[0026] Fig. 20 is a circuit diagram of a single segment of an ADC with a buffer amplifier to provide a reference signal to the ADC. DETAILED DESCRIPTION

[0027] Overview

[0028] A stage suitable for an ADC or DAC where the stage includes multiple segments that can operate together to form a composite output, reducing thermal noise, while each segment itself has a small enough capacitance to respond quickly to changes in the digital code applied to that segment. This allows for fast conversions without sacrificing noise performance.

[0029] According to a first aspect of the present disclosure, a stage of an analog-to-digital converter is provided, the stage comprising: an analog-to-digital converter coupled to a first acquisition circuit having a first time constant, and a plurality of circuits, each circuit comprising: an acquisition circuit having a time constant substantially the same as the first time constant; and a digital-to-analog converter for receiving a corresponding control signal based on a digital output of the analog-to-digital converter and forming a difference between a sampled voltage maintained by each acquisition circuit and the output of the digital-to-analog converter.

[0030] Preferably, the first acquisition circuit and the acquisition circuits in the plurality of circuits are formed by structurally similar "sampling slices". The sampling slices may include at least one capacitor with an associated switch, wherein the physical dimensions of the components within the slices on the semiconductor wafer are the same between the slices, or the slices are proportional to each other. In one example, if the area of ​​the capacitor (a given capacitor) in the first slice is Q times larger than the corresponding capacitor in the second slice, the transistor associated with connecting one plate of the given capacitor in the first slice to the signal node of the signal to be sampled has an aspect ratio that is Q times that of the corresponding transistor in the second slice. In this example, it has been assumed that the intervening dielectric thickness of the capacitors is the same and that the transistors are nominally doped identically. Therefore, the signal acquisition and sampling performance between the first acquisition circuit and the acquisition circuits of the plurality of circuits are matched.

[0031] The acquisition circuits may be provided as sample and hold or track and hold circuits.Each acquisition circuit may be implemented within a respective "sampling segment" of the stage.

[0032] It is thus possible to use one segment to form a digital representation of an analog input value, and to use the other segments together to form an analog residual having a reduced sampled thermal noise compared to a single segment. The analog residual represents the quantization error of the analog-to-digital converter, being the difference between the sampled analog value and the analog equivalent of the digital value output from the analog-to-digital converter stage. The segments can advantageously be produced to be identical (within manufacturing tolerances), e.g., the same size and shape, and using shared manufacturing steps. This produces an excellent match between the segments.

[0033] According to a second aspect of the present disclosure, an analog-to-digital converter is provided, using multiple segments with substantially matched time constants, which segments can be operated together to form a residual having reduced thermal noise compared to the thermal noise of a single segment. In such an arrangement, one segment can be used to perform analog-to-digital conversion in response to a signal from a suitably configured controller, and the remaining segments can be used as slaves to form the residual.

[0034] According to a third aspect of the present disclosure, there is provided a segment DAC comprising a plurality of substantially identical switched capacitor sampling DACs adapted to be connected in parallel to form a composite DAC output having reduced thermal noise compared to the thermal noise of any individual segment.

[0035] Preferably, the sampling DAC stages are set in response to the output of the analog-to-digital converter and do not participate in the analog-to-digital conversion, for example, they do not participate in the bit experimentation of a successive approximation converter in the same stage as the sampling DAC. The sampling DAC stages may be set bit by bit or bits may be set in groups to reduce transient currents.

[0036] According to a fourth aspect of the present disclosure, there is provided a method of operating a plurality of matched sampling DAC segments to form an ADC result and a residual, the method comprising operating one of the segments to perform an analog-to-digital conversion, and operating at least two segments to perform a digital-to-analog conversion, thereby forming a difference between a sampled input and a digital approximation of the sampled input.

[0037] According to another aspect of the present disclosure, a plurality of sampling DAC segments are provided, wherein for a first capacitor, if an area of ​​the capacitor plates divided by the plate spacing distance in the first segment differs from an area of ​​a corresponding capacitor in a second segment by a first ratio, then a width-to-length ratio of a transistor switch associated with a first capacitor in the first segment differs from a width-to-length ratio of a corresponding transistor in the second segment by substantially the first ratio.

[0038] The sampling DAC segments may have substantially the same physical footprint on a substrate.The substrate may be a semiconductor upon which the capacitors and switches of the segments have been formed by known fabrication techniques.

[0039] According to another aspect of the present disclosure, a plurality of sampling DAC segments are provided, wherein the sampling DAC segments include a plurality of unit cells, each unit cell including a respective unit-sized capacitor and an associated unit-sized transistor switch, and wherein the plurality of unit cells are combined together to form a weighted capacitor within the sampling DAC segments, and wherein the sampling DAC segments are connected to a shared input node to unify the sampling input signals, and are connectable to a shared output node to form an average of their respective residuals.

[0040] Design Challenges of Analog-to-Digital Converters

[0041] Analog-to-digital converters are widely used, for example, in telecommunication equipment, cameras, audio equipment, gaming consoles, industrial systems, medical devices, automotive applications, aerospace applications, and a whole host of other applications and systems where analog values ​​(which can represent light intensity, sound, pressure, speed, voltage, current, radio signals, etc.) can be converted into digital quantities that can be processed by data processors, embedded digital circuits, computers, etc.

[0042] The required conversion speed and the number of bits of resolution required can vary dramatically.

[0043] As discussed above, it is desirable to provide an ADC with high conversion throughput, for example, operating at good resolution (e.g., greater than 14 bits) with signal bandwidths between 10 and 100 MHz. The present disclosure provides structures for achieving such excellent performance levels. However, achieving such performance is difficult, and to recognize how difficult and therefore understand the nature of the inventive aspects of the present disclosure, it is useful to outline the structure of commonly used converter architectures before looking at some basic limitations of the physics associated with sampling circuits and digital-to-analog converters.

[0044] A particularly popular variation of the ADC is to use a switched capacitor array to act both as a sample and hold circuit and as a capacitive DAC that is driven to test a bit trial value against a sampled analog signal value. The analog-to-digital converter is often provided as a differential circuit. Although the present disclosure contemplates single-ended converters (because they are simpler), the comments and considerations discussed herein apply equally to differential analog-to-digital converters.

[0045] Figure 1A prior art arrangement is schematically shown comprising a sampling switched capacitor digital to analog converter, generally indicated at 10, which is provided within an integrated circuit implementing an analog to digital converter 14 and receives a first reference voltage Vref1 from an external reference circuit, generally indicated at 12. In this context, "external" means that the reference circuit (or at least not all of it) is not provided on the same silicon chip as the switched capacitor charge redistribution digital to analog converter 10. However, all or some parts of the reference circuit may be co-packaged with the die carrying the analog to digital converter 14 so that from a user's perspective, all components are provided by the same chip scale package or integrated circuit. The reference circuit includes a precision voltage reference 16, which is typically (but not necessarily) buffered by a buffer 18. Further stabilization of the output voltage at the output of the buffer 18 may be provided by packaging a relatively large storage capacitor 8 external to or with the integrated circuit die inside the chip scale package, even though other parts of the circuit, such as the ADC, may provide a buffer or reference voltage source on the silicon chip. The DAC 10 also receives Vref2, which may be a local 0V, ground or Vss to which all other voltages are referenced.

[0046] Although charge redistribution digital-to-analog converters as part of a successive approximation analog-to-digital converter are well known, their operation will be briefly described here for the sake of completeness. The charge redistribution digital-to-analog converter includes a plurality of capacitors, of which three capacitors 20, 22 and 24 are shown in this example. Other capacitors may exist between capacitors 22 and 24. In a converter without redundancy, the capacitors are binary weighted and follow a binary progression. Thus, if there are only three capacitors and capacitor 24 has a nominal and arbitrary value of "1C", capacitor 22 will have a value of "2C" and capacitor 20 will have a value of "4C". Each capacitor can be considered to represent a bit in a binary word, so the largest capacitor (capacitor 20 in this example) represents the most significant bit MSB with a weight of 4C, while the smallest capacitor 24 represents the least significant bit. Such capacitor arrays used in analog-to-digital converters typically provide a resolution of 12 to 16 bits, which means a corresponding number of capacitors. It is also well known that in order to avoid scaling issues between MSB and LSB, the capacitor array can be split or segmented once or multiple times. This effectively allows rescaling between capacitors in each segment of the array and avoids the need for the largest capacitor of the DAC to be, for example, 215 times the size of the smallest capacitor of a 16-bit converter. Although not shown, the switched capacitor array or a portion thereof is typically terminated by an additional termination capacitor having a value equal to the lowest effective capacitor within the array. For completeness, this will be discussed later with respect to Figure 2 Discuss splitting arrays.

[0047] continue Figure 1 As is well known, varying the “weights” (i.e., the relative capacitance of the capacitors) or number of capacitors in an array is done to provide some redundancy, i.e., the ability to recover from incorrect bit decisions during the conversion process. This can allow the designer to reduce the settling time between each attempt to achieve a faster conversion rate. For example, redundancy can be achieved by occasionally inserting at least one additional capacitor in the array that repeats the weight so that the capacitors are still binary weighted, but do not follow a binary weighting sequence. Another way to provide redundancy is to change the “cardinality” of the capacitors in the array from 2 (representing the binary weighting) to a smaller number, such as 1.8. Thus, the ratio of one capacitor to its neighbor becomes 1.8, rather than 2. This inserts redundancy into the array so that incorrect bit decisions can be corrected as the conversion process proceeds. In either case, as is known to those skilled in the art, redundancy is implemented to allow errors of either sign (i.e., errors that cause the result to be underweight or overweight) to be corrected as the conversion proceeds.

[0048] like Figure 1 As shown, each capacitor 20, 22, 24 has a first plate, also referred to as the top plate, which is connected to a conductor 30, which itself is connected to a first input of a comparator 32. The capacitor also has a second plate, also referred to as the bottom plate, which is connected to an electronic switch. The first capacitor 20 is connected to a first switch 40, the second capacitor 22 is connected to a second switch 42, and the third capacitor 24 is connected to a third switch 44. The switches are schematically shown as three position switches, although in practice they can be implemented as three field effect transistors per switch, which are controlled by a switch controller (not shown). The switch 40 can be considered to be operable in a first position or first mode to connect the bottom plate of the capacitor 20 to the signal input terminal Vin. In a second position or second mode, it is operable to connect the bottom plate of the capacitor 20 to Vref1, while in a third position or third mode, it connects the bottom plate of the capacitor 20 to a second input Vref2, which typically corresponds to a local ground or "negative" power rail. The second switch 42 and the third switch 44 are similarly configured, and in this example, the second input of the comparator is also connected to a local ground via a conductor 50. As previously mentioned, for simplicity only three capacitors and their associated switches are shown, but more switches may be provided within the ADC.

[0049] In the sampling or tracking phase of the operation of the analog-to-digital converter described in this example, switches 40, 42 and 44 are connected to Vin, and another switch 52 is closed to connect conductor 30, thereby grounding conductor 30 and the top plate of the capacitor, or connecting it to other appropriate reference voltages or bias voltages. This allows capacitors 20, 22 and 24 to be charged by voltage Vin. The analog-to-digital converter then enters a conversion phase in which switch 52 is disconnected to allow the voltage on conductor 30 to float, and switches 40, 42 and 44 are initially connected to Vref2. The bit test sequence can then begin. First, the first bit, the most significant bit, is tested by connecting the bottom plate of capacitor 20 to Vref1. When the capacitors form a voltage divider, this causes a redistribution of charge between the capacitors. As a result, the voltage at the first input of the comparator changes, and after a period of stabilization time, the comparator is gated (i.e., its output is checked) to determine whether the voltage at the first input is greater than or less than the voltage at the second input. If the voltage at Vin is large enough to exceed a value equal to Vref1 / 2, the voltage at the first input of the comparator exceeds the voltage at the second input of the comparator and the most significant bit is retained and capacitor 20 remains connected to Vref1, otherwise the bit is discarded and switch 40 is operated to connect the bottom plate of the MSB capacitor 20 back to Vref2. The process proceeds to the next bit trial, that is, after a settling time, the lower plate of the test capacitor 22 is connected to the second bit of Vref1 (the state of switch 40 remains unchanged from whatever position it was left in after the first bit trial), and the output of comparator 32 is checked to see if switch 42 should remain as it is, or reset back to connect the lower plate of capacitor 22 to Vref2. Switch 42 is then either reset or remains unchanged, and the test proceeds to the next capacitor 24, with switch 44 changing from Vref2 to Vref1. After the settling time, the output of the comparator is checked again to see if switch 44 should be left in its current position or reset. At the end of the trial sequence, the positions of switches 40, 42, and 44 can be checked, representing the results after the conversion. The sequence can be extended to include more than three capacitors. Similarly, the sequence can be extended to include switched capacitor arrays with redundancy, either by adding additional redundant capacitors or by using a radix less than 2, but the switching sequence then needs to be checked and further converted into a binary word. Although the ADC has been described as a single-ended device, the above description can be extended to differential converters. In addition, the term "bit trial" originates from the early days of SAR converters, where only one bit could be determined at each conversion. More modern designs enable multiple bits to be determined during a bit trial, and the term "bit trial" as used herein includes determining more than one bit during a given bit trial.

[0050] As mentioned above, the DAC may be implemented as a subdivided or segmented capacitor array, e.g. Figure 2 As shown. The subdivided capacitor array, generally designated 70, includes a first capacitor array 72 and a second capacitor array 74. The first capacitor array 72 includes capacitors C6 to C10, which are configured to form a sampling capacitor DAC 73, as described with respect to Figure 1 As discussed. The top plates of C6 to C10 are connected to a shared conductor 78, which is connected to a node 84, to which a comparator can be connected and / or a residual amplifier can be connected. The purpose of the residual amplifier will be discussed later. Capacitors C6 to C10 have three position switches S6 to S10, respectively, so that capacitors C6 to C10 can be connected to Ref1 or Ref2 to sample the input voltage Vin (using switch 82 as a sampling switch). Capacitors C6 to C10 can be binary weighted to represent, for example, the five most significant bits of a 10-bit converter. One or more capacitors can be provided as repetition weights, thereby reducing the number of bits from 5 to 4 or 3, but allowing the converter to include redundancy so that it can recover from incorrect bit trial decisions. The second capacitor array 74 includes capacitors C1 to C5 and serves as a sub-DAC 75. Sub-DAC 75 is connected to sampling capacitor DAC73 via coupling capacitor 76. Capacitors C1 to C5 can form the five least significant bits of the DAC. In this example, the sub-DAC is not a sampling DAC because the capacitors therein have no connection to Vin. If desired, the sub-DAC can be set to sample the input signal.

[0051] This segmentation breaks the scaling between capacitors and reduces the space required to implement the DAC. For example, in an array of 10 capacitors without segmentation and without redundancy, the capacitor weights would follow the pattern C1=1, C2=2, C3=4, C4=8, C5=16, C6=32, and so on until C10=512. Therefore, the total area required for the capacitors of such an array would be 1023 times the area of ​​the unit capacitor. If the array is subdivided into 2 arrays, each containing 5 capacitors, and the arrays are coupled via a unit-sized coupling capacitor 76, then we can see that C1=1, C2=2,.....C5=16, C6=1, C7=2, and so on until C10=16, so the array's capacitors occupy 63 times the area of ​​the unit capacitor. This is a significant space saving, and therefore cost saving.

[0052] In any switched capacitor array, whether interpolated or not, bit testing takes time. Figure 1It is clear that any of the switches 40, 42 and 44 will cause a circulating current to flow. Therefore, if the switch 40 is switched from Vref2 to Vref1, thereby raising the bottom plate voltage of the capacitor 20, there is a transient circulating current from the capacitor 20 through the capacitors 22 and 24 and their associated switches to Vref2. The current then flows through the storage capacitor 8 of the reference voltage 12 and returns to the bottom plate of the first capacitor 20 through the terminal Vref1 and the switch 40.

[0053] This current also flows along the bond wires between the external pins of the integrated circuit and the nodes Vref1 and Vref2, and also along the conductor traces within the printed circuit board to the voltage reference, or along the bond wires in a co-packaged device. Both the traces and the bond wires exhibit parasitic inductance and parasitic resistance. These unwanted impedances are caused by Figure 1 The inductance LP and resistance RP within the dotted line 62 of , and similar parasitic components LP' and RP' in the path from the switched capacitor array to ground. In addition, the storage capacitor 8 will also exhibit inductance and resistance, and these parasitic components can also be represented within the values ​​of LP and RP. Similarly, switches 40, 42 and 44 also exhibit resistance, which can again be represented within the value of RP.

[0054] The reference circuit includes a reference voltage generator 16, which is a precision voltage reference of any suitable implementation technology, which optionally provides an output to the input of a buffer 18. The buffer 18 protects the reference voltage 16 from having to supply current to the switched capacitor digital-to-analog converter 10 within the analog-to-digital converter. By its very nature, the buffer 18 consumes power even when the analog-to-digital converter is not active, for example, because the ADC has completed one conversion and is waiting until another conversion is scheduled.

[0055] In each operation of switches 40, 42 and 44, circulating current flows through various capacitors as well as parasitic inductors and resistors. The combination of capacitors and inductors has the potential to form an LC circuit that may ring. To avoid this, the circuit should be at least critically damped or nearly critically damped. The resistance Rcritical (see Figure 1 ) is RP = (4L / C). The time constant Tcritical of the critical damping circuit is (4LC)1 / 2. The settling time of the switched capacitor array determined by Tcritical is limited by the parasitic inductance LP and the capacitance C of the sampling DAC.

[0056] Some ADCs replicate the reference voltage "on chip" and avoid any circulating current through LP. Thus, the reference voltage is brought into the same integrated circuit as the switched capacitor charge redistribution digital-to-analog converter within the ADC, thereby reducing the value of L. Such techniques can be used with embodiments of the present disclosure.

[0057] The ringing time of the DAC during bit trials is not the only limitation affecting the speed of the ADC. The sampling circuit also plays a critical role. Although the sampling circuit is integrated in the sampling DAC, the issues regarding sampling circuit performance still apply to all sampling circuit configurations. Consider Figure 3 The simplified ADC shown.

[0058] Figure 3 The circuit in includes a sampling capacitor 110 having a first capacitor plate 110a and a second capacitor plate 110b, and wherein the first capacitor plate 110a can be selectively connected to or disconnected from an input node 112 at a voltage Vin via a switch 114. The switch 114 is typically formed of a field effect transistor, which has a high impedance when off and a low but undefined impedance when on because the on-state resistance of a FET varies with the gate-to-source voltage of the FET. In some circuits, a transmission gate using parallel NMOS and PMOS transistors can reduce the variation of the input resistance with Vin. Another approach is to use a bootstrap circuit to keep the gate voltage fixed relative to the source voltage when the transistor switch is "on".

[0059] In this embodiment, another switch 116 is provided to connect the second plate 110b of the sampling capacitor 110 to a reference voltage Vbias (e.g., local ground or more preferably Vref / 2), where Vref represents a first reference voltage applied to the ADC and the second reference voltage is taken as 0 V. When switches 114 and 116 are closed, the capacitor 110 is charged to the input voltage Vin (or more strictly Vin-Vbias) at the node 112. When switch 116 is open, the charge on the capacitor 110 is sampled and frozen on the capacitor 110. Figure 3The circuit also includes a DAC 120, which can be any suitable technology, such as based on switched capacitors or resistors, and can be connected to the plate 110a of the sampling capacitor via a switch 122. Effectively, the voltage stored on capacitor 110 is subtracted from the voltage output by DAC 120 at node 123, the result of this subtraction is quantized as negative or positive by comparator 125, and the result is provided to a controller 130, such as a state machine that performs a continuous approximation search. The advantage of this topology is that the comparator only needs to be good at making decisions around the voltage Vbias, rather than doing so over the entire range of possible input voltages. The disadvantage of this topology is that unless Vbias is set to Vref / 2, the voltage on the input node 123 of the comparator may be driven to a significantly negative voltage during the first 1 or 2 bit trials.

[0060] Returning to considering the performance of the sampling stage, the transistors used as switches 114 and 116 can provide a combined fixed impedance of RΩ when turned on. R is typically on the order of a few ohms to a few hundred ohms. Assuming the value of R is fixed, it is worth considering the value of C that should be chosen. The following sections discuss the trade-off between sampling speed and noise, and how small component variations in the sampling circuit can introduce errors equivalent to several LSBs in the analog-to-digital converter.

[0061] Assume that there is an initial voltage Vinit across the capacitor, and at time T=0, the sampling switch is immediately closed to connect the sampling capacitor to the input node 12 at the voltage Vin.

[0062] The capacitor will exchange charge with the input node through the resistance R of the switch, and the voltage Vc across the capacitor will change with time t.

[0063]

[0064] Where ΔV=Vin-Vinit

[0065] from Figure 4 It can be seen that the voltage Vc approaches Vin asymptotically, and the degree to which Vc matches Vin can be expressed as a function of time, measured in units of RC time constants. Displayed in graphical form, it would appear that one only needs to wait a few time constants until the sampling capacitor is charged. However, this is misleading. Also, since the sampling time is usually a fixed time defined by digital electronics, it is also necessary to consider the effects of component variations and variations in RC values.

[0066] The following table (Table 1) shows the evolution of the voltage from 0 to an arbitrary value '1' as a function of the time constant Tc of the first RC combination, exemplified by the voltage across the first sample and hold circuit and the second sample and hold circuit, whose time constant Tc' differs by 10% from Tc.

[0067] In other words, while the first sample and hold circuit has acquired 10 time constants of the input voltage, the second sample and hold circuit has only seen 9 of its own time constants.

[0068]

[0069] Table 1

[0070] After 10 time constants, the first RC circuit has an error of only 0.0045%, while the second RC circuit has an error of 0.012%. These numbers may seem small at first glance. However, they need to be considered within the resolution of modern ADCs.

[0071] The following expresses resolution as a percentage of the full-scale value:

[0072] 8 digits = 0.390625%

[0073] 10 digits = 0.097656%

[0074] 12 digits = 0.024414%

[0075] 14 digits = 0.006104%

[0076] 16 bits = 0.001526%

[0077] 18 digits = 0.000381%

[0078] 20 digits = 0.000095%

[0079] Therefore, waiting for 10 RC time constants is not enough to achieve 14-bit resolution because the error of the sampled voltage will be greater than 1LSB.

[0080] Typically, for a 16-bit converter, the sampling circuit samples at least 12 time constants; for an 18-bit conversion, the sampling circuit samples at least 14 time constants, and for a 20-bit conversion, the sampling circuit samples 15 time constants.

[0081] The performance of the transistor switch in terms of on-state resistance, RON, is limited by the manufacturing process. Transistors can be connected in parallel or made wider to reduce RON, but this is at the expense of increased charge injection from the gate of the transistor to the sampling capacitor, which can be seen as a characteristic of the gate-to-channel parasitic capacitance of the transistor. Therefore, it is not automatic to make the transistor switch wider to reduce RON compared to the value of the capacitor connected to the switch, as the charge injection problem worsens and reduces the accuracy of the analog-to-digital converter. However, as will be seen, subsequent embodiments of the present disclosure allow and intentionally increase the on-resistance while still maintaining good speed and noise performance.

[0082] Another way to reduce the time constant is to reduce the sampling capacitor. However, this raises another fundamental problem in the form of thermal (Johnson-Nyquist) noise. It is well known that the thermal noise Vn on a capacitor can be expressed as:

[0083]

[0084] This noise is not caused by the capacitor itself, but by the thermodynamic fluctuations in the amount of charge on the capacitor caused by the switch resistance. This random fluctuation is captured by the capacitor once it is disconnected from the conducting circuit.

[0085] The RMS thermal noise NRMS on a 300K capacitor for a range of capacitor sizes is listed below:

[0086] capacitance Noise voltage 1nF 2μV 100pF 6.4μV 10pF 20μV 1pF 64μV 100fF 200μV 10fF 640μV 1fF 2mV

[0087] The minimum capacitor size that can be tolerated in the sampling circuit can be calculated based on the input resolution. It is known to those skilled in the art that the maximum RMS signal value is related to Vref, so for ADC, the signal-to-noise ratio can be expressed as:

[0088]

[0089] There is also a quantization noise contribution. The uncertainty in the ADC is ±1 / 2LSB. If the error is assumed to be triangular on the analog input signal, the effective number of bits ENOB becomes

[0090]

[0091] Assume that the ADC is to sample a 5V full-scale input with 18-bit resolution. The LSB value is 5÷2 18 =19μV. However, when quantization noise is taken into account, the sampling noise needs to be reduced further to around 11μV RMS, which indicates an input capacitance of about 40pF if the noise is less than 1LSB. If the full-scale dynamic range is reduced, the LSB size will be reduced accordingly, and the input capacitance must be increased to obtain the same noise performance (expressed in bits).

[0092] The speed of the sampling stage is not the only factor to consider, as the ADC takes some time to convert and therefore it is not possible to acquire samples back to back.

[0093] As mentioned previously, a balance must be struck between speed and power. Many ADCs are used in battery-powered devices (e.g., mobile phones / smart phones) where available battery life is an important parameter. Furthermore, fast conversions are not necessary if the converter has poor dynamic nonlinearity.

[0094] As a result of these tradeoffs, a suitable technology that can achieve both resolution and lower power is the switched capacitor ADC, where an array of switched capacitors can be used as both the sampling capacitors and the bit test DAC.

[0095] As mentioned before, the process of trying a bit by switching the capacitor between the reference voltages causes a redistribution of charge inside the DAC, and the charge flowing through the transistor is thus affected by the RC time constant. The switching between the capacitor and the reference voltage also causes a sudden charge draw from the reference voltage, which interacts with the inductance of the conductor / trace between the reference voltage and the capacitor, and the capacitance of the capacitor itself, causing ringing.

[0096] Both ringing and capacitor-to-capacitor charge redistribution limit the conversion rate. The ringing needs to be given time to subside to get below an appropriate value, such as 1LSB (or the amount of error that the redundancy within the ADC can reasonably be expected to correct), and the charge redistribution must also asymptotically approach an appropriate value. Fortunately, it turns out that we do not need to wait 14 to 16 time constants after setting the bit in the bit test after setting the comparator to see the result of the bit test through the bit comparator. In fact, it is reasonable to wait for a shorter time (such as about 4 time constants) in a converter with redundancy. It can be seen that this can add another (18+3)4=84 time constants to the conversion time of an 18-bit converter with 3 redundant bits. With a simple estimate of RON of 10 ohms and capacitance of 40pF, and the sampling capacitors involved in the bit test of the successive approximation converter, and an average settling time of 14 time constants for each sample of the input signal, this means that the conversion rate is about 1 / (10×40×10 -12 ×(14+84))≈25MHz.

[0097] Pipelining allows the bit trials to be split between different stages of the ADC, and while pipelining does not improve the conversion time between sampling and outputting the result, it does nearly double the conversion rate in a two-stage pipeline. Another benefit of pipelining is signal amplification, so the comparator can make faster decisions.

[0098] Pipelining also allows a residual, representing the difference between the sampled analog value and the digital approximation of that analog value, to be formed and obtained before being passed to the next stage of the pipeline converter. Pipelining also allows different stages of the pipeline to be formed with different resolutions and / or different analog-to-digital converter technologies. Figure 5 A schematic diagram of a two-stage pipeline converter is shown.

[0099] Here, the first analog-to-digital converter 150 performs a partial conversion and outputs a digital result D1 representing the analog input value to a limited resolution, for example between 4 and 10 bits (these suggestions are not limiting). The analog-to-digital converter 150 is also arranged to output an analog value A1 representing the difference between Vin and the equivalent analog value of D1. Figure 1 and 2 The switched capacitor array shown does this naturally as part of the conversion process, so no additional overhead is incurred in forming A1, which is referred to as the "residual". The residual is further analog-to-digital converted by the second analog-to-digital converter 152. The second analog-to-digital converter 152 can generate a digital result D2 based on A1. The residual A1 can be amplified by an amplifier 160. This is beneficial because it reduces the effects of offsets within the comparator of the second converter.

[0100] Pipelining means that instead of a single ADC having to do 16 or 18 bit trials, the first ADC 150 can do a number of trials (e.g. 8 or 9) while the second ADC 152 does the rest. Since each ADC only does half the bit trials, the effective conversion rate is doubled, since ADC1 does not only take half the time to accept a new conversion input. ADC1 can be doing its N+1th conversion while the second converter ADC2 completes its Nth conversion. This assumes that there is no time overhead in receiving and amplifying the residuals. Furthermore, the settling time of the second ADC can be reduced compared to the first, since it does not have to draw such a large amount of current during its bit tests, and any errors it makes are by definition less significant since they involve reducing less significant bits.

[0101] The conversion speed, and thus the throughput, can be increased by performing some of the bit tests quickly, for example by using a flash ADC to perform the first two, three, or four tests and using a successive approximation search to perform the remaining bit tests (or other ADC strategies). Figure 6 , where a micro ADC 151, such as a flash ADC, can perform two or three bit tests quickly and with lower precision and use the results as a starting point for the bit tests of the first ADC 150. Since the errors will be encoded as residuals and removed by the second ADC 152, any errors, such as wrong decisions, can be recovered from.

[0102] Achieve higher sampling rates without noise loss

[0103] Despite all of these approaches, it is still desirable to operate at higher sampling rates without incurring noise penalties. As mentioned previously, the problem is that none of the solutions are easy. A smaller sampling capacitor will reduce the RC time constant, allowing for higher throughput, but at the expense of increased thermal noise.

[0104] The inventors recognize that architectural changes can be made to partially decouple the noise problem from speed, since improving noise performance suggests using more capacitors, while improving speed performance suggests using smaller capacitors. The inventors note that these problems can be mitigated by using multiple DACs, for example, a switched capacitor array consisting of multiple switched capacitor arrays working together as "segments" in a single ADC block - either an instance of one converter in a segmented converter or a converter of its own.

[0105] Therefore, the ADC can be divided into multiple channels or segments. The segments can be made with relatively small capacitance values, so that the slices can be used to perform ADC conversions and obtain intermediate results relatively quickly, but with noise losses. The intermediate results can be used by one or more other segments to form residuals. One or more other segments may have larger C values, or work in parallel to synthesize larger C values, so that the thermal noise coefficient of the residual is improved.

[0106] Operating multiple sampling stages in parallel is not as simple as just connecting the loads of the multiple stages together. Like many things in high-speed analog-to-digital converters, this ignores some of the basic physics that makes the task so challenging.

[0107] These stages should be "matched" to set their RC time constants within acceptable values. The limits that constitute "acceptable" are determined by the time budget used to sample the input signal and allow charge redistribution and ringing to settle to about 1LSB of the channel or segment. The problem of mismatched RC time constants has been described earlier for direct current (DC) signals. The following paragraphs will describe the problem of mismatched RC time constants for alternating current (AC) signals.

[0108] Looking more specifically at the sampling issue, this is again a function of the converter's dynamic range and its maximum bandwidth.

[0109] Assume that a sampler samples a sinusoidal Vinput with a dynamic range of 5V at 10MHz. Its amplitude is 2.5V and its angular frequency is 2π×10×10 per second. 6 radian.

[0110] Vinput=2.5sin(2π×10×10 6 )Equation 5

[0111] The maximum rate of change of voltage occurs near the zero crossing point and is 2.5×2×π×10×10 per second. 6 =157×10 6 Volt.

[0112] Therefore, a sampling skew (timing error) of 1 picosecond will equal an error of 157μV. For a dynamic range of 5V and 18-bit resolution, the LSB size is 19μV. Therefore, this small timing skew of 1ps introduces an error of 8.3LSB. This timing skew interacts with any variation in the RC time constant between stages or segments to increase the mismatch error in the voltage sampled onto each segment.

[0113] To address this issue, the inventors selected an architecture where, for each segment integrated circuit, lithographic precision is used to ensure that the capacitors and transistors in each sampling device are scaled together to maintain matched RC sampling time constants, and the sampling switches are located in substantially the same location to minimize timing skew.

[0114] In embodiments where the slices are formed from switched capacitor arrays, each slice includes a sampling DAC, and the sampling stages are matched so that a given electrical location in one slice has substantially the same capacitors and transistors as equivalent capacitors and transistors in other slices.

[0115] In an embodiment of the present disclosure, a unit cell including a unit size capacitor C and a unit size transistor associated with one of the plates of the capacitor to Vin, Ref1, and Ref2, respectively, is reused to form a segment. The electrical performance of each unit cell is nominally the same as the other unit cells. Cells can be grouped together, either permanently, or as part of a dynamic assignment of cells to groups. Two cells can be grouped together to form C7 (with a 2C capacitance). Figure 2 ), four cells can be grouped together to form C8 with 4C capacitance, 8 cells can be grouped together to form C9, and so on. If desired, cells do not need to be grouped together in binary order of weights. Cells can be grouped to form capacitors to provide redundancy. Cells can also be connected in series to form effective capacitances of C / 2, C / 3, C / 4, etc.

[0116] The fragments can be connected to sub-DACs, e.g. Figure 2 The sub-DACs C1 to C5 are included.

[0117] Returning to the issue of matching RC time constants, they have an effect on sampling AC signals. Table 1 shows that variations in the time constants can cause large errors in the sampled values ​​of DC signals. However, ADCs typically sample varying (AC) signals.

[0118] The segments need to sample the same value within an acceptable range, but this raises the question of how important matching is when looking at AC signals. The inventors realized that the matching problem has been ignored in the past. The document "A 1mW71.5dB SNDR 50MS / s 13bit fully differential ring amplifier based SAR assistedpipeline ADC", Yong Lim and Michael P Flynn, IEEE Journal of Solid State Circuits, Vol.50, No.12December 2015 shows a circuit (referenced in this article) Figure 6 and Fig.16 ), where the first stage of the pipeline converter resolves the 6MSBs of the signal to be digitized. The input signal Vin is sampled onto two sampling DACs. One sampling DAC, referred to as the "big DAC," has three times the capacitance of the other sampling DAC, referred to as the "small DAC." The small DAC is used to perform the SAR experiment to save power, but once completed, both DACs are connected to a common node so that their residues can be merged together to meet the 13-bit noise requirement. However, there is no teaching of scaling the transistor switches to match the sampling time constant of the DAC, nor is there any teaching of co-locating the sampling switches to minimize timing skew.

[0119] This is easiest to understand if you think of the change in the RC time constant as a phase shift.

[0120] The phase shift can be modeled as that of an RC low-pass filter, where Given by:

[0121] φ=-arctan(2πfRC)Equation 6

[0122] Assume that you want to design the RC sampling circuit to have a -3dB bandwidth of 10MHz. Also assume that C is selected to be 40pF to meet the noise performance indicators required to achieve 18-bit resolution. For example:

[0123]

[0124] f = 10 MHz, and

[0125] C=40pF

[0126] We can then calculate the value of R using Equation 7, which gives R = 40Ω.

[0127] By evaluating Equation 6 based on the values ​​of f, R, and C, the phase shift can be determined:

[0128]

[0129]

[0130] At first glance, this phase shift may seem negligible. However, if RC changes by +10%,

[0131] This is a difference of 0.001 rad, which is equal to the time difference of:

[0132]

[0133] So in this example, a 10% change in the RC time constant produces a 1×10 -3 radians, but this phase change equals 16 picoseconds of timing error, which is equal to 133LSB fragment of a 5V peak-to-peak input signal at 10MHz.

[0134] The calculations above show that as the frequency increases, the mismatch in component values ​​manifests itself as a larger sampling time error. However, this problem seems to have been ignored in the past.

[0135] Having noted that variations in the RC values ​​of the sampling stages can introduce small phase shifts that can manifest themselves as many LSB errors, the inventors have taken the step of adding series resistors to the RC sampling circuit in some embodiments of the present disclosure. This is counter-intuitive because adding a resistor significantly reduces the bandwidth of the circuit, thereby increasing the sampling time of the input signal. This approach is diametrically opposed to the steps taken to build a fast ADC. However, the effective "on" impedance of the transistor switches can vary by several percentage points with temperature and input voltage, and although careful layout and bootstrapping can greatly reduce the variation, adding series resistors (which are thermally more stable than transistors) can improve the matching between segments. The value of the resistor can be between ohms and several hundred ohms. In one embodiment, a resistor of approximately 160Ω is used. The on-resistance of the transistors may be only a few ohms, and the on-resistance variation between transistors may be only a fraction of an ohm. This approach significantly improves the matching between the sampling DAC segments.

[0136] As a result, it is preferred to make the sampled portion of each segment nominally identical to each sampled portion of the other segments.

[0137] Figure 7 A circuit 200 constituting an embodiment of the present disclosure is schematically shown. The circuit comprises a plurality of sampling circuits and a plurality of digital-to-analog converters. The circuit may form the entirety of an analog-to-digital converter, or more likely be used as a "stage" of a multi-stage converter, e.g. Figure 5 or Figure 6The pipeline converter shown, wherein the pipeline may have two or more stages. In this embodiment, a switched capacitor array is used to form a sampling digital-to-analog converter, with each sampling DAC acting as a segment 210.1 to 210.n of the circuit 200. The segments 210.1 to 210.n are advantageously reconfigurable so that one or more segments 210.1 to 210.n can be associated with a SAR controller and other segments in the slice can be updated based on the SAR output. In this case, "updated based on..." includes the possibility that different segments in the slice can be updated or set to individual values ​​that may be different from the SAR value. However, it is temporarily assumed that the first segment 210.1 is coupled to a comparator 210, which provides its output to a SAR controller 214. The SAR controller may be a state machine, which is arranged to drive the sampling DAC segment 210.1 to perform analog-to-digital conversion using the segment 210.1 in this example to resolve multiple bits of the digital output word.

[0138] Some or all of the remaining DAC segments 210.2 to 210.n are configured to sample input Vin simultaneously with segment 210.1 and act together to form a residual DAC 220 to form an analog output voltage Vresidue representing the difference between Vin and Vdac, where Vdac is the voltage produced by the residual DAC 220 when driven by the SAR controller 214 to produce a P-bit conversion, the "result" of the analog-to-digital conversion formed by the first DAC segment 210.1, where P is the effective resolution (in bits) of the segment 210.1.

[0139] The first DAC segment 210.1 may be composed of Figure 1 The non-subdivided switched capacitor array shown in Figure 2 The segmented or subdivided switched capacitor array shown or Figure 3 The sampling capacitor and associated DAC are shown in Figure 1. Figure 2 The segmented arrays shown are commonly used due to their relative compactness, so for the purposes of this section we will assume that segment 210.1 contains Figure 2 The subdivision array shown.

[0140] In this arrangement, if Figure 2 As shown, the sampling DAC stage 73 is connected to the sub-DAC stage 75. The other segments can be formed identically to the first segment 210.1, i.e., including two sampling DAC stages and one sub-DAC. However, it is also possible to use shortened sub-DACs or omit the sub-DAC altogether, as long as the coupling capacitor is adjusted and coupled to ground or in series with a capacitor in series with the capacitor of the replica sub-DAC.

[0141] In use, each of the segments 210.1 to 210.n is coupled to Vin and is used to sample Vin. The sampling switches 82 of the segments (see Figure 2 ) are co-located to ensure that they receive their "hold" instructions at the same time and also to ensure that each switch 82 is subject to the same process, voltage and temperature (PVT) variations as the other switches. This helps ensure that each sampling DAC circuit has the same electrical performance as the other sampling DACs, e.g., matched RC time constants, and that switches 82 transition between conducting and non-conducting at the same slew rate and at the same time, thereby avoiding phase shifts between DAC segments 210.1 to 210.n when operating simultaneously to acquire (e.g., sample and hold) a shared input signal.

[0142] After the input signal has been acquired, the first DAC segment 210.1 can be used to form a successive approximation routine conversion of the sampled signal. Such a conversion can include the use of an additional sub-ADC, for example in the form of a flash ADC, to provide a nearly instantaneous conversion of the first two or three bits of the P-bit conversion performed by the DAC segment 210.1. Given that methods for performing SAR conversions are well known to those skilled in the art, they are not described in detail here, except to point out that such conversions can also include additional bits to provide redundancy in the results, and as is known to those skilled in the art, the conversion can also be performed using radix <2 techniques, and multiple bits can be determined in a single bit tracking cycle, for example, by using a three-level quantizer instead of a comparator. As the bit experiment proceeds, the state of the most significant bit of the P-bit output word is known before the state of the least significant bit of the P-bit output word. This allows the output from the SAR logic 214 to be provided to the segments 210.2 to 210.n in the residual DAC 220 so that the bits in those DAC segments are set bit by bit, thereby allowing the voltage transitions caused by switching the capacitors in each segment to the appropriate configuration and the ringing that may be introduced to disappear before the residual amplifier 230 absorbs the output of the residual DAC 220.

[0143] To reduce the amplitude of the voltage transitions, the setting of the bits in the segments 210.2 to 210.n in the residual DAC 220 may be staggered in time so that the transitions do not occur uniformly. In addition, by first setting half of the segments 210.2 to 210.n where the most significant bit is set, and the other half of the segments where the most significant bit is not set to the initial value, the amplitude of the initial transition (e.g., with respect to the most significant bit and the next most significant bit) may be reduced. Thus, as a result of the first bit trial, statistically only half of the DAC segments may have to transition. The same technique may be used for the next most significant bit, and so on. An alternative approach may be based on the fact that in use, the input signal may be oversampled compared to its Nyquist frequency limit, so that statistically the first few bits of the input word are unlikely to change between one sample and the immediately following sample.

[0144] It is also possible to allow one or more DACs in the residual DAC to participate in several bit trials. In other words, if only DAC segment 210.1 is used for analog-to-digital conversion, a single DAC segment can only perform one bit trial at a time. However, if three of the DAC segments (e.g., 210.2, 210.3, and 210.4 of the residual DAC 220) are temporarily enabled to work with respective comparators (not shown) coupled to the SAR logic 214, then Figure 7 The configuration shown can perform two bit tests simultaneously, thereby reducing the time required to switch the P bit in stage 200.

[0145] The use of a segment arrangement allows each DAC segment 210.1 to 210.n to have a smaller capacitance therein, which reduces the RC time constant of each DAC segment and therefore allows faster conversions to be performed. Earlier in this specification, the thermal noise associated with a 300K capacitor was listed. This was used to show that in a working example, to convert a 5V dynamic range with 18-bit resolution, the minimum capacitance of the DAC should be at least ~40pF. However, if all DAC segments are formed to each have an effective capacitance of 4pF, then the DAC segments 210.2 to 210.n are connected to form a residual DAC, placing their capacitances in parallel. Therefore, if 10 DAC segments 210.2 to 210.11 are provided in the residual DAC 220, connecting them in parallel will produce an effective capacitance of 40pF, even though each residual DAC has an excellent sampling time and settling speed (compared to the 4pF DAC segment). It should also be noted that the residual at the output of the first DAC segment 210.1 can also be connected to the output of the residual DAC 220, so that it also helps to reduce the thermal noise of the capacitor bank.

[0146] As mentioned earlier, a sampling DAC can be formed from repeated unit cells. Figure 8 One such unit cell 270 having a value of 1C is shown in FIG. The unit cell comprises a capacitor 272 having a value of 1C. One of its plates, namely Figure 8 The topmost plate in the , connected to the shared conductor 78 ( Figure 2 The bottom plate of the capacitor is connected through a three-way switch formed by transistors 274, 276 and 278 to isolate the bottom plate and connect to Vin, Vref1 (usually from a precision voltage reference such as Figure 1 The buffer 18 in the circuit is Vref 2 (usually 0V). Each transistor is composed of a Figure 7 The SAR logic block 214 in FIG. 2 is a block diagram of a schematic diagram of a SAR logic block 214 in FIG. 20 . The transistor 274 connecting the capacitor to the input node Vin can be connected in series with a resistor 280 to more accurately define the "on" resistance presented by the unit cell when it samples the input signal at Vin. The transistor 274 can have a gate control signal modified by a bootstrap circuit 282 to keep the Vgs of the transistor 274 constant relative to Vin. Bootstrap circuits are known to those skilled in the art. The unit cell 270 can be placed in parallel with other unit cells to form a combination of switches and capacitors in appropriate proportions, such as unit cells 270a and 270b placed in parallel to form a 2C weight, etc.

[0147] For example, if the switched capacitor DAC ( Figure 2 ), only 5 binary weighted sampling capacitors are needed in the sampling portion 73 of the integrated circuit, then 25-1=31 unit cells 270 are needed. The unit cells can be well matched in the integrated circuit, which means that the unit cells can be permanently assigned to 1, 2, 4, 8 and 16 groups as required, or alternatively, the groupings can be dynamically formed by the switch controller at each sampling event to randomize any mismatch errors.

[0148] Fig. 9 Shows Figure 7 A variation of , in which a micro ADC 285 (e.g., a 3-bit flash converter) is used to more quickly set the three most significant bits of the SAR converter. The flash converter 285 can convert less or more than 3 bits.

[0149] The remaining voltage can then be obtained by a residual amplifier 230 before providing the voltage residual to another analog-to-digital converter 240. It should also be noted that Fig.10 As shown, the residual amplifier 230 need not be provided.

[0150] Fig.11A modification that can be applied to any of the arrangements described herein is shown in which the second DAC 240 can be allowed to modify the switch positions within the residual DAC 220. This can allow the ADC 240 to modify the residual (and the digital word from the first DAC 200) if the residual is inconveniently too large for the residual amplifier or comparator in the second ADC to handle without compromising its linearity. In this example, the second ADC 240 is implemented as a SAR ADC, which includes a comparator 240a, a SAR controller 240b, and a DAC 240c.

[0151] Fig.12 The schematic diagram in more detail shows Figure 7 In this example, each of the segments 210.1 to 210.n is identical, and each segment includes a segmented capacitor array that together with the sub-DAC forms a sampling DAC. The sampling DACs are identical. In addition, Fig.12 In the configuration shown, the sub-DACs are also identical, but need not be. If desired, the sub-DACs may be formed at a lower resolution. For example, assuming that DAC segment 210.1 is an 8-bit segment, if eight DAC segments 210.2 through 210.9 are provided in the residual DAC 220, each containing 5 bits in its main DAC (N=5) and 3 bits in its sub-DAC (M=3), then the eight residual DACs may be effectively driven with different control words to provide an additional 3 bits of resolution, either within the sub-DAC or the main DAC, bringing the residual DAC back up to an 8-bit device. Thus, the sub-DACs of segments 210.2 through 210.n may be shortened or omitted if desired. Alternatively, if the segments are identical, the sub-DACs may be configured to be 8-bit devices. Fig.12 If all is the same as shown, then the residual DAC can be driven to apply sub-LSB dithering to its output signal to be provided to the next stage of the pipelined analog-to-digital converter. These methods can be used together.

[0152] exist Fig.12 In the arrangement shown, a data manipulation block 250 is provided between the SAR register 214 and each segment 210.2 to 210.n in the residual DAC 220. The data manipulation block allows a digital word to be passed to each DAC segment 210.2 to 210.n for individual settings. Thus, intentionally choosing different words can improve resolution or introduce jitter.

[0153] Fig.13 yes Fig.12A general representation of where each segment 210.1 to 210.n is divided into a sampling DAC portion 210.1a, 210.2a, and so on, up to 210.na, and sub-DACs 210.1b, 210.2b, 210.3b, and so on. The segment sampling DACs 210.2a to 210.na are identical to each other. The sampling DAC 210.1a can be identical or different to the sampling DACs 210.2a to 210.na, but advantageously has very similar electrical characteristics, which can be best achieved by forming the same unit cell construction as the other segments. The sub-DACs do not have to be identical. For example, the sub-DAC 210.1b can be formed with more bits than the other sub-DACs. In practice, not all segments need to be provided with sub-DACs. Here, the sub-DACs associated with the sampling DAC 210.na have been omitted.

[0154] It was noted earlier in this disclosure that current flowing between capacitors along the bond wires can interfere with the reference voltage. Figure 1 In the arrangement shown, the reference voltage is buffered by a buffer amplifier to reduce disturbances applied thereto. An advantage of the arrangement described herein is that disturbances of the voltage reference are reduced during a bit trial sequence and also provides the potential for providing a buffered version of the reference voltage to the DAC segments 210.2 to 210.n in the residual DAC, which signal can be provided by a further buffer so that the reference voltage provided to the first segment 210.1 is not disturbed by the switching of capacitors in the segments 210.2 to 210.n to establish the residual DAC. It can be seen that if the capacitance of the capacitor array is effectively reduced from 40pF to 4pF, then the current drawn from the reference voltage is reduced accordingly. The energy required for the conversion is therefore reduced.

[0155] For example, if all sampling DACs 210.1 to 210.n are built in the same way and the residual DAC has 8 segments totaling 40pF (for noise purposes), each segment will have a capacitance of 5pF. For example, the 5pF is distributed between 31 unit cells in the 5-bit example or 63 unit cells in the 6-bit example of the sampling DAC array. In the 5-bit case, the unit capacitance size is 161fF; in the 6-bit case, the unit capacitance size is 79fF. It can be seen that since the RC value of each unit cell is very small, this approach allows the segment ADC to achieve a high bandwidth even with a modest series resistor to swamp any transistor-to-transistor differences. Moreover, since only one of the segments performs the bit test, the current drawn from the current source is greatly reduced. The reduction in charge required to perform the bit test also means that some resistance can be intentionally introduced into the charge path to reduce ringing within the supply voltage of the DAC capacitor.

[0156] Fig.14An arrangement is shown in which each of the segments 210.2 to 210.n of the residual DAC is connected to an external reference through a respective buffer 300.2 to 300.n, which can be selectively disconnected from the segment 210.2 to 210.n by a series switch 302.2 to 302.n, wherein the segment 201.2 to 210.n can also be directly connected to the external reference through another switch 304.2 to 304.n. Thus, the residual DAC segments 210.2 to 210.n can be charged through the buffer during most of the settling time, thereby reducing the current drawn from the external reference voltage source, and connected to the external reference voltage source at the end of the settling time so that they settle to a correct voltage, unaffected by the offset in the respective buffer. In addition, each switched capacitor array can limit its bandwidth through a selected connection to the bandwidth limiting resistor 320 through a respective switch 322.1 to 322.n.

[0157] Fig. 20 The concept of buffer 300 is shown in more detail, this time for a single segment. In particular, a fast amplifier can be used as buffer 300 between bit trials to bring the internal reference to the signal level of the internal reference so that then when the external reference voltage is switched on, it settles down very quickly with almost no charge transferred therefrom. Fig. 20 A single fragment of a pipelined successive approximation (SAR) converter analog-to-digital converter (ADC) architecture that forms the basis of the present disclosure is shown. Here, the ADC converter includes an analog-to-digital converter ADC1, which receives a signal to be converted from an input node Vin. ADC1 performs a relatively low resolution conversion using an internal reference voltage Vref2_internal, which is derived from an accurate external reference voltage Vref through an amplifier Amp2. Amp2 may be a slower, relatively inaccurate amplifier because the conversion performed by ADC1 does not require a high-precision reference input. ADC1 feeds its converted data to a digital-to-analog converter DAC1, which also receives Vin. DAC1 outputs a residual signal to a residual amplifier RA, which outputs an amplified residual signal to the analog-to-digital converter ADC2 to complete the conversion. The complete operation of the fragmented pipelined SAR ADC is described elsewhere herein; however, for the purposes of this description, it must be recognized that DAC1 does require an accurate reference input in order to operate correctly and produce accurate conversions.

[0158] exist Fig. 20In the arrangement, the reference input of DAC1 is provided by another internal reference signal Vref_internal, which is derived from an accurate, temperature-compensated external (i.e., off-chip) reference Vref in the following manner. A voltage source Vref provides an accurate reference signal Vref to an input pin, to which a large (10uF) stabilizing capacitor C1 is also connected, so that the stabilizing capacitor C1 is charged to Vref. A high bandwidth fast amplifier Amp1 is further provided, whose non-inverting input is connected to the input pin to which Vref is provided. Its output is connected to the reference input node of DAC1 through a first "conversion" switch, at which Vref_internal is provided. The inverting input of Amp1 is also connected to the same node at which Vref_internal is measured, namely the Vref_internal node at the reference input of DAC1. The Vref internal node is also connected to the input pin to which Vref is provided through a second "sampling" switch. The "sampling" and "conversion" switches operate in anti-phase, i.e., one is open (closed) and the other is closed (open).

[0159] The operation of the above circuit is as follows. Before the ADC (DAC1) generates a residual error, the "convert" switch is closed and the "sample" switch is opened. As a result, amplifier AMP1 operates to try to keep the Vref_internal node at the same voltage as the Vref node. Before the residual error is generated, the "convert" switch is open and the "sample" switch is closed to allow the external reference voltage Vref to be fed into DAC1. However, because Amp1 always keeps Vref_internal very close to Vref, very little current needs to be drawn from Vref or C1, so Vref_internal settles to Vref very quickly, thus allowing a high sampling rate.

[0160] For the sake of completeness, Fig.15 An embodiment of the present disclosure is schematically shown in which a micro ADC 228 formed by one of the segments works together with the other eight segments forming a residual DAC to drive a residual amplifier 230. In this embodiment, the residual amplifier is connected to another ADC 240. In this example, the first ADC provides 6 or more bits of resolution, while the second ADC 152 provides the remaining number of bits, such as 8 or more 9 bits of resolution, to achieve the required overall ADC resolution.

[0161] In other examples, each segment may present 3.2pF of capacitance, but the total number of analog-to-analog converters provided to generate thermal noise totals 25.6pF with the DACs operating in parallel.

[0162] As can be seen, the time to complete a SAR conversion is expected to be longer than the time required to set up a single DAC segment in the residual DAC. Furthermore, the output of the residual DAC is only actually needed after the SAR conversion of the first ADC is completed. This allows the possibility of sharing the residual DAC between two or more SAR segments. The SAR segments can be operated in a ping-pong manner so that one of them is approximately halfway through the conversion when sampling. In such an arrangement, the residual DAC must be sampled at the same time as each SAR segment, but it can be preset with at least half of the output word immediately after sampling is completed. The use of this method is further enhanced by the use of sub-ADCs (such as flash ADCs) in order to quickly perform the first few bits of a bit trial or to reduce the signal swing during the trial.

[0163] Fig.16 An alternative embodiment of a pipeline architecture is schematically illustrated, in which two flash ADCs 330 and 332 are provided within ADC1 200, and each flash ADC is associated with 8 DAC segments. The first ADC 200 operates in a ping-pong interleaved manner, so an unusually small mismatch may still result in the generation of an oversampled tone. To mitigate this, one or more segments may be shuffled between multiple segments of each residual DAC to reduce the risk of tones.

[0164] Fig.17 Schematically shows Fig.16 It can be seen that in Fig.16 and 17 Each of the first ADCs designated as "A" and "B" in the ADC 330 operates out of phase with each other so that while ADC "A" 330 performs its acquisition in the time period TA between successive "convert start" signals, ADC "B" performs its bit trials and then passes its results to the residual amplifier. In each period TA, the residual amplifier extends its time by approximately half to amplify the residual from one of the residual DACs associated with the respective chip ADCs "A" and "B", while the other half of it undergoes auto-zeroing AZ in order to eliminate offset errors therefrom. The techniques and methods used in auto-zeroing are well known to those skilled in the art and need not be described here.

[0165] Although the description focuses on a DAC segment in the form of a switched capacitor array, which can simultaneously serve as a sampling capacitor and a host for a digital-to-analog converter, the teachings of the present invention can also be applied to circuit arrangements where the sampling arrangement and the DAC are separate, such as Figure 3 The arrangement shown. Therefore, Figure 3The circuit will be replicated several times to provide each sampling and DAC segment, but the size of the sampling capacitor will be reduced in each segment, and each segment will include cross-coupling switches to the other segments so that the capacitors will be connected in parallel to meet the required noise performance.

[0166] The number of stages in the pipeline can vary between the resolution of the converter and the resolution. In other words, each stage in the pipeline can be arranged to convert only one bit. The teachings of the present disclosure will still apply to such a deeply pipelined arrangement because the time constant of each stage will be reduced by multiple fragments of a given stage that will act in parallel to provide the required noise performance. Therefore, the present disclosure is highly flexible and can be used in a large number of configurations that require a DAC to interact with a capacitor-based sampling circuit.

[0167] The interleaving ratio may be 2 times or greater.

[0168] Fig.18 Schematically shows Fig.16 . The DAC segments are arranged in parallel between the comparator comp associated with the segment ADC and the residual amplifier RA associated with the stage. In this example, one segment in each set of switched capacitor DACs is allocated as a segment ADC SADC.

[0169] As mentioned above, all of these circuits can be implemented in the differential ADC device 220', such as Fig.19 Here, the capacitor arrays associated with the +ve and -ve inputs each provide a residual signal to the differential residual amplifier 230 .

[0170] It is often desirable for analog-to-digital converters to operate at reduced power consumption, for example due to their use in battery-powered mobile devices (e.g., mobile phones, etc.). The desire to reduce power consumption has led to the adoption of deep submicron processors. This, in turn, has led to the adoption of reduced supply voltages in order to reduce the effects of leakage and power consumption in increasingly dense integrated circuits. It is now quite common for circuit designers to try to target supply voltages of 1 to 1.3 volts. The adoption of these relatively low voltages has made the design of the residual amplifier 230 increasingly complex. The residual amplifier is typically provided as a differential input stage (long tail pair) configuration, with the tail current set by a current source, and an active load providing a reasonably high gain. Given the operating speed of the residual amplifier, it is also often desirable to include a cascode stage. It can be seen that when the designer must provide sufficient voltage margin to operate the tail current generator, which is usually part of a current mirror, an active load, and provide voltage margin to place the cascode stage within the circuit, the voltage swing that the actual amplifying transistor of the input stage can withstand is limited to a very limited extent. This applies even when techniques such as folded cascode stages are used to try to mitigate some of the required headroom. The limited headroom means that the voltage Vresidue applied to the residual amplifier 230 must be appropriately limited and within a reduced dynamic range. This mitigates the possibility of using a longer bit range within the first ADC converter stage, thereby correspondingly reducing the residual, and / or reducing the gain within the residual amplifier. The second stage ADC is able to change one or more digital codes provided to the residual DAC segment, thereby being able to adjust the residual to fit the operating range of the residual amplifier.

[0171] Therefore, multiple sampling DACs can be used to work together to produce an improved ADC without sacrificing noise performance.

[0172] The claims herein are presented in a single dependency format suitable for filing at the USPTO, but it is understood that for purposes of jurisdictions allowing multiple dependent claims, each claim may be dependent on any prior claim of the same type unless this is clearly technically infeasible.

[0173] example

[0174] Example 1 is a stage of an analog-to-digital converter, comprising: an analog-to-digital converter coupled to an acquisition circuit having a first time constant; and a plurality of circuits, each circuit comprising: an acquisition circuit having a time constant substantially the same as the first time constant; and a digital-to-analog converter for receiving a corresponding control signal based on a digital output of the analog-to-digital converter and forming a differential signal as a difference between a sampled voltage maintained by the acquisition circuit and the output of the digital-to-analog converter.

[0175] In Example 2, the stage according to Example 1 may optionally include: respective control signals to the digital-to-analog converters are variable.

[0176] In Example 3, the stage according to Example 1 or 2 may optionally include: at least two outputs of the plurality of circuits are combined

[0177] In Example 4, the stage according to any of Examples 1-3 can optionally include: the acquisition circuit of the plurality of circuits is a sampling capacitor digital-to-analog converter.

[0178] In Example 5, the stage according to any of Examples 1-4 may optionally include: the analog-to-digital converter includes a switched capacitor array forming a first sampling digital-to-analog converter.

[0179] In Example 6, the stage according to Example 5 can optionally include: each of the plurality of circuits includes a switched capacitor array forming an additional sampling digital-to-analog converter matched to the first sampling digital-to-analog converter.

[0180] In Example 7, the stage according to Example 6 can optionally include: the sampling digital-to-analog converters of the plurality of circuits are formed by a plurality of unit cells.

[0181] In Example 8, the stage according to any one of Examples 1-7 can optionally include: in at least one of the plurality of circuits, the acquisition circuit is part of the first sampling digital-to-analog converter and is connected to a first sub-digital-to-analog converter.

[0182] In Example 9, the stage according to any one of Examples 1-8 may optionally include: a data manipulation block for receiving a digital output of the analog-to-digital converter and modifying the output to provide a corresponding control word to a digital-to-analog converter in the plurality of circuits.

[0183] In Example 10, the stage according to any of Examples 1-9 can optionally include: updating the digital word provided to a digital-to-analog converter of the plurality of circuits is time-shifted from updating the digital-to-analog converter of the plurality of circuits.

[0184] In Example 11, the stage according to any of Examples 1-10 can optionally include: at least one spare circuit arranged to be swapped with other circuits of the other circuits.

[0185] In Example 12, the stage according to any of Examples 1-11 can optionally include: the analog-to-digital converter includes a flash converter.

[0186] In Example 13, the stage according to any one of Examples 1-11 may optionally include: the digital-to-analog converter is a pipelined analog-to-digital converter, including one or more stages according to claim 1.

[0187] Example 14 is an analog-to-digital converter utilizing multiple segments having substantially matched sampling time constants that are operable together in response to an estimate of a digital word formed by the analog-to-digital converter, wherein the analog-to-digital converter includes at least one but not all of the segments to form a residual having reduced thermal noise compared to the thermal noise of a single segment.

[0188] In Example 15, the analog-to-digital converter according to Example 14 may optionally include: the segments are formed by the same sampling digital-to-analog converter.

[0189] Example 16 is a digital-to-analog converter (DAC) comprising a plurality of substantially identical switched capacitor DAC stages, one of which is adapted to act as a main stage and at least two other stages are adapted to be connected in parallel to form a composite DAC output having reduced thermal noise compared to the thermal noise of any individual segment.

[0190] In Example 17, the DAC according to Example 16 may optionally include: the DAC stage is a sampling DAC, operable to sample an input voltage and form an output as a function of an average value of the sampled input voltage and a digital word applied to the DAC stage.

[0191] Example 18 is a method of operating multiple matched digital-to-analog converter segments to form analog-to-digital converter results and residuals, the method comprising: operating one of the matched digital-to-analog converter segments to perform analog-to-digital conversion; and operating at least two matched digital-to-analog converter segments to perform digital-to-analog conversion, thereby forming a difference between a sampled input and a digital approximation of the sampled input.

[0192] Example 19 is an analog-to-digital converter, comprising: a plurality of sampling digital-to-analog converter segments, wherein for a first capacitor, an area of ​​a capacitor plate divided by a plate spacing distance in the first segment differs from an area of ​​a corresponding capacitor in a second segment by a first ratio, and a width-to-length ratio of a transistor switch associated with a first capacitor in the first segment differs from a width-to-length ratio of a corresponding transistor in the second segment by substantially the first ratio.

[0193] Example 20 is a plurality of sampling digital-to-analog converter (DAC) segments, wherein the sampling DAC segments include: a plurality of unit cells, each unit cell including a respective unit-sized capacitor and an associated unit-sized transistor switch, and wherein the plurality of unit cells are combined together to form a weighted capacitor within the sampling DAC segments, and wherein the sampling DAC segments are connected to a shared input node to uniformly sample input signals, and are connectable to a shared output node to form an average of their respective residuals.

[0194] Example A is an apparatus comprising means for implementing / performing any one of the methods described herein.

[0195] Variants and implementations

[0196] Note that the activities discussed above with reference to the accompanying drawings apply to any integrated circuit that involves processing analog signals and converting them to digital data using one or more ADCs. These functions may be particularly beneficial for high speed ADCs with higher input frequencies (e.g., in the megahertz to gigahertz range). ADCs may be applicable to medical systems, scientific instrumentation, wireless and wired communication systems (especially those requiring high sampling rates), radar, industrial process control, audio and video equipment, instrumentation, and other systems that use ADCs. The performance levels provided by high speed ADCs are particularly suitable for products and systems in demanding markets such as high speed communications, medical imaging, synthetic aperture radar, digital beamforming communication systems, wideband communication systems, high performance imaging, and advanced test / measurement systems (oscilloscopes).

[0197] The present disclosure includes devices that can perform the various methods described herein. Such devices may include circuits shown in the accompanying drawings and described herein. The components of various devices may include electronic circuits to perform the functions described herein. The circuit may be operated in an analog domain, a digital domain, or a mixed signal domain. In some cases, one or more parts of the device may be provided by a processor specifically configured to perform the functions described herein (e.g., control-related functions, timing-related functions). In some cases, the processor may be an on-chip processor with an ADC. The processor may include one or more dedicated components, or may include a programmable logic gate configured to perform the functions described herein. In some cases, the processor may be configured to perform the functions described herein by executing one or more instructions stored on one or more non-transitory computer media.

[0198] It must also be noted that all specifications, dimensions, and relationships (e.g., number of processors, logical operations, etc.) outlined herein are provided for purposes of example and instruction only. Considerable changes may be made to this information without departing from the spirit of the present disclosure or the scope of the appended claims (if any) or the examples described herein. These specifications apply only to one non-limiting example, and therefore, they should be interpreted as such. In the foregoing description, example embodiments have been described with reference to specific processors and / or component arrangements. Various modifications and changes may be made to these embodiments without departing from the scope of the appended claims (if any) or the examples described herein. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive.

[0199] Note that, with the numerous examples provided herein, interactions can be described based on two, three, four or more electrical components or parts. However, this is done only for the purpose of clarity and example. It should be understood that the system can be combined in any suitable manner. Along similar design alternatives, any components, modules, boxes and elements shown in the drawings can be combined in various possible configurations, all of which are obviously within the broad scope of this specification. In some cases, it may be easier to describe one or more functions of a given set of processes with reference to only a limited number of electrical components. It should be understood that the circuits of the drawings and their teachings are easy to expand and can accommodate a large number of components, as well as more complex / complex arrangements and configurations. Therefore, the examples provided should not limit the scope or inhibit the broad teachings of electronic circuits that may potentially be applied to countless other architectures.

[0200] Note that in this specification, references to various features (e.g., elements, structures, modules, components, steps, operations, features,) included in "one embodiment", "example embodiment", "embodiment", "another embodiment", "certain embodiments", "various embodiments", "other embodiments", "alternative embodiments", etc.) are intended to indicate that any such features are included in one or more embodiments of the present disclosure, but may or may not be combined in the same embodiment. It is also important to note that the functions described herein only illustrate some possible functions that can be performed by or within the systems / circuits shown in the drawings. Some of these operations may be deleted or removed in appropriate places, or these operations may be significantly modified or changed without departing from the scope of the present disclosure. In addition, the timing of these operations may be greatly changed. The foregoing operational flows have been provided for purposes of example and discussion. The embodiments described herein provide great flexibility in that any suitable arrangement, timing, configuration, and timing mechanism may be provided without departing from the teachings of the present disclosure. Many other changes, substitutions, changes, alterations, and modifications may be determined by those skilled in the art, and it is intended that the present disclosure encompasses all such changes, substitutions, changes, alterations, and modifications that fall within the scope of the appended claims (if any) or the examples described herein. Note that all optional features of the apparatus described above may also be implemented with respect to the methods or processes described herein, and that the details in the examples may be used anywhere in one or more embodiments.

Claims

1. An analog-to-digital converter device comprising at least one stage, the stage comprising: an analog-to-digital converter coupled to the acquisition circuit having a first time constant; and a plurality of circuits, each circuit comprising: an acquisition circuit having a time constant substantially the same as the first time constant; and a digital-to-analog converter for receiving a corresponding control signal based on the digital output of the analog-to-digital converter and forming a differential signal as a difference between a sampled voltage maintained by the acquisition circuit and the output of the digital-to-analog converter.

2. An analog-to-digital converter arrangement according to claim 1, wherein the corresponding control signal to the digital-to-analog converter is variable.

3. The analog-to-digital converter device of claim 1, wherein outputs of at least two of the plurality of circuits are combined. 4 . The analog-to-digital converter device of claim 1 , wherein the acquisition circuit of the plurality of circuits is a sampling capacitor digital-to-analog converter.

5. The analog-to-digital converter arrangement of claim 1, wherein the analog-to-digital converter comprises an array of switched capacitors forming a first sampling digital-to-analog converter.

6. The analog-to-digital converter arrangement of claim 5, wherein each of the plurality of circuits comprises a switched capacitor array forming a further sampling digital-to-analog converter matched to the first sampling digital-to-analog converter. 7 . The analog-to-digital converter device according to claim 6 , wherein the sampling digital-to-analog converters of the plurality of circuits are formed by a plurality of unit cells.

8. The analog-to-digital converter device of claim 1, wherein in at least one of the plurality of circuits, the acquisition circuit is part of a first sampling digital-to-analog converter and is connected to a first sub-digital-to-analog converter.

9. The analog-to-digital converter arrangement of claim 1, further comprising a data manipulation block for receiving a digital output of the analog-to-digital converter and modifying the output to provide corresponding control words to digital-to-analog converters in the plurality of circuits.

10. The analog-to-digital converter arrangement of claim 1, wherein updating of a digital word provided to one of the digital-to-analog converters of the plurality of circuits is offset in time from updating of another of the digital-to-analog converters of the plurality of circuits.

11. The analog-to-digital converter arrangement of claim 1, further comprising at least one spare circuit arranged to be swapped with other of the other circuits.

12. The analog-to-digital converter device of claim 1, wherein the analog-to-digital converter device comprises a flash converter.

13. The analog-to-digital converter device of claim 1, wherein the analog-to-digital converter device is a pipeline analog-to-digital converter comprising one or more of said stages.

14. The analog-to-digital converter device according to claim 1, wherein the acquisition circuit comprises: a plurality of unit cells, each unit cell comprising a respective unit-sized capacitor and an associated unit-sized transistor switch, and wherein the plurality of unit cells are grouped together to form a weighted capacitor within the acquisition circuit, and wherein the acquisition circuit is connected to a shared input node to uniformly sample input signals, and is connectable to a shared output node to form an average of their respective residuals.

15. The analog-to-digital converter device according to claim 1 further includes a buffer amplifier selectively connected to the digital-to-analog converter to provide an internal reference signal generated by the buffer amplifier to the digital-to-analog converter during a first phase of operation of a corresponding stage in the at least one stage, and the corresponding stage further includes a switching circuit to provide an external reference signal generated by an external reference source to the digital-to-analog converter during a second phase of operation of the corresponding stage to replace the internal reference signal.

16. An analog-to-digital converter device, comprising: a plurality of segments, each segment comprising an acquisition circuit having substantially matched sampling time constants, and a digital-to-analog converter; as well as an analog-to-digital converter, comprising at least one but not all of the segments, The plurality of segments are operable together in response to a digital output of the analog-to-digital converter to form a residual that is a difference between a sampled voltage maintained by the acquisition circuit and the digital output, the residual having reduced thermal noise compared to thermal noise of a single segment.

17. Analog-to-digital converter arrangement according to claim 16, wherein the segments are formed by the same sampling digital-to-analog converter.

18. The analog-to-digital converter device of claim 16, wherein for a first capacitor, an area of ​​a capacitor plate in a first segment divided by a plate spacing distance differs from an area of ​​a capacitor plate of a corresponding capacitor in a second segment divided by a plate spacing distance by a first ratio, and a width-to-length ratio of a transistor switch associated with the first capacitor in the first segment differs from a width-to-length ratio of a corresponding transistor in the second segment by the first ratio.

19. The analog-to-digital converter device according to claim 16, wherein the acquisition circuit comprises: a plurality of unit cells, each unit cell comprising a respective unit-sized capacitor and an associated unit-sized transistor switch, and wherein the plurality of unit cells are grouped together to form a weighted capacitor within the acquisition circuit, and wherein the acquisition circuit is connected to a shared input node to uniformly sample input signals, and is connectable to a shared output node to form an average of their respective residuals.

20. A method of operating an analog-to-digital converter device, the analog-to-digital converter device being the analog-to-digital converter device according to claim 16, wherein the plurality of DAC segments are configured to form DAC results and residuals, The method includes: operating one of the matched digital-to-analog converter segments to perform analog-to-digital conversion; and At least two of the matched digital-to-analog converter segments are operated to perform digital-to-analog conversion to form a difference between a sampled input and a digital approximation of the sampled input.

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