Variable read scan for quality of service of solid-state storage devices

Abstract

A method and apparatus for dynamically determining when or how often to perform a read scan operation on a solid-state storage drive. A solution adjusts a read scan interval as part of performing a read scan operation. First, a bit error rate is determined for one of a plurality of storage blocks of a non-volatile memory array. Next, a crossover temperature metric is determined for the storage block. The read scan interval is changed in response to the crossover temperature metric satisfying a crossover temperature threshold. Next, data in the storage block is relocated to a free storage block in response to the bit error rate satisfying a relocation threshold.

Description

Background Art

[0001] Solid-state storage drives (SSDs) use periodic data integrity checks to determine whether to perform a data cleanup operation or a data refresh operation on data at locations within the drive that are at risk of degradation. This data integrity check is referred to herein as a read scan operation. Such risky locations may develop based on an increased number of program / erase (PE) cycles, length of time since data was written, cross-temperature effects, and the like.

[0002] Read scan, read scrub and / or data refresh operations are expensive operations in terms of storage device bandwidth and latency. Performing a read scan operation may interrupt the host interacting with the SSD, use additional PE cycles that cause write amplification, and take time to read all logical erase blocks (LEBs) (also called metablocks or superblocks) used on the storage device.

[0003] Implementing SSDs in markets such as server applications where Quality of Service (QoS) is critical increasingly requires intelligent balancing of SSD read scan operations with quality and speed of service. Therefore, there is a need to implement SSD read scan operations in a more efficient manner than conventional periodic schemes. Summary of the invention

[0004] The present disclosure relates to a method for dynamically implementing a read scan operation on an SSD. First, a bit error rate is determined for one of a plurality of storage blocks of a non-volatile memory array. Next, a cross temperature metric of the storage block is determined. A read scan interval may be changed in response to the cross temperature metric satisfying a cross temperature threshold. Finally, data in the storage block is relocated to a free storage block in response to the bit error rate satisfying a relocation threshold. A "read scan interval" refers to a period of time between consecutive executions of a read scan operation.

[0005] The present disclosure also relates to a device, which includes a read scanner, an error correction code decoder, a health manager, and a data mover. The read scanner is configured to read data from one of a plurality of storage blocks of a non-volatile memory array. The non-volatile memory array includes a plurality of memory dies. Each memory die includes a temperature sensor. The error correction code decoder is configured to determine a bit error rate of data read by the read scanner. The health manager is configured to determine that a storage block spans the hottest memory die among the plurality of memory dies based on the die temperature reported by each temperature sensor. The data mover is configured to move data from a storage block to a free storage block in response to the bit error rate satisfying a read bit error rate threshold. The read scanner is configured to reduce a read scan interval of a read scan operation in response to determining that a storage block spans the hottest memory die.

[0006] Finally, the present disclosure relates to a device, which includes a plurality of memory blocks and a memory controller. The memory controller is configured to determine a memory block among the plurality of memory blocks having a bit error rate higher than a read bit error rate threshold. The memory controller then iteratively attempts to read data from the memory block using a predetermined number of different read levels. In response to successfully reading the data of the memory block via iterative reading, the memory controller changes one or more read levels of the memory block to one or more of the predetermined number of different read levels used to successfully read the data of the memory block. Finally, the memory controller increases the read scan frequency of the plurality of memory blocks in response to changing the one or more read levels. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] To easily identify the discussion of any particular element or act, the most significant digit(s) in a reference number refers to the figure number in which the element is first introduced.

[0008] Figure 1 is a block diagram of a storage system 100 according to one embodiment.

[0009] Figure 2 is a block diagram of storage device 102 in one embodiment.

[0010] Figure 3 A memory array 300 is shown according to one embodiment.

[0011] Figure 4 is a block diagram of an example storage system 400 according to one embodiment.

[0012] Figure 5 A memory block configuration 500 is shown according to one embodiment.

[0013] Figure 6 is a block diagram of an example storage system 600 according to one embodiment.

[0014] Figure 7 Configuration parameters of a multi-level memory cell 700 associated with one embodiment are shown.

[0015] Figure 8 Adjusted configuration parameters of a multi-level memory cell 800 are shown according to one embodiment.

[0016] Fig. 9 is a block diagram of an example storage system 900 according to one embodiment.

[0017] Fig.10 A configuration parameter table 1000 is shown for use with one embodiment.

[0018] Fig.11 A memory block configuration 1100 is shown according to one embodiment.

[0019] Fig.12 A method 1200 is shown according to one embodiment.

[0020] Fig.13 is an example block diagram of a computing device 1300 that may incorporate certain embodiments. DETAILED DESCRIPTION

[0021] When the SSD has experienced a long period of time or a high number of PE cycles since data was written, the bit error rate may increase. Cross-temperature effects may also cause higher bit error rates. Therefore, a dynamically implemented read scan solution may adjust the frequency of the read scan or the interval for initiating the read scan, or whether to initiate the read scan operation immediately. The read scan frequency may be adjusted based on detected cross-temperature conditions, based on a temperature scan indicating a temperature increase of a particular logical erase block, metablock, or die within a metablock, and / or based on a cell threshold voltage distribution (CVD) scan that detects that the read level needs to be changed because the bit error rate at the current read level is too high.

[0022] A "read scan operation" refers to a maintenance operation performed to identify and mitigate or avoid or count errors in data or memory cells and / or other components of a non-volatile storage device. A read scan operation may be interchangeably referred to as a "read scan" or "read scan operation."

[0023] In one embodiment, the read scan operation involves reading data from memory cells in a memory block, or sensing a determinable physical characteristic or memory state of the memory cells. Next, the read scan operation checks the memory state of the memory cells for any errors, corrects as many errors as possible, and determines a bit error rate. Next, the read scan operation determines whether the bit error rate meets a threshold, such as a read bit error rate threshold.

[0024] In one embodiment, the read scan operation reads data from each logical page or word line of the memory block. In another embodiment, the read scan operation selects less than all logical pages of the memory block. In other words, the read scan operation can sample the logical pages of the memory block from which data is read for the read scan operation.

[0025] If the read bit error rate threshold is met, then the read scan operation may perform a data scrubbing operation or a data refresh operation. In some embodiments, the read scan operation may always include a data scrubbing operation or a data refresh operation. In other embodiments, performing a data scrubbing operation or a data refresh operation may be conditional on the bit error rate meeting the read bit error rate threshold. In such embodiments, the read scan operation may be referred to as a "read scrubbing" or a "read scrubbing operation". In these embodiments, the read scan operation may conditionally include a data scrubbing operation.

[0026] In some embodiments, the read scan operation may be operated as a foreground process, meaning that the read scan operation interrupts or delays the non-volatile storage device from servicing a read command or a write command from the host. In addition, the read scan operation may need to complete work on a particular storage block and thereby delay a host read command for data on the particular storage block. Therefore, the read scan operation may affect the quality of service level between the host and the non-volatile storage device.

[0027] "PE cycles" refers to a count of the number of times a set of memory cells is programmed and erased. A set of memory cells may include any set of memory cells, including a data block, a word line, a page, a logical page, an erase block, a logical erase block, a memory array, a memory die, or the like. PE cycles (PEC) may be specified in thousands, such as 4k, 50k, and the like.

[0028] Non-volatile storage devices such as solid-state memory may have lower data retention capacity at higher temperatures, and this lower capacity may further deteriorate as the memory wears. Non-volatile storage devices may be configured to provide a certain level of error correction capacity. If errors exceed this level, the data with these errors may become unreadable. However, data stored on non-volatile memory media within a range of temperatures may exhibit lower susceptibility to data retention issues, even if the memory has experienced wear.

[0029] Cross temperature is a common phenomenon in non-volatile memory media such as NAND flash memory and is related to the temperature difference between storage operations. "Cross temperature" refers to the condition where the die temperature of a memory cell when the memory cell is read / sensed is different from the die temperature of the same memory cell when the memory cell is written (programmed). In some embodiments, the cross temperature may be represented by a value called a cross temperature metric. In certain types of non-volatile memory media (such as NAND memory cells), when the difference between the die temperature when the memory cell is written and the die temperature when the memory cell is read is high enough, the data of the memory cell may become unreadable (the read command results in an error). Currently, non-volatile memory devices have countermeasures so that data stored in non-volatile memory subjected to cross temperature conditions can be read, however, the non-volatile memory device should detect the cross temperature conditions so that these countermeasures can be adopted.

[0030] This crossover temperature phenomenon is known to produce both a shift in the cell threshold voltage distribution (CVD) and a widening of the CVD. The shift phenomenon may be related to the different sensitivities of different NAND cells to the crossover temperature. When the CVD has shifted far enough, it may affect the bit error rate and thus may contribute to conditions requiring data scrubbing operations.

[0031] Figure 1is a schematic block diagram illustrating one embodiment of a storage system 100 according to the disclosed solution. The storage system 100 includes a storage device 102, a storage controller 104, a memory die 108, a host 110, a user application 112, a storage client 114, a logical address space 116, metadata 118, a flash translation layer 120, a data bus 122, a bus 124, at least one host 126, and a network 128.

[0032] "Storage Client" refers to any hardware, software, firmware, or logic component or module configured to communicate with a storage device in order to use a storage service. Examples of storage clients include, but are not limited to, operating systems, file systems, database applications, database management systems ("DBMS"), server applications, servers, volume managers, kernel-level processes, user-level processes, applications, mobile applications, threads, processes, and the like. "Hardware" refers to functional elements embodied as analog and / or digital circuitry. "Firmware" refers to logic embodied as processor-executable instructions stored on volatile memory media and / or non-volatile memory media. "Software" refers to logic implemented as processor-executable instructions in machine memory (e.g., read / write volatile memory media or non-volatile memory media). "Logic" refers to machine memory circuits, non-transitory machine-readable media, and / or circuitry that, by virtue of its material and / or material energy configuration, includes control and / or program signals, and / or settings and values ​​(e.g., resistance, impedance, capacitance, inductance, current / voltage ratings, etc.) that can be applied to affect the operation of the device. Magnetic media, electronic circuits, optoelectronic memory (both volatile and non-volatile), and firmware are examples of logic. Logic specifically excludes pure signals or software per se (although it does not exclude machine memory that includes software and thereby forms a configuration of matter).

[0033] "Data block" refers to the smallest physical amount of storage space on a physical storage medium that is accessible and / or addressable using storage commands. The physical storage medium may be a volatile memory medium, a non-volatile memory medium, a permanent storage device, a non-volatile storage device, a flash storage medium, a hard drive, or the like. Some conventional storage devices divide the physical storage medium into volumes or logical partitions (also referred to as partitions). Each volume or logical partition may contain multiple sectors. One or more sectors are organized into blocks (also referred to as data blocks). In applications such as those related to In some storage systems that interface with an operating system, data blocks are referred to as clusters. In other storage systems, such as those that interface with UNIX, Linux, or similar operating systems, data blocks are simply referred to as blocks. A data block or cluster represents the smallest physical amount of storage space on a storage medium that is managed by a storage controller. A block storage device may associate n data blocks that can be used to store user data across a physical storage medium with logical block addresses (LBAs), numbered from 0 to n. In some block storage devices, logical block addresses may range from 0 to n per volume or logical partition. In conventional block storage devices, a logical block address maps directly to one and only one data block.

[0034] A "storage operation" refers to an operation performed on a memory cell to change or obtain the value of data represented by the state characteristic of the memory cell. Examples of storage operations include, but are not limited to, reading data from a memory cell (or sensing the state of a memory cell), writing (or programming) data to a memory cell, and / or erasing data stored in a memory cell.

[0035] "Storage command" refers to any command related to storage operations. Examples of storage commands include, but are not limited to, read commands, write commands, maintenance commands, diagnostic commands, test mode commands, countermeasure commands, and any other command that a storage controller may receive from a host or issue to another component, device, or system. "Countermeasure command" refers to a storage command configured to implement a countermeasure to mitigate or reverse degradation of a storage block and / or degraded storage block health.

[0036] "Volatile memory medium" refers to any hardware, device, component, element, or circuit configured to maintain a changeable physical property used to represent a binary value of zero or one, wherein when main power is removed or unless main power is used to refresh the represented binary value, the changeable physical property reverts to a default state that no longer represents the binary value. Examples of volatile memory media include, but are not limited to, dynamic random access memory (DRAM), static random access memory (SRAM), double data rate random access memory (DDR RAM), or other random access solid-state memory.

[0037] Although volatile memory media is referred to herein as "memory media," in various embodiments, volatile memory media may be more generally referred to as volatile memory.

[0038] In certain embodiments, data stored in the volatile memory medium may be addressed at a byte level, which means that the data in the volatile memory medium is organized into data bytes (8 bits) that each have a unique address (eg, a logical address).

[0039] "Memory" refers to any hardware, circuit, component, module, logic, device, or apparatus that is configured, programmed, designed, arranged, or engineered to retain data. Some types of memory require constant power to be available to store and retain data. Other types of memory retain and / or store data when power is not available.

[0040] "Uncorrectable bit error rate" refers to a measure of the rate that indicates the number of bits that are uncorrectable and erroneous for a given number of bits processed. Uncorrectable bits are considered uncorrectable after trying one or more error correction techniques (e.g., using error correction codes (ECC), using Bose, Chaudhuri, Hocquenghem (BCH) codes, using low-density parity check (LDPC) algorithms, and the like).

[0041] "Fail bit count" refers to a measurement of the number of bits that are in error for a given unit of measurement. An errored bit is a bit that is stored with one value, but when the same bit is read or sensed, the bit indicates a different value. The fail bit count may be measured for a data block (e.g., 4K), erase block, page, logical erase block, zone, namespace, or the like. In other words, the fail bit count may be the number of bits that differ between data written to a data block, physical erase block, or other grouping of memory cells and data subsequently read from the data block, physical erase block, or other grouping of memory cells.

[0042] The storage system 100 includes at least one storage device 102, which includes a storage controller 104 and one or more memory dies 108 connected by a bus 124. In some embodiments, the storage system 100 may include two or more memory devices. A "storage device" refers to any hardware, system, subsystem, circuit, component, module, non-volatile memory medium, hard drive, storage array, device, or apparatus that is configured, programmed, designed, or engineered to store data for a period of time and to retain the data in the storage device when the storage device is not using power from a power source. Examples of storage devices include, but are not limited to, hard drives, flash memories, MRAM memories, solid-state storage devices, just-in-one disks (JBODs), just-in-one flash memories (JBOFs), external hard drives, internal hard drives, and the like.

[0043] "Memory die" refers to a small piece of semiconductor material on which a given functional circuit is fabricated. Integrated circuits are typically produced in bulk on a single wafer of electronic grade silicon (EGS) or other semiconductors (e.g., GaAs) by processes such as photolithography. The wafer is cut (sliced) into many pieces, each containing a copy of the circuit. Each of these pieces is called a bare die or memory die. (Search for "bare die (integrated circuit)" on Wikipedia.com, October 9, 2019, accessed November 18, 2019.)

[0044] In one embodiment, a memory die is a die that includes one or more functional circuits for operating as a non-volatile memory medium and / or a non-volatile memory array. "Non-volatile memory medium" refers to any hardware, device, component, element, or circuit that is configured to maintain a changeable physical property used to represent a binary value of zero or one after the removal of main power. Examples of changeable physical properties include, but are not limited to, the threshold voltage of a transistor, the resistance level of a memory cell, the current level through the memory cell, the magnetic polarity orientation, the spin transfer torque, and the like.

[0045] The changeable physical property is such that once set, the physical property remains sufficiently fixed that the changeable physical property can be measured, detected, or sensed when reading, retrieving, or sensing a binary value when the main power supply for the non-volatile memory medium is unavailable. In other words, the non-volatile memory medium is a storage medium configured such that data stored on the non-volatile memory medium can be retrieved after the power supply for the non-volatile memory medium is removed and subsequently restored. The non-volatile memory medium may include one or more non-volatile memory elements, which may include, but are not limited to: chips, packages, planes, memory dies, and the like.

[0046] Examples of non-volatile memory media include, but are not limited to, ReRAM, memristor memory, programmable metallization cell memory, phase change memory (PCM, PCME, PRAM, PCRAM, bidirectional universal memory, chalcogenide RAM or C-RAM), NAND flash memory (e.g., 2D NAND flash memory, 3D NAND flash memory), NOR flash memory, nano random access memory (nano RAM or NRAM), nanocrystalline wire-based memory, silicon-oxide-based sub-10 nanometer process memory, graphene memory, silicon-oxide-nitride-oxide-silicon (SONOS), programmable metallization cell (PMC), conductive bridge RAM (CBRAM), magnetoresistive RAM (MRAM), magnetic storage media (e.g., hard disk, tape), optical storage media, or the like.

[0047] Although non-volatile memory media are referred to herein as "memory media", in various embodiments, non-volatile memory media may be more generally referred to as non-volatile memory. Since non-volatile memory media are able to store data when power is removed, non-volatile memory media may also be referred to as recording media, non-volatile recording media, non-volatile storage media, storage devices, non-volatile memory, volatile memory media, non-volatile storage media, non-volatile storage devices, or the like.

[0048] In some embodiments, data stored in the non-volatile memory medium may be addressed at a block level, which means that the data in the non-volatile memory medium is organized into data blocks each having a unique logical address (e.g., LBA). In other embodiments, data stored in the non-volatile memory medium may be addressed at a byte level, which means that the data in the non-volatile memory medium is organized into data bytes (8 bits) each having a unique address (e.g., logical address). An example of a byte-addressable non-volatile memory medium is a storage class memory (SCM).

[0049] "Non-volatile memory" is short for non-volatile memory medium. In some embodiments, non-volatile memory medium refers to non-volatile memory medium and logic, controller, processor, state machine and / or other peripheral circuits that manage the non-volatile memory medium and provide access to the non-volatile memory medium. "Non-volatile memory array" refers to a collection of non-volatile memory cells (also called memory cells or non-volatile memory cells) organized into an array structure having rows and columns. The memory array can be addressed using row identifiers and column identifiers.

[0050] A "memory cell" refers to a type of storage medium that is configured to represent one or more binary values ​​by means of a determinable physical characteristic of the storage medium when the storage medium is sensed, read, or detected to determine the binary value last stored in the memory cell. Memory cell and storage cell are used interchangeably herein.

[0051] "Memory cell" refers to a type of storage medium that is configured to represent one or more binary values ​​by means of a determinable characteristic of the storage medium when the storage medium is sensed, read, or detected to determine the binary value stored or represented by the determinable characteristic of the memory cell. Storage cell and memory cell are used interchangeably herein.

[0052] The type of determinable characteristic used to store data in a memory cell may vary depending on the type of memory or storage technology used. For example, in a flash memory cell where each memory cell includes a transistor having a source lead, a drain lead, and a gate, the determinable characteristic is the voltage level that, when applied to the gate, causes the memory cell to conduct current between the drain lead and the source lead. In this example, the voltage level is referred to herein as a threshold voltage. The threshold voltage may also be referred to as a control gate reference voltage (CGRV), a read voltage, or a reference voltage.

[0053] Examples of physical characteristics that may be determined include, but are not limited to, the threshold voltage of a transistor, the resistance level of a memory cell, the current level through a memory cell, magnetic polarity orientation, spin transfer torque, and the like.

[0054] Each storage device 102 may include two or more memory dies 108, such as flash memory, nano random access memory ("nano RAM or NRAM"), magnetoresistive RAM ("MRAM"), dynamic RAM ("DRAM"), phase change RAM ("PRAM"), etc. In further embodiments, the data storage device 102 may include other types of non-volatile and / or volatile data storage devices, such as dynamic RAM ("DRAM"), static RAM ("SRAM"), magnetic data storage devices, optical data storage devices, and / or other data storage technologies. The memory dies 108 may be configured into a non-volatile memory array 106. A "memory array" refers to a collection of memory cells (also referred to as memory cells) organized into an array structure having rows and columns. The memory array may be addressed using row identifiers and column identifiers.

[0055] Thus, a nonvolatile memory array is a memory array having memory cells configured so that the characteristics of the memory cells (e.g., threshold voltage level, resistance level, conductivity, etc.) used to represent stored data retain the properties of the memory cells without requiring the use of a power source to maintain the characteristics.

[0056] The memory array may be addressed using row and column identifiers. Those skilled in the art recognize that the memory array may include a set of memory cells within a plane, a set of memory cells within a memory die, a set of memory cells within a set of planes, a set of memory cells within a set of memory dies, a set of memory cells within a memory package, a set of memory cells within a set of memory packages, or have other known memory cell arrangement architectures and configurations.

[0057] A memory array may include a collection of memory cells at a storage system or several organizational levels within a memory system. In one embodiment, memory cells within a plane may be organized into a memory array. In one embodiment, memory cells within multiple planes of a memory die may be organized into a memory array. In one embodiment, memory cells within multiple memory dies of a memory device may be organized into a memory array. In one embodiment, memory cells within multiple memory devices of a storage system may be organized into a memory array.

[0058] The storage device 102 (also referred to herein as a storage device) can be a component within the host 110 as depicted herein and can be connected using a data bus 122, such as a Peripheral Component Interconnect Express ("PCI-e") bus, a Serial Advanced Technology Attachment ("Serial ATA") bus, or the like. In another embodiment, the storage device 102 is external to the host 110 and connects a Universal Serial Bus ("USB") connection, an Institute of Electrical and Electronics Engineers ("IEEE") 1394 bus ("FireWire"), or the like. In other embodiments, the storage device 102 is connected to the host 110 using a Peripheral Component Interconnect ("PCI") Express bus that uses an external electrical or optical bus extension or bus networking solution, such as InfiniBand or PCI Express Advanced Switching ("PCIe-AS"), or the like.

[0059] In various embodiments, storage device 102 may be in the form of a dual in-line memory module ("DIMM"), a daughter card, or a micromodule. In another embodiment, storage device 102 is a component within a rack-mounted blade. In another embodiment, storage device 102 is contained within a package that is directly integrated onto a higher-level assembly (e.g., a backplane, a laptop computer, a graphics processor). In another embodiment, various components comprising storage device 102 are directly integrated onto a higher-level assembly without an intermediate package.

[0060] In yet another embodiment, the data storage device 102 may be connected to the host 110 via a data network, rather than being directly connected to the host 110 as a DAS. For example, the data storage device 102 may include a storage area network ("SAN") storage device, a network attached storage ("NAS") device, a network share, or the like. In one embodiment, the storage system 100 may include a data network, such as the Internet, a wide area network ("WAN"), a metropolitan area network ("MAN"), a local area network ("LAN"), a token ring, a wireless network, a fiber channel network, a SAN, a NAS, an ESCON, or the like, or any combination of networks. The data network may also include a network from the IEEE 802 family of network technologies, such as Ethernet, token ring, Wi-Fi, Wi-Max, and the like. The data network may include servers, switches, routers, cables, wireless, and other instruments used to facilitate networking between the host 110 and the data storage device 102.

[0061] The storage system 100 includes at least one host 110 connected to the storage device 102. "Host" refers to any computing device or computer device or computer system configured to send and receive storage commands. Examples of hosts include, but are not limited to, computers, laptops, mobile devices, appliances, virtual machines, enterprise servers, desktop computers, tablet computers, mainframes, and the like.

[0062] A plurality of hosts 110 may be used and may include servers, storage controllers of a storage area network ("SAN"), workstations, personal computers, laptop computers, handheld computers, supercomputers, computer clusters, network switches, routers or appliances, databases or storage appliances, data acquisition or data capture systems, diagnostic systems, test systems, robots, portable electronic devices, wireless devices, or the like. In another embodiment, the host 110 may be a client and the storage device 102 operates autonomously to service data requests sent from the host 110. In this embodiment, the host 110 and the storage device 102 may be connected using a computer network, a system bus, direct attached storage (DAS), or other communication means suitable for connection between a computer and an autonomous storage device 102.

[0063] The depicted embodiment shows a user application 112 in communication with a storage client 114 as part of a host 110. In one embodiment, the user application 112 is a software application that operates on or in conjunction with the storage client 114.

[0064] The storage clients 114 manage files and data and utilize the functions and features of the storage controller 104 and the associated memory die 108. Representative examples of storage clients include, but are not limited to, servers, file systems, operating systems, database management systems ("DBMS"), volume managers, and the like. The storage clients 114 communicate with the storage controller 104 within the storage device 102. In some embodiments, the storage clients 114 may include remote storage clients operating on a host 126 or otherwise accessible via a network 128. The storage clients may include, but are not limited to, operating systems, file systems, database applications, server applications, kernel-level processes, user-level processes, applications, and the like.

[0065] The storage client 114 may present a logical address space 116 to the host 110 and / or the user application 112. The logical address space 116 may include a plurality (e.g., a range of) logical addresses. As used herein, a logical address refers to any identifier used to reference a memory resource (e.g., data), including but not limited to a logical block address (LBA), a cylinder / head / sector (CHS) address, a file name, an object identifier, an index section, a universally unique identifier (UUID), a globally unique identifier (GUID), a hash code, a signature, an index entry, a range, an extent, or the like.

[0066] "Logical address space" refers to a logical representation of a memory resource. A logical address space may include multiple (e.g., a range of) logical addresses. "Logical address" refers to any identifier used to reference a memory resource (e.g., data), including but not limited to a logical block address (LBA), a cylinder / head / sector (CHS) address, a file name, an object identifier, an index section, a universally unique identifier (UUID), a globally unique identifier (GUID), a hash code, a signature, an index entry, a range, an extent, or the like. A logical address does not indicate the physical location of data on a storage medium, but is an abstract reference to data. "Logical block address" refers to a value used in a block storage device to associate an address with each of n data blocks that may be used to store user data across a storage medium. In some block storage devices, logical block addresses (LBAs) may range from 0 to n per volume or partition. In a block storage device, each LBA maps directly to a specific data block, and each data block maps to a specific set of physical sectors on a physical storage medium.

[0067] In one embodiment, a device driver of the host 110 (and / or storage client 114) may maintain metadata 118 within the storage client 114, such as a logical to physical address mapping structure to map logical addresses of the logical address space 116 to storage locations on the memory die 108. In another embodiment, such metadata 118 may be stored and maintained by the storage controller 104. The device driver may be configured to provide storage services to one or more storage clients.

[0068] The storage client 114 may include a flash translation layer 120. "Flash translation layer" refers to logic in a flash memory device that includes an abstract logical-to-physical address translation that provides logical block addresses used by the storage client and physical block addresses where the storage controller stores data. The logical-to-physical translation layer maps logical block addresses (LBAs) to physical addresses of data stored on the solid-state storage medium. This mapping allows data to be referenced in the logical block address space using a logical identifier, such as a block address. The logical identifier does not indicate the physical location of the data on the solid-state storage medium, but is an abstract reference to the data.

[0069] The flash translation layer 120 receives the processed data and one or more control signals to determine the flash translation layer queue depth. The flash translation layer 120 can determine the appropriate physical addresses to send data and commands to the memory die 108 and the volatile memory. In certain embodiments, the storage client 114 can include the flash translation layer 120 and can manage metadata 118 associated with the flash translation layer 120. In one embodiment, the flash translation layer 120 also receives data output from the memory die 108.

[0070] In one embodiment, the storage system 100 includes one or more clients connected to one or more hosts 126 via one or more computer networks 128. The host 126 may be a server, a storage controller of a SAN, a workstation, a personal computer, a laptop computer, a handheld computer, a supercomputer, a computer cluster, a network switch, a router or an appliance, a database or storage appliance, a data acquisition or data capture system, a diagnostic system, a test system, a robot, a portable electronic device, a wireless device, or the like. The network 128 may include the Internet, a wide area network ("WAN"), a metropolitan area network ("MAN"), a local area network ("LAN"), a token ring, a wireless network, a fiber channel network, a SAN, a network attached storage ("NAS"), ESCON, or the like, or any combination of networks. The network 128 may also include a network from the IEEE 802 family of network technologies, such as Ethernet, token ring, WiFi, WiMax, and the like.

[0071] The network 128 may include servers, switches, routers, cabling, wireless, and other equipment used to facilitate networking of the host 110 or hosts with the host 126 or clients. In one embodiment, the storage system 100 includes multiple hosts communicating as peers via the network 128. In another embodiment, the storage system 100 includes multiple storage devices communicating as peers via the network 128. Those skilled in the art will recognize other computer networks including one or more computer networks and related equipment with single or redundant connections between one or more clients, or other computers with one or more storage devices or one or more storage devices connected to one or more hosts. In one embodiment, the storage system 100 includes two or more storage devices connected to the host 126 via the network 128 without the host 110.

[0072] In one embodiment, the storage client 114 communicates with the storage controller 104 through a host interface including an input / output (I / O) interface. For example, the storage device 102 may support the ATA interface standard maintained by the International Committee for Information Technology Standards ("INCITS"), the ATA Packet Interface ("ATAPI") standard, the Small Computer System Interface ("SCSI") standard, and / or the Fibre Channel standard.

[0073] In some embodiments, the storage medium of the memory device is divided into volumes or partitions. Each volume or partition may contain multiple sectors. Traditionally, a sector is 512 bytes of data. One or more sectors are organized into blocks (interchangeably referred to herein as blocks and data blocks).

[0074] In one example embodiment, a data block contains eight sectors of 4 KB. In some storage systems that interface with an operating system, a block of data is referred to as a cluster. In other storage systems, such as those that interface with UNIX, Linux, or similar operating systems, a block of data is simply referred to as a block. A block or data block or cluster represents the smallest physical amount of storage space on a storage medium that is managed by a storage manager, such as a storage controller, storage system, storage unit, storage device, or the like.

[0075] In some embodiments, storage controller 104 may be configured to store data on one or more asymmetric write-once storage media, such as solid-state storage memory cells within memory die 108 .

[0076] "Write-once storage media" refers to storage media, such as storage cells, that must be reinitialized (e.g., erased) before new data or changes to data are written or programmed thereon. In other words, data on a write-once storage medium cannot be overwritten, and the write-once storage medium must be erased before data is subsequently written to the write-once storage medium. A read scan operation may not be interruptible or may not be easily interruptible.

[0077] As used herein, an "asymmetric" storage medium refers to a storage medium that has different latencies for different storage operations. Many types of solid-state storage media (e.g., memory dies) are asymmetric; for example, read operations may be much faster than write / program operations, and write / program operations may be much faster than erase operations (e.g., reading a storage medium may be hundreds of times faster than erasing, and tens of times faster than programming a storage medium). The memory die 108 may be partitioned into memory partitions (e.g., erase blocks) that may be erased as a group, in order to particularly account for the asymmetric nature of the memory die 108 or the like.

[0078] Thus, modifying a single data segment in-place may include erasing an entire erase block including the data, and overwriting the modified data to the erase block along with the initial unchanged data. This may result in inefficient write amplification, which may excessively wear the memory die 108. "Write amplification" refers to the measurement of write programming operations performed on a non-volatile storage device that result in any data and (particularly) user data being written more times than the data was initially written in the first case. In some embodiments, write amplification may count the number of write operations performed by the non-volatile storage device in order to manage and maintain the data stored on the non-volatile storage device. In other embodiments, write amplification measures the amount of data, the number of bits, written in addition to the initial storage of data on the non-volatile storage device.

[0079] Thus, in some embodiments, the storage controller 104 may be configured to write data offsite. As used herein, writing data "offsite" refers to writing the data to a different media storage location, rather than overwriting the data "in place" (e.g., overwriting the data's original physical location). Modifying data offsite may avoid write amplification, since existing valid data on an erase block having data to be modified does not have to be erased and re-copied. Additionally, writing data offsite may remove erase from the latency path of many storage operations (e.g., erase latency is no longer part of the primary path of a write operation).

[0080] Managing data blocks by the storage manager specifically includes addressing specific data blocks for read operations, write operations, or maintenance operations. Block storage devices may associate n blocks available for storing user data across storage media with logical addresses, numbered from 0 to n. In some block storage devices, logical addresses may range from 0 to n per volume or partition.

[0081] In conventional block storage devices, logical addresses are directly mapped to specific data blocks on the physical storage medium. In conventional block storage devices, each data block is mapped to a specific set of physical sectors on the physical storage medium. However, some storage devices do not directly or necessarily associate logical addresses with specific physical data blocks. These storage devices can emulate conventional block storage interfaces to maintain compatibility with block storage clients 114.

[0082] In one embodiment, the storage controller 104 provides a block I / O emulation layer that acts as a block device interface or API. In this embodiment, the storage client 114 communicates with the storage device through this block device interface. In one embodiment, the block I / O emulation layer receives commands and logical addresses from the storage client 114 according to this block device interface. Therefore, the block I / O emulation layer provides storage device compatibility with the block storage client 114.

[0083] In one embodiment, storage clients 114 communicate with storage controller 104 through a host interface including a direct interface. In this embodiment, the storage devices directly exchange information specific to non-volatile storage devices. "Non-volatile storage device" refers to any hardware, device, component, element, or circuit configured to maintain a changeable physical property used to represent a binary value of zero or one after the removal of main power. Examples of non-volatile storage devices include, but are not limited to, hard disk drives (HDDs), solid-state drives (SSDs), non-volatile memory media, and the like.

[0084] Storage devices using a direct interface may store data in the memory die 108 using various organizational structures including, but not limited to, blocks, sectors, pages, logical blocks, logical pages, erase blocks, logical erase blocks, ECC code words, logical ECC code words, or any other format or structure that is conducive to the technical characteristics of the memory die 108.

[0085] The storage controller 104 receives logical addresses and commands from the storage client 114 and performs corresponding operations associated with the memory die 108. The storage controller 104 may support block I / O emulation, direct interface, or both. A "storage controller" refers to any hardware, device, component, element, or circuit configured to manage data operations on a non-volatile memory medium, and may include one or more processors, programmable processors (e.g., FPGAs), ASICs, microcontrollers, or the like. In some embodiments, the storage controller is configured to store data on and / or read data from a non-volatile memory medium, to transfer data to / from a non-volatile memory device, and the like.

[0086] Figure 2is a block diagram of a memory device 102. The memory device 102 may include a memory controller 104 and a non-volatile memory array 106. Each memory die 108 in the non-volatile memory array 106 may include a die controller 202 and at least one memory cell array 210 in a three-dimensional array, and a read / write circuit 204.

[0087] The memory cell array 210 is addressable by word lines corresponding to rows via a row decoder 206, and by bit lines via a column decoder 208. A "word line" refers to a structure within a memory array that includes a collection of memory cells. The memory array is configured so that the operational memory cells of a word line are read or sensed during a read operation. Similarly, the memory array is configured so that the operational memory cells of a word line are read or sensed during a read operation. The read / write circuit 204 includes a plurality of sense blocks SB1, sense blocks SB2, ... sense blocks SBp (sense circuitry) and allows pages of memory cells to be read or programmed in parallel. In some embodiments, each memory cell across a row of the memory array together forms a physical page.

[0088] A physical page may include memory cells for a single plane or for a single memory die along a row of a memory array. In one embodiment, a memory die includes a memory array consisting of two planes of equal size. In one embodiment, a physical page of one plane of a memory die includes four data blocks (e.g., 16KB). In one embodiment, a physical page of a memory die (also referred to as a "die page") includes two planes with four data blocks (e.g., 32KB) each.

[0089] Commands and data, such as those that cause storage operations 130 to occur, are communicated between the host 110 and the storage controller 104 via data bus 122 and between the storage controller 104 and one or more memory dies 108 via bus 124 .

[0090] The memory cell array 210 may be two-dimensional (2D arrangement in a single manufacturing plane) or three-dimensional (3D arrangement in multiple manufacturing planes). The memory cell array 210 may include one or more arrays of memory cells including a 3D array. In one embodiment, the memory cell array 210 may include a monolithic three-dimensional memory structure (3D array) in which multiple memory levels are formed above a single substrate such as a wafer without an intervening substrate (and not formed in the single base). The memory cell array 210 may include any type of non-volatile memory monolithically formed in one or more physical levels of an array of memory cells having active regions disposed above a silicon substrate. The memory cell array 210 may be in a non-volatile solid-state drive having circuitry associated with the operation of the memory cells (whether the associated circuitry is above or within the substrate).

[0091] "Circuitry" refers to a circuit system having at least one discrete circuit, a circuit system having at least one integrated circuit, a circuit system having at least one application-specific integrated circuit, a circuit system forming a general-purpose computing device configured by a computer program (for example, a general-purpose computer configured by a computer program that at least partially performs the processes or devices described herein, or a microprocessor configured by a computer program that at least partially performs the processes or devices described herein), a circuit system forming a memory device (for example, in the form of random access memory), or a circuit system forming a communication device (for example, a modem, a communications switch, or an optoelectronic instrument).

[0092] A word line may include a segment of a layer containing memory cells disposed in a layer above a substrate.Multiple word lines may be formed on a single layer with the aid of trenches or other non-conductive isolation features.

[0093] The die controller 202 cooperates with the read / write circuit 204 to perform memory operations on the memory cells of the memory cell array 210, and includes a state machine 212, an address decoder 214, and a power control 216. The state machine 212 provides chip-level control of memory operations.

[0094] The address decoder 214 provides an address interface between the address interface used by the host or storage controller 104 and the hardware address used by the row decoder 206 and the column decoder 208. The power control 216 controls the power and voltage supplied to various control lines during memory operations. The power control 216 and / or the read / write circuit 204 may include drivers for word lines, source gate select (SGS) transistors, drain gate select (DGS) transistors, bit lines, substrates (in 2D memory structures), charge pumps, and source lines. In certain embodiments, the power control 216 may detect sudden power failures and take preventive actions. The power control 216 may include various first voltage generators (e.g., drivers) to generate the voltages described herein. In one approach, the sense block may include a bit line driver and a sense amplifier.

[0095] In some embodiments, some of the components may be combined. In various designs, in addition to the memory cell array 210, one or more of the components (alone or in combination) may be considered to be at least one control circuit or memory controller configured to perform the techniques described herein. For example, the control circuit may include any one or combination of the following: die controller 202, state machine 212, address decoder 214, column decoder 208, power control 216, sense block SB1, sense block SB2...sense block SBp, read / write circuit 204, memory controller 104, and the like.

[0096] In one embodiment, host 110 is a computing device (e.g., laptop, desktop, smartphone, tablet, digital camera) that includes one or more processors, one or more processor-readable storage devices (RAM, ROM, flash memory, hard drive, solid-state memory) that stores processor-readable code (e.g., software) for programming storage controller 104 to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces and / or one or more input / output devices that communicate with the one or more processors, and other components well known in the art.

[0097] The associated circuitry is typically used for the operation of the memory cell and for communicating with the memory cell. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory cell to implement functions such as programming and reading. This associated circuitry may be located on the same substrate as the memory cell and / or on a separate substrate. For example, a memory controller for memory read and write operations may be located on a separate memory controller chip and / or located on the same substrate as the memory cell.

[0098] Those skilled in the art will recognize that the disclosed techniques and apparatus are not limited to the two and three dimensional exemplary structures described, but instead cover all related memory structures within the spirit and scope of the technology as described herein and as understood by those skilled in the art.

[0099] Figure 3 A memory array 300 is shown in accordance with one embodiment. In the illustrated embodiment, the memory array 300 is organized into logical erase blocks (LEBs) (also referred to herein as "metablocks" or "superblocks") as depicted by logical erase block 302. These LEBs include a plurality of physical erase blocks (PEBs) illustrated by physical erase block 0 304, physical erase block n 306, physical erase block 0 308, physical erase block n 310, physical erase block 0 312, and physical erase block n 314. A "physical erase block" refers to the smallest unit of storage within a given memory die that can be erased at a given time (e.g., due to the wiring of the storage cells on the memory die).

[0100] Physical erase blocks may be located in separate storage dies depicted as die 0 316, die 1 318, and die n 320. In some embodiments, the die is divided into planes. A "plane" refers to a partition of a die that permits certain storage operations to be performed on two planes using certain physical row addresses and certain physical column addresses.

[0101] Those skilled in the art understand the relationship and differences between physical erase blocks and logical erase blocks, and may refer to one or the other or both by using the shorthand versions erase block, block, or storage block. Those skilled in the art understand from the context in which an erase block is mentioned whether a physical erase block or a logical erase block (or metablock or superblock) is being referred to. The concepts and techniques used in the art and the concepts and techniques recited in the claims may be equally applicable to physical erase blocks or logical erase blocks.

[0102] "Erase block" refers to a logical erase block or a physical erase block. In one embodiment, a physical erase block represents the smallest storage unit within a given memory die that can be erased at a given time (e.g., due to the wiring of the storage cells on the memory die). In one embodiment, a logical erase block represents the smallest storage unit or storage block that can be erased by a storage controller in response to receiving an erase command. In such an embodiment, when the storage controller receives an erase command specifying a particular logical erase block, the storage controller may erase each physical erase block within the logical erase block at the same time. It should be noted that the physical erase blocks within a given logical erase block may be considered to be continuous within the physical address space, even if they reside in separate dies. Therefore, the term "continuous" may be applicable not only to data stored in the same physical medium, but also to data stored in separate media.

[0103] A "memory block" refers to a collection of memory cells organized so that memory operations can be performed on groups of memory cells in parallel. The organization of a collection of memory cells can be implemented at a physical level or a logical level. Thus, in one embodiment, a memory block may include, for example, physical pages of word lines, logical pages including physical pages across planes and / or memory dies, a physical erase block including a collection of physical pages, a logical erase block (LEB) including a collection of logical pages, or the like. A memory block may be referred to herein as a "block," "memory block," or LEB.

[0104] As used herein, a "physical" structure, such as a physical page, a physical word line, a physical erase block, a physical plane, a physical memory die, or the like, refers to a single physical structure that a controller, manager, module, or other logical component of a system can control and / or communicate with at a level within one or more levels of physical abstraction in the organization of a device, system, or equipment. Similarly, a "logical" structure, such as a logical page, a logical word line, a logical erase block, a logical plane, a logical memory die, or the like, refers to a single physical structure of the same type that a controller, manager, module, or other logical component of a system can control and / or communicate with at a level within one or more levels of physical abstraction in the organization of a device, system, or equipment. It should be noted that one or the other or both of the "physical" structure and the "logical" structure may have distinct addresses that can be used to identify one "physical" structure or "logical" structure relative to other structures of similar nature and type.

[0105] "Logical erase block" refers to another term for a storage block. In some embodiments, a logical erase block refers to a set of logical pages that span planes, memory dies, and / or chips. Since physical pages may not be directly coupled to each other, this organization of storage cells is considered to be 'logical'. However, physical pages are operated in parallel as if they were a single page. In a similar manner, multiple physical erase blocks can be operated in parallel as if they were a single erase block, and are therefore referred to as logical erase blocks. The terms logical erase block, metablock, and superblock are used interchangeably herein. "Logical page" refers to a set of physical pages that are considered a single page for storage operations. "Physical page" means that a physical page represents the smallest storage block that can be written in a single operation within a given memory die.

[0106] A logical erase block, such as logical erase block 302, is further divided into a plurality of logical pages, logical page 322, which in turn includes a plurality of physical pages, such as physical page 0 324, physical page n 326, physical page 0 328, physical page n 330, physical page 0 332, and physical page n 334. A physical page may include a plurality of packets, which may be grouped into error correction code (ECC) chunks.

[0107] In one embodiment, a physical page represents the smallest block of storage within a given die that can be written to at a given time. In one embodiment, a logical page is the smallest writable block of storage supported by a storage controller. (In one embodiment, the storage controller may include a buffer configured to store up to a logical page of data; while filling the buffer, the storage controller may simultaneously write the contents of the buffer to a single logical page.) In some cases, dividing the logical pages across multiple dies can result in faster access times for data sets when multiple dies are accessed in parallel. A logical page configuration can be mapped to any physical page on a die or across multiple memory dies, just like a logical erase block.

[0108] In some embodiments, the storage controller 104 may associate metadata (also referred to as media characteristics) with one or more of the storage blocks (logical erase blocks, physical erase blocks, logical pages, and / or physical pages). The storage controller 104 may manage metadata identifying the logical addresses at which the logical erase blocks store data, as well as the logical address space 116 ( Figure 1 ) within the storage controller 104. The storage controller 104 may store metadata or media characteristic data in a variety of locations including on a non-volatile storage medium, in a volatile memory, in a structure stored with each logical erase block, or the like.

[0109] "Metadata" refers to system data that may be used to facilitate the operation of a non-volatile storage device. Metadata is contrasted with, for example, data generated by an application (i.e., "application data"), data generated by a user, a host, or data that would be considered "user data" by an operating system.

[0110] For example, a logical erase block may include metadata that specifies, but is not limited to, usage statistics (e.g., the number of program-erase cycles performed on the logical erase block, health statistics (e.g., a value indicating how often corrupted data has been read from the logical erase block), security or access control parameters, sequence information (e.g., a sequence indicator), a persistent metadata flag (e.g., indicating inclusion in an atomic storage operation), a transaction identifier, or the like. In some embodiments, a logical erase block includes metadata identifying the logical addresses at which the logical erase block stores data, and a corresponding number of stored data blocks / packets per logical block or sector.

[0111] In some embodiments, the metadata includes a crossover temperature of a logical erase block, an average crossover temperature of an enabled logical erase block of a nonvolatile memory device, a temperature change rate, an average program erase count of a logical erase block, an uncorrectable bit error rate (UBER) of a logical erase block, a bit error rate, a failed bit count of a logical erase block, and a charge leakage rate. In one embodiment, the metadata may include a media characteristic. "Charge leakage rate" refers to the rate at which charge leaks from a memory cell when the memory cell is in a passive state, not being read or written.

[0112] Figure 4 A schematic block diagram of a memory system 400 according to one embodiment is shown. In the memory system 400, the memory device 102 includes a memory controller 402, which includes a R / W circuit 404, an error correction code decoder 406, and a flash translation layer 120. The non-volatile memory array 106 may include a plurality of memory dies 108, each having a temperature sensor 408.

[0113] R / W circuit 404 or “read-write circuit” refers to a device, component, element, module, system, subsystem, circuit system, logic, hardware, or circuit configured and / or operated to read data from and write data to a storage medium (e.g., a storage cell of a storage array).

[0114] The error correction code decoder 406 may be configured to provide bit error rate and error correction of data read by the R / W circuit 404. An “error correction code decoder” refers to any hardware, software, firmware, circuit, component, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to detect and / or correct errors in a data set (e.g., codeword) using redundant information defined for the data set (e.g., codeword).

[0115] In one embodiment, the error correction code decoder may include one or more types of decoders, including but not limited to a low-density parity-check (LDPC) decoder, a Reed-Solomon code decoder, a Golay code decoder, a Bose-Chaudhuri-Hokwenheim (BCH) code decoder, a Turbo code decoder, a multidimensional parity-check code decoder, a Hamming code decoder, a Hadamard code decoder, an expander code decoder, a Reed-Muller code decoder, a Viterbi decoder, a Fano decoder, or the like.

[0116] The temperature sensor 408 assigned to each memory die 108 can provide a reading of the physical temperature at the die. "Temperature sensor" refers to any suitable technology that can implement a temperature sensor, including technology currently employed in conventional memory die temperature sensors. In addition, it should be noted that while the temperature sensor may be located in the memory die in this embodiment, the temperature sensor may be located in another component in the memory system (such as a controller), or may be a separate component in the memory system.

[0117] Figure 5 A memory block configuration 500 according to one embodiment is shown. The non-volatile memory array 106 may include a plurality of memory dies 108. Each memory die 108 may incorporate a temperature sensor 408. A signal from the temperature sensor 408 indicating the temperature of the memory die may be carried to a memory controller via a bus 124. The memory die may be configured to report a record die temperature at a specific interval, such as every second. The value of the die temperature may reside in a control register on the memory die 108, and the memory die 108 may report the die temperature in response to a specific command from the memory controller. Alternatively, the memory die may automatically report its die temperature, and the current die temperature may be maintained in a control register of the memory controller.

[0118] Figure 5 An example of a memory block 502 is shown. In this example, the memory block can be configured to span physical erase blocks on multiple memory dies 108. For example, as shown, the memory block 502 can include memory die D0, memory die D1, memory die D2, and portions of memory die D3, such as physical erase blocks. Since the memory block is a logical structure, the memory block configuration can be adjusted to take into account failures, wear, or erroneous physical erase blocks of various memory dies of the non-volatile memory array 106.

[0119] Figure 6 6 is a schematic block diagram of a storage system 600 according to one embodiment. The storage system 600 may include a storage device 102 including a storage controller 602 and a non-volatile memory array 106. The storage controller 602 may further include an R / W circuit 604 including a data mover 606, an error correction code decoder 608, a cross temperature manager 610, and a health manager 612 including a read scanner 614 and an adjustment module 616. Those skilled in the art will appreciate that in certain embodiments, these components may be incorporated into other components of the storage device 102 or may be implemented by the host 110.

[0120] The R / W circuitry 604 is configured to service storage operations to provide storage services to one or more storage clients 114. A "storage operation" refers to an operation performed on a memory cell to change or obtain the value of data represented by a state characteristic of the memory cell. Examples of storage operations include, but are not limited to, reading data from a memory cell (or sensing the state of a memory cell), writing (or programming) data to a memory cell, and / or erasing data stored in a memory cell. The R / W circuitry 604 coordinates with the error correction code decoder 608 to service write commands and read commands.

[0121] A "write command" refers to a storage command configured to direct a recipient to write or store one or more blocks of data on a permanent storage medium (e.g., a hard drive, a non-volatile memory medium, or the like). A write command may include any storage command that can cause data to be written to the physical storage medium of a storage device. A write command may include enough data to fill one or more blocks of data, or a write command may include enough data to fill a portion of one or more blocks of data. In one embodiment, a write command includes a starting LBA and a count indicating the number of LBAs of data written to the storage medium. A "read command" refers to a type of storage command that reads data from a memory cell.

[0122] In one embodiment, the cross temperature manager 610 determines a cross temperature metric for a memory block. The cross temperature manager 610 may be further configured to monitor the cross temperature metric for each memory block of the non-volatile memory array 106. In certain embodiments, the cross temperature manager 610 determines the cross temperature metric for the memory block being examined during a read scan operation.

[0123] The crossover temperature manager 610 may determine the crossover temperature by comparing the current die temperature to the die temperature when the memory block was last written (referred to herein as the write temperature or programming temperature). The "write temperature" or "programming temperature" refers to the die temperature of the memory die or non-volatile memory device when data is written or programmed to the memory die or non-volatile memory device. The die temperature when data was last written to the memory block may be stored by the memory block on the storage medium in metadata or media properties, or in another set of tables or management data managed by the storage controller 602.

[0124] In one embodiment, the cross temperature manager 610 may track the average current die temperature of the memory dies that make up the memory blocks. In another embodiment, the cross temperature manager 610 may track the cross temperature condition of each physical erase block of each memory block. The cross temperature manager 610 may manage and / or maintain one or more cross temperature thresholds and / or one or more alarm thresholds for the non-volatile memory array 106. A "threshold" refers to a level, point, or value above which a condition is true or will occur and below which a condition is not true or will not occur. (Search for "threshold" on Merriam-Webster.com. Merriam-Webster, 2019. Web. Edited November 14, 2019.)

[0125] "Crossing temperature threshold" refers to a type of threshold value that is predefined such that when a value, a rated value, or a condition meets the crossing temperature threshold, the component, circuit, device, system, apparatus, or method is configured to signal any crossing temperature condition. "Alarm threshold" refers to a type of threshold value that is predefined such that when a value, a rated value, or a condition meets the alarm threshold, the system, apparatus, or method is configured to signal a problem or error or the possibility of an impending problem or error condition.

[0126] One or more cross temperature thresholds and / or one or more alarm thresholds may be defined, such that there is one for each level, health, cross temperature, and / or the like. The cross temperature manager 610 may detect, determine, maintain, and / or calculate a cross temperature metric for each memory block. A "cross temperature metric" refers to a measurement of a cross temperature condition. In one embodiment, the cross temperature metric includes the difference between the die temperature when programming / writing a memory cell and the die temperature when reading or attempting to read a memory cell.

[0127] In one embodiment, the cross temperature manager 610 may determine a cross temperature metric of a memory block being checked during a read scan operation. When the cross temperature metric of a memory block being checked, tested, or monitored in a read scan operation meets a cross temperature threshold, the cross temperature manager 610 may reduce the read scan interval. If a memory block being checked, tested, or monitored in a read scan operation meets an alert threshold, the cross temperature manager 610 may initiate an immediate read scan operation for one or more other memory blocks.

[0128] In one embodiment, the health manager 612 can manage and monitor the health of the non-volatile storage media of the non-volatile memory array 106. In one embodiment, the health manager 612 performs a read scan operation on one or more memory blocks or each of the memory blocks of the non-volatile memory array 106. In this way, the health manager 612 can manage the health of the memory block level. When the health manager 612 detects a memory block with a health condition that causes more bit errors (higher bit error rate), the health manager 612 can implement countermeasures to reduce the bit error rate, recover data, and / or extend the service life of the non-volatile storage media.

[0129] "Bit error rate" refers to a measure of the number of erroneous bits out of the total number of bits processed. In some embodiments, the bit error rate is calculated after an error correction code (ECC) decoder has made one or more attempts to correct one or more erroneous bits.

[0130] "Countermeasure" means a method, process step, or operation configured to mitigate a negative attribute, factor, or condition. It should be noted that in some cases, a feasible countermeasure is to take no action in response to an identified negative attribute, factor, or condition. While taking no action may be considered a negative activity, such a response to a negative attribute, factor, or condition is considered a countermeasure in this article.

[0131] In some embodiments, the countermeasures are specific to a particular problem or indication of a problem. Examples of countermeasures that can be used include actively changing the die temperature of the erase block, relocating data to another storage location, adjusting the alarm threshold, using a separate cell voltage distribution (CVD) table to manage one or more physical erase blocks, and taking no action.

[0132] The health manager 612 may include a read scanner 614 and an adjustment module 616. The read scanner 614 reads data from the memory blocks of the non-volatile memory array 106 and coordinates with the health manager 612 to determine the health of the memory cells of the memory blocks. The read scanner 614 may function as part of a read scan operation and may check the condition of each memory block. For memory blocks with degraded conditions, the health manager 612 may implement countermeasures.

[0133] The read scanner 614 can read data from a storage block in a plurality of storage blocks of the non-volatile memory array 106 of the memory die 108 associated with the plurality of temperature sensors. The read scanner 614 can coordinate with the error correction code decoder 608 to determine a bit error rate for each read of the storage block, which bit error rate can be referred to as a read bit error rate. If the read bit error rate meets the read bit error rate threshold, the health manager 612 communicates with the R / W circuit 604 and the data mover 606 to move the data of the storage block to a new storage block, a free storage block. The data mover 606 moves data out of the storage block to the free storage block.

[0134] In certain embodiments, hot spots (locally elevated temperatures) may be generated within a memory die of the non-volatile memory array 106. These hot spots may cause the data in the memory cells of the hot spots to have a higher bit error rate when read. In certain embodiments, as part of a read scan operation, the health manager 612 may be configured to detect these hot spots and implement countermeasures to address, remedy, or mitigate the increased bit error rate and / or preserve the data on the non-volatile storage media.

[0135] In one embodiment, the health manager 612 may determine that one or more memory blocks span memory dies with elevated die temperatures. In one embodiment, the health manager 612 makes this determination by comparing the current die temperature to a reference die temperature, such as a die temperature threshold. In particular, the health manager 612 may determine that the memory blocks span the hottest memory die among the plurality of memory dies 108 based on the die temperature. In one embodiment, the die temperature is reported by a temperature sensor 408 on each memory die. The hottest memory die may include a memory die among the plurality of memory dies of a row within the non-volatile memory array 106, and the hottest memory die may be the memory die of the row with the highest die temperature.

[0136] If the health manager 612 determines that the memory blocks read (i.e., tested or checked) by the read scanner 614 span the hottest memory die, then the read scanner 614 may reduce the read scan interval of the read scan operation. This means that the read scan operation will be performed earlier. In one embodiment, the read scanner 614 may reduce the read scan interval by a fixed amount, such as 15 minutes. Alternatively or additionally, in one embodiment, the read scanner 614 may reduce the read scan interval by a percentage, such as 10 percent. Additionally or in another embodiment, the read scanner 614 or the health manager 612 or the storage controller 602 may reduce the read scan interval. Additionally or in another embodiment, the read scanner 614 or the health manager 612 or the storage controller 602 may increase the read scan frequency, such as by causing the health manager 612 or the storage controller 602 to run the read scan operation more frequently. "Read scan frequency" refers to a measurement of the frequency with which a read scan operation is performed within a particular time period.

[0137] In one embodiment, the storage controller 602 may include a health manager 612 having an adjustment module 616. The adjustment module 616 makes adjustments to parameters and settings used when performing storage operations with the non-volatile memory array 106. In one embodiment, a read scan operation may include the use of the adjustment module 616.

[0138] In one embodiment, the adjustment module 616 manages the non-volatile memory array 106 by actively setting and adjusting configuration parameters of the memory cells of the non-volatile memory array 106. By actively determining the configuration parameters before an error occurs, the adjustment module 616 can prevent certain errors from occurring without the performance penalty of retrying reads or taking other remedial measures for the errors that were prevented. In some embodiments, the adjustment module 616 adjusts the configuration parameters that are appropriate for the use case of the storage device 102 to configure the memory cells of the use case, rather than using default configuration parameters.

[0139] Configuration parameters are parameters of a set of memory cells that can be changed by means of an interface, such as a read threshold, a write or programming threshold, an erase threshold, or the like. The interface for modifying configuration parameters may include programmable data registers, a command interface of a control bus of the non-volatile memory array 106, an API of a device driver of the memory device 102, control parameters of the memory controller 104, or the like.

[0140] The adjustment module 616 references one or more media characteristics of the set of storage units to determine configuration parameters for the set of storage units.

[0141] "Characteristic" refers to any property, quality, or attribute of an object or thing. Examples of characteristics include, but are not limited to, condition, readiness for use, unreadiness for use, size, weight, composition, feature set, and the like. "Media characteristic" refers to an attribute or statistic of a particular set of storage cells, such as a program / erase cycle count for a set of storage cells, a read count for a set of storage cells, a retention time since a previous write to a set of storage cells (also known as data retention time), a residence time for a set of storage cells such as a logical or physical erase block (e.g., the time between programming of an erase block and erasure of an erase block), an average of multiple previous residence times for a set of storage cells, error statistics for a set of storage cells, or the like.

[0142] The media characteristics of a collection of storage units may be substantially static or may be dynamic and change over time. In one embodiment, the media characteristics are statistics, heuristics, mathematical models, transformations, or other descriptors associated with properties of the non-volatile memory medium.

[0143] In one embodiment, the media characteristics include or relate to the brand, model, manufacturer, product version, or the like of the storage device and / or the non-volatile memory medium. In another embodiment, the media characteristics may include or relate to the environmental conditions or usage of the storage device and / or the non-volatile memory medium, such as temperature, use case (e.g., cache use case, archive use case, server use case, enterprise use case, consumer use case, etc.), or the like.

[0144] In response to determining the configuration parameters of the set of storage cells, the adjustment module 616 may configure the set of storage cells to use the determined configuration parameters. The adjustment module 616 may periodically update the media characteristics of the set of storage cells, update the configuration parameters of the set of storage cells, and reconfigure the set of storage cells to use the updated configuration parameters. The adjustment module 616 may configure the storage cells with the configuration parameters during performing input / output operations during boot operations in response to a background scan or the like of the set of storage cells indicating changed media characteristics.

[0145] To reduce the burden associated with tracking configuration parameters for each storage cell, each page, each erase block, or the like, in one embodiment, the adjustment module 616 can manage configuration parameters in groups or collections. For example, the adjustment module 616 can determine and manage configuration parameters for groups or collections of pages, physical erase blocks, logical erase blocks, metablocks, superblocks, storage blocks, word lines, error correction code blocks or codewords, chips, dies, planes in a die, or other storage areas. The adjustment module 616 can group pages or other storage areas with similar media characteristics (e.g., similar error rates, similar ages, similar PE cycle counts, similar physical media locations, similar locations in programming order, similar architectures, similar temperatures or cross-temperatures, or the like) and determine different configuration parameter settings for different groups. For example, in some embodiments, the adjustment module 616 may group upper pages (e.g., MSB pages), lower pages (e.g., LSB pages), subsets of upper and / or lower pages, a set of first N pages in page programming order, a set of middle N pages in page programming order, a set of last N pages in page programming order, and / or other subsets of pages or other storage areas, and configuration parameter settings may be managed by the groups or sets.

[0146] In one embodiment, the read scan operation may include the use of an adjustment module 616. In one embodiment, if the read scanner 614 determines that the bit error rate of the memory block exceeds a certain threshold, the read scanner 614 may signal the adjustment module 616 to determine adjustments for the memory block, if any adjustments may be made.

[0147] In one example embodiment of the adjustment module 616 operating in conjunction with a read scan operation, the adjustment module 616 may iteratively attempt to read data of a memory block using a predetermined number of different read levels. A "read level" refers to a voltage level configured to test or check which memory cells conduct at the voltage level. In some embodiments, a memory cell may include a transistor and the read voltage is a voltage level at or above a threshold voltage of the memory cell, which causes the memory cell to conduct current.

[0148] In some embodiments, a single read / sense operation using a single read voltage may determine the memory state of a memory cell, depending on the type of encoding used to store data on the memory cell and the number of bits encoded on each memory cell. In other embodiments, several read / sense operations, each performed at a different read voltage level, may be used to determine the memory state of a memory cell. The determined memory state may then be decoded into a representation of the data bits stored by the memory cell. "Read voltage" is shorthand for "read threshold voltage." "Read level" is another term often used to describe "read voltage," and the two terms are used interchangeably herein.

[0149] In response to successfully reading the data of the memory block via the last of a predetermined number of different read levels in the iterative attempt, the adjustment module 616 can determine the bit error rate of the data of the read memory block and reduce the read scan interval in response to the bit error rate satisfying the read bit error rate threshold. In this way, the disclosed solution can reconfigure the memory block containing the memory cells affected by the cell threshold voltage distribution shift. Alternatively or additionally, the adjustment module 616 can be configured to schedule subsequent read scan operations to start with the memory block for which the adjustment module 616 has made adjustments.

[0150] In certain embodiments, the memory controller 602 may be configured to implement a countermeasure as part of the read scan operation, wherein the countermeasure includes cooling one or more memory dies of the non-volatile memory array 106. For example, in one embodiment, the memory controller 602 may be configured to cool a memory die that is the hottest memory die among the plurality of memory dies 108 that together form a memory block examined by the read scan operation. In one embodiment, the memory controller 602 cools the hottest memory die by activating an active cooling system or subsystem, such as a fan, liquid cooling, or the like.

[0151] In one embodiment, the storage controller 602 cools the hottest memory die by instructing the R / W circuit 604 to direct incoming write commands from the host to one or more memory blocks that do not contain the hottest memory die. By redirecting write commands away from one or more memory blocks that use the hottest memory die, the hottest memory die may have a chance to cool due to natural heat dissipation. Alternatively, in addition, or in another embodiment, the storage controller 602 may cool the hottest memory die by instructing the data mover 606 to move data across each memory block of the hottest memory die to another set of memory blocks and temporarily stop using (reading and writing) the hottest memory die so that this die cools by not being used.

[0152] Figure 7A graph of cell threshold voltage distributions and configuration parameters for a multi-level memory cell 700, such as a multi-level NAND flash memory cell or the like, with an example encoding or programming model is depicted. In the depicted embodiment, a Gray code encoding model is used to encode memory states, where the binary values ​​of adjacent memory states differ by a single bit in the encoding. A "memory state" refers to a condition of a memory cell or storage cell designed and / or configured to represent an encoding of one or more data bit values. In certain embodiments, the memory state can be changed by using a storage operation. In a non-volatile memory cell, the memory cell maintains its memory state in the absence of power.

[0153] "Cell threshold voltage distribution" refers to a process or method for determining the threshold voltage of each memory cell in a set of memory cells. The cell threshold voltage distribution may be referred to simply as a cell voltage distribution and may be referred to using the acronym "CVD".

[0154] Cell threshold voltage distribution can be performed during research and development of non-volatile memory technology to understand how memory cells perform under different conditions. In some embodiments, cell threshold voltage distribution can be performed during operation of the non-volatile memory to determine whether the read levels used to read the memory cells are sufficient. If the bit error rate of the first set of read levels is insufficient, then countermeasures can be taken to reduce the bit error rate.

[0155] In one embodiment, these countermeasures may include adjusting configuration parameters so that the bit error rate is reduced. In some embodiments, the steps of determining the cell threshold voltage distribution, checking the read level and other media characteristics relative to the bit error rate, and taking any countermeasures may be referred to as a CVD scan. Due to the various steps involved and the number of memory cells scanned, a CVD scan may require a significant amount of time to complete. "Threshold voltage" refers to the voltage level that, when applied to the gate electrode of a transistor, causes the transistor to conduct current between the drain electrode and the source electrode.

[0156] Figure 7 The value "11" is shown to be associated with the lowest memory state (labeled L0, the "erased" state), the value "01" is associated with the next lowest read voltage state (labeled L1), the value "00" is associated with the next highest read voltage state (labeled L2), and the value "10" is associated with the highest read voltage state (labeled L3). Figure 7, the lowest memory state L0 is depicted as a negative voltage below the depicted 0.0V. The value, magnitude, size, and the like of the read voltage may vary depending on the manufacturer and the type of non-volatile memory cell, each of which is covered by this disclosure. In the depicted embodiment, default read level 702, default read level 704, and default read level 706 are read levels that separate memory state Lo from memory state L1, memory state L1 from memory state L2, and memory state L2 from memory state L3, respectively. Default read level 702, default read level 704, and default read level 706 are an example of media characteristics or metadata.

[0157] A non-volatile memory storage controller may interpret four discrete levels of voltage stored in a multi-level storage cell as representing two binary bits, one represented by the most significant bit (MSB) in the cell encoding and one represented by the least significant bit (LSB) in the cell encoding. Other programming and encoding models may be used. In addition, some non-volatile memory media may have more than four possible states, allowing more than two binary values ​​to be stored in a single multi-level storage cell. Memory state L0, memory state L1, memory state L2, and memory state L3 may or may not be continuous; for example, in some embodiments, the voltage levels are separated by a band gap called a guard band. For example, L0 and L1 may be separated by 0.3V.

[0158] In one embodiment, the LSB corresponds to the lower page of data and the MSB corresponds to the upper page of data. In certain embodiments, the multi-level storage cells may follow a two-phase programming model that includes writing the LSB before the MSB can be written, or vice versa. In another embodiment, the LSB and MSB may be programmed separately by the storage controller. This approach may be taken due to vendor or manufacturer requirements for page pairing (e.g., pairing the LSB bit of an MLC cell with the MSB bit of a different MLC cell) and page addressing (e.g., programming the LSB page before the MSB page or vice versa). In some cases, the LSB is written before the MSB, the MSB is written before the LSB, or the like.

[0159] In certain embodiments, the non-volatile memory medium may employ a two-stage programming model. In such a model, a binary value is first written to the LSB with the aid of a first write command to the lower page. The write command causes the multi-level memory cell to move from its initial state (e.g., the 11 state in L0) to an intermediate state (the lower to middle LM state between L1 and L2) configured so that the 00 state is subsequently read. For example, writing a "0" to the lower page causes the multi-level memory cell to change from the L0 state (where both the LSB and MSB are 1) to the L2 state (where the LSB changes to 0). Subsequent writing of a "0" to the upper page causes the multi-level memory cell to move from an intermediate state (usually between the L1 state and the L2 state) to the L2 state, so that both bits of the MLC are "0".

[0160] Thus, in such an embodiment, two writes (one to the lower page and one to the upper page) are required to move the multi-level cell from L0 to L2, since the cell transitions through an intermediate state and the MLC device includes programming the lower page before programming the upper page and does not allow for partial programming of a page without an intervening erase operation. Writing a "1" to either the upper or lower page will cause the MLC to transition to L1 or L3, depending on the binary value of the lower page at that time. Additionally, a certain non-volatile memory media vendor may impose a requirement to write the lower page before the upper page, or the like. In other embodiments, the non-volatile memory media may employ a two-phase programming model, where the binary value is first written to the MSB with a first write command to the upper page.

[0161] In some embodiments, the adjustment module 616 determines and manages read levels or other configuration parameters separately for one or more of abodes (i.e., memory states) L0, L1, L2, L3, thereby determining different settings or adjustments for configuration parameters in different abodes L0, L1, L2, L3. In one embodiment, the adjustment module adjusts one or more read levels based on a subset of binary data stored in the multi-level storage cell (e.g., only the upper page, only the lower page, or the like). In such an embodiment, checking the state change of the LSB bit indicates that the direction of the voltage in the multi-level storage cell is changing. For Gray code encoding of bit values ​​(e.g., Figure 7 In both 100-bit and 100-bit binary code encoding, the LSB of the multi-level memory cell transitions between binary zero and binary one between two intermediate states (the L1 state and the L2 state in the depicted embodiment).

[0162] For other coding models, the MSB may transition between binary zero and binary one, or the like, between the middle two states or states. For Gray or binary code coding models, the LSB has a value of "1" for the read voltage in the lower range (including the lower two states or states, L0 and L1), and the LSB has a value of "0" for the read voltage in the upper range (including the upper two states or states, L2 and L3). By using only the LSBs of the MLC memory cells to determine whether the read level deviates from the known read level, in one embodiment, the adjustment module may make a determination in a similar manner by counting or counting binary ones and / or binary zeros, or the like, of the LSB data set to determine whether the read level of the SLC memory cells deviates from the known read level.

[0163] For some types of multi-level storage cells, the default read level 704 (e.g., the intermediate read level) and the adjacent L1 state and L2 state may be more sensitive to read disturbance or other factors that may cause read voltage drift. In addition, in some embodiments, the LSB and MSB of a single multi-level storage cell may represent data stored in different physical pages. In one embodiment, using a single bit from each of a plurality of multi-level storage cells as a data set may reduce the number of read operations to retrieve the data set. In other embodiments, the use of a single bit from each of a plurality of multi-level storage cells in the lower page simplifies the process of detecting the deviation and direction of the read level from the known read level of the multi-level storage cell.

[0164] In one embodiment, the direction module may determine the deviation direction of the grouping of multi-level memory cells based on a data set including data from one or more lower pages of the multi-level memory cells. In some embodiments, since the lower page includes the LSB, the direction module determines that the read level is deviated toward a greater read voltage in response to a difference between the read level of the lower page and the known read level of the lower page indicating that the memory cell value of the LSB has transitioned from binary one to binary zero. For the LSB transitioning from binary one to binary zero, the direction module determines that the read level is deviated toward a greater read voltage. Figure 7 The read voltage of the multi-level memory cell of the encoding model drifts from the L0 state or the L1 state to the L2 state or the L3 state, thereby indicating that one or more of the read levels (702, 704, 706) should be increased to set the read voltage back to the initial L0 state or the L1 state.

[0165] Similarly, in some embodiments, the direction module may determine that the read level is deviating toward a smaller read voltage in response to the difference between the read level of the lower page and the known read level of the lower page indicating that the memory cell value of the LSB has transitioned from binary zero to binary one. For the LSB transition from binary zero to binary one, the read voltage of the multi-level memory cell may drift from the L3 state or the L2 state to the L1 state or the L0 state, indicating that one or more of the read levels should be reduced to place the read voltage back to the initial L3 state or L2 state. In some embodiments, deviations across multiple states may be unlikely, and deviations that can be detected using the LSB may be between the L1 state and the L2 state, indicating a clear deviation direction in either direction.

[0166] In another embodiment, the deviation direction may be determined based at least in part on the encoding type used for the storage cells of the non-volatile memory medium, the physical and / or electrical architecture of the storage cells of the non-volatile memory medium, or the like. For example, the deviation direction may be determined based on a 2-bit multi-level storage cell media type, based on whether the data set includes an upper page or a lower page, based on a Gray code encoding type, based on the magnitude of the determined deviation, or the like. In yet another embodiment, the LSBs and MSBs from separate or disparate addresses (e.g., different physical pages or the like) may be transformed or combined into a single data set, or may be coordinated in other ways to determine the deviation direction.

[0167] In some embodiments, using each bit stored in the multi-level storage cell to determine the read level adjustment can improve the accuracy of the read level adjustment, but may increase the number of read operations or increase the complexity of the determination. Figure 6 If the error correction code decoder 608 shown in FIG. 6 detects a data error in an upper page of a group of multi-level storage cells, the R / W circuit 604 may retrieve one or more lower pages of the group, and the adjustment module 616 may adjust the read level of the group based on the lower pages.

[0168] Figure 8 An example of an adjusted configuration parameter for a multi-level storage cell 800 is shown, showing adjusted read levels 802, adjusted read levels 804, and adjusted read levels 806 for a set of multi-level storage cells of a non-volatile memory medium. In some embodiments, the read levels are default configuration parameters set by a manufacturer, supplier, or the like, and an adjustment module (e.g., adjustment module 616) may adjust the read levels to the default values ​​set by the manufacturer, supplier, or the like. Figure 7The default read level 702, the default read level 704, and the default read level 706 shown in the figure are adjusted or configured to the adjusted read level 802, the adjusted read level 804, and the adjusted read level 806, respectively. In one embodiment, the adjustment module determines different adjustments to the default read levels to generate the adjusted read levels. In the depicted embodiment, the adjustment module can determine the adjustment 808, the adjustment 810, and the adjustment 812 for different residences L0, residences L1, residences L2, residences L3 having different magnitudes, different directions, and the like, thereby individually customizing different adjusted read levels 802, adjusted read levels 804, and adjusted read levels 806 for the media characteristics of different residences L0, residences L1, residences L2, residences L3.

[0169] Adjusted read level ratio Figure 7 The default read levels in more closely match Figure 8 The actual distribution of storage unit states. If the corresponding storage unit set is Figure 8 If the distribution of memory cell states of the ...

[0170] In one embodiment, the adjustment module 616 reactively uses a deviation module, a direction module, an adjustment module, or the like to determine the adjusted configuration parameter adjusted read level 802, adjusted read level 804, and adjusted read level 806. In another embodiment, the adjustment module proactively uses a medium characteristic module and the adjustment module 616 to determine the adjusted read levels based on the medium characteristics of the corresponding set of storage cells.

[0171] The process by which the adjustment module 616 determines the adjusted read level 802, the adjusted read level 804, and / or the adjusted read level 806 is a form of maintenance in which the memory controller 104 manages the nonvolatile memory array 106 to compensate for wear and degradation as the memory devices 102 are used. The process by which the adjustment module 616 determines and makes these adjustments may be referred to as a CVD scan, as the process may involve determining the threshold voltage of each memory cell of a memory block.

[0172] The CVD scan may be performed as an independent maintenance operation or in conjunction with other operations. In one embodiment, the CVD scan may be run in conjunction with a read scan operation.

[0173] Fig. 9 900 according to one embodiment. The memory system 900 includes a plurality of memory blocks implemented across the memory dies 108 of the non-volatile memory array 106 and a memory controller 902. The memory controller 902 may include an R / W circuit 904 having a data mover 906, an error correction code decoder 908, a cross temperature manager 910, and a health manager 912 including a read scanner 914 and an adjustment module 916.

[0174] The memory controller 902 may determine, through action of the error correction code decoder 908, a memory block from among the plurality of memory blocks having a bit error rate 918 that is above a read bit error rate threshold 920. Determining that the bit error rate 918 is above or meets the read bit error rate threshold 920 may be done as part of a read scan operation and / or may be done as part of a CVD scan in which the memory controller 902 attempts to find an adjusted read level.

[0175] In one embodiment, as part of performing a CVD scan, the storage controller 902 may also determine to change the read scan interval of the read scan operation. As part of the CVD scan, the storage controller 902 may iteratively read data (or attempt to read data if there are too many errors to correctly read the data) from the storage block using a predetermined number of different read levels through the action of the read scanner 914. In one example, each iterative read of the data may use a read level that is more likely to correct and / or avoid the last read bit error rate. When the iterative reading of the data results in a higher bit error rate, the storage controller 902 may use the read level of the last iterative read as the adjusted read level. In response to successfully reading the storage block data through the iterative attempt, the adjustment module 916 may be used to change one or more of the read levels of the storage block to one or more of the predetermined number of different read levels that caused the successful data read.

[0176] The predetermined number of different read levels 1010 are examples in Fig.10 1000. Configuration parameter table 1000 includes rows of memory blocks, each having a memory block identifier 1002. Configuration parameter table 1000 includes three example read levels: read level R1 1004, read level R2 1006, and read level R3 1008. Of course, more read levels may be used in other embodiments of the predetermined number of different read levels 1010.

[0177] For example, the SB0 of row 1012 may be read using a read level R1 1004 that may return an excessively high bit error rate 918. The storage controller 902 may configure the read scanner 914 to attempt to read the SB0 using a read level R2 1006 that may still cause an excessively high bit error rate 918. Finally, the read scanner 914 may read the SB0 using a read level R3 1008 that may still cause errors but may reduce the bit error rate 918 to below the read bit error rate threshold 920. The adjustment module 916 may then change the configuration of the SB0 to be read using the read level R3 1008. Once one or more read levels have changed, the storage controller 902 may instruct the read scanner 914 to reduce the read scan frequency of the storage block so that the storage block is scanned more frequently. In this way, the read scan frequency may be dynamically adjusted based on one or more of the CVD scan and / or read scan operations.

[0178] In one embodiment, the memory controller 902 may include a cross-temperature manager 910 configured to determine a cross-temperature metric 922 of a memory block. When the cross-temperature metric 922 of the memory block satisfies a cross-temperature threshold 926, the cross-temperature manager 910 may instruct the read scanner 914 to change the read scan frequency 924. The cross-temperature manager 910 may determine the cross-temperature metric 922 by first determining a write temperature 928 of the memory block data and then determining a current temperature 930. The cross-temperature metric 922 may include a difference between the write temperature 928 and the current temperature 930. In addition to changing the read scan frequency as part of a CVD scan and / or a read scan operation, in some embodiments, the read scan frequency may also be changed based on the cross-temperature metric 922 of the memory block.

[0179] The memory controller 902 may be configured to perform multiple read scan operations, such as a read scan operation 932 and a subsequent read scan operation 934. In some embodiments, the memory controller 902 may further measure a data retention die temperature threshold 936. Those skilled in the art will recognize that while these parameters are indicated where functionally convenient, the illustration is not intended to limit the configuration of circuitry constructed to implement this functionality within the memory controller 902.

[0180] Fig.10An embodiment of a configuration parameter table 1000 is depicted. The configuration parameter table 1000 includes a plurality of rows 1012 of a set of memory cells. In the depicted embodiment, the set of memory cells, memory blocks, are organized by memory block identifiers 1002, and the rows 1012 correspond to memory blocks 1002 from SB0 to SBn. Each row 1012 further includes configuration parameters 1014 for the corresponding memory block identifier 1002. In the depicted embodiment, the configuration parameters 1014 include read voltage threshold adjustments for read levels including read level R1 1004, read level R2 1006, and read level R3 1008, each as a hexadecimal offset from a default read voltage threshold. For example, in the depicted embodiment, the read voltage threshold adjustment varies between FAh (a hexadecimal number corresponding to the decimal number -6, in two's complement representation, where "h" represents hexadecimal) and 05h (a hexadecimal number corresponding to the decimal number 5), including values ​​such as 01h, 02h, 04h, FEh, FCh, FDh, FAh, 03h, and 05h. Thus, the configuration parameter table 1000 may contain a predetermined number of different read levels 1010 for use in a read scan operation and / or a CVD scan operation, as described below. Fig.11 Discussed.

[0181] Although, as described above, in the depicted embodiment, configuration parameter 1014 is shown as a read voltage threshold adjustment, in other embodiments, configuration parameter 1014 may include a resistivity threshold, a write or programming threshold, an erase threshold, and / or other modifiable parameters of a non-volatile memory medium. In addition, three configuration parameters 1014 are provided by way of example, and in other embodiments, other quantities and types of configuration parameters may be included. For example, in one embodiment, certain 20nm non-volatile memory media or the like may have ten different read voltage thresholds R1 to R10 set using different registers or the like, and adjustment module 616 may determine different values ​​of R1 to R10 for different sets, groups, storage areas, and / or different residences / storage states. Configuration parameter 1014 may include absolute data values, offsets or adjustments to data values, other parameters. A configuration update module may cooperate with adjustment module 616 to update configuration parameter table 1000.

[0182] Fig.11 A memory block configuration 1100 is shown according to one embodiment. A memory block 1102 is depicted, which is one of a plurality of memory blocks. The plurality of memory blocks may include a next memory block 1104 and a hottest memory die 1106, as shown.

[0183] Each of the plurality of memory blocks may span across a plurality of memory dies, such as memory die 108 shown within non-volatile memory array 106. Each memory die 108 may incorporate a temperature sensor 408 capable of providing the die temperature.

[0184] A typical non-volatile memory array 106 may include eight to sixteen memory dies 108, such as D0, D1, D2, D3, D4, D5, D6, and D7 as shown. When determining the hottest memory die 1106, all memory dies 108 of the non-volatile memory array 106 may be considered, rather than just those memory dies spanned by the memory block 1102. Then, in the illustrated case, D2 is not only the hottest memory die 1106 of the four memory dies 108 (D0 to D3) spanned by the memory block 1102. D2 may be understood as the hottest memory die 1106 of the entire non-volatile memory array 106 (D0 to D7).

[0185] A storage controller in communication with the non-volatile memory array 106 may include a health manager, such as Fig. 9 106. When the memory controller iteratively attempts to read data in the memory block 1102, the health manager can determine that the memory block 1102 includes the hottest memory die 1106 of the plurality of memory dies 108 based on the die temperature of each memory die 108 spanned by the memory block. The health manager can change the read scan frequency in response to determining that the memory block 1102 includes the hottest memory die 1106.

[0186] In one embodiment, the health manager may queue the memory block 1102 including the hottest memory die 1106 as the next memory block 1104 for a subsequent read scan operation. In another embodiment, the health manager may be configured to reconfigure the memory blocks 1102 to exclude the hottest memory die 1106. For example, in such a configuration, the memory block 1102 may include D0, D1, D6, and D3, but not D2. The memory controller may also be configured to move data from the memory block 1102 including the hottest memory die 1106 to a free memory block 1108 that does not span the hottest memory die 1106. A "free memory block" refers to a memory block that is available to receive data for writing to a storage unit of the memory block due to a storage command.

[0187] Fig.12A method 1200 for dynamically changing the time at which a read scan operation occurs is shown according to one embodiment. This method 1200 can be implemented on a storage system such as storage system 400, storage system 600, or storage system 900. As will be apparent to one skilled in the art, the order of steps may differ from the order shown while providing equivalent functionality. The order of operations presented herein is not intended to be limiting.

[0188] The error correction code decoder of the memory controller may first determine 1202 a bit error rate of a memory block among a plurality of memory blocks of the non-volatile memory array. In one embodiment, determining the bit error rate of the memory block may include sampling one or more logical pages of memory cells of the memory block. The bit error rate of the sampled logical pages may represent the bit error rate of the memory block.

[0189] If the bit error rate meets 1204 the relocation threshold, the data mover may relocate 1206 the data from the storage block to a free storage block. "Relocation threshold" refers to a threshold identified when data of a storage block is to be moved from a first storage block to a second storage block.

[0190] In one embodiment, relocating the memory block data may include the memory controller initiating a data scrubbing operation on the non-volatile memory array 106. In one embodiment, the memory controller 902 may perform a data refresh operation instead of a data scrubbing operation.

[0191] A "data scrubbing operation" refers to an operation in which valid data of a set of data blocks of a storage block is read from a storage block and stored in a new location on a non-volatile storage device (typically in a non-volatile memory medium). The data scrubbing operation leaves invalid data in the storage block and the invalid data is deleted when the storage block is erased. Once the data scrubbing operation successfully relocates the valid data, the data scrubbing operation configures the storage block to be erased.

[0192] In some embodiments, the data cleaning operation immediately erases the storage block. In other embodiments, the data cleaning operation queues the storage block to be erased later. "Valid data" refers to the data of the storage block, which is stored by the host and should be retained and maintained until the host indicates that the data is no longer needed and can or should be deleted. "Invalid data" refers to data stored in the storage block that the host has definitely deleted or indicated that it is no longer needed and can be deleted because the data has been replaced by a new version or a changed version of the data. In a non-volatile storage medium including a storage unit of a write-once storage medium. If the data is modified by the host, the modified version of the data causes the initial data stored in the write-once storage medium to become invalid data, and the data becomes invalid because it no longer represents the current version of the data.

[0193] A "data refresh operation" refers to an operation in which all data of a set of data blocks of a storage block is read from a storage block and stored in a new location on a non-volatile storage device. A data refresh operation does not distinguish and does not provide different treatment for invalid data and valid data of a storage block. Therefore, a data refresh operation can be faster than a data cleanup operation.

[0194] Next, the cross temperature manager may determine 1208 a cross temperature metric for the memory block. If the cross temperature metric satisfies 1210 a cross temperature threshold, the adjustment module may change 1212 a read scan interval. In one embodiment, changing the read scan frequency 924 may mean decreasing the read scan interval so that read scan operations are performed more frequently. In one embodiment, changing the read scan frequency 924 may mean increasing the read scan frequency so that read scan operations are performed more frequently.

[0195] The memory controller may determine 1214 the hottest memory die among the plurality of memory dies based on the die temperatures reported by each temperature sensor. In some embodiments, the die temperatures may be read directly from the temperature sensors by the memory controller. In another embodiment, the memory controller may access a memory location updated by another process (e.g., a periodic temperature scan) to contain temperature sensor readings taken, for example, once per second.

[0196] If the memory block spans 1216 the hottest memory die, then the adjustment module may change 1218 the read scan interval. The adjustment module may further schedule 1220 the read scan operation to start at the memory block the next time the read scan operation is performed. In some embodiments, the memory controller 902 cools 1222 the hottest memory die so that the die temperature drops below a data retention die temperature threshold. The data retention die temperature threshold may include a threshold below which data stored on the non-volatile storage medium has an acceptably low bit error rate.

[0197] Fig.13 is an example block diagram of a computing device 1300 that may incorporate an embodiment of the solution. Fig.13 Only machine systems that implement aspects of the technical processes described herein are shown and do not limit the scope of the claims. Those skilled in the art will recognize other variations, modifications, and alternatives. In some embodiments, computing device 1300 includes data processing system 1302, communication network 1304, communication network interface 1306, input device 1308, output device 1310, and the like.

[0198] like Fig.13, data processing system 1302 may include one or more processors 1312 and a storage subsystem 1314. A "processor" refers to any circuit system, component, chip, die, package, or module configured to receive, interpret, decode, and execute machine instructions. Examples of processors may include, but are not limited to, central processing units, general-purpose processors, special application processors, graphics processing units (GPUs), field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), systems on chips (SoCs), virtual processors, processor cores, and the like.

[0199] Processor 1312 communicates with a number of peripheral devices via bus subsystem 1316. These peripheral devices may include input device 1308, output device 1310, communication network interface 1306, and storage subsystem 1314. In one embodiment, storage subsystem 1314 includes one or more storage devices and / or one or more memory devices.

[0200] In one embodiment, storage subsystem 1314 includes volatile memory 1318 and non-volatile memory 1320. "Volatile memory" is short for volatile memory media. In certain embodiments, volatile memory refers to volatile memory media and logic, controllers, processors, state machines, and / or other peripheral circuits that manage and provide access to the volatile memory media. Volatile memory 1318 and / or non-volatile memory 1320 may store computer executable instructions that, alone or together, form logic 1322, which, when applied and executed by processor 1312, implements embodiments of the processes disclosed herein.

[0201] Input devices 1308 include devices and mechanisms for inputting information into data processing system 1302. These may include a keyboard, a keypad, a touch screen incorporated into a graphical user interface, an audio input device such as a voice recognition system, a microphone, and other types of input devices. In various embodiments, input device 1308 may be embodied as a computer mouse, a trackball, a trackpad, a joystick, a wireless remote control, a drawing tablet, a voice command system, an eye tracking system, and the like. Input device 1308 typically allows a user to select objects, icons, control areas, text, and the like that appear on a graphical user interface via commands such as clicking a button or the like.

[0202] Output devices 1310 include devices and mechanisms for outputting information from data processing system 1302. These may include graphical user interfaces, speakers, printers, infrared LEDs, etc., also as understood in the art. In some embodiments, the graphical user interface is coupled directly to bus subsystem 1316 by means of a wired connection. In other embodiments, the graphical user interface is coupled to data processing system 1302 by means of communication network interface 1306. For example, the graphical user interface may include a command line interface on a separate computing device 1300, such as a desktop computer, server, or mobile device.

[0203] The communication network interface 1306 provides an interface to communication networks (e.g., communication network 1304) and devices external to the data processing system 1302. The communication network interface 1306 may serve as an interface for receiving data from other systems and transmitting data to other systems. Embodiments of the communication network interface 1306 may include an Ethernet interface, a modem (telephone, satellite, cable, ISDN), a (asynchronous) digital subscriber line (DSL), FireWire, USB, a wireless communication interface such as Bluetooth or WiFi, a near field communication wireless interface, a cellular interface, and the like.

[0204] Communication network interface 1306 may be coupled to communication network 1304 via an antenna, cable, or the like. In some embodiments, communication network interface 1306 may be physically integrated on a circuit board of data processing system 1302, or in some cases may be implemented in software or firmware (e.g., a "soft modem" or the like).

[0205] Computing device 1300 may include logic that allows communications over a network using protocols such as HTTP, TCP / IP, RTP / RTSP, IPX, UDP, and the like.

[0206] The volatile memory 1318 and the non-volatile memory 1320 are examples of tangible media configured to store computer-readable data and instructions to implement various embodiments of the processes described herein. Other types of tangible media include removable memory (e.g., pluggable USB memory devices, mobile device SIM cards), optical storage media such as CD-ROMs, DVDs, semiconductor memories such as flash memories, non-transitory read-only memories (ROMs), battery-backed volatile memories, networked storage devices, and the like. The volatile memory 1318 and the non-volatile memory 1320 can be configured to store basic programming and data constructs that provide the functionality of the disclosed processes and other embodiments thereof that fall within the scope of the required solution.

[0207] Logic 1322 implementing one or more portions of an embodiment of the solution may be stored in volatile memory 1318 and / or non-volatile memory 1320. Logic 1322 may be read and executed by processor 1312 from volatile memory 1318 and / or non-volatile memory 1320. Volatile memory 1318 and non-volatile memory 1320 may also provide repositories for storing data used by logic 1322.

[0208] The volatile memory 1318 and non-volatile memory 1320 may include several memories including a main random access memory (RAM) for storing instructions and data during program execution and a read-only memory (ROM) for storing read-only non-transitory instructions. The volatile memory 1318 and non-volatile memory 1320 may include a file storage subsystem that provides permanent (non-volatile) storage for program and data files. The volatile memory 1318 and non-volatile memory 1320 may include a removable storage system, such as removable flash memory.

[0209] Bus subsystem 1316 provides a mechanism for allowing the various components and subsystems of data processing system 1302 to communicate with each other as intended. Although communication network interface 1306 is schematically depicted as a single bus, some embodiments of bus subsystem 1316 may utilize multiple distinct busses.

[0210] It will be readily apparent to those skilled in the art that computing device 1300 may be a device such as a smartphone, a desktop computer, a laptop computer, a rack-mounted computer system, a computer server, or a tablet computer device. As is generally known in the art, computing device 1300 may be implemented as a series of multiple networked computing devices. In addition, computing device 1300 will typically include operating system logic (not shown), the type and nature of which are well known in the art.

[0211] Terms used herein should be given their ordinary meaning in the relevant art, or the meaning indicated by their usage in context, but if an explicit definition is provided, that meaning shall control.

[0212] Within the present disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured" to perform one or more tasks or operations. The expression "an entity" configured to "perform one or more tasks" is used herein to refer to a structure (i.e., a physical object such as an electronic circuit). More specifically, this expression is used to indicate that this structure is arranged to perform one or more tasks during operation. A structure may be referred to as being "configured to" perform some tasks even if the structure is not currently being operated. "Credit allocation circuitry configured to allocate credits to multiple processor cores" is intended to cover, for example, an integrated circuit having circuitry that performs this function during operation, even if the integrated circuit in question is not currently being used (e.g., it is not connected to a power source). Therefore, an entity described or recited as being "configured to" perform some task refers to a physical object, such as a device, a circuit, a memory storing program instructions that can be executed to perform a task, etc. This phrase is not used herein to refer to an intangible object.

[0213] The term “configured to” does not mean “configurable to.” For example, although an unprogrammed FPGA “can be configured to” perform some specific function after being programmed, the unprogrammed FPGA would not be considered to be “configured to” perform that function.

[0214] As used herein, the term "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the determination. That is, a determination may be based solely on specified factors or based on specified factors and other unspecified factors. Consider the phrase "determining A based on B." This phrase specifies B as a factor used to determine A or influence the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover embodiments in which A is determined based solely on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0215] As used herein, the phrase "in response to" describes one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect. That is, the effect may be responsive to only those factors, or may be responsive to the specified factors as well as other unspecified factors. Consider the phrase "in response to B, A is performed." This phrase specifies B as the factor that triggers the performance of A. This phrase does not exclude that the performance of A may also be responsive to some other factor, such as C. This phrase is also intended to cover embodiments where A is performed only in response to B.

[0216] As used herein, unless otherwise stated, the terms "first," "second," and the like are used as noun markers preceding them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). For example, in a register set having eight registers, the terms "first register" and "second register" may be used to refer to any two of the eight registers, rather than, for example, only logical registers 0 and 1.

[0217] When used in the claims, the term "or" is used as an inclusive or rather than an exclusive or. For example, the phrase "at least one of x, y, or z" means any one of x, y, and z, and any combination thereof.

Claims

1. A method comprising: determining a bit error rate of a memory block in a plurality of memory blocks of a non-volatile memory array; determining a crossover temperature metric of the memory block; changing a read scan interval in response to the cross-temperature metric of the memory block satisfying a cross-temperature threshold; and In response to the bit error rate satisfying a relocation threshold, data of the memory block is relocated to a free memory block.

2. The method of claim 1 , wherein the nonvolatile memory array comprises a plurality of memory dies, each memory die comprising a temperature sensor, the method further comprising: determining, based on the die temperature reported by each temperature sensor, that the memory block includes a hottest memory die among the plurality of memory die; as well as A read scan interval is changed in response to determining that the memory block includes the hottest memory die. 3 . The method of claim 2 , further comprising scheduling the read scan operation to start at the memory block the next time the read scan operation is performed.

4. The method of claim 2, further comprising cooling the hottest memory die so that the die temperature drops below a data retention die temperature threshold.

5. The method of claim 1, determining the bit error rate of the memory block comprises sampling one or more logical pages of memory cells of the memory block, the sampled one or more logical pages of memory cells representing the bit error rate of the memory block.

6. The method of claim 1, wherein relocating data of the memory block comprises initiating a data scrubbing operation by a memory controller managing the non-volatile memory array. The method of claim 1 , wherein changing the read scan interval comprises decreasing the read scan interval.

8. A device comprising: a read scanner configured to read data from a memory block of a plurality of memory blocks of a nonvolatile memory array comprising a plurality of memory dies, each memory die including a temperature sensor; an error correction code decoder configured to determine a bit error rate of the data read by the read scanner; a health manager configured to determine that the memory block spans a hottest memory die among the plurality of memory dies based on the die temperature reported by each temperature sensor; A data mover configured to move the data of the storage block to a free storage block in response to the bit error rate satisfying a read bit error rate threshold; and Wherein the read scanner is configured to reduce a read scan interval of a read scan operation in response to determining that the memory block spans the hottest memory die.

9. The apparatus of claim 8, further comprising a crossover temperature manager configured to: determining a crossover temperature metric for the memory block; and A read scan interval is reduced in response to the cross-temperature metric of the memory block satisfying a cross-temperature threshold.

10. The apparatus according to claim 8, further comprising an adjustment module, wherein the adjustment module is configured to: iteratively attempting to read data of the memory block using a predetermined number of different read levels; and In response to successfully reading the data of the storage block via a last one of the predetermined number of different read levels in the iterative attempt, determining a bit error rate of the data of the storage block read and reducing the read scan interval in response to the bit error rate satisfying the read bit error rate threshold. 11 . The apparatus of claim 10 , wherein the adjustment module is further configured to schedule the read scan operation to start from the memory block when the read scan operation is next performed.

12. The apparatus of claim 8, further comprising a memory controller configured to cool the hottest memory die of the plurality of memory die.

13. The apparatus of claim 12, wherein the memory controller cools the hottest memory die by directing incoming write commands to one or more memory blocks that do not contain the hottest memory die.

14. The apparatus of claim 12, wherein the storage controller cools the hottest memory die by directing the data mover to move data across each memory block of the hottest memory die to another plurality of memory blocks and temporarily stopping use of the hottest memory die, so that the hottest memory die cools due to non-use.

15. An apparatus comprising: Multiple storage blocks; as well as A storage controller configured to: determining a memory block of the plurality of memory blocks having a bit error rate above a read bit error rate threshold; iteratively reading data of the memory block using a predetermined number of different read levels; responsive to successfully reading the data of the memory block via the iterative reading, changing one or more read levels of the memory block to one or more of the predetermined number of different read levels used to successfully read the data of the memory block; as well as A read scan frequency of the plurality of memory blocks is increased in response to changing the one or more read levels.

16. The apparatus of claim 15, further comprising a crossover temperature manager configured to: determining a crossover temperature metric for the memory block; and The read scan frequency is changed in response to the cross-temperature metric of the memory block satisfying a cross-temperature threshold.

17. The apparatus of claim 16, wherein the cross temperature manager determines the cross temperature metric by: determining a writing temperature of the data of the storage block; determining a current temperature of the memory block; and The crossover temperature metric is set to be the difference between the write temperature and the current temperature.

18. The apparatus of claim 15, wherein each memory block of the plurality of memory blocks spans a plurality of memory dies, the apparatus further comprising a health manager configured to: In response to iteratively attempting to read the data of the memory block, determining that the memory block includes a hottest memory die of the plurality of memory die based on a die temperature of each memory die spanned by the memory block; and The read scan frequency is changed in response to determining that the memory block includes the hottest memory die.

19. The apparatus of claim 18, wherein the health manager is further configured to queue the memory block including the hottest memory die as a next memory block for a subsequent read scan operation.

20. The apparatus of claim 18, wherein the memory controller is configured to reconfigure the memory blocks to exclude the hottest memory die.

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