Semiconductor device and method for manufacturing a semiconductor device

Abstract

The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. A semiconductor device includes a plurality of wirings each having a damascene structure on a semiconductor layer, wherein the plurality of wirings includes a first wiring and a second wiring adjacent to each other, wherein the first wiring includes a first portion, a second portion, and a third portion between the first portion and the second portion along a direction in which the first wiring extends, and wherein a width of the third portion is greater than each of a width of the first portion and a width of the second portion.

Description

TECHNICAL FIELD

[0001] Aspects of the present application relate generally to semiconductor devices. BACKGROUND

[0002] In semiconductor devices, damascene wiring is used for the purpose of miniaturizing wiring. Japanese Patent Application Laid-Open No. 2014-229749 discusses a method of forming damascene wiring by connective exposure. SUMMARY

[0003] According to an aspect of the present application, a semiconductor device includes a plurality of wirings each having a damascene structure on a semiconductor layer, wherein the plurality of wirings includes a first wiring and a second wiring adjacent to each other, wherein a distance between a first end and a second end of the first wiring is greater than 33 mm, wherein the first wiring includes a first portion, a second portion, and a third portion between the first portion and the second portion along a direction in which the first wiring extends, wherein each of a width of the first portion and a width of the second portion is less than 180 nm, and wherein a width of the third portion is greater than each of the width of the first portion and the width of the second portion.

[0004] According to another aspect of the present application, a semiconductor device includes a plurality of wirings each having a damascene structure on a semiconductor layer, wherein the plurality of wirings includes a first wiring and a second wiring adjacent to each other, wherein the first wiring includes a first portion, a second portion, and a third portion between the first portion and the second portion along a direction in which the first wiring extends, wherein a distance between the first portion and the second portion of the first wiring is greater than 33 mm, and wherein a width of the third portion is a maximum width of the first wiring in a range from the first portion to the second portion and is less than 180 nm.

[0005] According to still another aspect of the present application, a method for manufacturing a semiconductor device includes preparing a wafer including a semiconductor layer and an insulator film provided on the semiconductor layer; exposing a positive type photoresist film provided on the insulator film; developing the photoresist film to form a resist pattern from the photoresist film; processing the insulator film with the resist pattern to form a trench on the insulator film; and forming a wiring in the trench, wherein the wafer includes a first region, a second region, and a third region between the first region and the second region, and the trench extends from the first region to the second region via the third region, wherein the exposing includes a first exposure shot for exposing the photoresist film on the first region and the third region, and a second exposure shot for exposing the photoresist film on the second region and the third region after the first exposure shot, wherein the wiring includes a first portion on the first region, a second portion on the second region, and a third portion on the third region along a direction in which the wiring extends, and wherein a width of the third portion is greater than each of a width of the first portion and a width of the second portion.

[0006] According to still another aspect of the present application, a semiconductor device includes a plurality of unit pixels arranged as a plurality of rows and a plurality of columns and each including a photoelectric conversion section, and a plurality of output lines connected to the unit pixels in a column and transmitting an output of the unit pixels, wherein the plurality of output lines includes at least a first output line, a second output line having a portion adjacent to the first output line, and a third output line having a portion adjacent to the second output line, wherein each of the first output line, the second output line, and the third output line includes a portion extending along a first direction, wherein the first output line, the second output line, and the third output line pass through a first position and a second position different from the first position, and wherein each of at least two of a distance between the first output line and the second output line, a distance between the second output line and the third output line, and a distance between the first output line and the third output line is longer at the second position than at the first position.

[0007] According to still another aspect of the present application, a method for manufacturing a semiconductor device includes preparing a wafer including a semiconductor layer and an insulator film provided on the semiconductor layer; exposing a positive type photoresist film provided on the insulator film; developing the photoresist film to form a resist pattern from the photoresist film; processing the insulator film with the resist pattern to form a trench on the insulator film; and forming a wiring in the trench, wherein the wafer includes a first region, a second region, and a third region between the first region and the second region, and the trench extends from the first region to the second region via the third region, wherein the exposing includes a first exposure shot for exposing the photoresist film on the first region and the third region, and a second exposure shot for exposing the photoresist film on the second region and the third region after the first exposure shot, wherein the photoresist film obtained between the first exposure shot and the second exposure shot of the exposing includes a first exposed portion on the first region and exposed with the first exposure shot, a second exposed portion on the third region and exposed with the first exposure shot, and a third exposed portion between the first exposed portion and the second exposed portion and exposed with the first exposure shot, wherein the photoresist film obtained after the second exposure shot of the exposing includes a fourth exposed portion on the second region and exposed with the second exposure shot, a fifth exposed portion on the third region and exposed with the second exposure shot, and a sixth exposed portion between the fourth exposed portion and the fifth exposed portion and exposed with the second exposure shot, wherein at least a portion of the fifth exposed portion includes the second exposed portion, wherein in the developing, the first exposed portion, the second exposed portion, the third exposed portion, the fourth exposed portion, the fifth exposed portion, and the sixth exposed portion are removed, and wherein a width of the second exposed portion is smaller than a width of the third exposed portion.

[0008] Other features of the present application will become apparent from the following description of example embodiments thereof, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0009] FIG. 1A 、 FIG. 1B and FIG. 1C are schematic views illustrating a semiconductor device.

[0010] FIG. 2A and FIG. 2B are schematic views illustrating a semiconductor device.

[0011] FIG. 3A1 、 FIG. 3A2 、 FIG. 3B1 、 FIG. 3B2 、 FIG. 3C1 、 FIG. 3C2 、 FIG. 3D1 and FIG. 3D2 are schematic views illustrating a method for manufacturing a semiconductor device.

[0012] FIG. 4A1 、 FIG. 4A2 、 FIG. 4B1 、 FIG. 4B2 、 FIG. 4C1 、 FIG. 4C2 、 FIG. 4D1 and FIG. 4D2 are schematic diagrams illustrating a method for manufacturing a semiconductor device.

[0013] FIG. 5A 、 FIG. 5B 、 FIG. 5C 、 FIG. 5D 、 FIG. 5E and FIG. 5F are schematic diagrams illustrating a semiconductor device and a manufacturing method.

[0014] FIG. 6A 、 FIG. 6B 、 FIG. 6C 、 FIG. 6D 、 FIG. 6E and FIG. 6F are schematic diagrams illustrating a semiconductor device and a manufacturing method.

[0015] FIG. 7A 、 FIG. 7B 、 FIG. 7C 、 FIG. 7D 、 FIG. 7E and FIG. 7F are schematic diagrams illustrating a semiconductor device and a manufacturing method.

[0016] FIG. 8A 、 FIG. 8B 、 FIG. 8C 、 FIG. 8D 、 FIG. 8E and FIG. 8F are schematic diagrams illustrating a semiconductor device and a manufacturing method.

[0017] FIG. 9A 、 FIG. 9B 、 FIG. 9C 、 FIG. 9D 、 FIG. 9E and FIG. 9F are schematic diagrams illustrating a semiconductor device and a manufacturing method.

[0018] FIG. 10A 、 FIG. 10B and FIG. 10C are schematic diagrams illustrating a semiconductor device and a manufacturing method.

[0019] FIG. 11A 、 FIG. 11B 、 FIG. 11C and FIG. 11D are schematic diagrams illustrating a semiconductor device.

[0020] FIG. 12 is a schematic view which illustrates a device.

[0021] FIG. 13A FIG. 13B and FIG. 13C is a schematic view which illustrates a semiconductor device.

[0022] FIG. 14A and FIG. 14B is a schematic view which illustrates a semiconductor device.

[0023] FIG. 15A1 FIG. 15A2 FIG. 15B1 FIG. 15B2 FIG. 15C1 FIG. 15C2 FIG. 15D1 and FIG. 15D2 is a schematic view which illustrates a method for manufacturing a semiconductor device.

[0024] FIG. 16A1 FIG. 16A2 FIG. 16B1 FIG. 16B2 FIG. 16C1 and FIG. 16C2 is a schematic view which illustrates a method for manufacturing a semiconductor device.

[0025] FIG. 17A1 FIG. 17A2 FIG. 17B1 FIG. 17B2 FIG. 17C1 and FIG. 17C2 is a schematic view which illustrates a method for manufacturing a semiconductor device.

[0026] FIG. 18A1 FIG. 18A2 FIG. 18B1 FIG. 18B2 FIG. 18C1 and FIG. 18C2 is a schematic view which illustrates a method for manufacturing a semiconductor device.

[0027] FIG. 19A FIG. 19B FIG. 19C FIG. 19D and FIG. 19E is a schematic view which illustrates a method for manufacturing a semiconductor device.

[0028] FIG. 20A and FIG. 20B is a schematic view which illustrates a semiconductor device and a device, respectively.

[0029] FIG. 21 is a schematic view which illustrates a configuration of a semiconductor device.

[0030] FIG. 22 ​​​​​​​​​​​​​​​​​​​​​​is a schematic view illustrating a configuration of a semiconductor device.

[0031] FIG. 23 is a schematic view illustrating an operation of a semiconductor device.

[0032] FIG. 24A 、 FIG. 24B and FIG. 24C is a schematic view illustrating a configuration of a semiconductor device.

[0033] FIG. 25A 、 FIG. 25B and FIG. 25C is a schematic view illustrating a configuration of a semiconductor device.

[0034] FIG. 26A 、 FIG. 26B and FIG. 26C is a schematic view illustrating a configuration of a semiconductor device.

[0035] FIG. 27A 、 FIG. 27B and FIG. 27C is a schematic view illustrating a configuration of a semiconductor device.

[0036] FIG. 28A 、 FIG. 28B and FIG. 28C is a schematic view illustrating a configuration of a semiconductor device. DETAILED DESCRIPTION

[0037] Various exemplary embodiments, features, and aspects of the present application will be described in detail below with reference to the accompanying drawings. Also, in the following description and drawings, constituent elements common to each other are assigned the same reference numerals in a plurality of drawings. Therefore, the constituent elements common to each other are described by cross-referencing the plurality of drawings, and the description of the constituent elements assigned the same reference numerals is not repeated as appropriate.

[0038] FIG. 1A A photoelectric conversion device is illustrated as an example of a semiconductor device APR. The photoelectric conversion device is, for example, a complementary metal-oxide semiconductor (CMOS) image sensor, and can be used in, for example, an imaging device, a distance measuring device, or an illuminance measuring device. The semiconductor device APR used as the photoelectric conversion device is a semiconductor device in which a plurality of wirings 110 FIG. 1C) is provided on the semiconductor layer 100. The semiconductor device APR includes a pixel portion 11 in which unit pixels each including a photoelectric conversion element are two-dimensionally arranged in m rows and n columns, and a signal processing circuit 12 formed around the pixel portion 11. The semiconductor device APR has a size larger than or equal to a maximum exposure region of an exposure apparatus (exposure machine), and cannot be manufactured by such an exposure apparatus using one-shot exposure. Thus, the semiconductor device APR is manufactured by a divisional exposure technique in which a device region is divided into a left region and a right region adjacent to each other, and exposure is performed on the left region and the right region individually. For example, a wiring layer can be formed by divisional exposure. In the following description, a direction toward a central portion of the semiconductor device APR on its plane is referred to as an inner periphery side, and a direction opposite to the inner periphery side is referred to as an outer periphery side.

[0039] The semiconductor device APR is not limited to a front-side irradiation type photoelectric conversion device, and can be a back-side irradiation type photoelectric conversion device. Either type of photoelectric conversion device can achieve improvement in performance by miniaturization of wiring. However, the front-side irradiation type photoelectric conversion device can achieve improvement in sensitivity by miniaturization of wiring, and thus is particularly advantageous. Further, the semiconductor device APR can be a semiconductor device including a first semiconductor layer including a photoelectric conversion portion and a second semiconductor layer stacked on the first semiconductor layer. The second semiconductor layer can be provided with a control circuit for controlling a pixel circuit including the photoelectric conversion portion and a processing circuit for processing a signal output from the pixel circuit. Further, the semiconductor device APR is not limited to a photoelectric conversion device, and can be a display device using an organic electroluminescence (EL) element or a liquid crystal element, or can be a liquid ejection device such as a piezoelectric type or thermal type inkjet head. The semiconductor device APR can be a memory device including a memory cell array in which a plurality of memory cells are arranged, or can be an arithmetic device such as a central processing unit (CPU) or a graphics processing unit (GPU).

[0040] FIG. 1B is a plan view illustrating a plurality of device regions DR formed on a wafer WF. Each device region DR has a size larger than a maximum exposure region of an exposure apparatus. Each device region DR is divided into regions each having a size smaller than or equal to the maximum exposure region of the exposure apparatus, and is formed by divisional exposure in which exposure is performed on the respective regions individually.

[0041] FIG. 1CThis is a conceptual diagram illustrating a device region DR. The device region DR is divided into at least a left region SL and a right region SR relative to a line A-A' used as a baseline, and the left region SL and right region SR are exposed using correspondingly different photomasks. Hereinafter, line A-A' is sometimes referred to as the "segmentation center line". The left region SL is defined by the area extending from its left end to line C-C', and the right region SR is defined by the area extending from its right end to line B-B'. Hereinafter, line C-C' is sometimes referred to as the "right end of the left region", and line B-B' is sometimes referred to as the "left end of the right region". The intermediate region SC located between line B-B' and line C-C' can be exposed when the left region SL is exposed, and can also be exposed when the right region SR is exposed. In this way, since the intermediate region SC is repeatedly exposed, it can also be referred to as the "repeating region". Furthermore, although the device region DR is divided into two regions in the description of this exemplary embodiment, the number of segments can be three or more. Furthermore, although the device region DR is divided into a left region and a right region in the example below, the division direction is optional and can therefore be divided into an upper region and a lower region.

[0042] FIG. 1A The semiconductor device APR illustrated in the diagram is formed in the following state, wherein multiple device regions DR are as follows: FIG. 1B The semiconductor device assembly (APR) is arranged two-dimensionally on a wafer (WF), undergoes additional manufacturing processes, and is then divided into individual semiconductor device portions (chips) by dicing (die-cutting). A semiconductor device assembly (APR) includes at least the semiconductor device portions (chips) thus formed. As described below, a semiconductor device APR may also include, in addition to the semiconductor device portions, a package in which the semiconductor device portions are housed.

[0043] FIG. 1C The illustration shows the dimensions of the device region DR of a semiconductor device APR manufactured by the manufacturing method of this exemplary embodiment. The vertical length W1 of the semiconductor device APR is 33 mm or less, and its horizontal length W2 is greater than 33 mm. For example, the vertical length W1 of the device region DR is 32 mm, and its horizontal length W2 is 42 mm. Therefore, an exposure apparatus with a maximum exposure area of ​​26 mm × 33 mm cannot perform a single exposure on the device region DR.

[0044] The distance W2L between the reference line A-A' (which divides the device region DR into the left side region SL and the right side region SR with respect to the reference line A-A') and the left end portion of the device region DR is thus set to 26 mm or less, for example, to 21 mm. Further, the distance W2R between the reference line A-A' and the right end portion of the device region DR is set to 26 mm or less, for example, to 21 mm. Further, the distance W3 between the line A-A' and the line B-B' is set to 10 nanometers (nm) to 1000 nm, advantageously to 50 nm to 500 nm, for example, to 100 nm. Further, the distance W4 between the line A-A' and the line C-C' is set to 10 nm to 1000 nm, advantageously to 50 nm to 500 nm, for example, to 100 nm.

[0045] Since the length W1 is 33 mm or less and the sum of the distance W2L and the distance W3 is 26 mm or less, the left side region SL and the middle region SC can be exposed by the exposure apparatus whose maximum exposure region is 26 mm x 33 mm.

[0046] Further, since the length W1 is 33 mm or less and the sum of the distance W2R and the distance W4 is 26 mm or less, the right side region SR and the middle region SC can be exposed by the exposure apparatus whose maximum exposure region is 26 mm x 33 mm.

[0047] Therefore, the semiconductor device APR whose length W1 is 33 mm or less and whose length W2 is greater than 33 mm can be exposed with the exposure apparatus whose maximum exposure region is 26 mm x 33 mm and in the case where the number of divisions of the device region DR is set to "2".

[0048] Further, in this example, the distance W2L and the distance W2R are set to be equal to each other, but the distance W2L and the distance W2R need not be equal to each other. Further, each of the line A-A', the line B-B', and the line C-C' is set to be a straight line, but it can be set to be a meandering line within a range in which the sum of the distance W21 and the distance W3 does not exceed the maximum exposure region, as appropriate, depending on the pattern in the device region.

[0049] Moreover, since in an exposure apparatus whose maximum exposure area is 26 mm x 33 mm, in some cases, the resolution of the edge portion of the maximum exposure area can be lower than that of the central portion thereof, the following case can occur: even the exposure apparatus whose maximum exposure area is 26 mm x 33 mm performs exposure using substantially only a portion of the maximum exposure area. In this case, the split exposure can be applied to a semiconductor device APR even having a size smaller than 26 mm x 33 mm. In other words, the size of the semiconductor device APR to which the split exposure in the present exemplary embodiment is applied is not particularly limited.

[0050] In the case of an image sensor of a full-size standard called 35 mm, FIG. 1A The size of the pixel portion 11 illustrated in FIG. 1 is 36 mm ± 1 mm x 24 mm ± 1 mm. In FIG. 1CIn the semiconductor device APR, the row wiring of the pixel section 11 among the plurality of wirings 110 is illustrated. The row wiring is a global wiring commonly connected to the pixel group included in one pixel row. The row wiring is, for example, a signal line via which an input signal (control signal) is transmitted to the pixel group included in one pixel row. Further, the row wiring is, for example, a power line via which power (power supply potential or ground potential) is supplied to the pixel group included in one pixel row. Further, the column wiring is a global wiring intersecting the row wiring and commonly connected to the pixel group included in one pixel column. The row wiring and the column wiring need to extend at least from one end of the pixel section 11 to the other end thereof. Therefore, the distance from one end of the row wiring to the other end thereof can need to be a length greater than or equal to the horizontal width (36 mm ± 1 mm) of the pixel section 11, and the distance from one end of the column wiring to the other end thereof can need to be a length greater than or equal to the vertical width (24 mm ± 1 mm) of the pixel section 11. The column wiring is, for example, a signal line via which an output signal (pixel signal) from the pixel group included in one pixel column is transmitted. Further, the column wiring is, for example, a power line via which power (power supply potential or ground potential) is supplied to the pixel group included in one pixel column. These row wirings and column wirings can be assigned to any one of the first wiring layer, the second wiring layer, the third wiring layer, and the fourth wiring layer arranged in order closer to the semiconductor layer 100. The first wiring layer can have a single damascene structure, and the second wiring layer, the third wiring layer, and the fourth wiring layer can have a dual damascene structure. For example, the power line serving as a global wiring (column wiring) can be arranged in the first wiring layer and / or the second wiring layer. For example, the signal line serving as a global wiring (row wiring) can be arranged in one of the third wiring layer and the fourth wiring layer (typically, the third wiring layer). For example, the signal line serving as a global wiring (column wiring) can be arranged in the other of the third wiring layer and the fourth wiring layer (typically, the fourth wiring layer). In addition, local wirings are arranged in each wiring layer, and particularly, a number of local wirings can be arranged in the first wiring layer. Although an example in which four wiring layers are present has been described here, for example, the second wiring layer can be omitted and local wirings and power lines can be arranged in the first wiring layer. Although the assignment of global lines to the wiring layers is not limited to the above-mentioned assignment, in view of these relationships, a wiring having a length exceeding 33 mm can be a power line (row wiring) having a single damascene structure or a signal line (row wiring) having a dual damascene structure.

[0051] FIG. 2Ais a plan view of a plurality of wirings 110 in the semiconductor device APR. Each of the wirings Q1, Q2, and Q3 has a damascene structure. The wirings Q1 and Q2 are adjacent to each other, and the wirings Q2 and Q3 are adjacent to each other. The distance between one end Ea and the other end Eb of the wiring Q2 is greater than 33 mm. As mentioned above, the distance between one end Ea and the other end Eb of the wiring Q2 can be 36 mm ± 1 mm or more. FIG. 2B is FIG. 2A is an enlarged view of the region AA illustrated in FIG. 2BIn the present embodiment, the width Wa of the left portion 110a, the width Wb of the right portion 110b, and the width Wc of the middle portion 110c are illustrated. It is characterized in that the width Wc of the middle portion 110c is greater than each of the width Wa of the left portion 110a and the width Wb of the right portion 110b (Wc > Wa, Wc > Wb). Each of the width Wa of the left portion 110a and the width Wb of the right portion 110b can be less than 230 nm. In the case where each of the width Wa of the left portion 110a and the width Wb of the right portion 110b is less than 230 nm, the advantageous effect of achieving miniaturization obtained by making the width Wc greater than each of the width Wa and the width Wb can be achieved significantly. In the case where each of the width Wa of the left portion 110a and the width Wb of the right portion 110b is 230 nm or more, the width Wc of the middle portion 110c can be the same as or different from each of the width Wa of the left portion 110a and the width Wb of the right portion 110b. Making the width Wc of the middle portion 110c greater than each of the width Wa and the width Wb in the case where each of the width Wa and the width Wb is 230 nm or more can be disadvantageous in terms of achieving miniaturization. Each of the width Wa of the left portion 110a and the width Wb of the right portion 110b can be less than 180 nm. In the case where each of the width Wa of the left portion 110a and the width Wb of the right portion 110b is less than 180 nm, the advantageous effect of achieving miniaturization obtained by making the width Wc greater than each of the width Wa and the width Wb can be achieved significantly. It is advantageous that the difference between the width Wc of the middle portion 110c and the width Wa of the left portion 110a (Wc - Wa) is greater than 50 nm, and this is advantageous in terms of making the width Wa of the left portion 110a less than 180 nm. It is advantageous that the difference between the width Wc of the middle portion 110c and the width Wb of the right portion 110b (Wc - Wb) is greater than 50 nm, and this is advantageous in terms of making the width Wb of the right portion 110b less than 180 nm. It is advantageous that the difference between the width Wc of the middle portion 110c and the width Wa of the left portion 110a (Wc - Wa) is less than the width Wa of the left portion 110a (Wc - Wa < Wa). It is also advantageous that the difference between the width Wc of the middle portion 110c and the width Wb of the right portion 110b (Wc - Wb) is less than the width Wb of the right portion 110b (Wc - Wb < Wb). It is also advantageous that the width Wc of the middle portion 110c is greater than 110 nm. It is also advantageous that the width Wc of the middle portion 110c is greater than 180 nm. The width Wc of the middle portion 110c can be less than 300 nm. Although the width Wb is equal to the width Wa in the present example, the width Wb can be different from the width Wa.

[0052] InFIG. 2B In the example, the distance Da between each of the wirings Q1 and Q3 and the left side portion 110a of the wiring Q2, the distance Db between each of the wirings Q1 and Q3 and the right side portion 110b of the wiring Q2, and the distance Dc between each of the wirings Q1 and Q3 and the middle portion 110c of the wiring Q2 are illustrated. Advantageously, the distance Dc between each of the wirings Q1 and Q3 and the middle portion 110c of the wiring Q2 is greater than the width Wa of the left side portion 110a (Dc > Wa). Advantageously, the distance Dc between each of the wirings Q1 and Q3 and the middle portion 110c of the wiring Q2 is greater than the width Wb of the right side portion 110b (Dc > Wb). Advantageously, the distance Da between each of the wirings Q1 and Q3 and the left side portion 110a of the wiring Q2 is less than the width Wc of the middle portion 110c (Da < Wc). Advantageously, the distance Db between each of the wirings Q1 and Q3 and the right side portion 110b of the wiring Q2 is less than the width Wc of the middle portion 110c (Db < Wc). Although the distance Db is equal to the distance Da in the present example, the distance Db can be different from the distance Da.

[0053] In FIG. 2B In the example, the length La of the left side portion 110a, the length Lb of the right side portion 110b, and the length Lc of the middle portion 110c are illustrated, which are taken along the direction in which the wirings Q1, Q2, and Q3 extend. The length Lc of the middle portion 110c can be greater than the width Wa of the left side portion 110a. The length Lc of the middle portion 110c can be greater than the width Wb of the right side portion 110b. The length Lc of the middle portion 110c can be less than the length La of the left side portion 110a. The length Lc of the middle portion 110c can be less than the length Lb of the right side portion 110b.

[0054] Generally, each of the width Wa, the width Wb, the distance Da, and the distance Db is less than each of the width Wc and the distance Dc.

[0055] An example in which the semiconductor device APR is applied to a photoelectric conversion device is described. Each of the wirings Q1, Q2, and Q3 is, for example, a row wiring having a dual damascene structure. Each of the wirings Q1, Q2, and Q3 is a signal line for transmitting a control signal to a pixel circuit including four transistors (a transfer transistor, a reset transistor, an amplification transistor, and a selection transistor) per one pixel P. For example, the wiring Q1 is a transfer signal line for controlling the transfer transistor, the wiring Q2 is a reset signal line for controlling the reset transistor, and the wiring Q3 is a selection signal line for controlling the selection transistor. The functions possessed by the plurality of wirings 110 and the wirings Q1, Q2, and Q3 in the present exemplary embodiment are not limited to the above-described examples.

[0056] InFIG. 2A In the drawing, the respective ranges of the plurality of pixels P are illustrated. For each pixel P, a portion in which the width of the wiring is thick (thick line portion) and a portion in which the width of the wiring is thin (thin line portion) are repeatedly provided. The left side portion 110a is located between the middle portion 110c and one end Ea along the direction in which the wirings Q1, Q2, and Q3 extend, of the range AA. The right side portion 110b is located between the middle portion 110c and the other end Eb along the direction in which the wirings Q1, Q2, and Q3 extend, of the range AA. Each of the wirings Q1, Q2, and Q3 includes, along the direction in which the wirings Q1, Q2, and Q3 extend, a thin line portion L4 located between the one end Ea and the left side portion 110a, and a thick line portion L5 located between the thin line portion L4 and the left side portion 110a. Further, each of the wirings Q1, Q2, and Q3 includes, along the direction in which the wirings Q1, Q2, and Q3 extend, a thin line portion R6 located between the other end Eb and the right side portion 110b, and a thick line portion R7 located between the thin line portion R6 and the right side portion 110b. The width of the thick line portion L5 is greater than each of the width Wa of the left side portion 110a, the width Wb of the right side portion 110b, the width of the thin line portion L4, and the width of the thin line portion R6. The width of the thick line portion R7 is greater than each of the width Wa of the left side portion 110a, the width Wb of the right side portion 110b, the width of the thin line portion L4, and the width of the thin line portion R6. Although it is advantageous for the width of the thick line portion L5 or the width of the thick line portion R7 to be equal to the width Wc, the width of the thick line portion L5 or the width of the thick line portion R7 can be different from the width Wc. Although it is advantageous for the width of the thin line portion L4 or the width of the thin line portion R6 to be equal to the width Wa or Wb, the width of the thin line portion L4 or the width of the thin line portion R6 can be different from the width Wa or Wb.

[0057] In this way, providing the thick line portions (i.e., the thick line portions L5 and R7) at positions corresponding to the range AA in the pixels away from the line A-A’ that do not include the middle region SC enables improving the uniformity of the layout of the wirings in each pixel, and thus increasing the uniformity of the characteristics of each pixel. In other words, providing such thick line portions enables reducing the difference in signal output between the pixels close to the line A-A’ that include the middle region SC and the pixels away from the line A-A’ that do not include the middle region SC, and preventing or reducing line noise appearing in the image along the line A-A’. Naturally, since the thick line portion L5 exists in the left side region SL and the thick line portion R7 exists in the right side region SR, the thick line portions L5 and R7 have little function of mitigating the effects of misalignment between the photomask used when the left side region SL is exposed and the photomask used when the right side region SR is exposed.

[0058] Each of the wirings Q1, Q2, and Q3 includes, along the direction in which the wirings Q1, Q2, and Q3 extend, a left side portion 110d between the left side portion 110a and the middle portion 110c, and a right side portion 110e between the right side portion 110b and the middle portion 110c. FIG. 2B In the present example, the width Wd of the left side portion 110d and the width We of the right side portion 110e are illustrated. The width Wd of the left side portion 110d is greater than the width Wa of the left side portion 110a (Wd > Wa), and the width We of the right side portion 110e is greater than the width Wb of the right side portion 110b (We > Wb). In the present example, the width Wd of the left side portion 110d is equal to the width Wc of the middle portion 110c (Wd = Wc). In the case where the width Wd of the left side portion 110d is different from the width Wc of the middle portion 110c, although the width Wd of the left side portion 110d can be greater than the width Wc of the middle portion 110c (Wd > Wc), it is advantageous that the width Wd of the left side portion 110d is less than the width Wc of the middle portion 110c (Wd < Wc). Similarly, the width We of the right side portion 110e is equal to the width Wc of the middle portion 110c (We = Wc). In the case where the width We of the right side portion 110e is different from the width Wc of the middle portion 110c, although the width We of the right side portion 110e can be greater than the width Wc of the middle portion 110c (We > Wc), it is advantageous that the width We of the right side portion 110e is less than the width Wc of the middle portion 110c (We < Wc). It is advantageous that the difference between the width Wc of the middle portion 110c and the width Wd of the left side portion 110d (|Wc - Wd|) is less than the difference between the width Wa of the left side portion 110a and the width Wd of the left side portion 110d (|Wd - Wa|) (|Wc - Wd| < |Wd - Wa|). Similarly, it is advantageous that the difference between the width Wc of the middle portion 110c and the width We of the right side portion 110e (|Wc - We|) is less than the difference between the width Wb of the right side portion 110b and the width We of the right side portion 110e (|We - Wb|) (|Wc - We| < |We - Wb|). Since there can be a relationship of Wc = Wd = We as mentioned above, the relationship between the width Wc and the widths Wa and Wb can be applied to the relationship between the widths Wd and We and the widths Wa and Wb. Furthermore, the left side portion 110d and the right side portion 110e can be omitted, and this is equivalent to making the width Wd of the left side portion 110d equal to the width Wa and making the width We of the right side portion 110e equal to the width Wb.

[0059] As FIG. 2BAs illustrated in the middle drawing, the wiring Q1 and the wiring Q3 are positioned obliquely between the left portion 110a and the left portion 110d. This achieves both Wa < Wc and Da < Dc. Similarly, the wiring Q1 and the wiring Q3 are positioned obliquely between the right portion 110b and the right portion 110e. This achieves both Wb < Wc and Db < Dc.

[0060] Further, making the width Wc larger than each of the width Wa and the width Wb (Wc > Wa & Wb) makes it possible to prevent or reduce disconnection of the pattern at the middle portion 110c even when misalignment occurs between the photomasks for the left region SL and the right region SR. This then makes it possible to form a more minute pattern at the left portion 110a and the right portion 110b. Further, making the distance Dc larger than each of the distance Da and the distance Db (Dc > Da & Db) makes it possible to prevent or reduce short-circuiting of the pattern in the middle portion 110c even when misalignment occurs between the photomasks for the left region SL and the right region SR.

[0061] As FIG. 2A As illustrated in the middle drawing, the wiring pitch Y2 in the Y direction can be made larger than the wiring pitch Y1 in the Y direction. This makes it possible to make the wiring opening in the Y direction wider, and thus improves the sensitivity of the photoelectric conversion device.

[0062] In the following description, reference is made to FIG. 3A1 、 FIG. 3A2 、 FIG. 3B1 、 FIG. 3B2 、 FIG. 3C1 、 FIG. 3C2 、 FIG. 3C2 and FIG. 3D1 as well as FIG. 3D2 、 FIG. 4A1 、 FIG. 4A2 、 FIG. 4B1 、 FIG. 4B2 、 FIG. 4C1 、 FIG. 4C2 and FIG. 4D1 describing methods for manufacturing semiconductor devices. In FIG. 4D2 and FIG. 3A1 to FIG. 3D2 the drawings having a figure number with a suffix "1" are cross-sectional views, and the drawings having a figure number with a suffix "2" are plan views. The cross-sectional view having a figure number with a suffix "1" represents a cross-section taken along the line D-D' in the plan view having a figure number with a suffix "2".

[0063] As illustrated in each of the plan views with the figure numbers with the suffix "2" attached, the wafer WF includes, in each of the plurality of device regions DR, a left side region SL left of the line C-C', a right side region SR right of the line B-B', and a middle region SC between the left side region SL and the right side region SR.

[0064] FIG. 4A1 to FIG. 4D2 and FIG. 3A1 A process A for manufacturing a wafer WF including a semiconductor layer 100 and a second insulator film 104 provided on the semiconductor layer 100 is illustrated. The wafer WF used for manufacturing the semiconductor device APR in the present exemplary embodiment includes the semiconductor layer 100 serving as an element functional layer. The semiconductor layer 100 to be used includes a silicon layer or a compound semiconductor layer. In the element functional layer, for example, a plurality of photoelectric conversion sections (not illustrated), a plurality of transistors (not illustrated), and an isolation structure (not illustrated) for isolating the plurality of photoelectric conversion sections from the plurality of transistors at portions where they are to be electrically isolated from each other. The element functional layer can be formed by a known method using a known material.

[0065] On the semiconductor layer 100 serving as the element functional layer, an interlayer insulating film 101 is formed. The interlayer insulating film 101 is formed to establish electrical insulation between structures included in the semiconductor layer 100 serving as the element functional layer and layers above the interlayer insulating film 101. The interlayer insulating film 101 to be used can be made of, for example, silicon oxide and can be formed by a known method.

[0066] In the interlayer insulating film 101, a contact plug 102 is formed at a portion intended to secure electrical conduction between structures included in the semiconductor layer 100 serving as the element functional layer and a wiring above the interlayer insulating film 101. On the contact plug 102, a first insulator film 103 serving as an etching stopper layer and a second insulator film 104 serving as an interlayer insulating film are formed. For example, the contact plug 102 can be made of tungsten, the first insulator film 103 can be a silicon carbide film or a silicon nitride film, and the second insulator film 104 can be a silicon oxide film. Furthermore, these configurations are not intended to limit the present exemplary embodiment but are described as examples only.

[0067] FIG. 3A2 and FIG. 3B1A process B for forming mask material films 105 and 106 on the wafer WF is illustrated. The manufacturing method forms a first mask material film 105 and a second mask material film 106 on the second insulator film 104 serving as an interlayer insulating film. The first mask material film 105 is configured with an inorganic material film 1051 and an organic material film 1052. For example, the inorganic material film 1051 can be a silicon nitride film, and the organic material film 1052 can be made of a novolak-type resin. In the present exemplary embodiment, the first mask material film 105 has the above-described configuration, but can have another configuration. The second mask material film 106 to be used includes, for example, a silicon oxide film.

[0068] FIG. 3B2 and FIG. 3C1 An exposure process C for exposing the positive photoresist film 111 set on one side of the layers above the insulator films 103 and 104 with a left-side exposure shot L is illustrated. The left-side exposure shot L is used to expose the photoresist film 111 in the left-side region SL and the middle region SC above. After forming the positive photoresist film 111 on the second photo mask material film 106, the manufacturing method exposes the photoresist film 111 with the left-side exposure pattern 111L using the photo mask PML in the left-side region SL and the middle region SC above. As FIG. 3C2 The left-side exposure pattern 111L is used to expose across the line A-A’ up to the line B-B’ as illustrated in the middle.

[0069] FIG. 3C2 and FIG. 3D1 An exposure process D for exposing the positive photoresist film 111 set on one side of the layers above the insulator films 103 and 104 with a right-side exposure shot R is illustrated. After the left-side exposure shot L, the right-side exposure shot R is used to expose the photoresist film 111 in the right-side region SR and the middle region SC above. After exposing the left-side region SL, the manufacturing method exposes the middle region SC and the right-side region SR using the photo mask PMR in the right-side region SR and the middle region SC above, thereby exposing the photoresist film 111 with the right-side exposure pattern 111R. The right-side exposure pattern 111R is used to expose across the line A-A’ up to the line C-C’.

[0070] In this way, the exposure process obtained by combining the exposure process C and the exposure process D includes the left-side exposure shot L and the right-side exposure shot R performed after the left-side exposure shot L. Further, although an example in which the right-side exposure shot R is performed after the left-side exposure shot L has been described here, the left-side exposure shot L can be performed after the right-side exposure shot R. Details of the left-side exposure pattern 111L and the right-side exposure pattern 111R are described below. The wavelength of the exposure light to be used advantageously includes, for example, 175 nm to 275 nm, and such exposure light includes, for example, exposure light of a wavelength of 225 nm to 275 nm (for example, a KrF excimer laser of a wavelength of 248 nm) and exposure light of a wavelength of 175 nm to 225 nm (for example, an ArF excimer laser of a wavelength of 193 nm). In terms of miniaturization of wiring, it is more advantageous to use an ArF excimer laser as the exposure light.

[0071] FIG. 3D2 and FIG. 4A1 An exposure process E for developing the photoresist film 111 to form a resist pattern 111D from the photoresist film 111 is illustrated. The manufacturing method performs the development process on the photoresist film 111 on which the latent image pattern has been formed via the left-side exposure shot L and the right-side exposure shot R, thereby forming the resist pattern 111D. Since the photoresist film 111 is positive, portions exposed by the exposure process in the photoresist film 111 are removed by the development process.

[0072] FIG. 4A2 and FIG. 4B1 A processing process F for performing processing on the mask material film 106 using the resist pattern 111D as a mask to transfer the resist pattern 111D to the mask material film 106 is illustrated. The manufacturing method forms the mask pattern 1061 by performing etching on the second mask material film 106 using the resist pattern 111D as a mask.

[0073] FIG. 4B2 and FIG. 4C1 A processing process G for performing processing on the insulator films 104 and 103 using the mask pattern 1061 as a mask to form the trench 109 in the insulator films 104 and 103 is illustrated. The manufacturing method performs etching on the first mask material film 105, the second insulator film 104 serving as an interlayer insulating film, and the first insulator film 103 using the mask pattern 1061 as a mask, thereby forming the trench 109. The trench 109 extends from the left-side region SL across the intermediate region SC to the right-side region SR.

[0074] Further, the processing obtained by combining the processing F and the processing G can be referred to as processing for forming trenches in the insulator films 104 and 103 by performing processing on the insulator films 104 and 103 using the resist pattern 111D. Although the processing F is included in the manufacturing method here, it is not necessary to refer to the processing F or to use the first mask material film 105. The resist pattern formed of the photoresist film formed directly above the insulator film 104 can itself be used as a mask to perform processing on the insulator films 104 and 103 to form trenches in the insulator films 104 and 103.

[0075] FIG. 4C2 and FIG. 4D1 The wiring processing H for forming the wiring 110 in the trench is illustrated. For example, the manufacturing method embeds a conductive material in the trench 109 using a plating method. The conductive material can be, for example, copper or a copper-containing alloy. Then, after the conductive material is embedded, the manufacturing method removes unnecessary conductive material formed on the second insulator film 104 using, for example, a chemical mechanical polishing (CMP) method. With this processing, the manufacturing method forms the wiring 110 in the trench 109. The wiring 110 extends from the left side region SL across the middle region SC to the right side region SR. The wiring 110 includes a left side portion 110L located on the left side region SL, a right side portion 110R located on the right side region SR, and a middle portion 110C located on the middle region SC along the direction in which the wiring 110 extends. In this way, the wiring formed by embedding a conductive material in an insulator film and then removing unnecessary conductive material is referred to as a "damascene wiring", and such processing is referred to as a "damascene processing".

[0076] Then, the manufacturing method forms at least one upper wiring layer (typically, a plurality of upper wiring layers). The formation of the upper wiring layer can be performed by applying a damascene processing similar to the above-described damascene processing to an interlayer insulator film formed on the second insulator film 104 and the wiring 110. In the case where the semiconductor device APR is a front-illuminated type photoelectric conversion device, after the upper wiring layer is formed, the manufacturing method can provide an opening to the plurality of interlayer insulator films including the second insulator film 104. The opening is for forming a light path for light to reach the photoelectric conversion section. A light-transmissive material different from the material of the first insulator film 103 and / or the second insulator film 104 can be embedded in the opening. For example, if the first insulator film 103 is made of silicon carbide or silicon nitride and the second insulator film 104 is made of silicon oxide, the light-transmissive material only needs to be silicon nitride, silicon oxide, or a resin.

[0077] In the above description, a case in which the method for manufacturing a semiconductor device is applied to formation of wirings has been described. The wiring layer includes wirings for transmitting power and signals common to respective columns of the pixel portion, and these wirings are arranged while extending between the left-side region SL and the right-side region SR. The use of split exposure in the present exemplary embodiment makes it possible to perform miniaturization processing on the wirings in the respective regions, and also makes it possible to perform miniaturization on the portions extending between the regions. The wirings obtained by connection using split exposure can be, for example, power lines for supplying power to cause the pixel portion or the column circuit to operate. Alternatively, the wirings obtained by connection using split exposure can be, for example, signal lines for supplying control signals to control operation of the pixel portion or the column circuit, or signal lines for transmitting output signals from the column circuit based on the amount of light received for each pixel. However, another type of wiring can be formed by connection using split exposure. Although the wirings whose manufacturing method has been described in the present exemplary embodiment are single damascene wirings formed by single damascene processing, a similar method can be applied to dual damascene wirings formed by dual damascene processing. Although "trench first" can be adopted for dual damascene processing, it is more advantageous to adopt "via first" in terms of miniaturization.

[0078] Furthermore, although the wiring layer whose manufacturing method has been described is one layer, the above-described exemplary embodiment can be applied to two or more wiring layers. Furthermore, the exposure apparatus used for exposure at the time of formation can be different between the wirings in the first layer and the wirings in the second layer. For example, when forming the wirings in the first layer, the manufacturing method can use an exposure apparatus using an ArF light source with a wavelength of 193 nm and a maximum exposure area of 26 mm x 33 mm, and when forming the wirings in the second and subsequent layers, the manufacturing method can use an exposure apparatus using a KrF light source with a wavelength of 248 nm and a maximum exposure area of 26 mm x 33 mm. The wirings in the first layer can be single damascene wirings and the wirings in the second layer can be dual damascene wirings. Then, the manufacturing method can apply connection exposure (split exposure) using an ArF light source to the single damascene wirings in the first layer, and connection exposure (split exposure) using a KrF light source to the dual damascene wirings in the second layer.

[0079] In the following description, reference is made to FIG. 4D2 Details of the left-side exposure pattern 111L and the right-side exposure pattern 111R in the exposure processing illustrated in FIG. 5A to FIG. 9F and FIG. 3C1 and FIG. 3C2 and FIG. 3D1 are described.

[0080] In FIG. 3D2In the middle, each of the drawings with the figure number accompanied by the suffix "A" illustrates a pattern on the photomask PML used at the time of the left exposure shot L for exposing the left side region SL. In the middle, each of the drawings with the figure number accompanied by the suffix "B" illustrates a left exposure pattern 111L of the photoresist film 111 between the left exposure shot L and the right exposure shot R of the exposure process C. In the drawings with the figure number accompanied by the suffix "B", the left exposure pattern 111L is indicated with the hatching of a diagonal line rising to the upper left. As illustrated in the drawings with the figure number accompanied by the suffix "B", the photoresist film 111 includes an exposed portion 111La located on the left side region SL and already exposed with the left exposure shot L, and an exposed portion 111Lc located on the middle region SC and already exposed with the left exposure shot L. Additionally, the photoresist film 111 includes an exposed portion 111Ld located between the exposed portion 111La and the exposed portion 111Lc and already exposed with the left exposure shot L. FIG. 5A to FIG. 9F In the middle, each of the drawings with the figure number accompanied by the suffix "C" illustrates a pattern on the photomask PMR used at the time of the right exposure shot R for exposing the right side region SR. Each of the photomasks PML and PMR includes a light-shielding region LS and a light-transmitting region LT. The photoresist film 111 is exposed with exposure light that has transmitted through the light-transmitting region LT.

[0081] In the middle, each of the drawings with the figure number accompanied by the suffix "D" illustrates a right exposure pattern 111R of the photoresist film 111 obtained after the right exposure shot R of the exposure process D. In the drawings with the figure number accompanied by the suffix "D", the right exposure pattern 111R is indicated with the hatching of a diagonal line rising to the upper right. As illustrated in the drawings with the figure number accompanied by the suffix "D", the photoresist film 111 includes an exposed portion 111Rb located on the right side region SR and already exposed with the right exposure shot R, and an exposed portion 111Rc located on the middle region SC and already exposed with the right exposure shot R. Additionally, the photoresist film 111 includes an exposed portion 111Re located between the exposed portion 111Rb and the exposed portion 111Rc and already exposed with the right exposure shot R. FIG. 5A to FIG. 9F In the middle, each of the drawings with the figure number accompanied by the suffix "A" illustrates a pattern on the photomask PML used at the time of the left exposure shot L for exposing the left side region SL. In the middle, each of the drawings with the figure number accompanied by the suffix "B" illustrates a left exposure pattern 111L of the photoresist film 111 between the left exposure shot L and the right exposure shot R of the exposure process C. In the drawings with the figure number accompanied by the suffix "B", the left exposure pattern 111L is indicated with the hatching of a diagonal line rising to the upper left. As illustrated in the drawings with the figure number accompanied by the suffix "B", the photoresist film 111 includes an exposed portion 111La located on the left side region SL and already exposed with the left exposure shot L, and an exposed portion 111Lc located on the middle region SC and already exposed with the left exposure shot L. Additionally, the photoresist film 111 includes an exposed portion 111Ld located between the exposed portion 111La and the exposed portion 111Lc and already exposed with the left exposure shot L.

[0082] In the middle, each of the drawings with the figure number accompanied by the suffix "D" illustrates a right exposure pattern 111R of the photoresist film 111 obtained after the right exposure shot R of the exposure process D. In the drawings with the figure number accompanied by the suffix "D", the right exposure pattern 111R is indicated with the hatching of a diagonal line rising to the upper right. As illustrated in the drawings with the figure number accompanied by the suffix "D", the photoresist film 111 includes an exposed portion 111Rb located on the right side region SR and already exposed with the right exposure shot R, and an exposed portion 111Rc located on the middle region SC and already exposed with the right exposure shot R. Additionally, the photoresist film 111 includes an exposed portion 111Re located between the exposed portion 111Rb and the exposed portion 111Rc and already exposed with the right exposure shot R. FIG. 5A to FIG. 9F In the middle, each of the drawings with the figure number accompanied by the suffix "D" illustrates a right exposure pattern 111R of the photoresist film 111 obtained after the right exposure shot R of the exposure process D. In the drawings with the figure number accompanied by the suffix "D", the right exposure pattern 111R is indicated with the hatching of a diagonal line rising to the upper right. As illustrated in the drawings with the figure number accompanied by the suffix "D", the photoresist film 111 includes an exposed portion 111Rb located on the right side region SR and already exposed with the right exposure shot R, and an exposed portion 111Rc located on the middle region SC and already exposed with the right exposure shot R. Additionally, the photoresist film 111 includes an exposed portion 111Re located between the exposed portion 111Rb and the exposed portion 111Rc and already exposed with the right exposure shot R.

[0083] In the middle, each of the drawings with the figure number accompanied by the suffix "D" illustrates a right exposure pattern 111R of the photoresist film 111 obtained after the right exposure shot R of the exposure process D. In the drawings with the figure number accompanied by the suffix "D", the right exposure pattern 111R is indicated with the hatching of a diagonal line rising to the upper right. As illustrated in the drawings with the figure number accompanied by the suffix "D", the photoresist film 111 includes an exposed portion 111Rb located on the right side region SR and already exposed with the right exposure shot R, and an exposed portion 111Rc located on the middle region SC and already exposed with the right exposure shot R. Additionally, the photoresist film 111 includes an exposed portion 111Re located between the exposed portion 111Rb and the exposed portion 111Rc and already exposed with the right exposure shot R. FIG. 5A to FIG. 9FIn the drawings having the figure numbers with the suffix "E", each of the drawings with the figure numbers with the suffix "E" is hatched to show a latent image pattern formed using the left-exposure pattern 111L and the right-exposure pattern 111R of the photoresist film 111 obtained after the left-exposure shot L and the right-exposure shot R in the exposure process D. In the drawings having the figure numbers with the suffix "E", the portion without hatching is a portion that is not removed by development. In the drawings having the figure numbers with the suffix "E", the left-exposure pattern 111L is indicated with hatching of a diagonal line rising in a diagonal left-upward direction. In the drawings having the figure numbers with the suffix "E", the right-exposure pattern 111R is indicated with hatching of a diagonal line rising in a diagonal right-upward direction.

[0084] In FIG. 5A to FIG. 9F In the drawings having the figure numbers with the suffix "E", in a region located on the left-side region SL and the right-side region SR, in the drawings having the figure numbers with the suffix "B" and the figure numbers with the suffix "D", the left-exposure pattern 111L and the right-exposure pattern 111R become latent image patterns. In FIG. 5A to FIG. 9F FIG. 5A to FIG. 9F In the drawings having the figure numbers with the suffix "E", in a region located on the middle region SC, since double exposure is performed with the left-exposure shot L and the right-exposure shot R, the latent image pattern can be changed from the left-exposure pattern 111L and the right-exposure pattern 111R illustrated in the drawings having the figure numbers with the suffix "B" and the figure numbers with the suffix "D". FIG. 5A to FIG. 9F

[0085] As illustrated in the drawings having the figure numbers with the suffix "E", the latent image pattern of the photoresist film 111 includes an exposed portion 111Rb located on the right-side region SR and having been exposed with the right-exposure shot R and an exposed portion 111LR located on the middle region SC and having been exposed with the right-exposure shot R. Additionally, the latent image pattern of the photoresist film 111 includes an exposed portion 111Re located between the exposed portion 111Rb and the exposed portion 111LR and having been exposed with the right-exposure shot R.

[0086] Here, in the photoresist film 111, the exposed portion located on the middle region SC includes a double-exposed portion 111LR having been exposed with both the left-exposure shot L and the right-exposure shot R. In FIG. 5A to FIG. 9F In the drawings having the figure numbers with the suffix "E", the double-exposed portion 111LR is indicated with hatching in which a diagonal line rising in a diagonal left-upward direction and a diagonal line rising in a diagonal right-upward direction intersect each other. Thus, the exposed portion 111LR having been exposed with at least the right-exposure shot R includes the exposed portion 111Lc. Further, in FIG. 5A to FIG. 9F and​​FIG. 8A to FIG. 8F In the middle region SC, the exposed portions include the exposed portion 111Lc that has been exposed with the left exposure L exposure and not exposed with the right exposure R exposure, and the exposed portion 111Rc that has not been exposed with the left exposure L exposure and has been exposed with the right exposure R exposure.

[0087] Since the photoresist film 111 is a positive type, the exposed portion 111La, the exposed portion 111Lc, the exposed portion 111Ld, the exposed portion 111Rb, the exposed portion 111Rc, the exposed portion 111LR, and the exposed portion 111Re are removed.

[0088] In the drawings with the figure number with the suffix "B", the width Ma of the exposed portion 111La, the width Md of the exposed portion 111Ld, and the width Mc' of the exposed portion 111Lc are illustrated. FIG. 9A to FIG. 9F In addition, in the drawings with the figure number with the suffix "D", the width Mb of the exposed portion 111Rb, the width Me of the exposed portion 111Re, and the width Mc" of the exposed portion 111Rc are illustrated. In addition, in the drawings with the figure number with the suffix "D", the width Mc" of the exposed portion 111Rc on the middle region SC exposed with the right exposure R exposure can be the same as the width Mc'.

[0089] FIG. 5A to FIG. 9F In addition, in the drawings with the figure number with the suffix "D", the width Mb of the exposed portion 111Rb, the width Me of the exposed portion 111Re, and the width Mc" of the exposed portion 111Rc are illustrated. In addition, in the drawings with the figure number with the suffix "D", the width Mc" of the exposed portion 111Rc on the middle region SC exposed with the right exposure R exposure can be the same as the width Mc'. FIG. 5A to FIG. 9F In addition, in the drawings with the figure number with the suffix "E", the width Ma of the latent image of the exposed portion 111La, the width Md of the latent image of the exposed portion 111Ld, the width Mb of the latent image of the exposed portion 111Rb, the width Me of the latent image of the exposed portion 111Re, and the width Mc of the latent image in the middle region SC are illustrated. In the drawings with the figure number with the suffix "B" and the drawings with the figure number with the suffix "E", the width Ma and the width Md are equal to each other.

[0090] FIG. 5A to FIG. 9F In addition, in the drawings with the figure number with the suffix "D", the width Mb of the exposed portion 111Rb, the width Me of the exposed portion 111Re, and the width Mc" of the exposed portion 111Rc are illustrated. In addition, in the drawings with the figure number with the suffix "D", the width Mc" of the exposed portion 111Rc on the middle region SC exposed with the right exposure R exposure can be the same as the width Mc'. FIG. 5A to FIG. 9F FIG. 5A to FIG. 9F In addition, in the drawings with the figure number with the suffix "D", the width Mb of the exposed portion 111Rb, the width Me of the exposed portion 111Re, and the width Mc" of the exposed portion 111Rc are illustrated. In addition, in the drawings with the figure number with the suffix "D", the width Mc" of the exposed portion 111Rc on the middle region SC exposed with the right exposure R exposure can be the same as the width Mc'.

[0091] ​​​It should be noted here that the width Mc' can be different from the width Mc. In the middle region SC, since double exposure is performed with the left-side exposure shot L and the right-side exposure shot R, the accumulated exposure amount increases, so that the width Mc can become larger than the width Mc' or Mc". This is because, due to the increase in the accumulated exposure amount, the amount of acid generation in the exposed portion increases, the protective group elimination reaction using acid as a catalyst occurs more frequently, and the region that is soluble in the developer liquid expands. Further, although diffraction of light can occur at the time of exposure, since double exposure is performed with both the diffracted light for the left-side exposure shot L and the diffracted light for the right-side exposure shot R, the width Mc can become larger than the width Mc'. Further, due to misalignment between the left-side exposure shot L and the right-side exposure shot R, the width Mc can also become different from the width Mc' or the width Mc". In FIG. 5A to FIG. 9F In the drawings having a drawing number with a suffix "E" attached thereto among FIG. 5A to FIG. 9F Each of the drawings having a drawing number with a suffix "F" attached thereto among FIG. 5A to FIG. 9F As illustrated in the drawings having a drawing number with a suffix "F" attached thereto among

[0092] In the drawings having a drawing number with a suffix "F" attached thereto among FIG. 5A to FIG. 9F In the drawings having a drawing number with a suffix "F" attached thereto among FIG. 7F In the drawings having a drawing number with a suffix "F" attached thereto among

[0093] In the following description, the widths Ma, Mb, Mc, Mc', Mc", Md, and Me of the respective exposure portions and the widths Wa, Wb, Wc, Wc', Wc", Wd, and We of the respective portions of the wiring are described with respect to the plurality of exemplary embodiments (the first exemplary embodiment to the fifth exemplary embodiment).

[0094] One of the commonalities between the first exemplary embodiment and the fifth exemplary embodiment is that the width Wc of the intermediate portion 110c is greater than each of the width Wa of the left side portion 110a and the width Wb of the right side portion 110b (Wc > Wa & Wb). Here, "Wa & Wb" means "Wa and Wb", and "Wc ≥ Wa & Wb" is synonymous with "Wc ≥ Wa and Wc ≥ Wb". In Wc ≥ Wa & Wb, Wa and Wb can be the same or can be different. This also applies to the following description. Furthermore, in the case of using an inequality with an equal sign, this means that the sign can be an equal sign or can be an inequality sign. Thus, "Wc ≥ Wa & Wb" is synonymous with "Wc = Wa & Wb" or "Wc > Wa & Wb".

[0095] In this way, making the width Wc of the wiring 110 in the intermediate region SC greater than each of the widths Wa and Wb makes it possible to prevent or reduce the wiring 110 from being broken in the intermediate region SC even when misalignment occurs between the photomask PML and the photomask PMR.

[0096] One of the commonalities between the first exemplary embodiment and the fifth exemplary embodiment is that the width Ma of the exposure portion 111La is smaller than the width Mc' of the exposure portion 111Lc (Ma < Mc'). One of the commonalities between the first exemplary embodiment and the fifth exemplary embodiment is that the width Mb of the exposure portion 111Rb is smaller than the width Mc" of the exposure portion 111Rc (Mb < Mc"). This makes it possible to increase the resolution in the exposure portion 111Lc and the exposure portion 111Rc compared to the exposure portion 111La and the exposure portion 111Rb. This makes it possible to prevent or reduce the exposure portion 111Lc and the exposure portion 111Rc from not being resolved under the conditions in which the exposure portion 111La and the exposure portion 111Rb are exposed.

[0097] Furthermore, one of the commonalities between the first exemplary embodiment and the fifth exemplary embodiment is that the width Md of the exposure portion 111Ld is greater than the width Ma of the exposure portion 111La (Md > Ma). One of the commonalities between the first exemplary embodiment and the fifth exemplary embodiment is that the width Me of the exposure portion 111Re is greater than the width Mb of the exposure portion 111Rb (Me > Mb).

[0098] One of the commonalities between the second to fifth example embodiments is that the width Mc' of the exposure portion 111Lc is smaller than the width Md of the exposure portion 111Ld (Mc' < Md). One of the commonalities between the second to fifth example embodiments is that the width Mc" of the exposure portion 111Rc is smaller than the width Me of the exposure portion 111Re (Mc" < Me).

[0099] One of the commonalities between the first to fifth example embodiments is that the difference between the width Ma of the exposure portion 111La and the width Md of the exposure portion 111Ld (|Md - Ma|) is larger than the difference between the width Mc' of the exposure portion 111Lc and the width Md of the exposure portion 111Ld (|Md - Mc'|) (|Md - Ma| > |Md - Mc'|). One of the commonalities between the first to fifth example embodiments is that the difference between the width Mb of the exposure portion 111Rb and the width Me of the exposure portion 111Re (|Me - Mb|) is larger than the difference between the width Mc" of the exposure portion 111Rc and the width Me of the exposure portion 111Re (|Me - Mc"|) (|Me - Mb| > |Me - Mc"|).

[0100] <First Example Embodiment>

[0101] FIG. 5A to FIG. 5F A method for manufacturing a semiconductor device APR according to the first example embodiment is illustrated. FIG. 5A A pattern on a photomask PML used when exposing the left side region SL is illustrated. FIG. 5B A left side exposure pattern 111L for exposing a photoresist film 111 is illustrated. FIG. 5C A pattern on a photomask PMR used when exposing the right side region SR is illustrated. FIG. 5D A right side exposure pattern 111R for exposing a photoresist film 111 is illustrated.

[0102] The first example embodiment satisfies the relationship Ma & Mb < Md & Me ≤ Mc' & Mc". Furthermore, the first example embodiment satisfies the relationship Wa & Wb < Wd & We < Wc.

[0103] As illustrated in FIG. 5B and FIG. 5D The width Mc' of the exposure portion 111Lc and the width Md of the exposure portion 111Ld become the same, and the width Mc" of the exposure portion 111Rc and the width Me of the exposure portion 111Re become the same. However, since exposure is performed twice in the middle region SC, as FIG. 5EThe width Mc in the middle region SC including the latent image pattern of the exposed portion 111LR formed on the photoresist film 111 can become larger than each of the width Mc' and the width MC" (Mc' & Mc" < Mc) as illustrated in the middle drawing. Thus, the width Mc of the latent image pattern in the middle region SC becomes larger than each of the widths Md and Me of the latent image pattern in the regions other than the middle region SC. Therefore, the opening of the resist pattern formed after development in the middle region SC becomes larger than each of the openings of the resist patterns formed after development in the left region SL and the right region SR other than the middle region SC. Thereby, it is possible to prevent or reduce an increase in the resistance of the wiring attributable to the middle region SC. Further, if there are no influences of the above-mentioned diffracted light, acid, and misalignment, the relationship of Mc' & Mc" = Mc can be obtained. Even when the relationship of Mc' & Mc" = Mc is obtained, if the relationship of Md & Me ≤ Mc' & Mc" is obtained, the relationship of Wd & We < Wc can be obtained.

[0104] In order to prevent or reduce a short circuit between the adjacent wiring patterns in the middle region SC, it is advantageous to increase the interval between the adjacent wiring patterns. FIG. 2B The distance Dc as the pitch between the wirings in the middle region SC is sufficient to be larger than each of the distance Da and the distance Db as illustrated in the middle drawing. The distance Dc can be smaller than or equal to the width Wc in terms of performing miniaturization.

[0105] <Second Exemplary Embodiment>

[0106] FIG. 6A to FIG. 6F A method for manufacturing the semiconductor device APR according to the second exemplary embodiment is illustrated. The semiconductor device APR in the second exemplary embodiment differs from the semiconductor device APR in the first exemplary embodiment in the region on the photoresist film 111 exposed.

[0107] FIG. 6A A pattern on a photomask PML used when the left region SL is exposed is illustrated. FIG. 6B A left exposure pattern 111L for exposing the photoresist film 111 is illustrated. FIG. 6C A pattern on a photomask PMR used when the right region SR is exposed is illustrated. FIG. 6D A right exposure pattern 111R for exposing the photoresist film 111 is illustrated. Each of the photomasks PML and PMR includes a light-shielding region LS and a light-transmitting region LT. The photoresist film 111 is exposed with exposure light that has transmitted through the light-transmitting region LT.

[0108] While the first example embodiment satisfies the relationship of Mc' & Mc" ≥ Md & Me, the second example embodiment satisfies the relationship of Mc' & Mc" < Md & Me. The second example embodiment satisfies the relationship of Ma & Mb < Mc' & Mc" ≤ Mc ≤ Md & Me. Furthermore, the second example embodiment satisfies the relationship of Wa & Wb < Wc ≤ Wd & We.

[0109] In the second example embodiment, as illustrated in FIG. 6B, the pattern width on the photomask PML corresponding to the middle region SC is partially thinned. Therefore, as illustrated in FIG. 6C, exposure is performed with the left-side exposure pattern 111L for exposing the photoresist film 111 in such a manner that the width Mc' in the middle region SC is thinner than the width Md in the left-side region SL other than the middle region SC. Furthermore, in the second example embodiment, as illustrated in FIG. 6D, the pattern width on the photomask PMR corresponding to the middle region SC is partially thinned. Therefore, as illustrated in FIG. 6E, exposure is performed with the right-side exposure pattern 111R for exposing the photoresist film 111 in such a manner that the width Mc" in the middle region SC is thinner than the width Me in the right-side region SR other than the middle region SC. FIG. 6A FIG. 6B In the second example embodiment, as illustrated in FIG. 6B, the pattern width on the photomask PML corresponding to the middle region SC is partially thinned. Therefore, as illustrated in FIG. 6C, exposure is performed with the left-side exposure pattern 111L for exposing the photoresist film 111 in such a manner that the width Mc' in the middle region SC is thinner than the width Md in the left-side region SL other than the middle region SC. Furthermore, in the second example embodiment, as illustrated in FIG. 6D, the pattern width on the photomask PMR corresponding to the middle region SC is partially thinned. Therefore, as illustrated in FIG. 6E, exposure is performed with the right-side exposure pattern 111R for exposing the photoresist film 111 in such a manner that the width Mc" in the middle region SC is thinner than the width Me in the right-side region SR other than the middle region SC. FIG. 6C FIG. 6D In the second example embodiment, as illustrated in FIG. 6B, the pattern width on the photomask PML corresponding to the middle region SC is partially thinned. Therefore, as illustrated in FIG. 6C, exposure is performed with the left-side exposure pattern 111L for exposing the photoresist film 111 in such a manner that the width Mc' in the middle region SC is thinner than the width Md in the left-side region SL other than the middle region SC. Furthermore, in the second example embodiment, as illustrated in FIG. 6D, the pattern width on the photomask PMR corresponding to the middle region SC is partially thinned. Therefore, as illustrated in FIG. 6E, exposure is performed with the right-side exposure pattern 111R for exposing the photoresist film 111 in such a manner that the width Mc" in the middle region SC is thinner than the width Me in the right-side region SR other than the middle region SC.

[0110] Since exposure is performed doubly in the middle region SC, the width Mc of the latent image pattern in the middle region SC including the exposed portion 111LR formed on the photoresist film 111 can become greater than each of the width Mc' and the width MC" (Mc' & Mc" < Mc). Furthermore, if there is no influence of the above-mentioned diffracted light, acid, and misalignment, the relationship of Mc' & Mc" = Mc can be obtained.

[0111] Setting the width Mc' and the width Mc" to appropriate values enables adjustment of the exposure amount accumulated in the middle region SC and makes the width Mc of the latent image pattern in the middle region SC close to the widths Md and Me of the latent image pattern in the regions other than the middle region SC. Although the relationship of Mc = Md & Me is obtained in the present example, the relationship of Mc < Md & Me can be employed.

[0112] ​​The development process is performed on the photoresist film on which the latent image has been formed in the above-described manner, so that the resist pattern 111D is formed. The resist pattern 111D is formed in such a manner that the pattern size on the developed photoresist film in the middle region SC is close to the pattern size on the developed photoresist film in the regions other than the middle region SC. This means that the difference between the width Mc and the width Md becomes smaller than the difference between the width Mc" and the width Md (|Mc-Md| < |Mc"-Md|).

[0113] In the manufacturing method in the second exemplary embodiment, each of the widths Mc' and Mc" of the exposure portions 111Lc and 111Rc of the middle region SC, which is a double-exposure region, is set to be smaller than each of the width Md of the left-side region SL and the width Me of the right-side region SR, each of which is a single-exposure region. Thereby, compared to the first exemplary embodiment, the second exemplary embodiment can more appropriately prevent or reduce short-circuiting between adjacent patterns. Further, the second exemplary embodiment enables the width of the latent image pattern in the middle region SC including the exposure portions 111LR to be smaller than in the first exemplary embodiment, and is thus more advantageous in terms of miniaturization than the first exemplary embodiment.

[0114] <Third Exemplary Embodiment>

[0115] FIG. 7A to FIG. 7F A method for manufacturing the semiconductor device APR according to the third exemplary embodiment is illustrated. The semiconductor device APR in the third exemplary embodiment differs from the semiconductor device APR in each of the first exemplary embodiment and the second exemplary embodiment in the regions on the photoresist film 111 that are exposed. In the semiconductor device APR in the third exemplary embodiment, similar photomasks PML and PMR to those in the second exemplary embodiment can be used.

[0116] FIG. 7A A pattern on the photomask PML used when the left-side region SL is exposed is illustrated. FIG. 7B A left-side exposure pattern 111L used for exposing the photoresist film 111 is illustrated. FIG. 7C A pattern on the photomask PMR used when the right-side region SR is exposed is illustrated. FIG. 7D A right-side exposure pattern 111R used for exposing the photoresist film 111 is illustrated.

[0117] The third exemplary embodiment satisfies the relationship of Mc' & Mc" < Md & Me. The third exemplary embodiment satisfies the relationship of Ma & Mb < Mc' & Mc" ≤ Mc ≤ Md & Me. Further, the third exemplary embodiment satisfies the relationship of Wa & Wb < Wc' & Wc" < Wc ≤ Wd & We.

[0118] In the third exemplary embodiment, as illustrated in FIG. 6B, the pattern width on the photomask PML is partially thinned in the region corresponding to the middle region SC and in a part of the region corresponding to the left side region SL. Accordingly, as illustrated in FIG. 6C, exposure is performed with the left side exposure pattern 111L for exposing the photoresist film 111 in such a manner that the width Mc' in the middle region SC is thinner than the width Md in the left side region SL other than the middle region SC. Further, the end portion of the left side region SL on the side of the middle region SC is exposed with the width Mc'. Further, in the third exemplary embodiment, as illustrated in FIG. 6D, the pattern width on the photomask PMR is partially thinned in the region corresponding to the middle region SC and in a part of the region corresponding to the right side region SR. Accordingly, as illustrated in FIG. 6E, exposure is performed with the right side exposure pattern 111R for exposing the photoresist film 111 in such a manner that the width Mc" in the middle region SC is thinner than the width Me in the right side region SR other than the middle region SC. Further, the end portion of the right side region SR on the side of the middle region SC is exposed with the width Mc". As with the second exemplary embodiment, due to the influence of the double exposure in the middle region SC, it is possible to obtain the relationship of Mc' & Mc" < Mc. FIG. 7A FIG. 7B FIG. 7C FIG. 7D Further, in the third exemplary embodiment, the distance between the line B-B' and the line C-C' is different from that in the second exemplary embodiment. Under this relationship, setting the width Mc' and the width Mc" of the exposure pattern in the middle region SC to appropriate values also makes it possible to make the size of the latent image pattern in the middle region SC close to the size of the latent image pattern in the regions other than the middle region SC, as illustrated in FIG. 6F.

[0119] Further, in the third exemplary embodiment, the distance between the line B-B' and the line C-C' is different from that in the second exemplary embodiment. Under this relationship, setting the width Mc' and the width Mc" of the exposure pattern in the middle region SC to appropriate values also makes it possible to make the size of the latent image pattern in the middle region SC close to the size of the latent image pattern in the regions other than the middle region SC, as illustrated in FIG. 6F. FIG. 7E

[0120] <Fourth Exemplary Embodiment>

[0121] FIG. 8A to FIG. 8F A method for manufacturing a semiconductor device APR according to the fourth exemplary embodiment is illustrated. The semiconductor device APR in the fourth exemplary embodiment differs from the semiconductor device APR in each of the first exemplary embodiment, the second exemplary embodiment, and the third exemplary embodiment in the region exposed on the photoresist film 111. In the semiconductor device APR in the fourth exemplary embodiment, photomasks PML and PMR similar to those in the second exemplary embodiment can be used.

[0122] FIG. 8A A pattern on the photomask PML used when the left side region SL is exposed is illustrated. FIG. 8B ​​​​The left-side exposure pattern 111L used for exposing the photoresist film 111 is illustrated. FIG. 8C The pattern on the photomask PMR used when exposing the right-side region SR is illustrated. FIG. 8D The right-side exposure pattern 111R used for exposing the photoresist film 111 is illustrated.

[0123] The fourth exemplary embodiment satisfies the relationship of Mc' & Mc" < Md & Me. The fourth exemplary embodiment satisfies the relationship of Ma & Mb < Mc' & Mc" ≤ Mc ≤ Md & Me. Furthermore, the fourth exemplary embodiment satisfies the relationship of Wa & Wb < Wc ≤ Wd & We.

[0124] In the fourth exemplary embodiment, as illustrated in FIG. 6B, in the region corresponding to the end portion on the side of the right-side region SR of the middle region SC, the pattern width on the photomask PML is partially thinned. Therefore, as illustrated in FIG. 6B, exposure is performed with the left-side exposure pattern 111L used for exposing the photoresist film 111 in such a manner that the width Mc' of the middle region SC on the side of the right-side region SR is thinner than the width Md in the left-side region SL other than the middle region SC. FIG. 8A FIG. 8B In the fourth exemplary embodiment, as illustrated in FIG. 6B, in the region corresponding to the end portion on the side of the right-side region SR of the middle region SC, the pattern width on the photomask PML is partially thinned. Therefore, as illustrated in FIG. 6B, exposure is performed with the left-side exposure pattern 111L used for exposing the photoresist film 111 in such a manner that the width Mc' of the middle region SC on the side of the right-side region SR is thinner than the width Md in the left-side region SL other than the middle region SC. FIG. 8C FIG. 8D In the fourth exemplary embodiment, as illustrated in FIG. 6B, in the region corresponding to the end portion on the side of the right-side region SR of the middle region SC, the pattern width on the photomask PML is partially thinned. Therefore, as illustrated in FIG. 6B, exposure is performed with the left-side exposure pattern 111L used for exposing the photoresist film 111 in such a manner that the width Mc' of the middle region SC on the side of the right-side region SR is thinner than the width Md in the left-side region SL other than the middle region SC.

[0125] Furthermore, in the fourth exemplary embodiment, the distance between the line B-B' and the line C-C' is different from that in the second exemplary embodiment. Under this relationship, setting the width Mc' and the width Mc" of the exposure pattern in the middle region SC to appropriate values also enables the size of the latent image pattern in the middle region SC to be close to the size of the latent image pattern in the region other than the middle region SC, as illustrated in FIG. 6B. Furthermore, in the fourth exemplary embodiment, the width Mc' of the middle region SC on the side of the right-side region SR is thinner than the width Md in the left-side region SL other than the middle region SC, and the width Mc" of the middle region SC on the side of the left-side region SL is thinner than the width Me in the right-side region SR other than the middle region SC. Therefore, the size of the latent image pattern in the middle region SC is close to the size of the latent image pattern in the region other than the middle region SC, as illustrated in FIG. 6B. FIG. 8E FIG. 8E In the fourth exemplary embodiment, as illustrated in FIG. 6B, in the region corresponding to the end portion on the side of the right-side region SR of the middle region SC, the pattern width on the photomask PML is partially thinned. Therefore, as illustrated in FIG. 6B, exposure is performed with the left-side exposure pattern 111L used for exposing the photoresist film 111 in such a manner that the width Mc' of the middle region SC on the side of the right-side region SR is thinner than the width Md in the left-side region SL other than the middle region SC. FIG. 8E ​​​The case where the relationship Ma & Mb < Mc' & Mc" < Mc < Md & Me is obtained is illustrated, but the width Mc can be formed equal to each of the width Md and the width Me to obtain the relationship Wc = Wd && We. In this case, a portion thicker than each of the width Md and the width Me can be formed near the line B-B' and near the line C-C' which are end portions of the intermediate region SC.

[0126] <the fifth exemplary embodiment>

[0127] FIG. 9A to FIG. 9F A method for manufacturing a semiconductor device APR according to the fifth exemplary embodiment is illustrated. The semiconductor device APR in the fifth exemplary embodiment differs from the semiconductor device APR in each of the first exemplary embodiment, the second exemplary embodiment, the third exemplary embodiment, and the fourth exemplary embodiment in the region exposed on the photoresist film 111. In the semiconductor device APR in the fifth exemplary embodiment, similar photomasks PML and PMR to those in the second exemplary embodiment can be used.

[0128] The fifth exemplary embodiment satisfies the relationship Mc' & Mc" < Md & Me. The fifth exemplary embodiment satisfies the relationship Ma & Mb < Mc' & Mc" ≤ Mc < Md & Me or the relationship Ma & Mb < Mc' & Mc" < Md & Me < Mc. Further, the fifth exemplary embodiment satisfies the relationship Wa & Wb < Wc < Wd & We or the relationship Wa & Wb < Wd & We < Wc.

[0129] The fifth exemplary embodiment is directed to a case where misalignment has occurred between the photomasks for the left-side region SL and the right-side region SR in the second exemplary embodiment. FIG. 9E The case where the right-side exposure shot R has been exposed downward with respect to the left-side exposure shot L in the FIG. 9E The state where exposure has been performed.

[0130] In the fifth exemplary embodiment, the width Md is made larger than the width Ma so that it is possible to prevent or reduce the breakage of the wiring 110 in the intermediate region SC even when misalignment occurs between the photomasks in the manner mentioned above. Additionally, in the left-side region SL and the right-side region SR where there is no influence of the misalignment of the photomask, it is possible to form a fine pattern having the width Ma and the width Mb.

[0131] Further, in the FIG. 9Efrom the illustration, regions in which a latent image is not formed only by the left-side exposure shot L or only by the right-side exposure shot R and in which a latent image is formed due to the influence of acid or double exposure due to diffracted light, such as those mentioned above, are omitted. In the fifth exemplary embodiment, a region in which a latent image can be formed due to the influence of acid generated in a double exposure region is located outside the exposure portion 111Lc and the exposure portion 111Rc. Also, in the fifth exemplary embodiment, due to misalignment occurring between the photomasks for the left-side region SL and the right-side region SR, the area of a double exposure region becomes smaller in the middle region SC compared to a case in which there is no misalignment between the photomasks, so the amount of exposure accumulated in the double exposure region decreases. Therefore, the amount of acid generated in the double exposure region decreases. Also, the area of a region in which double exposure is performed using diffracted light due to the left-side exposure shot L and diffracted light due to the right-side exposure shot R decreases. These effects can make the width of a latent image pattern in the middle region SC finer compared to a case in which there is no misalignment between the photomasks for the left-side region SL and the right-side region SR. FIG. 9E

[0132]

[0133]

[0134] <Sixth Exemplary Embodiment>

[0135] The sixth exemplary embodiment can be applied to any one of the first exemplary embodiment to the fifth exemplary embodiment. FIG. 11A The sixth exemplary embodiment is illustrated in FIG. 12. In the sixth exemplary embodiment, the photomask 110L for the left-side region SL and the photomask 110R for the right-side region SR are misaligned in the vertical direction in the middle region SC. The sixth exemplary embodiment is different from the fifth exemplary embodiment in that the photomask 110L for the left-side region SL and the photomask 110R for the right-side region SR are misaligned in the middle region SC. FIG. 1C ​​​The diagram shows an enlarged view of lines A-A', B-B', and C-C' within range S of the device area DR, and the relationship between these lines and wiring 110. In this way, for example, lines A-A', B-B', and C-C' can be bent according to the pattern in a way that avoids the pattern.

[0136] FIG. 11B The diagram illustrates the relationship between and FIG. 11A The same wiring 110 shown in the diagram treats lines A-A', B-B', and C-C' as straight lines. FIG. 11B In the scenario illustrated, pattern P1 crosses line A-A' but does not reach line B-B'. In this case, the amount of exposure accumulated in the double exposure region is compared between pattern P1 and pattern P2, which crosses line A-A' and extends to the right-hand region across line B-B'. Assume the linewidth of pattern P1 is represented by LP1, the double exposure region of pattern P1 by E1, the linewidth of pattern P2 by LP2, and the double exposure region of pattern P2 by E2. Even if the linewidths LP1 and LP2 are equal, the areas of regions E1 and E2 are different. Therefore, the amount of exposure accumulated in the double exposure region between patterns P1 and P2 can be different, resulting in different linewidths in the double exposure region between patterns P1 and P2. FIG. 11A The diagram shows that lines A-A', B-B', and C-C' are zigzagged to avoid pattern P1, thus eliminating the need to divide pattern P1 into portions for a photomask used for exposure on the left region SL and a portion for exposure on the right region SR.

[0137] <Seventh Exemplary Example>

[0138] FIG. 11C and FIG. 11D This is a cross-sectional view of a semiconductor device APR manufactured by the manufacturing method in the seventh exemplary embodiment. FIG. 2A and FIG. 2B This is a plan view of a semiconductor device APR manufactured by the manufacturing method in the seventh exemplary embodiment. FIG. 11C and FIG. 11D A cross-section of the semiconductor device APR in the seventh exemplary embodiment is illustrated. FIG. 11C The diagram illustrates along FIG. 2A and FIG. 2B The cross section cut by the dividing center line A-A' shown in the diagram. FIG. 11D The diagram shows a cross-section of the area located far from the dividing center line A-A'.

[0139] The semiconductor device APR includes a silicon layer serving as a semiconductor layer 100, and an element functional layer (not shown) in which, for example, a photoelectric conversion section, a transistor, and an isolation structure are formed is formed on the semiconductor layer 100.

[0140] The element functional layer can be formed by split exposure, or can be formed by single exposure using an exposure device having a maximum exposure area that widens in the case of resolution reduction. Further, such split exposure and single exposure can be selectively used depending on the degree of miniaturization in a plurality of photolithography processes required to form the element functional layer.

[0141] On the element functional layer, an interlayer insulating film 101 made of silicon oxide is formed, and a contact plug made of tungsten is formed in the interlayer insulating film 101. Then, on the interlayer insulating film 101, a first insulator film 103 made of silicon carbide and a second insulator film 104 made of silicon oxide serving as an interlayer insulating film are formed. A wiring 110 made of copper is formed in the second insulator film 104 serving as an interlayer insulating film and the first insulator film 103.

[0142] As FIG. 11C illustrated in FIG. 11D illustrated in

[0143] <Eighth Exemplary Embodiment>

[0144] FIG. 12 A device 9191 including a semiconductor device 930 is illustrated. The eighth exemplary embodiment can be applied to any one of the first exemplary embodiment to the seventh exemplary embodiment. FIG. 12 is a schematic view illustrating a device 9191 including the semiconductor device 930 according to the present exemplary embodiment. The device 9191 including the semiconductor device 930 is described in detail. The semiconductor device 930 has characteristics in the structure and / or the manufacturing method described above with respect to the semiconductor device APR. The semiconductor device 930 includes a central portion 901 in which a circuit unit 900 is arranged, and a peripheral portion 902 located around the central portion 901. The pixel portion 11 described with reference to FIG. 1A The pixel portion 11 described with reference to FIG. 1AThe signal processing circuit 12 described is provided in the peripheral portion 902. The semiconductor device 930 includes a semiconductor device portion 910, and the semiconductor device portion 910 includes the semiconductor layer 100 included in the semiconductor device APR. The semiconductor device 930 can include, in addition to the semiconductor device portion 910 including the semiconductor layer 100, a package 920 in which the semiconductor device portion 910 is housed. The package 920 can include a base to which the semiconductor device portion 910 is fixed, and a cover such as a glass film facing the semiconductor device portion 910. The package 920 can also include a bonding member such as a bonding wire or a bump that interconnects a terminal provided in the base and a terminal provided in the semiconductor device portion 910.

[0145] The device 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, an image device 970, a storage device 980, and a mechanical device 990. The optical device 940 is associated with the semiconductor device 930. The optical device 940 includes, for example, a lens, a shutter, a mirror, and a filter. The control device 950 controls the semiconductor device 930. The control device 950 is a semiconductor device such as an application specific integrated circuit (ASIC).

[0146] The processing device 960 processes a signal that has been output from the semiconductor device 930 or a signal to be input to the semiconductor device 930. The processing device 960 is a semiconductor device such as a central processing unit (CPU) or an ASIC for configuring an analog front end (AFE) or a digital front end (DFE).

[0147] The image device 970 is an electroluminescence (EL) display device or a liquid crystal display device for displaying information (image) obtained by the semiconductor device 930 in a case where the semiconductor device 930 is an opto-electric conversion device (imaging device). The image device 970 can be an opto-electric conversion device (imaging device) for capturing an image to be displayed on the semiconductor device 930 in a case where the semiconductor device 930 is a display device.

[0148] The storage device 980 is a magnetic device or a semiconductor device portion for storing information (image) processed by the semiconductor device 930. The storage device 980 is a volatile memory such as a static random access memory (SRAM) or a dynamic random access memory (DRAM), or a non-volatile memory such as a flash memory or a hard disk drive.

[0149] The mechanical device 990 includes a moving portion or a propulsion portion such as a motor or an engine. The device 9191 displays a signal output from the semiconductor device 930 on the image device 970 or transmits a signal output from the semiconductor device 930 to the outside via a communication device (not illustrated) included in the device 9191. For such a reason, it is advantageous that the device 9191 includes the storage device 980 and the processing device 960 in addition to a storage circuit or a calculation circuit included in the semiconductor device 930. The mechanical device 990 can be configured to be controlled on the basis of a signal output from the semiconductor device 930.

[0150] Further, the device 9191 is suitable for an electronic device such as an information terminal (for example, a smartphone or a wearable terminal) having an image capturing function or a camera (for example, a lens-interchangeable camera, a compact camera, a video camera, or a monitoring camera). The mechanical device 990 in the camera can drive components of the optical device 940 to perform zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can drive the semiconductor device 930 to perform image stabilization operation.

[0151] Further, the device 9191 can be a transport device such as a vehicle, a ship or a vessel, or an aircraft. The mechanical device 990 in the transport device can be used as a moving device. The device 9191 used as the transport device is suitable for a device for transporting the semiconductor device 930 or a device for assisting or automating driving (steering) using an image capturing function. The processing device 960 for assisting or automating driving (steering) can perform processing for operating the mechanical device 990 used as the moving device on the basis of information obtained by the semiconductor device 930. Alternatively, the device 9191 can be medical equipment such as an endoscope, measurement equipment including a range-finding sensor, analysis equipment including an electron microscope, or office equipment including a copier or a printer.

[0152] According to the above-described example embodiments, it is possible to form superior wiring. Thus, it is possible to improve the value of the semiconductor device. The improvement of the value as mentioned herein refers to at least one of addition of a function, improvement of performance, improvement of characteristics, improvement of reliability, improvement of manufacturing yield, reduction of environmental load, reduction of cost, reduction of size, and reduction of weight.

[0153] Therefore, use of the semiconductor device 930 according to the present exemplary embodiment for the device 9191 also makes it possible to improve the value of the device 9191. For example, when the semiconductor device 930 is installed on a transport device to be used to perform image capturing outside the transport device or measure its external environment, superior performance can be achieved. Therefore, in manufacturing and selling a transport device, it is advantageous to determine to install the semiconductor device according to the present exemplary embodiment on the transport device in terms of improving the performance of the transport device itself. In particular, the semiconductor device 930 is suitable for a transport device that performs driving assistance and / or automated driving of the transport device using information obtained by the semiconductor device.

[0154] [Example 1]

[0155] Example 1 is described in which the manufacturing method uses an exposure device that uses a wavelength of 193 nm with an ArF light source and a maximum exposure area of 26 mm x 33 mm to form the wiring 110. In Example 1, in the configuration illustrated in FIG. 5A to FIG. 5F Example 1, each of the width Ma and the width Mb is set to 120 nm, each of the width Mc’ and the width Mc” is set to 230 nm, and each of the width Md and the width Me is set to 230 nm. Further, the length of the portion exposed with each of the width Mc’ and the width Mc” (i.e., the length from the line B-B’ to the line C-C’) is set to 200 nm. Further, the length of the portion exposed with each of the width Md and the width Me is set to 200 nm. This corresponds to the row i) illustrated in FIG. 10A and FIG. 10B This makes it possible to form the wiring 110 in which each of the width Wa and the width Wb is 120 nm, the width Wc is 290 nm, and each of the width Wd and the width We is 230 nm. This corresponds to the row i) illustrated in FIG. 10C Example 1.

[0156] Here, FIG. 2B each of the distance Da and the distance Db is 120 nm, and the distance Dc is 170 nm. Further, as in the configuration illustrated in FIG. 9A to FIG. 9F Example 5, misalignment in the Y direction can occur between the photomask PML and the photomask PMR. Further, misalignment in the X direction illustrated in FIG. 2A Example 5 can also occur between the photomask PML and the photomask PMR. If the amount of misalignment is as high as 60 nm, it is highly likely that neither disconnection nor short-circuiting occurs in the wiring Q1, the wiring Q2, and the wiring Q3 even when misalignment in the Y direction illustrated in FIG. 2A Example 5 occurs between the photomask PML and the photomask PMR.

[0157] When an misalignment of 60 nm occurs in the Y direction illustrated in FIG. 2A , the distance Dc illustrated in FIG. 2B becomes 120 nm. If the misalignment amount is greater than this, the distance Dc illustrated in FIG. 2B becomes less than FIG. 2B Each of the distance Da and the distance Db illustrated in FIG. 2B becomes very likely to occur a short circuit in the portion associated with the distance Dc illustrated in

[0158] In the present example, the length of each of the portions exposed with the width Md and the width Me is set to 200 nm. Therefore, even in a case where an misalignment has occurred in the X direction illustrated in FIG. 2A , the area of the double-exposed region has changed, and the exposure amount accumulated in the double-exposed region has changed between the photomask PML and the photomask PMR, it is possible to reduce such an influence up to the region exposed with the width Ma and the width Mb.

[0159] [Example 2]

[0160] Example 2 is described in which the manufacturing method uses an exposure apparatus with a wavelength of 193 nm using an ArF light source and a maximum exposure region of 26 mm x 33 mm to form the wiring 110. In Example 2, in the configuration illustrated in FIG. 6A to FIG. 6F , each of the width Ma and the width Mb is set to 120 nm, each of the width Mc’ and the width Mc” is set to 180 nm, and each of the width Md and the width Me is set to 230 nm. Further, the length of the portion exposed with each of the width Mc’ and the width Mc” (i.e., the length from the line B-B’ to the line C-C’) is set to 200 nm. Further, the length of the portion exposed with each of the width Md and the width Me is set to 200 nm. This corresponds to FIG. 10A and FIG. 10B line ii) illustrated in . This makes it possible to form the wiring 110 in which each of the width Wa and the width Wb is 120 nm and each of the width Wc, the width Wd, and the width We is 230 nm. This corresponds to FIG. 10C line ii) illustrated in . Here, FIG. 2B each of the distance Da and the distance Db illustrated in is 120 nm, and the distance Dc is 230 nm. Further, as in the configuration illustrated in FIG. 9A to FIG. 9F as a fifth example embodiment, an misalignment can occur in the Y direction between the photomask PML and the photomask PMR. Further, an misalignment can also occur in the FIG. 2AAn misalignment occurs in the Y direction illustrated in FIG. 6. If the misalignment amount is as large as 95 nm, it is highly likely that a short circuit occurs in the portion associated with the distance Dc illustrated in FIG. 6. FIG. 2A When an misalignment occurs in the Y direction illustrated in FIG. 6 between the photomask PML and the photomask PMR,

[0161] When an misalignment occurs in the Y direction illustrated in FIG. 6 between the photomask PML and the photomask PMR, FIG. 2A When an misalignment of 95 nm occurs in the Y direction illustrated in FIG. 6, FIG. 2B The distance Dc illustrated in FIG. 6 becomes 120 nm. If the misalignment amount is larger than this, a short circuit is highly likely to occur in the portion associated with the distance Dc illustrated in FIG. 6. FIG. 2B The distance Dc illustrated in FIG. 6 becomes smaller than FIG. 2B Each of the distance Da and the distance Db illustrated in FIG. 6 is set so that a short circuit is highly likely to occur in the portion associated with the distance Dc illustrated in FIG. 6. FIG. 2B The distance Dc illustrated in FIG. 6 becomes 120 nm. If the misalignment amount is larger than this, a short circuit is highly likely to occur in the portion associated with the distance Dc illustrated in FIG. 6.

[0162] In the present example, the length of each of the portions exposed with the width Md and the width Me is set to 200 nm. Therefore, even in the case where an misalignment has occurred in the X direction illustrated in FIG. 6 between the photomask PML and the photomask PMR, the area of the double-exposed region has changed, and the exposure amount accumulated in the double-exposed region has changed, it is possible to reduce the influence of this to the region exposed with the width Ma and the width Mb. FIG. 2A

[0163] [Example 3]

[0164] Example 3 is described in which the manufacturing method uses an exposure apparatus with a wavelength of 248 nm using a KrF light source and a maximum exposure region of 26 mm x 33 mm to form the wiring 110. In Example 3, in the configuration illustrated in FIG. 6 as the second exemplary embodiment, FIG. 6A to FIG. 6F Each of the width Ma and the width Mb is set to 140 nm, each of the width Mc’ and the width Mc” is set to 180 nm, and each of the width Md and the width Me is set to 240 nm in the configuration illustrated in FIG. 6. Furthermore, the length of the portion exposed with each of the width Mc’ and the width Mc” (i.e., the length from the line B-B’ to the line C-C’) is set to 300 nm. Furthermore, the length of the portion exposed with each of the width Md and the width Me is set to 150 nm. This corresponds to FIG. 10A and FIG. 10B line ii) illustrated in FIG. 6. This makes it possible to form the wiring 110 in which each of the width Wa and the width Wb is 140 nm and each of the width Wc, the width Wd, and the width We is 240 nm. This corresponds to FIG. 10C line ii) illustrated in FIG. 6. Here, FIG. 2B ​Each of the distances Da and Db illustrated in the middle is 140 nm, and the distance Dc is 240 nm. Furthermore, as in the configuration illustrated in FIG. 9A to FIG. 9F As in the configuration illustrated in the middle, misalignment can occur in the Y direction between the photomask PML and the photomask PMR. Furthermore, misalignment can also occur in the FIG. 2A X direction between the photomask PML and the photomask PMR. If the amount of misalignment is up to 80 nm, it is highly likely that even when misalignment occurs in the FIG. 2A Y direction between the photomask PML and the photomask PMR, neither disconnection nor short-circuiting occurs in the wiring Q1, the wiring Q2, and the wiring Q3.

[0165] When misalignment of 80 nm occurs in the Y direction between the photomask PML and the photomask PMR, FIG. 2A the distance Dc illustrated in the middle becomes 140 nm. If the amount of misalignment is greater than this, the distance Dc becomes less than FIG. 13A the distance Dc illustrated in the middle. If the amount of misalignment is greater than this, the distance Dc becomes less than FIG. 13C the distance Dc illustrated in the middle. If the amount of misalignment is greater than this, the distance Dc becomes less than FIG. 13B Each of the distances Da and Db illustrated in the middle is set so that disconnection does not occur in the portion associated with the distance Dc illustrated in the middle. FIG. 13C It becomes highly likely that short-circuiting occurs in the portion associated with the distance Dc illustrated in the middle.

[0166] In the present example, the length of each of the portions exposed with the width Md and the width Me is set to 150 nm. Therefore, even in the case where misalignment has occurred in the X direction between the photomask PML and the photomask PMR, the area of the double-exposed region has changed, and the exposure amount accumulated in the double-exposed region has changed, it is possible to reduce the influence thereof up to the regions exposed with the width Ma and the width Mb. FIG. 13A

[0167] [Example 4]

[0168] Example 4 is described in which the manufacturing method uses an exposure apparatus with a wavelength of 193 nm using an ArF light source and a maximum exposure region of 26 mm x 33 mm to form the wiring 110. In Example 4, the configuration illustrated in the middle as the second exemplary embodiment is used. FIG. 13B In the configuration illustrated in the middle as the fifth exemplary embodiment, each of the width Ma and the width Mb is set to 120 nm, each of the width Mc’ and the width Mc” is set to 120 nm, and each of the width Md and the width Me is set to 230 nm. Furthermore, the length of the portion exposed with each of the width Mc’ and the width Mc” (i.e., the length from the line B-B’ to the line C-C’) is set to 200 nm. Furthermore, the length of the portion exposed with each of the width Md and the width Me is set to 200 nm. This corresponds to FIG. 13C and​FIG. 13A Line iii) illustrated in FIG. 12. This makes it possible to form a wiring 110 in which each of the width Waand the width Wb is 120 nm, the width Wcis 160 nm, and each of the width Wdand the width Weis 230 nm. This corresponds to FIG. 13C Line iii) illustrated in FIG. 12. Here, FIG. 14A Each of the distance Daand the distance Dbis 120 nm, and the distance Dcis 300 nm, in the configuration illustrated in FIG. 12. Furthermore, as in the configuration illustrated in FIG. 11 as the fourth exemplary embodiment, FIG. 14B As in the configuration illustrated in FIG. 12 as the fifth exemplary embodiment, misalignment in the Y direction can occur between the photomask PML and the photomask PMR. Furthermore, misalignment in the FIG. 19A As in the configuration illustrated in FIG. 12, misalignment in the X direction can occur between the photomask PML and the photomask PMR. If the amount of misalignment is as high as 120 nm, it is highly likely that even when misalignment in the FIG. 19B As in the configuration illustrated in FIG. 12, misalignment in the Y direction can occur between the photomask PML and the photomask PMR. If the amount of misalignment is as high as 120 nm, it is highly likely that even when misalignment in the

[0169] As in the configuration illustrated in FIG. 12, misalignment in the Y direction can occur between the photomask PML and the photomask PMR. If the amount of misalignment is as high as 120 nm, it is highly likely that even when misalignment in the FIG. 19A When misalignment in the Y direction as illustrated in FIG. 12 of 120 nm or more occurs between the photomask PML and the photomask PMR, the exposure portion 111Lc and the exposure portion 111Rc become non-overlapping with each other, so that it becomes highly likely that disconnection occurs in the wiring Q1, the wiring Q2, and the wiring Q3.

[0170] <First Exemplary Embodiment>

[0171] In the following description, the first exemplary embodiment is described. Furthermore, in the following description and the drawings, constituent elements common to each other among the drawings are assigned corresponding identical reference numerals. Therefore, the constituent elements common to each other are described by cross-referencing the drawings, and the description of the constituent elements assigned with corresponding identical reference numerals is not repeated as appropriate.

[0172] FIG. 14A An opto-electric conversion device as an example of a semiconductor device APR is illustrated. The opto-electric conversion device is, for example, a complementary metal-oxide semiconductor (CMOS) image sensor, and can be used for, for example, an imaging device, a distance measuring device, or an illuminance measuring device. The semiconductor device APR used as the opto-electric conversion device is a semiconductor device in which a plurality of wirings 110 each having a damascene structure (a wiring 110a, a wiring 110b, a wiring 110c, a wiring 110d, and a wiring 110e) are arranged in parallel. FIG. 14B) provided on the semiconductor layer 100. The semiconductor device APR includes a pixel portion 11 in which unit pixels each including a photoelectric conversion element are arranged two-dimensionally in m rows and n columns, and a signal processing circuit 12 formed around the pixel portion 11. The semiconductor device APR has a size larger than or equal to a maximum exposure region of an exposure apparatus (an exposure machine), and cannot be manufactured by single exposure with such an exposure apparatus. Therefore, the semiconductor device APR is manufactured by a split exposure technique in which a device region is divided into a left side region and a right side region adjacent to each other, and exposure is performed on the left side region and the right side region individually. For example, a wiring layer can be formed by split exposure. In the following description, a direction toward a central portion of the semiconductor device APR on a plane thereof is referred to as an inner periphery side, and a direction opposite to the inner periphery side is referred to as an outer periphery side.

[0173] FIG. 19B is a plan view illustrating a plurality of device regions DR formed on a wafer WF. Each device region DR has a size larger than a maximum exposure region of an exposure apparatus. Each device region DR is divided into regions each having a size smaller than or equal to the maximum exposure region of the exposure apparatus, and is formed by split exposure in which exposure is performed on the respective regions individually.

[0174] FIG. 19A is a conceptual view illustrating one device region DR. The device region DR is divided into at least a left side region SL and a right side region SR with respect to a line A-A’ serving as a baseline, and the left side region SL and the right side region SR are exposed with respective different photomasks. Hereinafter, the line A-A’ is sometimes referred to as a “split center line”. The left side region SL is defined by a region extending from a left end to a line C-C’, and the right side region SR is defined by a region extending from a right end to a line B-B’. Hereinafter, the line C-C’ is sometimes referred to as a “right end of the left side region”, and the line B-B’ is sometimes referred to as a “left end of the right side region”. An intermediate region SC located between the line B-B’ and the line C-C’ can be exposed when the left side region SL is exposed, and can also be exposed when the right side region SR is exposed. In this way, since exposure is repeated on the intermediate region SC, the intermediate region SC can also be referred to as a “repeated region”. Furthermore, although the device region DR is divided into two regions in the description of the present exemplary embodiment, the split number can be three or more. Furthermore, although the device region DR is divided into a left side region and a right side region in the following example, the split direction is optional, and thus can be divided into an upper side region and a lower side region.

[0175] FIG. 19B The semiconductor device APR illustrated in FIG. 6A is formed in a state in which a plurality of device regions DR are divided as described above. FIG. 14AThe semiconductor device APR is arranged two-dimensionally on the wafer WF, subjected to additional manufacturing processes, and then divided into individual semiconductor device portions (dies) by cutting (die cutting). The semiconductor device APR includes at least the semiconductor device portions (dies) thus formed. As described below, the semiconductor device APR can include a package in which the semiconductor device portions are housed, in addition to the semiconductor device portions.

[0176] FIG. 19A The size of the device region DR of the semiconductor device APR manufactured by the manufacturing method in the present exemplary embodiment is illustrated. The length W1 in the vertical direction of the semiconductor device APR is 33 mm or less, and the length W2 in the horizontal direction thereof is greater than 33 mm. For example, the length W1 in the vertical direction of the device region DR is 32 mm, and the length W2 in the horizontal direction thereof is 42 mm. Therefore, a maximum exposure region of an exposure apparatus of 26 mm x 33 mm cannot perform single exposure on the device region DR.

[0177] The distance W2L between the reference line A-A' (which divides the device region DR into the left side region SL and the right side region SR with respect to the reference line A-A') and the left end portion of the device region DR is set to 26 mm or less, for example, 21 mm. Further, the distance W2R between the reference line A-A' and the right end portion of the device region DR is set to 26 mm or less, for example, 21 mm. Further, the distance W3 between the line A-A' and the line B-B' is set to 10 nm to 1000 nm, advantageously 50 nm to 500 nm, for example, 100 nm. Further, the distance W4 between the line A-A' and the line C-C' is set to 10 nm to 1000 nm, advantageously 50 nm to 500 nm, for example, 100 nm.

[0178] Since the length W1 is 33 mm or less and the sum of the distance W2L and the distance W3 is 26 mm or less, the left side region SL and the middle region SC can be exposed by the exposure apparatus whose maximum exposure region is 26 mm x 33 mm.

[0179] Further, since the length W1 is 33 mm or less and the sum of the distance W2R and the distance W4 is 26 mm or less, the right side region SR and the middle region SC can be exposed by the exposure apparatus whose maximum exposure region is 26 mm x 33 mm.

[0180] Therefore, the semiconductor device APR whose length W1 is 33 mm or less and whose length W2 is greater than 33 mm can be exposed with the exposure apparatus whose maximum exposure region is 26 mm x 33 mm and in the case where the division number of the device region DR is set to "2".

[0181] In this example, the distance W2L and the distance W2R are set to be equal to each other, but the distance W2L and the distance W2R need not be equal to each other. Further, each of the line A-A', the line B-B', and the line C-C' is set to be a straight line, but it can be set to be a meandering line within a range in which the sum of the distance W21 and the distance W3 does not exceed the maximum exposure area, depending on the pattern in the device region.

[0182] Since, in an exposure apparatus whose maximum exposure area is 26 mm x 33 mm, the resolution of the edge portion of the maximum exposure area can be lower than that of the central portion in some cases, the following case can occur: the exposure apparatus whose maximum exposure area is 26 mm x 33 mm performs exposure using substantially only a portion of the maximum exposure area. In this case, the split exposure can be applied to a semiconductor device APR having a size smaller than 26 mm x 33 mm as well. In other words, the size of the semiconductor device APR to which the split exposure in the present example embodiment is applied is not particularly limited.

[0183] In the case of an image sensor of a full-size standard called 35 mm, FIG. 14A The size of the pixel portion 11 illustrated in FIG. 6 is 36 mm ± 1 mm x 24 mm ± 1 mm. In the case of an image sensor of a full-size standard called 35 mm, FIG. 14AIn the semiconductor device APR, a row wiring of the pixel section 11 among the plurality of wirings 110 is illustrated. The row wiring is a global wiring commonly connected to the pixel group included in one pixel row. The row wiring is, for example, a signal line via which an input signal (control signal) is transmitted to the pixel group included in one pixel row. Further, the row wiring is, for example, a power line via which power (power supply potential or ground potential) is supplied to the pixel group included in one pixel row. Further, the column wiring is a global wiring intersecting the row wiring and commonly connected to the pixel group included in one pixel column. The row wiring and the column wiring need to extend at least from one end of the pixel section 11 to the other end thereof. Thus, the distance from one end of the row wiring to the other end thereof can need to be a length greater than or equal to the horizontal width (36 mm ± 1 mm) of the pixel section 11, and the distance from one end of the column wiring to the other end thereof can need to be a length greater than or equal to the vertical width (24 mm ± 1 mm) of the pixel section 11. The column wiring is, for example, a signal line via which an output signal (pixel signal) from the pixel group included in one pixel column is transmitted. Further, the column wiring is, for example, a power line via which power (power supply potential or ground potential) is supplied to the pixel group included in one pixel column. These row wirings and column wirings can be assigned to any one of the first wiring layer, the second wiring layer, the third wiring layer, and the fourth wiring layer arranged in order closer to the semiconductor layer 100. The first wiring layer can have a single damascene structure, and the second wiring layer, the third wiring layer, and the fourth wiring layer can have a dual damascene structure. For example, the power line serving as a global wiring (column wiring) can be arranged in the first wiring layer and / or the second wiring layer. For example, the signal line serving as a global wiring (row wiring) can be arranged in one of the third wiring layer and the fourth wiring layer (typically, the third wiring layer). For example, the signal line serving as a global wiring (column wiring) can be arranged in the other of the third wiring layer and the fourth wiring layer (typically, the fourth wiring layer). In addition, a local wiring is arranged in each wiring layer, and particularly, a number of local wirings can be arranged in the first wiring layer. Although an example in which four wiring layers are present has been described here, for example, the second wiring layer can be omitted and the local wirings and the power line can be arranged in the first wiring layer. Although the assignment of global lines to the wiring layers is not limited to the above-mentioned assignment, in view of these relationships, a wiring having a length exceeding 33 mm can be a power line (row wiring) having a single damascene structure or a signal line (row wiring) having a dual damascene structure.

[0184] FIG. 19A and FIG. 19B is a plan view of the semiconductor device APR in the present exemplary embodiment. FIG. 14A and FIG. 14A is a cross-sectional view of the semiconductor device APR in the present exemplary embodiment. FIG. 19A is a plan view of the semiconductor device APR in the present exemplary embodiment. FIG. 19Band FIG. 14B A cross section taken at the center split line A-A' is illustrated in FIG. 6B. FIG. 14A A cross section of a region positioned away from the center split line A-A' is illustrated in FIG. 6C. The semiconductor device APR includes a silicon layer serving as a semiconductor layer 100, and on the semiconductor layer 100, an element functional layer (not illustrated) in which, for example, a photoelectric conversion section, a transistor, and an isolation structure are formed is formed. The element functional layer can be formed with a split exposure, or can be formed with a single exposure using an exposure apparatus having a maximum exposure area that widens in the case of resolution reduction. Further, such a split exposure and a single exposure can be selectively used depending on the degree of miniaturization in a plurality of photolithography processes required to form the element functional layer. On the element functional layer, an interlayer insulating film 101 made of silicon oxide is formed, and a contact plug made of tungsten is formed in the interlayer insulating film 101. Then, on the interlayer insulating film 101, a first insulator film 103 made of silicon carbide and a second insulator film 104 made of silicon oxide serving as an interlayer insulating film are formed. A wiring 110 made of copper is formed in the second insulator film 104 serving as an interlayer insulating film and the first insulator film 103. As illustrated in FIG. 6C, the wiring 110 includes a portion of the wiring 110 formed on the middle region SC at a pitch Dc and with a width Wc. Further, as illustrated in FIG. 6C, the wiring 110 includes a portion of the wiring 110 formed in each of the left side region SL and the right side region SR at a pitch Dh and with a width Wh. Here, the width Wc is greater than the width Wh, and the pitch Dc is greater than the pitch Dh, but the present exemplary embodiment is not limited thereto. FIG. 14B FIG. 14B

[0185] FIG. 14B is a plan view of a plurality of wirings 110 in the semiconductor device APR. Each of the wirings Q1, Q2, and Q3 has a damascene structure. The wiring Q1 is adjacent to the wiring Q2, and the wiring Q2 is adjacent to the wiring Q3. A distance between one end Ea of the wiring Q2 and the other end Eb thereof is greater than 33 mm. As mentioned above, the distance between the one end Ea of the wiring Q2 and the other end Eb thereof can be 36 mm ± 1 mm or more. Although the one end Ea of the wiring Q2 and the other end Eb thereof have been described here, the same applies to the one end Ea and the other end Eb of each of the wiring Q1 and the wiring Q3.

[0186] ​​Each of the wirings Q1, Q2, and Q3 includes a portion Ph, a portion Pm, and a portion Pc located between the portion Ph and the portion Pm in a direction in which the wirings Q1, Q2, and Q3 extend. Here, the portion Ph and the portion Pm are disposed in such a manner that a distance between the portion Ph and the portion Pm is greater than 33 mm. In each of the wirings Q1, Q2, and Q3, a width Wmax of the portion Pc is a maximum width of each of the wirings Q1, Q2, and Q3 in a range from the portion Ph to the portion Pm. Each of the wirings Q1, Q2, and Q3 can include a portion (not illustrated) having a width Wmax' exceeding the width Wmax of the portion Pc outside the range from the portion Ph to the portion Pm. Thus, the maximum width Wmax' of each of the wirings Q1, Q2, and Q3 in the entirety of each of the wirings Q1, Q2, and Q3 can be greater than the width Wmax of the portion Pc (Wmax' > Wmax) or can be equal to the width Wmax of the portion Pc (Wmax' = Wmax). Thus, each of the wirings Q1, Q2, and Q3 only needs to have a width not exceeding the width Wmax of the portion Pc at least in a length of 33 mm. Although the portion Pc is located in the range AA in the present example, the position of the portion Pc can be anywhere as long as it is between the portion Ph and the portion Pm. Generally, the portion Ph is located in the left-side region SL, the portion Pm is located in the right-side region SR, and the portion Pc is located in the middle region SC.

[0187] FIG. 14A A cross section of a portion having a structure equivalent to the portion Ph illustrated in FIG. 14B A cross section taken along the line E-E' in FIG. 14B In FIG. 14A The maximum width Wmax of each of the wirings Q1, Q2, and Q3 is illustrated as a width Wc (Wmax = Wc). The thickness of the portion having the maximum width Wmax of each of the wirings Q1, Q2, and Q3 is illustrated as a thickness Tc. FIG. 15A1 A cross section of a portion having a structure equivalent to the portion Ph illustrated in FIG. 15A2 A cross section taken along the line E-E' in FIG. 15B1The width Wh of the portion Ph of each of the wirings Q1, Q2, and Q3 is illustrated as a width Wh. Further, the width Wm in the portion Pm of each of the wirings Q1, Q2, and Q3 can be equal to the width Wh, or can be different from the width Wh. Since the width Wc of the portion Pc is the maximum width Wmax in the range from the portion Ph to the portion Pm, each of the width Wh and the width Wm is not more than the width Wc. The width Wc can be greater than each of the width Wh and the width Wm (Wc > Wh & Wm), or the width Wc can be equal to each of the width Wh and the width Wm (Wc = Wh & Wm). Here, it is advantageous that the maximum width Wmax is less than 230 nm. It is more advantageous that the maximum width Wmax is less than 180 nm. It is more advantageous in terms of preventing or reducing an increase in the resistance of each of the wirings Q1, Q2, and Q3 that the maximum width Wmax is greater than 65 nm. The maximum width Wmax can be greater than or equal to 90 nm, and the maximum width Wmax can be greater than or equal to 120 nm. Making the width of each of the wirings Q1, Q2, and Q3 less than 230 nm in the range from the portion Ph to the portion Pm enables miniaturization of each of the wirings Q1, Q2, and Q3. It is advantageous that, as illustrated in FIG. 6, the width Wh of the portion Ph of each of the wirings Q1, Q2, and Q3 is less than 230 nm, and the width Wm in the portion Pm of each of the wirings Q1, Q2, and Q3 is less than 230 nm. FIG. 15B2 As illustrated in FIG. 6, the thickness Tc of the portion Pc is greater than each of the width Wh of the portion Ph and the width Wm of the portion Pm (Tc > Wh & Wm). Making the thickness Tc of the portion Pc greater than each of the width Wh and the width Wm enables preventing or reducing an increase in the resistance of each of the wirings Q1, Q2, and Q3 even when each of the wirings Q1, Q2, and Q3 is miniaturized (the width of each of the wirings Q1, Q2, and Q3 is reduced). In FIG. 15C1In the present example, the thickness Th of the portion Ph is illustrated. Although the thickness Th is equal to the thickness Tc (Tc = Th) in the present example, the thickness Th can be greater than the thickness Tc, or the thickness Th can be less than the thickness Tc. Similarly, the thickness Tm of the portion Pm can be greater than the thickness Tc, or the thickness Tm can be less than the thickness Tc. Advantageously, the thickness Th is greater than the width Wh. Making the thickness Th of the portion Ph greater than the width Wh enables preventing or reducing an increase in the resistance of each of the wirings Q1, Q2, and Q3 even when each of the wirings Q1, Q2, and Q3 is miniaturized (reducing the width of each of the wirings Q1, Q2, and Q3). Similarly, advantageously, the thickness Tm is greater than the width Wm. Although the thickness Tm is equal to the thickness Th (Tm = Th) in the present example, the thickness Tm can be greater than the thickness Tc, or the thickness Tm can be less than the thickness Th. In order to miniaturize each of the wirings Q1, Q2, and Q3, advantageously, each of the width Wh of the portion Ph and the width Wm of the portion Pm is less than 230 nm, more advantageously, each of the width Wh of the portion Ph and the width Wm of the portion Pm is less than 180 nm, and further advantageously, each of the width Wh of the portion Ph and the width Wm of the portion Pm is less than 140 nm. In order to prevent or reduce an increase in the resistance of each of the wirings Q1, Q2, and Q3 each having a length greater than or equal to 33 mm, advantageously, each of the width Wh of the portion Ph and the width Wm of the portion Pm is greater than 65 nm. Each of the width Wh of the portion Ph and the width Wm of the portion Pm can be 90 nm or greater, or each of the width Wh of the portion Ph and the width Wm of the portion Pm can be 120 nm or greater. In order to prevent or reduce an increase in the resistance of each of the wirings Q1, Q2, and Q3 each having a length greater than or equal to 33 mm, advantageously, the thickness Tc (similarly, the thickness Th and / or the thickness Tm) is greater than 130 nm. At least one of the thickness Tc, the thickness Th, and the thickness Tm can be 150 nm or greater, or can be greater than 180 nm. Advantageously, each of the distance Dc between the wiring Q2 and the wiring Q3 in the portion Pc and the distance between the wiring Q2 and the wiring Q1 in the portion Pc is less than the thickness Tc (Dc < Tc). Advantageously, each of the distance Dh between the wiring Q2 and the wiring Q3 in the portion Ph and the distance between the wiring Q2 and the wiring Q1 in the portion Ph is less than the thickness Th (Dh < Th). Similarly, advantageously, each of the distance between the wiring Q2 and the wiring Q3 in the portion Pm and the distance between the wiring Q2 and the wiring Q1 in the portion Pm is less than the thickness Tm.

[0188] FIG. 15C2 is FIG. 15D1An enlarged view of the region AA in the middle of the drawing. Each of the wirings Q1, Q2, and Q3 includes a left side portion 110a, a right side portion 110b, and an intermediate portion 110c located between the left side portion 110a and the right side portion 110b, along a direction in which the wiring Q1, Q2, or Q3 extends. The left side portion 110a is located in the left side region SL, the right side portion 110b is located in the right side region SR, and the intermediate portion 110c is located in the middle region SC.

[0189] In FIG. 15D2In the middle, the width Wa of the left portion 110a, the width Wb of the right portion 110b, and the width Wc of the middle portion 110c are illustrated. Here, since the width Wa and the width Wh can be equal to each other (Wa = Wh), the description regarding the width Wa in the following description can also be applied to the width Wh. Similarly, since the width Wb and the width Wm can be equal to each other (Wb = Wm), the description regarding the width Wb in the following description can also be applied to the width Wm. Although it is also advantageous that the width Wc of the middle portion 110c is larger than each of the width Wa of the left portion 110a and the width Wb of the right portion 110b (Wc > Wa, Wc > Wb), the widths of the wirings Q1, Q2, and Q3 can be equal to each other in the range between the portion Ph and the portion Pm. Each of the width Wa of the left portion 110a and the width Wb of the right portion 110b can be smaller than 230 nm. In the case where each of the width Wa of the left portion 110a and the width Wb of the right portion 110b is smaller than 230 nm, the advantageous effect of achieving miniaturization obtained by making the width Wc larger than each of the width Wa and the width Wb can be significantly obtained. The maximum width Wmax of any one of the wirings Q1, Q2, and Q3 can be 230 nm or more. In the case where each of the width Wa of the left portion 110a and the width Wb of the right portion 110b is 230 nm or more, the width Wc of the middle portion 110c can be equal to or different from each of the width Wa of the left portion 110a and the width Wb of the right portion 110b. Making the width Wc of the middle portion 110c larger than each of the width Wa and the width Wb in the case where each of the width Wa and the width Wb is 230 nm or more can be disadvantageous in terms of achieving miniaturization. Each of the width Wa of the left portion 110a and the width Wb of the right portion 110b can be smaller than 180 nm. In the case where each of the width Wa of the left portion 110a and the width Wb of the right portion 110b is smaller than 180 nm, the advantageous effect of achieving miniaturization obtained by making the width Wc larger than each of the width Wa and the width Wb can be significantly obtained. It is advantageous that the difference (Wc - Wa) between the width Wc of the middle portion 110c and the width Wa of the left portion 110a is larger than 50 nm, and this is advantageous in making the width Wa of the left portion 110a smaller than 180 nm. It is advantageous that the difference (Wc - Wb) between the width Wc of the middle portion 110c and the width Wb of the right portion 110b is larger than 50 nm, and this is advantageous in making the width Wb of the right portion 110b smaller than 180 nm. It is advantageous that the difference (Wc - Wa) between the width Wc of the middle portion 110c and the width Wa of the left portion 110a is smaller than the width Wa of the left portion 110a (Wc - Wa < Wa).It is also advantageous that the difference between the width Wc of the middle portion 110c and the width Wb of the right portion 110b (Wc-Wb) is smaller than the width Wb of the right portion 110b (Wc-Wb < Wb). It is also advantageous that the width Wc of the middle portion 110c is larger than 110 nm. It is also advantageous that the width Wc of the middle portion 110c is larger than 180 nm. The width Wc of the middle portion 110c can be smaller than 300 nm. Although the width Wb is equal to the width Wa in the present example, the width Wb can be different from the width Wa.

[0190] In FIG. 16A1 each of the wirings Q1 and Q3 and the left portion 110a of the wiring Q2, the distance Db between each of the wirings Q1 and Q3 and the right portion 110b of the wiring Q2, and the distance Dc between each of the wirings Q1 and Q3 and the middle portion 110c of the wiring Q2 are illustrated. It is advantageous that the distance Dc between each of the wirings Q1 and Q3 and the middle portion 110c of the wiring Q2 is larger than the width Wa of the left portion 110a (Dc > Wa). It is advantageous that the distance Dc between each of the wirings Q1 and Q3 and the middle portion 110c of the wiring Q2 is larger than the width Wb of the right portion 110b (Dc > Wb). It is advantageous that the distance Da between each of the wirings Q1 and Q3 and the left portion 110a of the wiring Q2 is smaller than the width Wc of the middle portion 110c (Da < Wc). It is advantageous that the distance Db between each of the wirings Q1 and Q3 and the right portion 110b of the wiring Q2 is smaller than the width Wc of the middle portion 110c (Db < Wc). Although the distance Db is equal to the distance Da in the present example, the distance Db can be different from the distance Da.

[0191] In FIG. 16A2 each of the wirings Q1 and Q3 and the left portion 110a of the wiring Q2, the distance Db between each of the wirings Q1 and Q3 and the right portion 110b of the wiring Q2, and the distance Dc between each of the wirings Q1 and Q3 and the middle portion 110c of the wiring Q2 are illustrated. It is advantageous that the distance Dc between each of the wirings Q1 and Q3 and the middle portion 110c of the wiring Q2 is larger than the width Wa of the left portion 110a (Dc > Wa). It is advantageous that the distance Dc between each of the wirings Q1 and Q3 and the middle portion 110c of the wiring Q2 is larger than the width Wb of the right portion 110b (Dc > Wb). It is advantageous that the distance Da between each of the wirings Q1 and Q3 and the left portion 110a of the wiring Q2 is smaller than the width Wc of the middle portion 110c (Da < Wc). It is advantageous that the distance Db between each of the wirings Q1 and Q3 and the right portion 110b of the wiring Q2 is smaller than the width Wc of the middle portion 110c (Db < Wc). Although the distance Db is equal to the distance Da in the present example, the distance Db can be different from the distance Da.

[0192] Generally, each of the width Wa, the width Wb, the distance Da, and the distance Db is smaller than each of the width Wc and the distance Dc.

[0193] An example in which the semiconductor device APR is applied to a photoelectric conversion device is described. Each of the wirings Q1, Q2, and Q3 is, for example, a row wiring having a dual damascene structure. Each of the wirings Q1, Q2, and Q3 is a signal line for transmitting a control signal to a pixel circuit including four transistors (a transfer transistor, a reset transistor, an amplification transistor, and a selection transistor) per one pixel P. For example, the wiring Q1 is a transfer signal line for controlling the transfer transistor, the wiring Q2 is a reset signal line for controlling the reset transistor, and the wiring Q3 is a selection signal line for controlling the selection transistor. The functions possessed by the plurality of wirings 110 and the wirings Q1, Q2, and Q3 in the present exemplary embodiment are not limited to the above-described examples.

[0194] In FIG. 16B1 which the respective ranges of the plurality of pixels P are illustrated. For each pixel P, a portion in which the width of the wiring is thick (thick line portion) and a portion in which the width of the wiring is thin (thin line portion) are repeatedly provided. The left side portion 110a is located between the middle portion 110c and one end Ea along the direction in which the wirings Q1, Q2, and Q3 extend. The right side portion 110b is located between the middle portion 110c and the other end Eb along the direction in which the wirings Q1, Q2, and Q3 extend. Each of the wirings Q1, Q2, and Q3 includes, along the direction in which the wirings Q1, Q2, and Q3 extend, the thin line portion L4 located between the one end Ea and the left side portion 110a and the thick line portion L5 located between the thin line portion L4 and the left side portion 110a. Further, each of the wirings Q1, Q2, and Q3 includes, along the direction in which the wirings Q1, Q2, and Q3 extend, the thin line portion R6 located between the other end Eb and the right side portion 110b and the thick line portion R7 located between the thin line portion R6 and the right side portion 110b. The width of the thick line portion L5 is larger than each of the width Wa of the left side portion 110a, the width Wb of the right side portion 110b, the width of the thin line portion L4, and the width of the thin line portion R6. The width of the thick line portion R7 is larger than each of the width Wa of the left side portion 110a, the width Wb of the right side portion 110b, the width of the thin line portion L4, and the width of the thin line portion R6. Although it is advantageous that the width of the thick line portion L5 or the width of the thick line portion R7 is equal to the width Wc, the width of the thick line portion L5 or the width of the thick line portion R7 can be different from the width Wc. Although it is advantageous that the width of the thin line portion L4 or the width of the thin line portion R6 is equal to the width Wa or Wb, the width of the thin line portion L4 or the width of the thin line portion R6 can be different from the width Wa or Wb.

[0195] In this way, providing the thick line portions (i.e., thick line portions L5 and R7) at positions corresponding to the range AA in the pixels away from the line A-A' excluding the intermediate region SC makes it possible to improve the uniformity of the layout of the wiring in each pixel, and thus increase the uniformity of the characteristics of each pixel. In other words, providing such thick line portions makes it possible to reduce the difference in signal output between the pixels near the line A-A' including the intermediate region SC and the pixels away from the line A-A' excluding the intermediate region SC, and prevent or reduce line noise appearing in the image along the line A-A'. Naturally, since the thick line portion L5 exists in the left side region SL and the thick line portion R7 exists in the right side region SR, the thick line portions L5 and R7 have little function of mitigating the influence of misalignment between the photomask used when the left side region SL is exposed and the photomask used when the right side region SR is exposed.

[0196] Each of the wirings Q1, Q2, and Q3 includes a left side portion 110d between the left side portion 110a and the intermediate portion 110c and a right side portion 110e between the right side portion 110b and the intermediate portion 110c in the direction in which the wirings Q1, Q2, and Q3 extend. FIG. 16B2In the present example, the width Wd of the left portion 110d is equal to the width Wc of the middle portion 110c (Wd = Wc). In cases where the width Wd of the left portion 110d is different from the width Wc of the middle portion 110c, it is advantageous that the width Wd of the left portion 110d is less than the width Wc of the middle portion 110c (Wd < Wc), although the width Wd of the left portion 110d can be greater than the width Wc of the middle portion 110c (Wd > Wc). Similarly, the width We of the right portion 110e is equal to the width Wc of the middle portion 110c (We = Wc). In cases where the width We of the right portion 110e is different from the width Wc of the middle portion 110c, it is advantageous that the width We of the right portion 110e is less than the width Wc of the middle portion 110c (We < Wc), although the width We of the right portion 110e can be greater than the width Wc of the middle portion 110c (We > Wc). It is advantageous that the difference between the width Wc of the middle portion 110c and the width Wd of the left portion 110d (|Wc - Wd|) is less than the difference between the width Wa of the left portion 110a and the width Wd of the left portion 110d (|Wd - Wa|) (|Wc - Wd| < |Wd - Wa|). Similarly, it is advantageous that the difference between the width Wc of the middle portion 110c and the width We of the right portion 110e (|Wc - We|) is less than the difference between the width Wb of the right portion 110b and the width We of the right portion 110e (|We - Wb|) (|Wc - We| < |We - Wb|). Since there can be a relationship of Wc = Wd = We as mentioned above, the relationship between the width Wc and the widths Wa and Wb can be applied to the relationship between the widths Wd and We and the widths Wa and Wb. Furthermore, the left portion 110d and the right portion 110e can be omitted, and this is equivalent to making the width Wd of the left portion 110d equal to the width Wa and making the width We of the right portion 110e equal to the width Wb.

[0197] As FIG. 16C1 As illustrated in the present example, the wiring Q1 and the wiring Q3 are positioned obliquely between the left portion 110a and the left portion 110d. This achieves both of Wa < Wc and Da < Dc. Similarly, the wiring Q1 and the wiring Q3 are positioned obliquely between the right portion 110b and the right portion 110e. This achieves both of Wb < Wc and Db < Dc.

[0198] Further, making the width Wc larger than each of the width Wa and the width Wb (Wc > Wa & Wb) makes it possible to prevent or reduce the pattern from being broken at the middle portion 110c even when misalignment occurs between the photomasks for the left and right regions SL and SR. This then makes it possible to form a more minute pattern at the left and right portions 110a and 110b. Further, making the distance Dc larger than each of the distance Da and the distance Db (Dc > Da & Db) makes it possible to prevent or reduce the pattern from being short-circuited in the middle portion 110c even when misalignment occurs between the photomasks for the left and right regions SL and SR.

[0199] As FIG. 16C2 illustrated in FIG. 6, the wiring pitch Y2 in the Y direction can be made larger than the wiring pitch Yl in the Y direction. This makes it possible to make the wiring opening in the Y direction wider, and thus improves the sensitivity of the photoelectric conversion device.

[0200] In the following description, reference is made to FIG. 17A1 , FIG. 17A2 , FIG. 17B1 , FIG. 17B2 , FIG. 17C1 , FIG. 17C2 , FIG. 15A1 to FIG. 15D2 and FIG. 16A1 to FIG. 16C2 , FIG. 17A1 to FIG. 17C2 , FIG. 14B , FIG. 15A1 , FIG. 15A2 , FIG. 15B1 and FIG. 15B2 as well as FIG. 15C1 , FIG. 15C2 , FIG. 15C2 , FIG. 15D1 , FIG. 15D2 , FIG. 16A1 describing methods for manufacturing semiconductor devices. In FIG. 16A2 , FIG. 16B1 and FIG. 16B2 , the drawings having the figure numbers with the suffix "1" are cross-sectional views, and the drawings having the figure numbers with the suffix "2" are plan views in the case where the semiconductor device is observed from the top. The cross-sectional view having the figure number with the suffix "1" represents a cross section taken along the line D-D' in the plan view having the figure number with the suffix "2". The line corresponding to the line D-D' is also illustrated in FIG. 16B2 . The members common between the drawings having the figure numbers with the suffix "1" and the drawings having the figure numbers with the suffix "2" are assigned the corresponding same hatching.

[0201] As illustrated in each of the plan views with the figure numbers with the suffix "2" attached, the wafer WF includes, in each of the plurality of device regions DR, a left side region SL left of the line C-C', a right side region SR right of the line B-B', and a middle region SC between the left side region SL and the right side region SR.

[0202] FIG. 16C1 and FIG. 16C2 A process A for manufacturing a wafer WF including a semiconductor layer 100 and an insulator film 104 provided on the semiconductor layer 100 is illustrated. The wafer WF used for manufacturing the semiconductor device APR in the present exemplary embodiment includes the semiconductor layer 100 serving as an element functional layer. The semiconductor layer 100 to be used includes a silicon layer or a compound semiconductor layer. In the element functional layer, for example, a plurality of photoelectric conversion sections (not illustrated), a plurality of transistors (not illustrated), and an isolation structure (not illustrated) for isolating the plurality of photoelectric conversion sections from the plurality of transistors at portions where they are to be electrically isolated from each other. The element functional layer can be formed by a known method using a known material.

[0203] On the semiconductor layer 100 serving as the element functional layer, an interlayer insulating film 101 is formed. The interlayer insulating film 101 is formed to establish electrical insulation between structures included in the semiconductor layer 100 serving as the element functional layer and layers above the interlayer insulating film 101. The interlayer insulating film 101 to be used can be made of, for example, silicon oxide and can be formed by a known method.

[0204] In the interlayer insulating film 101, a contact plug 102 is formed at a portion where conduction between a structure included in the semiconductor layer 100 intended to secure an element function layer and a wiring above the interlayer insulating film 101 is intended to be secured. On the contact plug 102, an insulator film 103 serving as an etching stopper layer and an insulator film 104 serving as an interlayer insulating film are formed. For example, the contact plug 102 can be made of tungsten, the insulator film 103 can be a silicon carbide film or a silicon nitride film, and the insulator film 104 can be a silicon oxide film. Further, the silicon oxide film is a film including oxygen and silicon as main constituent elements, and can include impurities such as carbon, nitrogen, fluorine, or chlorine at a lower ratio than that of each of oxygen and silicon. Similarly, the silicon nitride film is a film including nitrogen and silicon as main constituent elements, and can include impurities such as carbon, oxygen, fluorine, or chlorine at a lower ratio than that of each of nitrogen and silicon. Similarly, the silicon carbide film is a film including carbon and silicon as main constituent elements, and can include impurities such as nitrogen, oxygen, fluorine, or chlorine at a lower ratio than that of each of carbon and silicon. Here, with respect to the composition of a silicon compound such as a silicon oxide film, a silicon nitride film, or a silicon carbide film, a light element such as hydrogen or helium is not regarded as a main constituent element. Therefore, the silicon oxide film, the silicon nitride film, or the silicon carbide film can include a light element such as hydrogen at a higher ratio than that of nitrogen and / or silicon. The insulator film 104 serving as an interlayer insulating film can be a silicon oxide film including carbon, an organic material film, a silicon nitride film, or a silicon carbide film. The insulator film 104 can be a porous film, or can be a low-k (material having a small relative dielectric constant (kappa) with respect to silicon dioxide) film. Further, these configurations are not intended to limit the present example embodiment, but are described merely as examples.

[0205] FIG. 17A1 and FIG. 17A2A process B for forming a mask material film 105 and a mask material film 106 on the wafer WF is illustrated. The manufacturing method forms the mask material film 105 and the mask material film 106 on the insulator film 104 serving as an interlayer insulating film. The mask material film 105 is configured with an inorganic material film 1051 and an organic material film 1052. For example, the inorganic material film 1051 can be a silicon nitride film, and the organic material film 1052 can be made of a novolak-type resin. The mask material film 105 can include an inorganic material film 1053 (not illustrated) provided on the organic material film 1052, and can have a stacked (laminated) structure in which the organic material film 1052 is sandwiched between the inorganic material film 1053 (not illustrated) and the inorganic material film 1051. The inorganic material film 1053 (not illustrated) on the organic material film 1052 can be a silicon oxide film. In the present exemplary embodiment, the mask material film 105 has the above-described configuration, but can have another configuration. The material of the mask material film 106 only needs to be a material different from the material of the uppermost layer of the mask material film 105. If the material of the uppermost layer of the mask material film 105 is the organic material film 1052, the mask material film 106 to be used can be an inorganic material film such as a silicon oxide film or a silicon nitride film. If the material of the uppermost layer of the mask material film 105 (for example, the inorganic material film 1053) is a silicon oxide film, the mask material film 106 to be used can be an inorganic material film such as a silicon nitride film or a titanium nitride film, which is different from the inorganic material film 1053. Furthermore, the mask material film 105 can be omitted, and in that case, the mask material film 106 only needs to be formed in such a manner as to be in contact with the insulator film 104.

[0206] FIG. 17B1 and FIG. 17B2 An exposure process C for exposing a positive photoresist film 107 provided on one side of the layer above the insulator films 103 and 104 with a left-side exposure shot L is illustrated. The left-side exposure shot L is for exposing the photoresist film 107 in the left-side region SL and the middle region SC. After forming the positive photoresist film 107 on the mask material film 106, the manufacturing method exposes the photoresist film 107 with the photomask PML in the left-side region SL and the middle region SC in a left-side exposure pattern 107H. The alignment (position adjustment) between the photomask PML and the wafer can be performed with the use of an alignment mark (not illustrated) formed in the layer below the mask material film 106. As illustrated in the middle, the left-side exposure pattern 107H is for exposing up to the line B-B’ across the line A-A’. The exposure process C makes it possible to form an exposure pattern 107A for alignment on the photoresist film 107 in addition to the left-side exposure pattern 107H. FIG. 17C1

[0207] FIG. 17C2 and FIG. 18A1 ​An exposure process F is illustrated that exposes a positive photoresist film 108 disposed on one side of the layers over the insulator films 103 and 104 with a right-side exposure shot R. The right-side exposure shot R is used to expose the photoresist film 108 in the right-side region SR and the middle region SC. After forming the positive photoresist film 108 on the mask material film 106, the manufacturing method exposes the photoresist film 108 with a right-side exposure pattern 108M using the photomask PMR in the right-side region SR and the middle region SC. As illustrated in the middle, the right-side exposure pattern 108M is used to expose up to line C-C’ across line A-A’. The exposure process F enables performing alignment between the photomask PMR and the wafer using the alignment marks 106A. In addition, the manufacturing method can perform alignment between the photomask PMR and the wafer using the alignment marks (not illustrated) formed in the layers under the mask material film 106 and the alignment marks 106A. This way enables accurately controlling any misalignment that occurs with respect to both the underlayer and the left-side region SL when exposing the right-side region SR.

[0208] FIG. 18A2 and FIG. 18B1 An exposure process F is illustrated that exposes a positive photoresist film 108 disposed on one side of the layers over the insulator films 103 and 104 with a right-side exposure shot R. The right-side exposure shot R is used to expose the photoresist film 108 in the right-side region SR and the middle region SC. After forming the positive photoresist film 108 on the mask material film 106, the manufacturing method exposes the photoresist film 108 with a right-side exposure pattern 108M using the photomask PMR in the right-side region SR and the middle region SC. As illustrated in the middle, the right-side exposure pattern 108M is used to expose up to line C-C’ across line A-A’. The exposure process F enables performing alignment between the photomask PMR and the wafer using the alignment marks 106A. In addition, the manufacturing method can perform alignment between the photomask PMR and the wafer using the alignment marks (not illustrated) formed in the layers under the mask material film 106 and the alignment marks 106A. This way enables accurately controlling any misalignment that occurs with respect to both the underlayer and the left-side region SL when exposing the right-side region SR.

[0209] FIG. 18B2 and FIG. 18C1 An exposure process F is illustrated that exposes a positive photoresist film 108 disposed on one side of the layers over the insulator films 103 and 104 with a right-side exposure shot R. The right-side exposure shot R is used to expose the photoresist film 108 in the right-side region SR and the middle region SC. After forming the positive photoresist film 108 on the mask material film 106, the manufacturing method exposes the photoresist film 108 with a right-side exposure pattern 108M using the photomask PMR in the right-side region SR and the middle region SC. As illustrated in the middle, the right-side exposure pattern 108M is used to expose up to line C-C’ across line A-A’. The exposure process F enables performing alignment between the photomask PMR and the wafer using the alignment marks 106A. In addition, the manufacturing method can perform alignment between the photomask PMR and the wafer using the alignment marks (not illustrated) formed in the layers under the mask material film 106 and the alignment marks 106A. This way enables accurately controlling any misalignment that occurs with respect to both the underlayer and the left-side region SL when exposing the right-side region SR. FIG. 18C2

[0210] FIG. 15A1 to FIG. 15D2 FIG. 18A1 to FIG. 18C2 An exposure process F is illustrated that exposes a positive photoresist film 108 disposed on one side of the layers over the insulator films 103 and 104 with a right-side exposure shot R. The right-side exposure shot R is used to expose the photoresist film 108 in the right-side region SR and the middle region SC. After forming the positive photoresist film 108 on the mask material film 106, the manufacturing method exposes the photoresist film 108 with a right-side exposure pattern 108M using the photomask PMR in the right-side region SR and the middle region SC. As illustrated in the middle, the right-side exposure pattern 108M is used to expose up to line C-C’ across line A-A’. The exposure process F enables performing alignment between the photomask PMR and the wafer using the alignment marks 106A. In addition, the manufacturing method can perform alignment between the photomask PMR and the wafer using the alignment marks (not illustrated) formed in the layers under the mask material film 106 and the alignment marks 106A. This way enables accurately controlling any misalignment that occurs with respect to both the underlayer and the left-side region SL when exposing the right-side region SR.

[0211] ​​FIG. 18A1 to FIG. 18C2 and FIG. 18A1 A processing process H for performing processing on the mask material film 106 using the resist pattern 108R as a mask to transfer the resist pattern 108R to the mask material film 106 is illustrated. The manufacturing method forms a mask pattern 106R by performing etching on the mask material film 106 using the resist pattern 108R as a mask. Thus, a mask pattern 106LR obtained by combining the mask pattern 106L and the mask pattern 106R is formed. After the mask pattern 106R (mask pattern 106LR) is formed, the manufacturing method can remove the resist pattern 108R.

[0212] Although an example in which the manufacturing method performs the right-side exposure shot R after the left-side exposure shot L has been described, the manufacturing method can perform the left-side exposure shot L after the right-side exposure shot R. Details of the left-side exposure pattern 107L and the right-side exposure pattern 108R are described below. The wavelength of the exposure light is, for example, in the range of 175 nm to 275 nm, and, for example, exposure light having a wavelength in the range of 225 nm to 275 nm (for example, a KrF excimer laser having a wavelength of 248 nm) or exposure light having a wavelength in the range of 175 nm to 225 nm (for example, an ArF excimer laser having a wavelength of 193 nm) is advantageous. In terms of miniaturization of wiring, it is more advantageous to use an ArF excimer laser as the exposure light. In order to form wiring having a width of less than 230 nm, it is advantageous for the wavelength of the exposure light (exposure wavelength) used in each of the exposure processes C and F to be less than 230 nm.

[0213] FIG. 18A2 and FIG. 18B1 A processing process I for performing processing on the insulator films 104 and 103 using the mask pattern 106LR as a mask to form trenches 109 in the insulator films 104 and 103 is illustrated. The manufacturing method performs etching on the mask material film 105, the insulator film 104 serving as an interlayer insulating film, and the insulator film 103 using the mask pattern 106LR as a mask, thereby forming the trenches 109. The trenches 109 extend from the left-side region SL across the intermediate region SC to the right-side region SR. It is advantageous for the depth of the trenches 109 in the intermediate region SC to be greater than the width of the trenches 109. The maximum depth of the trenches 109 can be greater than the maximum width of the trenches 109 throughout the trenches 109.

[0214] FIG. 18B2 and FIG. 18B1A wiring process J for forming a wiring 110 in the trench 109 is illustrated. For example, the manufacturing method embeds a conductive material in the trench 109 using a plating method. The conductive material can be, for example, copper or a copper-containing alloy. Then, after embedding the conductive material, the manufacturing method removes unnecessary conductive material formed on the insulator film 104 using, for example, a chemical mechanical polishing (CMP) method. With this process, the manufacturing method forms the wiring 110 in the trench 109. The wiring 110 extends from the left side region SL across the middle region SC to the right side region SR. The wiring 110 includes a left side portion 110L located on the left side region SL, a right side portion 110R located on the right side region SR, and a middle portion 110C located on the middle region SC along the direction in which the wiring 110 extends. In this way, the wiring formed by embedding a conductive material in an insulator film and then removing unnecessary conductive material is called a "damascene wiring", and this process is called a "damascene process". Although a case where this process is applied to a single damascene process has been described here, a similar method can also be applied to a dual damascene process.

[0215] Then, the manufacturing method forms at least one upper wiring layer (typically, a plurality of upper wiring layers). The formation of the upper wiring layer can be performed by applying a damascene process similar to the above-described damascene process to an interlayer insulating film formed on the insulator film 104 and the wiring 110. In a case where the semiconductor device APR is a front-illuminated type photoelectric conversion device, after forming the upper wiring layer, the manufacturing method can provide an opening to the plurality of interlayer insulating films including the insulator film 104. This opening is used to form a light path for light to reach the photoelectric conversion section. A light-transmissive material different from the material of the insulator film 103 and / or the insulator film 104 can be embedded in this opening. For example, if the insulator film 103 is made of silicon carbide or silicon nitride and the insulator film 104 is made of silicon oxide, the light-transmissive material only needs to be silicon nitride, silicon oxide, or a resin.

[0216] In the above description, a case in which the method for manufacturing a semiconductor device is applied to formation of wirings has been described. The wiring layer includes wirings for transmitting power and signals that are common to respective columns of the pixel portion, and these wirings are arranged while extending between the left-side region SL and the right-side region SR. Applying the split exposure according to the present exemplary embodiment makes it possible to perform miniaturization processing on the wirings in the respective regions, and also makes it possible to perform miniaturization on the portions extending between the regions. The wirings obtained by connection using the split exposure can be, for example, power lines for supplying power to cause the pixel portion or the column circuit to operate. Alternatively, the wirings obtained by connection using the split exposure can be, for example, signal lines for supplying control signals to control operation of the pixel portion or the column circuit, or signal lines for transmitting output signals from the column circuit based on the amount of light received for each pixel. However, another type of wiring can be formed by connection using the split exposure. Although the wirings whose manufacturing method has been described in the present exemplary embodiment are single damascene wirings formed by a single damascene process, a similar method can be applied to dual damascene wirings formed by a dual damascene process. Although "trench first" can be adopted for the dual damascene process, it is more advantageous in terms of miniaturization to adopt "via first".

[0217] Furthermore, although the wiring layer whose manufacturing method has been described is one layer, the above-described exemplary embodiment can be applied to two or more wiring layers. Furthermore, the exposure apparatus used for exposure at the time of formation can be different between the wirings in the first layer and the wirings in the second layer. For example, when forming the wirings in the first layer, the manufacturing method can use an exposure apparatus that uses an ArF light source with a wavelength of 193 nm and a maximum exposure area of 26 mm x 33 mm, and when forming the wirings in the second and subsequent layers, the manufacturing method can use an exposure apparatus that uses a KrF light source with a wavelength of 248 nm and a maximum exposure area of 26 mm x 33 mm. The wirings in the first layer can be single damascene wirings and the wirings in the second layer can be dual damascene wirings. Then, the manufacturing method can apply connection exposure (split exposure) using the ArF light source to the single damascene wirings in the first layer, and connection exposure (split exposure) using the KrF light source to the dual damascene wirings in the second layer.

[0218] Although in the above-described exemplary embodiment, a case in which each of the photoresist films 107 and 108 is positive type has been described, the photoresist film 107 and the photoresist film 108 can be configured to be negative type. In that case, the manufacturing method can use a photomask PML and PMR configured to expose a portion of the negative type photoresist film corresponding to a portion in which a wiring is not to be formed, and can remove an unexposed portion of the negative type photoresist film by a development process.

[0219] In the following description, reference is made toFIG. 18B2 、 FIG. 18C1 、 FIG. 18C2 、 FIG. 18C2 、 FIG. 19C and FIG. 19D Details of the left exposure pattern 107H and the right exposure pattern 108M in the exposure process illustrated in FIG. 11A are described. FIG. 19E

[0220] FIG. 19C Among the drawings having the figure numbers with the suffix "1" attached thereto, the plan view of FIG. 11A is a plan view illustrating the positional relationship between the left exposure pattern 107H for the left region SL and the right exposure pattern 108M for the right region SR. Further, among the drawings having the figure numbers with the suffix "2" attached thereto, the plan view of FIG. 11B is a plan view obtained when the mask pattern 106LR composed of the mask pattern 106L and the mask pattern 106R has been formed. FIG. 19C

[0221] FIG. 19D A form in which the left exposure pattern 107H and the right exposure pattern 108M overlap each other in the middle region SC is illustrated. In the positions where the left exposure pattern 107H and the right exposure pattern 108M overlap each other, the hatching obtained by overlapping the hatching of the left exposure pattern 107H and the hatching of the right exposure pattern 108M with each other is illustrated. The present exemplary embodiment is characterized in that, as mentioned above, the left exposure pattern 107H is formed on the photoresist film 107 and the right exposure pattern 108M is formed on the photoresist film 108.

[0222] ​​On the other hand, if the left-side region SL is exposed with the left-side exposure pattern 107H and the right-side region SR is exposed with the right-side exposure pattern 108M with respect to the same photoresist film, double exposure in which exposure is performed twice with such exposure patterns occurs in the middle region SC. This can cause a problem of line width variation due to the double exposure. In the middle region SC, since the double exposure is performed with the left-side exposure shot L and the right-side exposure shot R, the accumulated exposure amount increases, so that the width of the latent image pattern can become larger than the width of the exposure pattern. This is because, due to the increase in the accumulated exposure amount, the amount of acid generation in the exposed portion increases, the protective group elimination reaction using acid as a catalyst occurs more frequently, and the region that is soluble in the developer solution expands. Furthermore, although diffraction of light can occur at the time of exposure, since the double exposure is performed with both the diffracted light for the left-side exposure shot L and the diffracted light for the right-side exposure shot R, line width variation can occur. Shaping the layout in the middle region SC, such as providing an auxiliary pattern, makes it possible to prevent or reduce line width variation due to the double exposure. In a method of providing such an auxiliary pattern, for example, in the case of a line pattern (a wiring in which a remaining pattern is formed), in order to prevent or reduce line width variation due to the double exposure, it is possible to arrange the auxiliary pattern in such a way that the line width becomes larger. At this time, in order to prevent or reduce resolution insufficiency between the auxiliary patterns, it is desirable to sufficiently secure the distance between the auxiliary patterns. Furthermore, in the case of a trench pattern (a wiring in which an opening pattern is formed), in order to prevent or reduce line width variation due to the double exposure, it is possible to arrange the auxiliary pattern in such a way that the line width becomes smaller. At this time, if the size of the auxiliary pattern is too large with respect to the trench width, since the trench can be broken, it is necessary to set the trench width to a size that is larger than or equal to a predetermined value. For the above-mentioned reasons, with only the method of providing an auxiliary pattern, there is a limit in terms of miniaturization of the pattern. On the other hand, the present exemplary embodiment is configured to form the mask pattern 106LR by performing exposure on the respective different photoresist films in the left-side region SL and the right-side region SR. Therefore, in the middle region SC, double exposure does not occur, and since it is possible to prevent or reduce variation in the size of the pattern in the middle region SC as illustrated in FIG. 10, the present exemplary embodiment is advantageous in terms of miniaturization of the pattern. FIG. 19E The present exemplary embodiment is advantageous in terms of miniaturization of the pattern.

[0223] FIG. 19C is a plan view that illustrates the positional relationship between the exposure patterns for the left-side region SL and the right-side region SR obtained when the left-side region SL and the right-side region SR have occurred misalignment in the X direction. Furthermore, FIG. 19Dis a plan view illustrating the mask pattern 106L and the mask pattern 106R formed on the mask material film 106 in that case. In the conventional split exposure technique, since exposure is performed on the same photoresist in the left region SL and the right region SR, if misalignment occurs in the X direction as illustrated in FIG. 19E The area of the middle region SC changes if misalignment occurs in the X direction as illustrated in the middle. In that case, since the exposure amount accumulated in the middle region SC changes, the line width of the pattern varies, so that pattern breakage or short-circuit between patterns can become a problem. In order to prevent pattern breakage even in a case where the line width of the pattern varies due to misalignment, an auxiliary pattern is provided in the middle region SC. However, because the size of the pattern width becomes large in the repeated region, this method is contrary to miniaturization. On the other hand, the present exemplary embodiment is configured to form a pattern by performing exposure on respective different photoresist films in the left region SL and the right region SR. Since it is possible to prevent or reduce the variation in the size of the pattern even in a case where the area of the middle region SC changes due to misalignment in the X direction, the present exemplary embodiment is advantageous in miniaturization of the pattern as illustrated in FIG. 16C2

[0224] FIG. 17A2 is a plan view illustrating the positional relationship between the exposure patterns for the left region SL and the right region SR obtained when the left region SL and the right region SR are misaligned in the Y direction. Further, FIG. 19C is a plan view illustrating the mask pattern 106L and the mask pattern 106R formed on the mask material film 106 in that case. Assuming that the width of the exposure pattern 107H is denoted by Mh, the width of the exposure pattern 108M is denoted by Mm, and the misalignment amount in the Y direction is denoted by My, the width of the wiring in the middle region SC becomes "My + (Mh + Mm) / 2". Further, the condition under which the wiring does not short-circuit is "My < Mh & Mm". Generally, the condition becomes "My + (Mh + Mm) / 2 ≈ Wmax". For example, in a case where Mh & Mm < 180 nm, if My < 50 nm, the relationship Wmax < 230 nm is obtained. In a case where Mh & Mm < 130 nm, if My < 100 nm, the relationship Wmax < 230 nm is obtained. In a case where Mh & Mm < 130 nm, if My < 50 nm, the relationship Wmax < 180 nm is obtained. In a case where Mh & Mm < 90 nm, if My < 80 nm, the relationship Wmax < 170 nm is obtained. In a case where Mh & Mm < 90 nm, if My < 40 nm, the relationship Wmax < 130 nm is obtained.

[0225] ​A typical split exposure technique is configured to perform exposure on the same photoresist film in the left region SL and the right region SR. Therefore, as... FIG. 19D As illustrated in the diagram, when misalignment occurs in the Y direction, the gap SS between the pattern for the left region SL and the pattern for the right region SR in the middle region SC becomes smaller. Therefore, the optical contrast required for resolution in this gap cannot be sufficiently obtained, making short circuits in the patterns potentially problematic. On the other hand, since this exemplary embodiment is configured to perform exposure on correspondingly different photoresist films in the left region SL and the right region SR, even when the distance SS between the patterns becomes smaller, the width of the portion Ps between adjacent mask patterns 106LR is unlikely to decrease. Therefore, compared to the case where exposure is performed on the same photoresist, this exemplary embodiment can prevent or reduce short circuits in the wiring.

[0226] In this way, the method in this exemplary embodiment performs exposure on corresponding different photoresist films in the left region SL and the right region SR, thereby preventing or reducing changes in size, pattern breakage and short circuits between adjacent patterns, and thus facilitating pattern miniaturization.

[0227] refer to FIG. 19E , FIG. 19C and FIG. 19C Describe the relationship between mask pattern 106L and resist pattern 108R. FIG. 19C The left half is a plan view of the semiconductor device in process G, viewed from the top, and FIG. 19C The right half is a plan view of the semiconductor device in process H as seen from the top. FIG. 18B1 and FIG. 18B2 It is along the location located FIG. 19D A cross-sectional view taken from line A-A' (not shown) between lines C-C' and B-B'. FIG. 19E and FIG. 19D The line A-A' in the middle is equivalent to FIG. 19E or FIG. 19C The line A-A' is shown in the diagram. FIG. 20A and FIG. 20B and FIG. 20B Common components are assigned the same shade. FIG. 1AIn the middle, in order to illustrate the relationship between the resist pattern 108R and the mask pattern 106L, a hatching (diagonal lines) for the photoresist film 108 and a hatching (dots) for the mask material film 106 when superimposed on each other are illustrated. If the side surface of the mask pattern 106L formed by etching in the process E is exposed to the outside through the resist pattern 108R in the process G, the side surface of the mask pattern 106L can be subjected to etching in the process H. Therefore, in the middle region SC in which the resist pattern 108R and the mask pattern 106L overlap each other, the side surface of the mask pattern 106L can be subjected to side etching. Then, the shape of the mask pattern 106LR can become different from the shape simply obtained by superimposing the exposure pattern 107H and the exposure pattern 108M on each other. FIG. 1A The left half illustrates the relationship between the mask pattern 106L and the resist pattern 108R, and FIG. 21 The right half shows the shape of the mask pattern 106LR. In FIG. 22 In the middle, six examples (i) to (vi) are illustrated. Examples (i), (iii), and (v) indicate a change corresponding to the amount of misalignment in the X direction illustrated in FIG. 22 and FIG. 23 Even if the amount of misalignment in the Y direction is zero as in example (i), the width of the wiring can become large in the middle region SC due to the side etching with the mask pattern 106L mentioned above. This portion can be the portion Pc having the largest width Wmax as mentioned above. As indicated in examples (i), (iii), and (v), as the amount of misalignment is larger, the portion included in the mask pattern 106L that is subjected to etching in the process H increases. Therefore, the range in which the wiring width is large increases. This is advantageous in terms of preventing or reducing an increase in the resistance of the wiring. However, this is disadvantageous in terms of reducing the pitch between adjacent wirings.

[0228] As illustrated in FIG. 22 and FIG. 24A It is effective to arrange a side surface protection member SWP that protects the side surface of the mask pattern 106L in the process H. The side surface protection member SWP is present between the opening of the resist pattern 108R and the side surface of the mask pattern 106L. For example, it is advantageous that, as illustrated in FIG. 22 the resist pattern 108R is configured to cover the side surface of the mask pattern 106L. Here, the side surface protection member SWP can be a portion of the resist pattern 108R. This configuration can be formed by making the size of the opening of the resist pattern 108R smaller than the size of the opening of the mask pattern 106L. This makes it possible to prevent or reduce deformation of the mask pattern 106L in the process H. Alternatively, as illustrated in FIG. 24AAs illustrated in the middle, a side surface protection member SWP can be arranged on the side surface of the mask pattern 106L. The side surface protection member SWP can be a part of the photoresist film 108, and can be a member that is isolated from the resist pattern 108R. Alternatively, the side surface protection member SWP can be configured with a material that is different from the material of the photoresist film 108.

[0229] FIG. 24A Each of the examples (ii), (iv), and (vi) illustrated in the middle indicates a configuration in which the resist pattern 108R covers the side surface of the mask pattern 106L. The resist pattern 108R is set thinner in the middle region SC than in other portions (portions on the right side region SR). Although the amount of misalignment in the X direction is the same between example (iii) and example (iv), the increase in the wiring width in the middle region SC is more prevented or reduced in example (iv) than in example (iii). Although the amount of misalignment in the X direction is the same between example (v) and example (vi), the increase in the wiring width in the middle region SC is more prevented or reduced in example (vi) than in example (v).

[0230] The present exemplary embodiments can also be applied to FIG. 24B The stacked semiconductor device APR illustrated in the middle. The stacked semiconductor device APR has a structure in which the photoelectric conversion chip 21 and the peripheral circuit chip 22 are stacked in layers. The photoelectric conversion chip 21 is a semiconductor component that includes a pixel array in which unit pixels including photoelectric conversion elements are arranged in a two-dimensional manner. The peripheral circuit chip 22 is a semiconductor component that has a structure in which a signal processing circuit 22L and a signal processing circuit 22R are arranged on the same substrate.

[0231] The circuit included in each of the signal processing circuit 22L and the signal processing circuit 22R is, for example, a timing generator (TG) circuit, an analog-to-digital converter (ADC) circuit, and a digital-to-analog converter (DAC) circuit.

[0232] The circuits included in each of the signal processing circuits 22L and 22R are, for example, digital front end (DFE) circuits, digital signal processor (DSP) circuits, vertical scanning circuits, and horizontal scanning circuits. The circuits included in each of the signal processing circuits 22L and 22R are, for example, static random access memory (SRAM) circuits and dynamic random access memory (DRAM) circuits. Furthermore, the signal processing circuits 22L and 22R can be interconnected by an inter-circuit wiring layer (not illustrated). The size of each of the photoelectric conversion chip 21 and the peripheral circuit chip 22 is larger than the size of the maximum exposure region of the exposure apparatus, and the size of each of the signal processing circuits 22L and 22R formed on the peripheral circuit chip 22 is smaller than the size of the maximum exposure region of the exposure apparatus. The method in the present exemplary embodiment can be applied to the patterning of the photoelectric conversion chip 21 and the peripheral circuit chip 22.

[0233] Reference FIG. 24A An apparatus 9191 including a semiconductor device 930 is described. FIG. 24C is a schematic diagram illustrating an apparatus 9191 including a semiconductor device 930 according to the present exemplary embodiment. The apparatus 9191 including a semiconductor device 930 is described in detail. The semiconductor device 930 has characteristics in the structure and / or the manufacturing method described above with respect to the semiconductor device APR. The semiconductor device 930 includes a central portion 901 in which the circuit unit 900 is arranged, and a peripheral portion 902 located around the central portion 901. Reference is made to FIG. 24A The pixel portion 11 described is equivalent to the central portion 901, and reference is made to FIG. 24A The signal processing circuit 12 described is provided in the peripheral portion 902. The semiconductor device 930 includes a semiconductor device portion 910, and the semiconductor device portion 910 includes the semiconductor layer 100 included in the semiconductor device APR. In addition to the semiconductor device portion 910 including the semiconductor layer 100, the semiconductor device 930 can include a package 920 in which the semiconductor device portion 910 is housed. The package 920 can include a base to which the semiconductor device portion 910 is fixed, and a cover such as a glass film facing the semiconductor device portion 910. The package 920 can further include a bonding member such as a bonding wire or a bump interconnecting a terminal provided in the base and a terminal provided in the semiconductor device portion 910.

[0234] The apparatus 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, an image device 970, a storage device 980, and a mechanical device 990. The optical device 940 is associated with the semiconductor device 930. The optical device 940 includes, for example, a lens, a shutter, a mirror, and a filter. The control device 950 controls the semiconductor device 930. The control device 950 is a semiconductor device such as an application specific integrated circuit (ASIC).

[0235] The processing device 960 processes a signal that has been output from the semiconductor device 930 or a signal to be input to the semiconductor device 930. The processing device 960 is a semiconductor device such as a central processing unit (CPU) or an ASIC for configuring an analog front end (AFE) or a digital front end (DFE).

[0236] The image device 970 is an electroluminescence (EL) display device or a liquid crystal display device for displaying information (image) obtained by the semiconductor device 930 in a case where the semiconductor device 930 is an optical-electric conversion device (imaging device). The image device 970 can be an optical-electric conversion device (imaging device) for capturing an image to be displayed on the semiconductor device 930 in a case where the semiconductor device 930 is a display device.

[0237] The storage device 980 is a magnetic device or a semiconductor device portion for storing information (image) processed by the semiconductor device 930. The storage device 980 is a volatile memory such as a static random access memory (SRAM) or a dynamic random access memory (DRAM) or a non-volatile memory such as a flash memory or a hard disk drive.

[0238] The mechanical device 990 includes a moving portion or a propelling portion such as a motor or an engine. The apparatus 9191 displays a signal output from the semiconductor device 930 on the image device 970 or transmits a signal output from the semiconductor device 930 to the outside via a communication device (not illustrated) included in the apparatus 9191. For such a reason, it is advantageous that the apparatus 9191 includes the storage device 980 and the processing device 960 in addition to a storage circuit or a calculation circuit included in the semiconductor device 930. The mechanical device 990 can be configured to be controlled based on a signal output from the semiconductor device 930.

[0239] Further, the device 9191 is suitable for an electronic device such as an information terminal (for example, a smartphone or a wearable terminal) or a camera (for example, a lens-interchangeable camera, a compact camera, a video camera, or a monitoring camera) having an image capturing function. The mechanical device 990 in the camera can drive components of the optical device 940 to perform zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can drive the semiconductor device 930 to perform image stabilization operation.

[0240] Further, the device 9191 can be a transport device such as a vehicle, a ship or a vessel, or an aircraft. The mechanical device 990 in the transport device can be used as a moving device. The device 9191 used as a transport device is suitable for a device for transporting the semiconductor device 930 or a device for assisting or automating driving (steering) using an image capturing function. The processing device 960 for assisting or automating driving (steering) can perform processing for operating the mechanical device 990 used as a moving device based on information obtained by the semiconductor device 930. Alternatively, the device 9191 can be medical equipment such as an endoscope, measuring equipment including a range-finding sensor, analysis equipment including an electron microscope, or office equipment including a copier or a printer.

[0241] According to the above-described example embodiments, it is possible to form superior wiring. Thus, it is possible to improve the value of the semiconductor device. The improvement of the value as mentioned herein refers to at least one of adding a function, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental load, reducing cost, reducing size, and reducing weight.

[0242] Thus, the use of the semiconductor device 930 according to the present example embodiments for the device 9191 also makes it possible to improve the value of the device 9191. For example, when the semiconductor device 930 is installed on a transport device to be used to perform image capturing outside the transport device or to measure an external environment thereof, superior performance can be achieved. Thus, in manufacturing and selling the transport device, it is determined to be advantageous to install the semiconductor device according to the present example embodiments on the transport device in terms of improving the performance of the transport device itself. In particular, the semiconductor device 930 is suitable for a transport device that performs driving assistance and / or automated driving of the transport device using information obtained by the semiconductor device.

[0243] <Tenth Example Embodiment>

[0244] FIG. 25Ais a schematic block diagram of a photoelectric conversion device according to the present exemplary embodiment. The photoelectric conversion device 1101 includes: an imaging region 1102 in which a plurality of pixels are arranged in a matrix manner; a vertical scanning circuit 1103 configured to drive each section included in each pixel; a horizontal scanning circuit 1105 configured to read out an electric signal output from each pixel; and an output unit 1106 configured to output the electric signal output from each pixel. The output unit 1106 outputs the electric signal to the outside of the photoelectric conversion device 1101. The photoelectric conversion device 1101 outputs an electric signal corresponding to the amount of light incident on the imaging region 1102. Further, the photoelectric conversion device 1101 includes a control unit 1104 that controls the operation of the vertical scanning circuit 1103, the horizontal scanning circuit 1105, and the output unit 1106. The control unit 1104 can also be referred to as a timing generator.

[0245] FIG. 22 is an equivalent circuit diagram of a pixel included in the imaging region 1102. Although a configuration consisting of three rows and two columns is illustrated in FIG. 25B for simplicity, the number of pixels is not limited thereto. Generally, several tens of millions of pixels are arranged in the imaging region 1102. Further, although three output lines 1018-1, 1018-2, and 1018-3 are arranged with respect to one column, the number of output lines is not limited thereto and more output lines can be arranged.

[0246] Each unit pixel 1201 includes a photoelectric conversion section 1001, a floating diffusion section 1002, and a transfer section 1011 provided between the photoelectric conversion section 1001 and the floating diffusion section 1002. Further, each unit pixel 1201 includes a capacity switching section 1012 configured to switch the capacity of the floating diffusion section 1002 as necessary. Additionally, each unit pixel 1201 includes a reset section 1013 configured to reset the floating diffusion section 1002, an amplification section 1014 configured to output a signal output from the floating diffusion section 1002, and a row selection section 1015 provided as necessary.

[0247] The photoelectric conversion section 1001 receives light incident on the unit pixel 1201 and generates electric charges corresponding to the amount of received light. The floating diffusion section 1002 temporarily stores the electric charges transferred from the photoelectric conversion section 1001 and, at the same time, functions as a charge-to-voltage conversion section that converts the stored electric charges into a voltage signal.

[0248] The transfer section 1011 driven by the signal pTX output from the vertical scanning circuit 1103 transfers the electric charges generated by the photoelectric conversion section 1001 to the floating diffusion section 1002.

[0249] The capacitance of the floating diffusion section 1002 is switched by the capacitance switching section 1012 driven by the signal pFDINC. Bringing the capacitance switching section 1012 into the on state makes it possible to add the gate capacitance section of the capacitance switching section 1012 to the floating diffusion section 1002. The signal pFDINC can be output from the vertical scanning circuit 1103 or can be output from the control unit 1104. In the case where the signal pFDINC is output from the vertical scanning circuit 1103, the capacitance switching section 1012 can switch the capacitance of the floating diffusion section 1002 for each row of pixels. In the case where the signal pFDINC is output from the control unit 1104, the capacitance switching section 1012 can switch the capacitance of the floating diffusion section 1002 in common for the entire imaging region 1102.

[0250] The reset section 1013 is driven by the signal pRES output from the vertical scanning circuit 1103. At this time, bringing the reset section 1013 and the capacitance switching section 1012 into the on state at the same time makes it possible to reset the floating diffusion section 1002.

[0251] The amplification section 1014 amplifies the voltage signal obtained by the conversion performed by the floating diffusion section 1002 and then outputs the amplified voltage signal as a pixel signal. The row selection section 1015 driven by the row selection drive pulse pSEL outputs the pixel signal output from the amplification section 1014 to any one of the output lines 1018-1, 1018-2, and 1018-3.

[0252] FIG. 25A is a timing chart obtained when a pixel signal obtained at the time of output at low luminance is taken as an example. The horizontal axis indicates time and the vertical axis indicates voltage, and the respective lines correspond to FIG. 25C The drive pulses illustrated in FIG. 12.

[0253] At time t1, the vertical scanning circuit 1103 brings the capacitance switching section 1012, the reset section 1013, and the row selection section 1015 of the pixels in a predetermined row into the on state. With this operation, the vertical scanning circuit 1103 selects the pixels and resets the floating diffusion section 1002. In the following description, the control of the pixels in the predetermined row that have been selected at that time is described.

[0254] At time t2, the vertical scanning circuit 1103 brings the capacitance switching section 1012 into the off state. This makes it possible to make the capacitance of the floating diffusion section 1002 small at the time of readout and thus reduce noise. Furthermore, at this time, the vertical scanning circuit 1103 outputs the signal that has been output to the output line 1018-m (m is any one of 1 to 3) to the output unit 1106 as a reset level signal via the amplification section 1014. Furthermore, when the output line is indicated in an all-encompassing manner, the output line 1018-m can be simply referred to as "output line 1018".

[0255] At time t3, the vertical scanning circuit 1103 brings the transfer section 1011 into an ON state. With this operation, the vertical scanning circuit 1103 transfers the charge accumulated in the photoelectric conversion section 1001 to the floating diffusion section 1002.

[0256] At time t4, the vertical scanning circuit 1103 brings the transfer section 1011 into an OFF state. The amplification section 1014 outputs a signal (pixel signal) corresponding to the charge of the floating diffusion section 1002 to the corresponding output line 1018-m. The pixel signal output to the output line 1018-m is subjected to processing such as amplification, noise reduction, and AD conversion by the corresponding column circuit. Then, the processed pixel signal is output from the column circuit in each column to the output unit 1106 by horizontal scanning performed by the horizontal scanning circuit 1105.

[0257] FIG. 25A is a plan view of the unit pixel 1201 in the present exemplary embodiment. The same or corresponding elements as those illustrated in FIG. 26A are assigned the corresponding same reference numerals. Furthermore, although each region is represented by a rectangle for simplicity in the plan view, the rectangle does not represent the shape of each portion, but indicates that each portion is located at least at the region. In the pixel transistor region 1401, for example, the reset section 1013, the amplification section 1014, and the row selection section 1015 are arranged. FIG. 22 The unit pixels 1201 arranged in two rows and two columns are illustrated. The output lines 1018-1 to 1018-3 extend along a first direction. Among the plurality of unit pixels, a first pixel includes the photoelectric conversion section 1001-1. A second pixel adjacent to the first pixel along a second direction different from the first direction includes the photoelectric conversion section 1001-2. Furthermore, a third pixel adjacent to the second pixel along the first direction includes the photoelectric conversion section 1001-3. In addition, a fourth pixel adjacent to the first pixel along the first direction includes the photoelectric conversion section 1001-4. The photoelectric conversion section 1001-3 is adjacent to the photoelectric conversion section 1001-4 along the second direction. FIG. 26B In the present exemplary embodiment, the first direction and the second direction are directions perpendicular to each other in the plan view when viewed from the top of the semiconductor substrate. The third pixel adjacent to the second pixel along the first direction includes the photoelectric conversion section 1001-3. In addition, the fourth pixel adjacent to the first pixel along the first direction includes the photoelectric conversion section 1001-4. The photoelectric conversion section 1001-3 is adjacent to the photoelectric conversion section 1001-4 along the second direction.

[0258] FIG. 26A is a cross-sectional view taken along the line G-G’ as the second position in FIG. 26C In addition, FIG. 26A is a cross-sectional view taken along the line G-G’ as the second position in FIG. 27Athe first pixel and the photoelectric conversion section 1001-3 of the third pixel. The second position is between the photoelectric conversion section 1001-1 of the first pixel and the photoelectric conversion section 1001-2 of the second pixel. Further, for convenience of explanation, wirings other than the output line 1018 are omitted from the drawing. The first output line 1018-1, the second output line 1018-2, and the third output line 1018-3 are configured into the same wiring layer. Here, as viewed in the G-G' cross section, the interval between the first output line 1018-1 and the second output line 1018-2 is denoted by S1A, and the interval between the second output line 1018-2 and the third output line 1018-3 is denoted by S2A. Further, the interval between the first output line 1018-1 and the third output line 1018-3 is denoted by S3A. Further, as viewed in the H-H' cross section, the interval between the first output line 1018-1 and the second output line 1018-2 is denoted by S1B, the interval between the second output line 1018-2 and the third output line 1018-3 is denoted by S2B, and the interval between the first output line 1018-1 and the third output line 1018-3 is denoted by S3B.

[0259] In the present exemplary embodiment, the wiring capacitance of the second output line 1018-2 located at the center of the first output line 1018-1, the second output line 1018-2, and the third output line 1018-3 is reduced. In the present exemplary embodiment, with respect to the distance between the first output line 1018-1 and the second output line 1018-2 and the distance between the second output line 1018-2 and the third output line 1018-3, the respective directions at the second position are made larger than the respective directions at the first position. Specifically, the interval S1A is made larger than the interval S1B, the interval S2A is made larger than the interval S2B, and the interval S3A is made larger than the interval S3B. This reduces the parasitic capacitance of the second output line 1018-2. This reduction in parasitic capacitance makes it possible to accelerate the statically determinate state of the potential of the output line 1018-2. Thus, it is possible to improve the readout speed of the pixel signal. Further, in the present exemplary embodiment, four control lines for transferring the signal pRES, the signal pFDINC, the signal pTX, and the signal pSEL, respectively, are provided with respect to the pixels in one row. As ​The distance between one end of the control line group including four control lines (the control line for the signal pRES) and the other end of the control line group (the control line for the signal pSEL) is distance D1, as illustrated in the drawing. On the other hand, as output lines for outputting pixel signals with respect to pixels in a column, three output lines 1018-1 to 1018-3 are provided. Between the plurality of transistor regions of adjacent unit pixels 1201, the distance between one end of the output line group including the output lines 1018-1 to 1018-3 (the output line 1018-1) and the other end of the output line group (the output line 1018-3) is distance D3. Further, between the plurality of photoelectric conversion sections 1001 of adjacent unit pixels 1201, the distance between one end of the output line group (the output line 1018-1) and the other end of the output line group (the output line 1018-3) is distance D2, which is greater than distance D3. In terms of one row and one column, more control lines are provided than output lines. Therefore, if even the distance between one end of the output line group and the other end thereof among the plurality of photoelectric conversion sections 1001 is set to distance D3, the distance between unit pixels among a plurality of rows tends to become greater than the distance between unit pixels among a plurality of columns. In terms of the opening of the photoelectric conversion section 1001 of one unit pixel 1201, the length thereof taken along the direction in which unit pixels in a plurality of rows are arranged side by side tends to become greater than the length thereof taken along the direction in which unit pixels in a plurality of columns are arranged side by side. On the other hand, in the present example embodiment, a portion in which the interval from each of the output lines 1018-1 and 1018-3 to the output line 1018-2 is expanded is provided in a region between the plurality of photoelectric conversion sections 1001. In terms of the opening of the photoelectric conversion section 1001 of one unit pixel 1201, this makes it possible to contribute to making the length thereof taken along the direction in which unit pixels in a plurality of rows are arranged side by side consistent with the length thereof taken along the direction in which unit pixels in a plurality of columns are arranged side by side. This makes it possible to make the crosstalk possibility between a plurality of rows of unit pixels 1201 consistent with the crosstalk possibility between a plurality of columns thereof. Here, a case is considered in which the plurality of unit pixels 1201 are provided with color filters having a Bayer array. With respect to a unit pixel 1201 provided with a color filter through which light of a wavelength corresponding to green light is transmitted, a unit pixel 1201 located in an adjacent row thereof and a unit pixel 1201 located in an adjacent column thereof are provided with respective color filters through which light of a wavelength corresponding to a different color is transmitted. Generally, a unit pixel 1201 provided with a color filter through which light of a wavelength corresponding to red light is transmitted and a unit pixel 1201 provided with a color filter through which light of a wavelength corresponding to blue light is transmitted are located in adjacent rows and adjacent columns, respectively, or in adjacent columns and adjacent rows, respectively.In this case, if the crosstalk possibility between the plurality of rows of unit pixels 1201 and the crosstalk possibility between the plurality of columns of unit pixels 1201 are different from each other, one of the signals output from the unit pixels 1201 for red and blue becomes likely to cause crosstalk with the unit pixels 1201 for green. This makes it likely to produce an image close to a color different from the original color in the image generated from the pixel signals output from the photoelectric conversion device. Thus, a degradation in image quality can occur. On the other hand, in the present exemplary embodiment, since it is possible to make the crosstalk between the plurality of rows and the crosstalk between the plurality of columns consistent, it becomes possible to make the crosstalk from the unit pixels 1201 for red consistent with the crosstalk from the unit pixels 1201 for blue. This makes it possible to contribute to acquisition of an image expressing the original color of the subject.

[0260] <Eleventh Exemplary Embodiment>

[0261] ​ is a plan view of the unit pixel 1201 in the present exemplary embodiment. The same or corresponding elements as those illustrated in ​ are assigned the corresponding same reference numerals. Further, although each region is represented by a rectangle for the sake of simplicity in the plan view, the rectangle does not represent the shape of each portion, but indicates that each portion is located at least at the region. In the pixel transistor region 1501, for example, the reset section 1013, the amplification section 1014, and the row selection section 1015 are arranged. Further, in the front-illuminated photoelectric conversion device, the waveguide structure 1502 can improve the pixel sensitivity by concentrating light onto the photoelectric conversion section 1001. However, it is necessary to arrange the waveguide structure 1502 in such a manner as not to overlap with any wiring.

[0262] ​ is a cross-sectional view taken along the line G-G' (first position) in ​ Further, in ​ is a cross-sectional view taken along the line G-G' (second position) in ​A cross-sectional view taken along the line H-H' (second position) in FIG. 10A. In the first position, the distance from one end of the first output line 1018-1 to one end of the fourth output line 1018-4 is indicated by the distance D4. Further, in the second position, the distance from one end of the first output line 1018-1 to one end of the fourth output line 1018-4 is indicated by the distance D5. There is a relationship in which the distance D5 is greater than the distance D4. Further, for ease of explanation, the wiring other than the output lines 1018 is omitted from the illustration. The first output line 1018-1, the second output line 1018-2, the third output line 1018-3, and the fourth output line 1018-4 are configured with the same wiring layer. Here, as viewed in the G-G' cross section, the interval between the first output line 1018-1 and the second output line 1018-2 is denoted by S1A, and the interval between the second output line 1018-2 and the third output line 1018-3 is denoted by S2A. In addition, the interval between the first output line 1018-1 and the third output line 1018-3 is denoted by S3A. Further, as viewed in the H-H' cross section, the interval between the first output line 1018-1 and the second output line 1018-2 is denoted by S1B, the interval between the second output line 1018-2 and the third output line 1018-3 is denoted by S2B, and the interval between the first output line 1018-1 and the third output line 1018-3 is denoted by S3B.

[0263] In the present exemplary embodiment, the wiring capacitance of the second output line 1018-2 among the first output line 1018-1, the second output line 1018-2, the third output line 1018-3, and the fourth output line 1018-4 is reduced. Specifically, the interval S1B is made greater than the interval S1A, and the interval S3B is made greater than the interval S3A. Further, the wiring capacitance of the third output line 1018-3 can also be reduced by a method similar to that for the second output line 1018-2. This reduces the parasitic capacitance of each of the second output line 1018-2 and the third output line 1018-3 located at the center. This reduction in parasitic capacitance enables acceleration of the settling state of each of the reset level signal and the pixel signal. Thus, it is possible to improve the readout speed of the pixel signal. Further, it is possible to prevent or reduce the reduction in the diameter of the waveguide structure 1502 caused by the output lines 1018-1 to 1018-3. This enables prevention or reduction of the reduction in the sensitivity of the photoelectric conversion section 1001.

[0264] <Twelfth Exemplary Embodiment>

[0265] ​ is a plan view of the unit pixel 1201 in the present exemplary embodiment. With ​Elements that are identical or corresponding in the diagram are assigned corresponding identical reference numerals. Furthermore, although each region is represented by a rectangle in the plan view for simplicity, the rectangle does not represent the shape of each part, but rather indicates that each part is at least located in that region. In the pixel transistor region 1601, for example, a reset section 1013, an amplification section 1014, and a row selection section 1015 are arranged. Furthermore, in the back-illuminated photoelectric conversion device, the shielding wiring 1602 can increase pixel sensitivity by reflecting light that has passed through the silicon substrate toward the photoelectric conversion section 1001. Therefore, a microlens is configured to be disposed above a first surface of the semiconductor substrate on which the photoelectric conversion section 1001 is disposed, serving as a light incident surface, and a wiring layer including the shielding wiring 1602 is configured to be disposed above a second surface facing the first surface. The shielding wiring 1602 is a metal film made of metal (including alloys).

[0266] ​ It is along ​ The cross-sectional view taken from line G-G', which is the first position in the diagram. Furthermore, ​ It is along ​ The diagram shows a cross-sectional view taken along line H-H', which represents the second position. In this exemplary embodiment, the first position is located in the region between the photoelectric conversion unit 1001-1 of the first pixel and the photoelectric conversion unit 1001-2 of the second pixel. The second position is located in the region between the photoelectric conversion unit 1001-1 of the first pixel and the photoelectric conversion unit 1001-3 of the third pixel. Furthermore, for ease of explanation, wiring other than shielding wiring 1602 is omitted from the illustration. The first output line 1018-1, the second output line 1018-2, the third output line 1018-3, and the fourth output line 1018-4 are configured with the same wiring layer. Here, as observed in the G-G' cross-section, the interval between the first output line 1018-1 and the second output line 1018-2 is represented by S1A, the interval between the second output line 1018-2 and the third output line 1018-3 is represented by S2A, and the interval between the first output line 1018-1 and the third output line 1018-3 is represented by S3A. Furthermore, as observed in the H-H' cross section, the interval between the first output line 1018-1 and the second output line 1018-2 is represented by S1B, the interval between the second output line 1018-2 and the third output line 1018-3 is represented by S2B, and the interval between the first output line 1018-1 and the third output line 1018-3 is represented by S3B.

[0267] In the present exemplary embodiment, the wiring capacitance of the second output line 1018-2 among the first output line 1018-1, the second output line 1018-2, the third output line 1018-3, and the fourth output line 1018-4 is reduced. In the present exemplary embodiment, the respective directions in the second position are made larger than the respective directions in the first position with respect to the distance between the first output line 1018-1 and the second output line 1018-2 and the distance between the second output line 1018-2 and the third output line 1018-3. Specifically, the interval S1B is made larger than the interval S1A, and the interval S3B is made larger than the interval S3A. Furthermore, the wiring capacitance of the third output line 1018-3 can also be reduced by a similar method to that for the second output line 1018-2. This reduces the parasitic capacitance of each of the second output line 1018-2 and the third output line 1018-3 located at the center. As a result, it is possible to accelerate the settling state of each of the reset level signal and the pixel signal, and thus it is possible to improve the readout speed of the pixel signal.

[0268] <Thirteenth Exemplary Embodiment>

[0269] ​ is a plan view of the unit pixel 1201 in the present exemplary embodiment. The same or corresponding elements as those illustrated in Figure 22 are assigned the respective same reference numerals. Furthermore, although each region is represented by a rectangle for the sake of simplicity in the plan view, the rectangle does not represent the shape of each portion, but indicates that each portion is located at least at the region. In the pixel transistor region 1701, for example, the reset section 1013, the amplification section 1014, and the row selection section 1015 are arranged.

[0270] Figure 27B is a cross-sectional view taken along the line G-G’ in Figure 27A . Furthermore, Figure 27C is a cross-sectional view taken along the line H-H’ in Figure 27A . Furthermore, for the sake of convenience in explanation, the wiring other than the output line 1018 is omitted from the illustration. In the G-G’ cross section, the first output line 1018-1 and the third output line 1018-3 are configured with the same wiring layer, but are configured with a wiring layer different from that of the second output line 1018-2. In the H-H’ cross section, the first output line 1018-1 and the third output line 1018-3 are switched to the same wiring layer as that of the second output line 1018-2 via the connection section 1702.

[0271] In the present exemplary embodiment, the wiring capacitance of the second output line 1018-2 located in the center among the first output line 1018-1, the second output line 1018-2, and the third output line 1018-3 is reduced. Specifically, the wiring layers of the first output line 1018-1 and the third output line 1018-3 located on the outer side are switched. This makes it possible to reduce the parasitic capacitance of the second output line 1018-2 and accelerate the steady state of each of the reset signal and the pixel signal. Thus, this makes it possible to improve the readout speed of the pixel signal.

[0272] <Fourteenth Exemplary Embodiment>

[0273] Figure 28A is a plan view of a unit pixel 1201 in the present exemplary embodiment. The same or corresponding elements as those illustrated in Figure 22 are assigned the corresponding same reference numerals. Furthermore, although each region is represented by a rectangle for the sake of simplicity in the plan view, the rectangle does not represent the shape of each portion, but indicates that each portion is located at least at the region. In the pixel transistor region 1801, for example, the reset section 1013, the amplification section 1014, and the row selection section 1015 are arranged.

[0274] Figure 28B is a cross-sectional view taken along the line G-G’ in Figure 28A Furthermore, Figure 28C is a cross-sectional view taken along the line H-H’ in Figure 28A Furthermore, for the sake of convenience of explanation, the wiring other than the output line 1018 is omitted from the illustration. In the G-G’ cross section, the first output line 1018-1 and the third output line 1018-3 are arranged in the same wiring layer, but are arranged in a wiring layer different from that of the second output line 1018-2. In the H-H’ cross section, the second output line 1018-2 is switched to the same wiring layer as that of the first output line 1018-1 and the third output line 1018-3 via the connection section 1802.

[0275] In the present exemplary embodiment, in order to reduce the wiring capacitance of the second output line 1018-2 located in the center among the first output line 1018-1, the second output line 1018-2, and the third output line 1018-3, the wiring layer for the second output line 1018-2 located in the center is switched. This makes it possible to reduce the parasitic capacitance of the second output line 1018-2 and accelerate the steady state of each of the reset signal and the pixel signal. Thus, this makes it possible to improve the readout speed of the pixel signal.

[0276] The semiconductor device in each of the above-described tenth to fourteenth exemplary embodiments can be applied to Figure 20AThe semiconductor device APR illustrated in FIG. 12. Furthermore, each of the above-described semiconductor devices can also be applied to Figure 20B The semiconductor device 930 illustrated in FIG. 13.

[0277] The present application is not limited to the above-described example embodiments, but can be modified in various ways. For example, examples in which a part of the configuration of any of the example embodiments is added to that of another example embodiment or in which a part of the configuration of any of the example embodiments is replaced with that of another example embodiment are also example embodiments of the present application. Furthermore, the disclosure in this specification includes not only what is described in this specification but also all items that can be understood from this specification and drawings accompanying this specification. Furthermore, the disclosure in this specification includes a complementary set of the concepts described in this specification. Therefore, if there is a description indicating, for example, "A is B" in this specification, it can be said that the description indicating "A is not B" is disclosed in this specification even when the description indicating "A is not B" is omitted. This is because, in a case where there is a description indicating "A is B", a case where "A is not B" is assumed is considered.

[0278] While the present application has been described with reference to example embodiments, it is to be understood that the application is not limited to the disclosed example embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all the modifications and equivalent structures and functions.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes multiple wirings, each having an damascene structure, on a semiconductor layer. The plurality of wirings includes first wirings and second wirings that are adjacent to each other. The distance between the first end and the second end of the first wiring is greater than 33mm. Wherein, the first wiring, extending along the direction of the first wiring, includes a first portion, a second portion, and a third portion located between the first portion and the second portion. Wherein, the width of the first portion and the width of the second portion are each less than 180 nm. The width of the third part is greater than the width of both the first part and the width of the second part. The first portion is located between the first end and the third portion along the stated direction. The second portion is located between the second end and the third portion along the stated direction. Wherein, the first wiring along the direction includes a fourth portion located between the first end and the first portion, a fifth portion located between the fourth portion and the first portion, a sixth portion located between the second end and the second portion, and a seventh portion located between the sixth portion and the second portion, and The width of the fifth part and the width of the seventh part are each greater than the width of the first part, the width of the second part, the width of the fourth part, and the width of the sixth part.

2. A semiconductor device, characterized in that, The semiconductor device includes multiple wirings, each having an damascene structure, on a semiconductor layer. The plurality of wirings includes first wirings and second wirings that are adjacent to each other. Wherein, the first wiring, extending along the direction of the first wiring, includes a first portion, a second portion, and a third portion located between the first portion and the second portion. Wherein, the distance between the first portion and the second portion of the first wiring is greater than 33mm. Wherein, the width of the third portion is the maximum width of the first wiring within the range from the first portion to the second portion and is less than 180nm. The first portion is located along the stated direction between the first end of the first wiring and the third portion. The second portion is located along the stated direction between the second end of the first wiring and the third portion. Wherein, the first wiring along the direction includes a fourth portion located between the first end and the first portion, a fifth portion located between the fourth portion and the first portion, a sixth portion located between the second end and the second portion, and a seventh portion located between the sixth portion and the second portion, and The width of the fifth part and the width of the seventh part are each greater than the width of the first part, the width of the second part, the width of the fourth part, and the width of the sixth part.

3. The semiconductor device according to claim 1, wherein, Each of the difference between the width of the third portion and the width of the first portion and the difference between the width of the third portion and the width of the second portion is greater than 50 nm.

4. The semiconductor device according to claim 2, wherein, Each of the difference between the width of the third portion and the width of the first portion and the difference between the width of the third portion and the width of the second portion is greater than 50 nm.

5. The semiconductor device according to claim 1, wherein, The difference between the width of the third part and the width of the first part is less than the width of the first part, and the difference between the width of the third part and the width of the second part is less than the width of the second part.

6. The semiconductor device according to claim 2, wherein, The difference between the width of the third part and the width of the first part is less than the width of the first part, and the difference between the width of the third part and the width of the second part is less than the width of the second part.

7. The semiconductor device according to claim 1, wherein, The width of the third part is greater than 110 nm.

8. The semiconductor device according to claim 2, wherein, The width of the third part is greater than 110 nm.

9. The semiconductor device according to claim 1, wherein, The distance between the third portion and the second wiring is greater than the width of the first portion and the width of the second portion.

10. The semiconductor device according to claim 2, wherein, The distance between the third portion and the second wiring is greater than the width of the first portion and the width of the second portion.

11. The semiconductor device according to claim 1, wherein, The distance between the first portion and the second wiring, and the distance between the second portion and the second wiring, are each less than the width of the third portion.

12. The semiconductor device according to claim 2, wherein, The distance between the first portion and the second wiring, and the distance between the second portion and the second wiring, are each less than the width of the third portion.

13. The semiconductor device according to claim 1, wherein, The length of the second portion along the direction is greater than the width of the first portion and the width of the second portion.

14. The semiconductor device according to claim 2, wherein, The length of the second portion along the direction is greater than the width of the first portion and the width of the second portion.

15. The semiconductor device according to claim 1, wherein, The semiconductor layer includes multiple photoelectric conversion units.

16. The semiconductor device according to claim 2, wherein, The semiconductor layer includes multiple photoelectric conversion units.

17. A semiconductor device, characterized in that, The semiconductor device includes: A plurality of unit pixels, the plurality of unit pixels being arranged in a plurality of rows and a plurality of columns, and each of the plurality of unit pixels including a photoelectric conversion unit; and Multiple output lines, which are connected to and transmit the output of a unit pixel in a column. The plurality of output lines include at least a first output line, a second output line having a portion adjacent to the first output line, and a third output line having a portion adjacent to the second output line. Each of the first, second, and third output lines includes a portion extending along a first direction. The first output line, the second output line, and the third output line pass through a first position and a second position different from the first position, and Wherein, at least two of the distances between the first and second output lines, the distances between the second and third output lines, and the distances between the first and third output lines are longer in the second position than in the first position.

18. The semiconductor device according to claim 17, in, The plurality of unit pixels includes a first pixel and a second pixel that are adjacent to each other in a direction different from the first direction, and a third pixel that is adjacent to the second pixel in the first direction. Wherein, the first position is the position between the corresponding photoelectric conversion units of the first pixel and the second pixel, and The second position is the position between the corresponding photoelectric conversion units of the first pixel and the third pixel.

19. The semiconductor device according to claim 17, in, The plurality of unit pixels includes a first pixel and a second pixel that are adjacent to each other in a direction different from the first direction, and a third pixel that is adjacent to the second pixel in the first direction. Wherein, the first position is the position between the corresponding photoelectric conversion units of the first pixel and the third pixel, and The second position is the position between the corresponding photoelectric conversion units of the first pixel and the second pixel.

20. The semiconductor device according to claim 17, in, The plurality of unit pixels are disposed on a semiconductor substrate, and a wiring layer is disposed above a second surface facing the semiconductor substrate on which light is incident. The wiring layer includes a metal film at the location where it overlaps with each photoelectric conversion unit in the plan view.

21. The semiconductor device according to claim 17, wherein, The number of wiring layers in which the first output line extends is greater than the number of wiring layers in which the second output line extends.

22. The semiconductor device according to claim 17, wherein, The second output line extends through a greater number of wiring layers than the first output line extends through a greater number of wiring layers.

23. A method for manufacturing a semiconductor device, characterized in that, The method includes: Fabricating a wafer, the wafer comprising a semiconductor layer and an insulating film disposed on the semiconductor layer; Expose the positive photoresist film disposed on the insulating film; The photoresist film is developed to form a resist pattern from the photoresist film; The insulating film is patterned using the resist to form trenches on the insulating film; and Wiring is formed in the trench. The wafer includes a first region, a second region, and a third region located between the first region and the second region, and the trench extends from the first region to the second region via the third region. The exposure includes a first exposure photograph for exposing the photoresist film on the first region and the third region, and a second exposure photograph after the first exposure photograph for exposing the photoresist film on the second region and the third region. Wherein, the wiring, extending along the direction of the wiring, includes a first portion located in the first region, a second portion located in the second region, and a third portion located in the third region, and The width of the third part is greater than the width of both the first part and the width of the second part. The photoresist film obtained between the first exposure and the second exposure in the exposure process includes a first exposure portion located on the first region and exposed by the first exposure, a second exposure portion located on the third region and exposed by the first exposure, and a third exposure portion located between the first exposure portion and the second exposure portion and exposed by the first exposure. The photoresist film obtained after the second exposure in the exposure process includes a fourth exposure portion located on the second region and exposed by the second exposure, a fifth exposure portion located on the third region and exposed by the second exposure, and a sixth exposure portion located between the fourth and fifth exposure portions and exposed by the second exposure. Wherein, at least a portion of the fifth exposure portion includes the second exposure portion. In the development process, the first exposure portion, the second exposure portion, the third exposure portion, the fourth exposure portion, the fifth exposure portion, and the sixth exposure portion are removed, and The width of the third exposure portion is greater than the width of the first exposure portion.

24. A method for manufacturing a semiconductor device, characterized in that, The method includes: Fabricating a wafer, the wafer comprising a semiconductor layer and an insulating film disposed on the semiconductor layer; Expose the positive photoresist film disposed on the insulating film; The photoresist film is developed to form a resist pattern from the photoresist film; The insulating film is patterned using the resist to form trenches on the insulating film; and Wiring is formed in the trench. The wafer includes a first region, a second region, and a third region located between the first region and the second region, and the trench extends from the first region to the second region via the third region. The exposure includes a first exposure photograph for exposing the photoresist film on the first region and the third region, and a second exposure photograph after the first exposure photograph for exposing the photoresist film on the second region and the third region. Wherein, the wiring, extending along the direction of the wiring, includes a first portion located in the first region, a second portion located in the second region, and a third portion located in the third region, and The width of the third part is greater than the width of both the first part and the width of the second part. The photoresist film obtained between the first exposure and the second exposure in the exposure process includes a first exposure portion located on the first region and exposed by the first exposure, a second exposure portion located on the third region and exposed by the first exposure, and a third exposure portion located between the first exposure portion and the second exposure portion and exposed by the first exposure. The photoresist film obtained after the second exposure in the exposure process includes a fourth exposure portion located on the second region and exposed by the second exposure, a fifth exposure portion located on the third region and exposed by the second exposure, and a sixth exposure portion located between the fourth and fifth exposure portions and exposed by the second exposure. Wherein, at least a portion of the fifth exposure portion includes the second exposure portion. In the development process, the first exposure portion, the second exposure portion, the third exposure portion, the fourth exposure portion, the fifth exposure portion, and the sixth exposure portion are removed, and The width of the second exposure portion is smaller than the width of the third exposure portion.

25. A method for manufacturing a semiconductor device, characterized in that, The method includes: Fabricating a wafer, the wafer comprising a semiconductor layer and an insulating film disposed on the semiconductor layer; Expose the positive photoresist film disposed on the insulating film; The photoresist film is developed to form a resist pattern from the photoresist film; The insulating film is patterned using the resist to form trenches on the insulating film; and Wiring is formed in the trench. The wafer includes a first region, a second region, and a third region located between the first region and the second region, and the trench extends from the first region to the second region via the third region. The exposure includes a first exposure photograph for exposing the photoresist film on the first region and the third region, and a second exposure photograph after the first exposure photograph for exposing the photoresist film on the second region and the third region. Wherein, the wiring, extending along the direction of the wiring, includes a first portion located in the first region, a second portion located in the second region, and a third portion located in the third region, and The width of the third part is greater than the width of both the first part and the width of the second part. The photoresist film obtained between the first exposure and the second exposure in the exposure process includes a first exposure portion located on the first region and exposed by the first exposure, a second exposure portion located on the third region and exposed by the first exposure, and a third exposure portion located between the first exposure portion and the second exposure portion and exposed by the first exposure. The photoresist film obtained after the second exposure in the exposure process includes a fourth exposure portion located on the second region and exposed by the second exposure, a fifth exposure portion located on the third region and exposed by the second exposure, and a sixth exposure portion located between the fourth and fifth exposure portions and exposed by the second exposure. Wherein, at least a portion of the fifth exposure portion includes the second exposure portion. In the development process, the first exposure portion, the second exposure portion, the third exposure portion, the fourth exposure portion, the fifth exposure portion, and the sixth exposure portion are removed, and Wherein, the difference between the width of the first exposure portion and the width of the third exposure portion is greater than the difference between the width of the second exposure portion and the width of the third exposure portion.

26. A method for manufacturing a semiconductor device, characterized in that, The method includes: Fabricating a wafer, the wafer comprising a semiconductor layer and an insulating film disposed on the semiconductor layer; Expose the positive photoresist film disposed on the insulating film; The photoresist film is developed to form a resist pattern from the photoresist film; The insulating film is patterned using the resist to form trenches on the insulating film; and Wiring is formed in the trench. The wafer includes a first region, a second region, and a third region located between the first region and the second region, and the trench extends from the first region to the second region via the third region. The exposure includes a first exposure photograph for exposing the photoresist film on the first region and the third region, and a second exposure photograph after the first exposure photograph for exposing the photoresist film on the second region and the third region. Wherein, the wiring, extending along the direction of the wiring, includes a first portion located in the first region, a second portion located in the second region, and a third portion located in the third region, and The width of the third part is greater than the width of both the first part and the width of the second part. The photoresist film obtained between the first exposure and the second exposure in the exposure process includes a first exposure portion located on the first region and exposed by the first exposure, a second exposure portion located on the third region and exposed by the first exposure, and a third exposure portion located between the first exposure portion and the second exposure portion and exposed by the first exposure. The photoresist film obtained after the second exposure in the exposure process includes a fourth exposure portion located on the second region and exposed by the second exposure, a fifth exposure portion located on the third region and exposed by the second exposure, and a sixth exposure portion located between the fourth and fifth exposure portions and exposed by the second exposure. Wherein, at least a portion of the fifth exposure portion includes the second exposure portion. In the development process, the first exposure portion, the second exposure portion, the third exposure portion, the fourth exposure portion, the fifth exposure portion, and the sixth exposure portion are removed, and The width of the sixth exposure portion is greater than the width of the fourth exposure portion.

27. A method for manufacturing a semiconductor device, characterized in that, The method includes: Fabricating a wafer, the wafer comprising a semiconductor layer and an insulating film disposed on the semiconductor layer; Expose the positive photoresist film disposed on the insulating film; The photoresist film is developed to form a resist pattern from the photoresist film; The insulating film is patterned using the resist to form trenches on the insulating film; and Wiring is formed in the trench. The wafer includes a first region, a second region, and a third region located between the first region and the second region, and the trench extends from the first region to the second region via the third region. The exposure includes a first exposure photograph for exposing the photoresist film on the first region and the third region, and a second exposure photograph after the first exposure photograph for exposing the photoresist film on the second region and the third region. Wherein, the wiring, extending along the direction of the wiring, includes a first portion located in the first region, a second portion located in the second region, and a third portion located in the third region, and The width of the third part is greater than the width of both the first part and the width of the second part. The photoresist film obtained between the first exposure and the second exposure in the exposure process includes a first exposure portion located on the first region and exposed by the first exposure, a second exposure portion located on the third region and exposed by the first exposure, and a third exposure portion located between the first exposure portion and the second exposure portion and exposed by the first exposure. The photoresist film obtained after the second exposure in the exposure process includes a fourth exposure portion located on the second region and exposed by the second exposure, a fifth exposure portion located on the third region and exposed by the second exposure, and a sixth exposure portion located between the fourth and fifth exposure portions and exposed by the second exposure. Wherein, at least a portion of the fifth exposure portion includes the second exposure portion. In the development process, the first exposure portion, the second exposure portion, the third exposure portion, the fourth exposure portion, the fifth exposure portion, and the sixth exposure portion are removed, and The width of the fifth exposure portion is smaller than the width of the sixth exposure portion.

28. A method for manufacturing a semiconductor device, characterized in that, The method includes: Fabricating a wafer, the wafer comprising a semiconductor layer and an insulating film disposed on the semiconductor layer; Expose the positive photoresist film disposed on the insulating film; The photoresist film is developed to form a resist pattern from the photoresist film; The insulating film is patterned using the resist to form trenches on the insulating film; and Wiring is formed in the trench. The wafer includes a first region, a second region, and a third region located between the first region and the second region, and the trench extends from the first region to the second region via the third region. The exposure includes a first exposure photograph for exposing the photoresist film on the first region and the third region, and a second exposure photograph after the first exposure photograph for exposing the photoresist film on the second region and the third region. Wherein, the wiring, extending along the direction of the wiring, includes a first portion located in the first region, a second portion located in the second region, and a third portion located in the third region, and The width of the third part is greater than the width of both the first part and the width of the second part. The photoresist film obtained between the first exposure and the second exposure in the exposure process includes a first exposure portion located on the first region and exposed by the first exposure, a second exposure portion located on the third region and exposed by the first exposure, and a third exposure portion located between the first exposure portion and the second exposure portion and exposed by the first exposure. The photoresist film obtained after the second exposure in the exposure process includes a fourth exposure portion located on the second region and exposed by the second exposure, a fifth exposure portion located on the third region and exposed by the second exposure, and a sixth exposure portion located between the fourth and fifth exposure portions and exposed by the second exposure. Wherein, at least a portion of the fifth exposure portion includes the second exposure portion. In the development process, the first exposure portion, the second exposure portion, the third exposure portion, the fourth exposure portion, the fifth exposure portion, and the sixth exposure portion are removed, and The difference between the width of the fourth exposure portion and the width of the sixth exposure portion is greater than the difference between the width of the fifth exposure portion and the width of the sixth exposure portion.

29. A method for manufacturing a semiconductor device, characterized in that, The method includes: Fabricating a wafer, the wafer comprising a semiconductor layer and an insulating film disposed on the semiconductor layer; Expose the positive photoresist film disposed on the insulating film; The photoresist film is developed to form a resist pattern from the photoresist film; The insulating film is patterned using the resist to form trenches on the insulating film; and Wiring is formed in the trench. The wafer includes a first region, a second region, and a third region located between the first region and the second region, and the trench extends from the first region to the second region via the third region. The exposure includes a first exposure photograph for exposing the photoresist film on the first region and the third region, and a second exposure photograph after the first exposure photograph for exposing the photoresist film on the second region and the third region. The photoresist film obtained between the first exposure and the second exposure includes a first exposure portion located on the first region and exposed by the first exposure, a second exposure portion located on the third region and exposed by the first exposure, and a third exposure portion located between the first and second exposure portions and exposed by the first exposure. The photoresist film obtained after the second exposure includes a fourth exposure portion located on the second region and exposed by the second exposure, a fifth exposure portion located on the third region and exposed by the second exposure, and a sixth exposure portion located between the fourth and fifth exposure portions and exposed by the second exposure. Wherein, at least a portion of the fifth exposure portion includes the second exposure portion. In the development process, the first exposure portion, the second exposure portion, the third exposure portion, the fourth exposure portion, the fifth exposure portion, and the sixth exposure portion are removed, and The width of the second exposure portion is smaller than the width of the third exposure portion.

30. The method according to claim 29, wherein, The width of the fifth exposure portion is smaller than the width of the sixth exposure portion.

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