Semiconductor device package and method of manufacturing the same

Abstract

A semiconductor device package is provided. The semiconductor device package includes a first die, a second die, and a heat dissipation element. The first die has a first surface. The second die is disposed on the first surface. The heat dissipation element is disposed on the first surface. The heat dissipation element includes a first portion extending in a first direction substantially parallel to the first surface and partially covered by the second die, and a second portion extending in a second direction substantially perpendicular to the first surface to be adjacent to an edge of the second die.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to a semiconductor device package, and to a semiconductor device package having a heat dissipation element and a method of manufacturing the same. BACKGROUND

[0002] To pursue efficient electrical performance, multiple semiconductor dies are often stacked. A semiconductor device package, such as a 3D IC package, can include a substrate on which multiple semiconductor dies are stacked to minimize the size of the semiconductor device package and pursue efficient electrical performance. However, heat dissipation from one or more upper semiconductor dies to an external environment can be hindered due to a relatively long heat dissipation path established between the multiple semiconductor dies and the substrate. As such, electrical performance of the one or more upper semiconductor dies will be adversely affected by the low thermal efficiency. SUMMARY

[0003] In one or more embodiments, a semiconductor device package includes a first die, a second die, and a heat dissipation element. The first die has a first surface. The second die is disposed on the first surface. The heat dissipation element is disposed on the first surface. The heat dissipation element includes a first portion extending in a first direction substantially parallel to the first surface and partially covered by the second die. The heat dissipation element further includes a second portion extending in a second direction substantially perpendicular to the first surface to be adjacent to an edge of the second die.

[0004] In one or more embodiments, a semiconductor device package includes a first electronic component, a second electronic component, and a first heat dissipation element. The first electronic component includes a plurality of vias. The second electronic component is disposed on the first electronic component. The first heat dissipation element includes a first portion disposed between the first electronic component and the second electronic component. The first heat dissipation element further includes a second portion connected to the first portion and extending through the first electronic component. The first heat dissipation element is electrically floating from the plurality of vias.

[0005] In one or more embodiments, a method of manufacturing a semiconductor device package includes providing a first die and at least one second die, and forming a heat dissipation element between the first die and the at least second die. The heat dissipation element includes a first portion disposed between the first die and the at least one second die, and a second portion protruding from the first portion. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the disclosure can be appreciated when considered in relation to the following detailed description together with the accompanying drawings, in which:

[0007] Figure 1A A top view of a semiconductor device package is shown in accordance with some embodiments of the present disclosure.

[0008] Figure 1B A cross-sectional view of a semiconductor device package is shown in accordance with some embodiments of the present disclosure. Figure 1A

[0009] Figure 1C Figure 1B An enlarged cross-sectional view of the structure in dashed box A shown in

[0010] Figure 2A A cross-sectional view of a semiconductor device package is shown in accordance with some embodiments of the present disclosure.

[0011] Figure 2B A cross-sectional view of a semiconductor device package is shown in accordance with some embodiments of the present disclosure.

[0012] Figure 2C A cross-sectional view of a semiconductor device package is shown in accordance with some embodiments of the present disclosure.

[0013] Figure 2D A cross-sectional view of a semiconductor device package is shown in accordance with some embodiments of the present disclosure.

[0014] Figure 2E A cross-sectional view of a semiconductor device package is shown in accordance with some embodiments of the present disclosure.

[0015] Figure 2F A cross-sectional view of a semiconductor device package is shown in accordance with some embodiments of the present disclosure.

[0016] Figure 2G A cross-sectional view of a semiconductor device package is shown in accordance with some embodiments of the present disclosure.

[0017] Figure 3A A top view of a semiconductor device package is shown in accordance with some embodiments of the present disclosure.

[0018] Figure 3B A cross-sectional view of a semiconductor device package is shown in accordance with some embodiments of the present disclosure. Figure 3A

[0019] Figure 4A ​​​A cross-sectional view of a semiconductor device package is shown in accordance with some embodiments of the present disclosure.

[0020] Figure 4B A cross-sectional view of a semiconductor device package is shown in accordance with some embodiments of the present disclosure.

[0021] Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D 、 Figure 5E 、 Figure 5F 、 Figure 5G 、 Figure 5H 、 Figure 5I and Figure 5J One or more stages of a method for manufacturing a semiconductor device package in accordance with some embodiments of the present application are shown.

[0022] Figure 6 One or more stages of a method for manufacturing a semiconductor device package in accordance with some embodiments of the present application are shown.

[0023] Figure 7A 、 Figure 7B , and Figure 7C One or more stages of a method for manufacturing a semiconductor device package in accordance with some embodiments of the present application are shown.

[0024] Figure 8A and Figure 8B One or more stages of a method for manufacturing a semiconductor device package in accordance with some embodiments of the present application are shown.

[0025] Common reference numerals and characters are used throughout the drawings and detailed description to indicate the same or similar elements. The present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0026] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to provide a thorough description of embodiments. These are, of course, merely examples and are not intended to be limiting. In the present disclosure, references to a first feature being formed over or on a second feature can include embodiments where the first feature and the second feature are formed in direct contact, and can also include embodiments where additional features can be formed between the first feature and the second feature such that the first feature and the second feature can not be in direct contact. In addition, the present disclosure can repeat certain originally described features and / or aspects in various examples. This repetition of the description is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the example in which the original feature and / or aspect is used and the example in which the same original feature and / or aspect is used. The disclosure now being fully described, it will be apparent to one of ordinary skill in the art that various modifications can be made without departing from the scope of the disclosure.

[0027] Embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the present disclosure, and do not limit the scope of the present disclosure.

[0028] Figure 1A A top view of a semiconductor device package is shown, Figure 1B A cross-sectional view of the semiconductor device package 1 taken along line A-A’ in Figure 1A is shown, and Figure 1C is Figure 1B is an enlarged cross-sectional view of the structure in the dashed box A. As Figure 1A , Figure 1B and Figure 1C shown, the semiconductor device package 1 includes at least one first die 10, a second die 11, and at least one heat dissipation element, such as a first heat dissipation element 12.

[0029] The first die 10 (e.g., an electronic component) can include a semiconductor die, a package substrate, a fan-out substrate, an interposer, or a combination thereof. The first die 10 has a first surface 101 facing the second die 11 and a second surface 102 opposite the first surface 101.

[0030] In some embodiments, the first die 10 can include a substrate 10S, a first redistribution layer (RDL) 10R1, a second RDL 10R2, and a plurality of through vias 10V. The substrate 10S is disposed between the first RDL 10R1 and the second RDL 10R2. The substrate 10S can be electrically connected with the first RDL 10R1 and / or the second RDL 10R2. The substrate 10S can include, for example, a logic device, a processor, a controller (e.g., a memory controller), a microcontroller (MCU), a memory die, a high-speed input / output device, or other electronic components.

[0031] The first RDL 10R1 is disposed adjacent to the first surface 101 of the first die 10. The first RDL 10R1 can include a fan-out structure. Referring to Figure 1CThe first RDL 10R1 includes a dielectric layer 10R11 and one or more redistribution structures 10R12 disposed in the dielectric layer 10R11. The material of the dielectric layer 10R11 can include one or more dielectric materials or one or more insulating materials. The redistribution structures 10R12 can include some conductive elements such as, but not limited to, one or more conductive traces, one or more pads, one or more contacts, one or more vias. The second RDL 10R2 is disposed adjacent to the second surface 102 of the first die 10. The second RDL 10R2 can include one or more redistribution structures and one or more insulating materials or one or more dielectric materials encapsulating the one or more redistribution structures. The second RDL 10R2 can include a fan-out structure. The redistribution structures can include some conductive elements such as, but not limited to, one or more conductive traces, one or more pads, one or more contacts, one or more vias. The plurality of vias 10V extends through the substrate 10S. The plurality of vias 10V is electrically connected with the first RDL 10R1 and the second RDL 10R2.

[0032] In some embodiments, a plurality of second dies 11 (e.g., a plurality of electronic components) is disposed on the first surface 101 of the first die 10. Each of the second dies 11 can be smaller than the first die 10. Referring to Figure 1A The adjacent second dies 11 can be separated by a space (also referred to as a first space) S1 in a certain direction. Still referring to Figure 1A The adjacent second dies 11 can be separated by a space (also referred to as a second space) S2 in another direction. The length D1 of the first space S1 can be the same as or different from the length D2 of the second space S2. The plurality of second dies 11 can each include a semiconductor die, a package substrate, a fan-out substrate, an interposer, or a combination thereof.

[0033] Each of the plurality of second dies 11 has a first surface 111 and a second surface 112 opposite to the first surface 111. The first surface 111 can be a non-active surface. The second surface 112 can be an active surface. In some embodiments, the first surface 111 can be exposed, but is not limited thereto. The second surface 112 faces the first surface 101 of the first die 10. The plurality of second dies 11 can each include a substrate 11S and a third RDL 11R electrically connected with the substrate 11S. The substrate 11S can include, for example, a logic device, a processor, a controller (e.g., a memory controller), a microcontroller (MCU), a memory die, a high-speed input / output device, or other electronic components. The third RDL 11R is disposed adjacent to the second surface 112 of the second die 11. Referring to Figure 1CThe third RDL 11R includes a dielectric layer 11R1, a redistribution structure 11R2 within the dielectric layer 11R1, and a dummy pad 11R3 disposed on the first portion 121. The third RDL 11R can include a fan-out structure. The material of the dielectric layer 11R1 can include one or more dielectric materials or one or more insulating materials. The redistribution structure 11R2 can include some conductive elements such as, but not limited to, one or more conductive traces, one or more pads, one or more contacts, one or more vias. The dummy pad 11R3 can include one or more conductive materials.

[0034] In some embodiments, the dummy pad 11R3 can have a floating voltage. For example, the dummy pad 11R3 is not electrically connected to the substrate 11S of the second die 11. In some embodiments, the first heat dissipation element 12 is electrically floated from the second die 11. In other words, the first heat dissipation element 12 does not transmit electrical signals from the first die 10 or the second die 11.

[0035] The first heat dissipation element 12 is disposed on the first surface 101 of the first die 10. The first heat dissipation element 12 is configured to assist the first die 10 and the second die 11 in heat dissipation. The material of the first heat dissipation element 12 can have a higher thermal conductivity than that of a polymer, a semiconductor material, or a molding compound, such that the first heat dissipation element 12 can improve the heat conduction efficiency. Examples of the material of the first heat dissipation element 12 can include metals such as copper (Cu), gold (Au), aluminum (Al), etc. In addition, the first heat dissipation element 12 can include a pre-formed structure. The pre-formed structure is formed before being disposed on the first die 10. The pre-formed structure can be formed by, for example, forging, molding, or shaping in one or more preliminary processes.

[0036] The first heat dissipation element 12 includes a first portion 121 disposed between the first die 10 and the second die 11. The first portion 121 extends in a first direction LI substantially parallel to the first surface 101. A first width W1 of the first portion 121 is greater than a length D1 of the first space S1 between two adjacent second dies 11. The first portion 121 is partially covered by at least one of the second dies 11 of the plurality of second dies 11. The covered section of the first portion 121 is in the first direction LI. Figure 1AThe first portion 121 can be covered by a border portion of at least one of the second dies 11. The first portion 121 is covered by a corner portion of at least one of the second dies 11. The first heat dissipation element 12 further includes a second portion 122 disposed on the first portion 121. In some embodiments, the second portion 122 can be connected to the first portion 121. The second portion 122 extends in a second direction L2 substantially perpendicular to the first surface 101. A second width W2 of the second portion 122 is less than the first length Dl. The second portion 122 extends adjacent to the edge 113 of the second die 11. In some embodiments, the second portion 122 is disposed between two adjacent second dies 11. In some embodiments, the second portion 122 is not equally spaced apart from the two adjacent second dies 11. In some embodiments, an upper surface of the second portion 122 and the first surface 111 of one or more of the second dies 11 are substantially coplanar.

[0037] In some embodiments, the semiconductor device package 1 can further include a thermally conductive layer 123 disposed between the second portion 122 and the first RDL 10R1 of the first die 10. The thermally conductive layer 123 can be in contact with the first RDL 10R1. In some embodiments, the first RDL 10R1 can be omitted such that the thermally conductive layer 123 is in contact with the substrate 10S of the first die 10. The thermally conductive layer 123 can include one or more thermal interface materials (TIMs) such as thermal paste, thermally conductive gel, thermally conductive putty, and thermal paste. In some embodiments, the thermally conductive layer 123 can include one of tungsten (W), titanium (Ti), tantalum (Ta), or a compound thereof.

[0038] In some embodiments, the semiconductor device package 1 can further include a pre-solder 14. The pre-solder 14 is disposed between the first portion 121 and the second surface 112 of the second die 11. In some embodiments, the pre-solder 14 can be in contact with the first portion 121 or the second surface 112. The pre-solder 14 can serve as an interface between the first heat dissipation element 12 and the second die 11 and thus can facilitate heat dissipation of the second die 11 to the first heat dissipation element 12. In some embodiments, the pre-solder 14 can protrude from a side surface of the first portion 121. In some embodiments, the pre-solder 14 can be in contact with the second portion 122. The pre-solder 14 can include, for example and without limitation, solder, adhesive (which can include electrically conductive adhesive (e.g., resin mixed with electrically conductive particles)), or one or more other suitable bonding materials.

[0039] In some embodiments, the semiconductor device package 1 can further include a connection structure 13. The connection structure 13 can be disposed between the first surface 101 and the second surface 112. The connection structure 13 is electrically conductive. The connection structure 13 can electrically connect the first die 10 to one or more of the plurality of second dies 11. The connection structure 13 can be in contact with the first RDL 10R1 of the first die 10. The connection structure 13 can be in contact with the third RDL 11R of the second die 11. In some embodiments, the connection structure 13 can be thermally conductive. Referring to Figure 1B The connection structure 13 has a height H1 in the second direction L2. The height H1 can be substantially equal to the distance between the first die 10 and the second die 11. The height H1 of the connection structure 13 is greater than the height H2 of the first portion 121 in the second direction L2.

[0040] The connection structure 13 can include a first conductive pad 131, a connection element 132, and a second conductive pad 133. The first conductive pad 131 is disposed on the second surface 112 of the second die 11. The second conductive pad 133 is disposed on the first surface 101 of the first die 10. The connection element 132 is disposed between the first conductive pad 131 and the second conductive pad 133. The first conductive pad 131 and the second conductive pad 133 can each include one or more electrically conductive materials. The first conductive pad 131 and the second conductive pad 133 can each include a metal, such as copper (Cu), gold (Au), aluminum (Al), etc. The connection element 132 can include, for example and without limitation, solder, an adhesive (which can include an electrically conductive adhesive (e.g., a resin mixed with electrically conductive particles)), or one or more other suitable bonding materials.

[0041] The semiconductor device package 1 can further include electrical contacts 15 disposed on the second surface 102 of the first die 10 to establish external electrical connections. For example, the first die 10 can be further electrically connected to a stack structure including a substrate or a printed circuit board (PCB) through the electrical contacts 15. The electrical contacts 15 can include solder balls or solder bumps. In some embodiments, the electrical contacts 15 can include controlled collapse chip connection (C4) bumps, a ball grid array (BGA), or a land grid array (LGA).

[0042] As Figure 1BAs shown, a first thermal conduction path TP1 is established between the second die 11, the connection structure 13, the first die 10, the electrical contacts 15, and an external stack structure connected to the electrical contacts 15. The external stack structure can include a plurality of semiconductor dies stacked on a PCB. The first thermal conduction path TP1 inevitably passes through dielectric materials with very low thermal conductivity in the first die 10 and the external stack structure. Subsequently, heat generated by the active surface (i.e., the second surface 112) of the second die 11 cannot be efficiently transferred to the external environment through the first die 10 and the external stack structure.

[0043] Still referring to Figure 1B , the first width W1 of the first portion 121 is greater than the second width W2 of the second portion 122, such that the first portion 121 and the second portion 122 form an inverted T-shaped structure. The first portion 121, which has a first width W1 greater than the first distance D1, can be in contact with the second die 11 through the pre-solder 14. The second portion 122, which has a second width W2 less than the first distance D1, can extend adjacent to the edge 113 of the second die and be in contact with an external element, such as a heat sink (also referred to as a heat spreader). A second thermal conduction path TP2 is established between the second die 11, the pre-solder 14, the first heat dissipation element 12, and the external element. Since the second thermal conduction path TP2 bypasses the first die 10 and the external stack structure, the second thermal conduction path TP2 is shorter than the first thermal conduction path TP1. Furthermore, the second thermal conduction path TP2 passes through materials with relatively high thermal conductivity compared to the dielectric materials passed through by the first thermal conduction path TP1. Thus, the second thermal conduction path TP2 provides more efficient heat dissipation for the active surface (i.e., the second surface 112) of the second die 11 compared to the first thermal conduction path TP1.

[0044] Figure 2A A cross-sectional view of a semiconductor device package 2a according to some embodiments of the present disclosure is shown. Figure 2A The semiconductor device package 2a is similar to the semiconductor device package 1 of Figure 1B and the differences between them are described below.

[0045] The semiconductor device package 2a further includes a heat spreader 16 and an adhesive layer 17 disposed between the heat spreader 16 and the first surface 111 of one or more of the plurality of second dies 11. The heat spreader 16 can include a planar bottom profile. The heat spreader 16 is disposed on the second portion 122 of the first heat dissipation element 12. The heat spreader 16 can be, for example, a tube, a finned heat sink, a planar heat sink, a liquid cooling tube, or a thermal vapor compressor (TVC). The adhesive layer 17 can include one or more TIMs such that heat dissipation between the heat spreader 16 and the second portion 122 can be improved. A third thermal conduction path TP3 is established between the second die 11, the pre-solder 14, the first heat dissipation element 12, the adhesive layer 17, and the heat spreader 16. The third thermal conduction path TP3 is shorter than the first thermal conduction path TP1 because the third thermal conduction path TP3 bypasses the external stack structure. Furthermore, the third thermal conduction path TP3 passes through a material with a relatively higher thermal conductivity compared to the dielectric material through which the first thermal conduction path TP1 passes. Thus, the third thermal conduction path TP3 provides a more efficient heat dissipation for the active surface (i.e., the surface 112) of the plurality of second dies 11 compared to the first thermal conduction path TP1.

[0046] In some embodiments, the adhesive layer 17 can be omitted, and the heat spreader 16 is in contact with the second portion 122 or the first surface 111 of one or more of the plurality of second dies 11.

[0047] Figure 2B A cross-sectional view of a semiconductor device package 2b according to some embodiments of the disclosure is shown. Figure 2B The semiconductor device package 2b is similar to the semiconductor device package 2a Figure 2A of the semiconductor device package 2a and the differences therebetween are described below. The adhesive layer 17 includes an extension portion 171 disposed at least partially in the first space S1 between the two adjacent second dies 11. The adhesive layer 17 can include one or more flexible materials. The extension portion 171 can be formed when a portion of the adhesive layer 17 flows into the first space during a mounting process of the heat spreader 16.

[0048] Figure 2C A cross-sectional view of a semiconductor device package 2c according to some embodiments of the disclosure is shown. Figure 2C The semiconductor device package 2c is similar to the semiconductor device package 2a Figure 2Asemiconductor device package 2a and the differences between them are described below. Semiconductor device package 2c further includes a molding compound 18 disposed in the first space S1. The molding compound 18 surrounds the second portion 122 of the first heat dissipation element 12. The molding compound 18 can be in contact with the first heat dissipation element 12. In some embodiments, the molding compound 18 can partially or completely fill a closed region defined by the adjacent second die 11, the first heat dissipation element 12, the pre-solder 14, and the adhesive layer 17.

[0049] Figure 2D A cross-sectional view of a semiconductor device package 2d according to some embodiments of the present disclosure is shown. Figure 2D The semiconductor device package 2d is similar to Figure 2C The semiconductor device package 2c and the differences between them are described below. The molding compound 18 can partially or completely fill a closed region defined by the adjacent second die 11, the first heat dissipation element 12, the pre-solder 14, and the extended portion 171 of the adhesive layer 17.

[0050] Figure 2E A cross-sectional view of a semiconductor device package 2e according to some embodiments of the present disclosure is shown. Figure 2E The semiconductor device package 2e is similar to Figure 2A The semiconductor device package 2a and the differences between them are described below. Semiconductor device package 2e further includes an underfill 19 disposed in the first space S1. The underfill 19 can be spaced apart from the adhesive layer 17. The underfill 19 can be in contact with the first heat dissipation element 12 or the pre-solder 14. The underfill 19 has a tapered profile. The underfill 19 can include an epoxy, a polyimide, a phenolic compound or material, a material including silicone dispersed therein, or a combination thereof.

[0051] Figure 2F A cross-sectional view of a semiconductor device package 2f according to some embodiments of the present disclosure is shown. Figure 2F The semiconductor device package 2f is similar to Figure 2B The semiconductor device package 2b and the differences between them are described below. Semiconductor device package 2f further includes an underfill 19 disposed in the first space S1. The underfill 19 can be in contact with the extended portion 171 of the adhesive layer 17.

[0052] Figure 2G A cross-sectional view of a semiconductor device package 2g according to some embodiments of the present disclosure is shown. Figure 2G The semiconductor device package 2g is similar to Figure 2Asemiconductor device package 2a and the differences between them are described below. The second portion 122 of the first heat dissipation element 12 of the semiconductor device package 2g has an upper surface 1221 in contact with the heat spreader 16. The upper surface 1221 can be higher than the first surfaces 111 of the plurality of second dies 11.

[0053] Figure 3A A top view of a semiconductor device package 3 according to some embodiments of the disclosure is shown, and Figure 3B A cross-sectional view of the semiconductor device package 3 taken along the line B-B’ in Figure 3A is shown. As Figure 3A and Figure 3B shown, the semiconductor device package 3 is similar to the semiconductor device package 1 and the differences between them are described below. The semiconductor device package 3 includes at least one first die 10, at least one second die 11, and a second heat dissipation element 22 instead of the first heat dissipation element 12. The second heat dissipation element 22 includes a first portion 221 and a second portion 222. The second portion 222 can be connected to the first portion 221. The first portion is disposed between the first die 10 and the second die 11. The first portion 221 is partially covered by one of the plurality of second dies 11. The covered section of the first portion 221 is indicated by a dashed line in Figure 3A . The first portion 221 has a wide region 2211 disposed on and substantially aligned with the second portion 222. The wide region 2211 can include a rectangular structure. The first portion 221 has a narrow region 2212 connected to another narrow region 2212 of another first portion 221. The width of the wide region 2211 can be greater than the width of the narrow region 2212.

[0054] Referring to Figure 3B , the second portion 222 of the second heat dissipation element 22 is disposed in the first die 10. The second portion 222 extends through the first RDL 10R1 and the substrate 10S. In some embodiments, the second portion 222 can extend through the second RDL 10R2. In some embodiments, the second portion 222 can extend from the first surface 101 through the first die 10 to the second surface 102.

[0055] Still referring to Figure 3B , a third width W3 of the first portion 221 is greater than a fourth width W4 of the second portion 222, such that the first portion 221 and the second portion 222 form a T-shaped structure.

[0056] The second heat dissipation element 22 is configured to assist the first die 10 and the second die 11 in heat dissipation. The second heat dissipation element 22 can comprise a material having a higher thermal conductivity than that of the polymer, the semiconductor material, or the molding material, such that the second heat dissipation element 22 can improve the heat conduction efficiency. The second heat dissipation element 22 can comprise a metal, such as copper (Cu), gold (Au), aluminum (Al), or the like. In addition, the second heat dissipation element 22 can comprise a preformed structure. The preformed structure is formed before being disposed on the first die 10. The preformed structure can be formed by, for example, forging, molding, or shaping in one or more preliminary processes.

[0057] In some embodiments, the semiconductor device package 3 can further comprise a pre-solder 24 disposed between the first portion 221 and the second surface 112 of the second die 11. In some embodiments, the pre-solder 24 can be in contact with the first portion 221 or the second surface 112. The pre-solder 24 can comprise, for example, but not limited to, a solder, an adhesive (which can comprise a conductive adhesive (e.g., a resin mixed with conductive particles)), or one or more other suitable bonding materials.

[0058] In some embodiments, the pre-solder 24 can serve as an interface between the second heat dissipation element 22 and the second die 11, and thus can facilitate heat dissipation from the second die 11 to the second heat dissipation element 22. The second heat dissipation element 22 and the electrical contacts 15 can be in contact with the second RDL 10R2. A fourth thermal conduction path TP4 is established between the second die 11, the second heat dissipation element 22, the second RDL 10R2, the electrical contacts 15, and the external stack structure connected with the electrical contacts 15. The fourth thermal conduction path TP4 passes through a material having a relatively higher thermal conductivity compared to the dielectric material through which the first thermal conduction path TP1 passes. Thus, the fourth thermal conduction path TP4 provides a more efficient heat dissipation for the active surface (i.e., the second surface 112) of the second die 11 compared to the first thermal conduction path TP1.

[0059] In addition, the second heat dissipation element 22 is electrically floating from the plurality of vias 10V. The second heat dissipation element 22 is electrically isolated from the plurality of vias 10V. The second heat dissipation element 22 is electrically floating from the first die 10 or the second die 11. The second heat dissipation element 22 does not transmit electrical signals from the first die 10 or the second die 11.

[0060] Figure 4A A cross-sectional view of a semiconductor device package 4a according to some embodiments of the present disclosure is shown. Figure 4A The semiconductor device package 4a of FIG. 4A is similar to Figure 1BThe semiconductor device package 4a has at least one of the thermal conduction paths TP1, TP2, and TP4 to dissipate heat generated by the plurality of second dies 11.

[0061] Figure 4B A cross-sectional view of a semiconductor device package according to some embodiments of the disclosure is shown. Figure 4B The semiconductor device package 4b is similar to Figure 1B The semiconductor device package 4b is similar to The semiconductor device package 4b has at least one of the thermal conduction paths TP1, TP2, and TP4 to dissipate heat generated by the plurality of second dies 11.

[0062] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F , Figure 5G , Figure 5H , Figure 5I and Figure 5J One or more stages of a method for manufacturing a semiconductor device package according to some embodiments of the disclosure are shown.

[0063] Referring to Figure 5A A first die 10 having a first surface 101 and a second surface 102 is provided. The first die 10 includes a substrate 10S, a first RDL 10R1 adjacent to the first surface 101, a second RDL 10R2 adjacent to the second surface 102, and a plurality of vias 10V extending through the substrate 10S.

[0064] Referring to Figure 5B A seed layer 50 is formed on the first surface 101 of the first die 10. Referring to Figure 5C A first photoresist layer 51 is formed on the seed layer 50 by, for example, a coating process followed by an exposure process. The first photoresist layer 51 defines a gap 51g on the seed layer 50. Referring to Figure 5DA first thermally conductive material 52 is formed within the gap 51g by, for example, an electroplating process. The first thermally conductive material 52 can include a metal, such as copper (Cu), gold (Au), aluminum (Al), and the like.

[0065] Referring to Figure 5E The first photoresist layer 51 is removed by, for example, a plasma ashing process. Referring to Figure 5F A portion of the bulk seed layer 50 exposed from the first thermally conductive material 52 is removed in an etching process to form a seed layer 50'.

[0066] Referring to Figure 5G A second photoresist layer 53 is formed on the first thermally conductive material 52 and the first surface 101 of the first die 10 by, for example, a coating process followed by an exposure process. The second photoresist layer 53 defines a gap 53g on the first thermally conductive material 52. Referring to Figure 5H A second thermally conductive material 54 is formed within the gap 53g by, for example, an electroplating process. The second thermally conductive material 54 can include a metal, such as copper (Cu), gold (Au), aluminum (Al), and the like. Referring to Figure 5I The second photoresist layer 53 is removed by, for example, a plasma ashing process. Subsequently, the thermally conductive materials 52 and 54 and the seed layer 50' form a first heat dissipation element 12 as described in Figure 1B The first width W1 of the first portion 121 of the first heat dissipation element 12 is greater than the second width W2 of the second portion 122 of the first heat dissipation element 12.

[0067] Referring to Figure 5J The at least one second die 11 is attached to the first surface 101 of the first die 10 by a plurality of connection structures 13. Prior to the attachment process of the plurality of second dies 11, a pre-solder 14 can be formed on the first portion 121 or the surface 112 of the at least one second die 11. The plurality of second dies 11 are separated from each other by a first space S1. The first distance D1 of the first space S1 is less than the first width W1. Meanwhile, the first distance D1 is greater than the second width W2.

[0068] Furthermore, an electrical contact 15 can be formed on the second surface 102 of the first die 10, and a singulation operation can be performed to form some of the semiconductor device packages 1 described and shown in Figure 1B

[0069] Figure 6 One or more stages of a method for manufacturing a semiconductor device package according to some embodiments of the present application are shown. Referring to Figure 6 The first heat dissipation element 12 is pre-formed prior to being attached to the first die 10. The first heat dissipation element 12 can include a thermally conductive layer 123 that serves as an interface material between the first heat dissipation element 12 and the first die 10. Figure 6 ​The stages in Figure 5J may occur prior to stages similar to those in Figure 1B . Thereafter, electrical contacts 15 can be formed on the second surface 102 of the first die 10, and a singulation operation can be performed to form some of the semiconductor device packages 1 described and shown in .

[0070] Figure 7A , Figure 7B , and Figure 7C illustrate one or more stages of a method for manufacturing a semiconductor device package according to some embodiments of the present application.

[0071] Referring to Figure 7A , a first die 10 having a first surface 101 and a second surface 102 is provided. The first die 10 includes a substrate 10S, a first RDL 10R1 adjacent to the first surface 101, a second RDL 10R2 adjacent to the second surface 102, and a plurality of vias 10V extending through the substrate 10S. A thermally conductive structure 70 is disposed in the first die 10. Referring to Figure 7B , the thermally conductive material can be formed in several stages similar to those in Figure 5C to 5E or those in Figure 6 . Subsequently, the thermally conductive structure 70 and the thermally conductive material form a second thermal dissipation element 22. A third width W3 of a first portion 221 of the thermal dissipation element 22 is greater than a fourth width W4 of a second portion 222 of the thermal dissipation element 22. Referring to Figure 7C , at least one second die 11 is attached to the first surface 101 of the first die 10 by a plurality of connection structures 13.

[0072] Furthermore, electrical contacts 15 can be formed on the second surface 102 of the first die 10, and a singulation operation can be performed to form some of the semiconductor device packages 3 described and shown in Figure 3B .

[0073] Figure 8A and Figure 8B illustrate one or more stages of a method for manufacturing a semiconductor device package according to some embodiments of the present application.

[0074] Referring to Figure 8A , after the stages in Figure 7B , a first thermal dissipation element 12 is attached to the first surface 101 of the first die 10. Referring to Figure 8B , at least one second die 11 is attached to the first surface 101 of the first die 10 by a plurality of connection structures 13.

[0075] Furthermore, electrical contacts 15 can be formed on the second surface 102 of the first die 10, and a singulation operation can be performed to form some of the semiconductor device packages 3 described and shown in Figure 4AThe semiconductor device package 4a described and shown.

[0076] As used herein, the term "active surface" can refer to a surface of an electronic assembly that is disposed with contact terminals such as contact pads, and a "non-active surface" can refer to another surface of the electronic assembly that is opposite the active surface and is not disposed with contact terminals.

[0077] Spatially relative terms such as "under", "below", "lower", "above", "upper", "left", "right", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms can be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. It will be understood that, when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected or coupled to the other element or one or more intervening elements can be present.

[0078] As used herein, the terms "about", "substantially", "essentially", and "approximately" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances where the event or circumstance occurs exactly, as well as instances where the event or circumstance occurs approximately. As used herein in reference to a given value or range, the term "approximately" generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein include the endpoints, unless otherwise indicated. The term "substantially co-planar" can refer to a position difference of two surfaces being positioned along the same plane within a number of micrometers (pm), such as within 10 pm, within 5 pm, within 1 pm, or within 0.5 pm. When a value or characteristic is referred to as "substantially" the same, the term can refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average of the value.

[0079] The foregoing outlines features of several embodiments and a detailed description of the disclosure. The embodiments described in the disclosure can be readily used as a basis for the design or manufacture of other processes and structures and can be employed in the manufacture of these other processes and structures without departing from the spirit and scope of the present disclosure. Such equivalent constructions do not depart from the spirit and scope of the present disclosure and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device package, comprising: a first die (10) having a first surface (101); a second die (11) disposed on the first surface, and having an active surface facing the first die; a first thermal dissipation element (12) disposed on the first surface and exposing a portion of the active surface of the second die, wherein the first thermal dissipation element includes a first portion (121) extending in a first direction substantially parallel to the first surface, and a second portion (122) extending in a second direction substantially perpendicular to the first surface to be adjacent to an edge of the second die; and a second thermal dissipation element (22) including a first portion (221) disposed between the first die and the second die, and a second portion (222) connected to the first portion of the second thermal dissipation element and extending through the first die. a connection structure (13) disposed between the exposed portion of the active surface of the second die and the first surface of the first die, and electrically connecting the second die to the first die, wherein the first thermal dissipation element is adjacent to a boundary portion of the second die, the second thermal dissipation element is adjacent to a central portion of the second die, and the connection structure is disposed between the first thermal dissipation element (12) and the second thermal dissipation element (22).

2. The semiconductor device package of claim 1, further comprising:

3. The semiconductor device package of claim 2, wherein the connection structure includes a first conductive pad, a solder, and a second conductive pad, and a height of the connection structure is greater than a height of the first portion of the second thermal dissipation element in the second direction.

4. The semiconductor device package of claim 1, wherein a width of the first portion of the second thermal dissipation element is greater than a width of the second portion of the second thermal dissipation element, and wherein the first die includes a plurality of vias, the second portion of the second thermal dissipation element is electrically isolated from the plurality of vias.

5. The semiconductor device package of claim 1, the second portion (122) of the first thermal dissipation element (12) has a first extension extending in the first direction and a second extension extending in a third direction substantially parallel to the first surface when viewed from a top view, the first direction is substantially perpendicular to the third direction, the first extension and the second extension are interleaved with each other to form a plurality of openings, and the semiconductor device package further comprises: a plurality of the second dies (11) each disposed in one of the plurality of openings. a heat sink disposed on the second dies, wherein an upper surface of the second portion of the first thermal dissipation element is in contact with a planar bottom of the heat sink.

6. The semiconductor device package of claim 1, further comprising: ​ and an adhesive layer disposed between the heat spreader and a non-active surface of the second die.

7. The semiconductor device package of claim 6, wherein the adhesive layer has an extension portion contacting a side surface of the second die.

8. The semiconductor device package of claim 7, further comprising: a molding compound (18) that completely fills a closed area defined by the adhesive layer, the first heat dissipation element (12), and the second die (11).

9. The semiconductor device package of claim 6, further comprising: an underfill (19) that is partially disposed on the first heat dissipation element, wherein the underfill has a tapered profile to expose a side surface of the second die.

10. The semiconductor device package of claim 9, wherein the adhesive layer has an extension portion contacting the side surface of the second die and the underfill.

11. The semiconductor device package of claim 1, wherein the second die includes a redistribution layer disposed adjacent to the active surface, wherein the redistribution layer includes dummy pads disposed on the first portion.

12. A method of fabricating a semiconductor device package, the method comprising: providing a first die (10); forming a first heat dissipation element (12) on the first die; forming a second die (11) on the first heat dissipation element, the second die having an active surface facing the first die, wherein the first heat dissipation element exposes a portion of the active surface of the second die, wherein the first heat dissipation element includes a first portion (121) disposed between the first die and the second die and a second portion (122) protruding from the first portion; and forming a second heat dissipation element (22) including a first portion (221) and a second portion (222), wherein the first portion of the second heat dissipation element is disposed between the first die and the second die, and the second portion of the second heat dissipation element is connected to the first portion and extends through the first die.

13. The method of claim 12, wherein after disposing the second portion of the second heat dissipation element on the first die, the first portion of the second heat dissipation element is disposed on the first die to connect the second portion of the second heat dissipation element.

14. The method of claim 12, wherein after forming the second heat dissipation element (22), the preformed first heat dissipation element is attached to the first die.

15. The method of claim 12, wherein the first die includes a plurality of vias, the second portion of the second heat dissipation element is electrically isolated from the plurality of vias, and the method further comprises: disposing a connection structure on the first die and electrically connecting the active surface.

16. The method of claim 12, further comprising: forming an adhesive layer on the second die and connecting a heat spreader to a non-active surface of the second die through the adhesive layer, wherein the adhesive layer has an extension portion (171) contacting a side surface of the second die.

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