Integrated circuit and method of forming the same

Abstract

Various embodiments of the present invention provide a through-hole first process for connecting a contact to a gate electrode. In some embodiments, a contact is formed, and the contact extends through a first interlayer dielectric (ILD) layer to a source / drain region adjacent to the gate electrode. An etch stop layer (ESL) covering the first ILD layer and the contact is deposited, and a second ILD layer covering the ESL is deposited. A first etch is performed on the first ILD layer, the second ILD layer, and the etch stop layer to form a first opening exposing the gate electrode. A series of etches are performed on the second ILD layer and the etch stop layer to form a second opening located above the contact and overlapping the first opening, so that the bottom of the second opening is tilted downward from the contact to the first opening. A gate to contact (GC) structure is formed that fills the first opening and the second opening. Embodiments of the present invention also relate to integrated circuits and methods for forming the same.

Description

Technical Field

[0001] Embodiments of the present invention relate to integrated circuits and methods of forming the same. Background Art

[0002] Over the past few decades, the integrated circuit (IC) manufacturing industry has experienced exponential growth. As ICs have evolved, functional density (e.g., the number of interconnected devices per chip area) has increased, while component size has decreased. One of the technologies used to continuously increase functional density is middle-of-line (MOL) processing. The MOL process is performed between the front-end-of-line (FEOL) process and the back-end-of-line (BEOL) process, and an MOL interconnect structure is formed, which provides local routing between devices. The MOL interconnect structure can be formed to have a high density and reduce the consumption of scarce routing resources during the BEOL process. Summary of the invention

[0003] An embodiment of the present invention provides an integrated circuit (IC), comprising: a substrate; a source / drain region located above the top of the substrate and inserted into the top of the substrate; a gate electrode adjacent to the source / drain region above the substrate; a first-level contact located above the source / drain region and electrically coupled to the source / drain region; a second-level contact located above the first-level contact and the gate electrode; and a gate through hole extending from the second-level contact to the gate electrode, wherein a bottom surface of the second-level contact is inclined downward from the first-level contact to the gate through hole.

[0004] Another embodiment of the present invention provides an integrated circuit (IC), comprising: a substrate; a device located on the substrate and including a gate electrode, wherein the substrate at least partially defines an active area (AR) of the device; an active area contact extending from the active area along the sidewall of the gate electrode to the top surface of the active area contact, the active area contact being elevated above the top surface of the gate electrode; and a gate-to-contact (GC) structure located above the active area contact and the gate electrode, wherein the gate-to-contact structure extends from the top surface of the gate electrode to the top surface of the active area contact, wherein the gate-to-contact structure defines the gate through hole, the gate through hole extends to the top surface of the gate electrode and is spaced apart from the active area contact, and wherein the width of the gate-to-contact structure increases continuously from the top of the gate through hole to the top surface of the active area contact.

[0005] Another embodiment of the present invention provides a method for forming an integrated circuit (IC), comprising: forming an active region (AR) contact extending through a first interlayer dielectric (ILD) layer to an active region of a semiconductor device; depositing an etch stop layer (ESL) and a second interlayer dielectric layer, the etch stop layer and the second interlayer dielectric layer covering the first interlayer dielectric layer and the active region contact, wherein the etch stop layer is located between the first interlayer dielectric layer and the second interlayer dielectric layer; performing a first etching on the etch stop layer and the first interlayer dielectric layer and the second interlayer dielectric layer to form an active region contact exposing the semiconductor device; A first opening for a gate electrode is formed; performing a second etching on the second interlayer dielectric layer, the second etching stopping on the etch stop layer to form a second opening located above the active area contact and overlapping the first opening; performing a third etching on the etch stop layer through the second opening to expose the active area contact, wherein the third etching causes the bottom of the second opening to tilt downward from the active area contact to the first opening; and forming a gate-to-contact (GC) structure, the gate-to-contact structure filling the first opening and the second opening and electrically connecting the gate electrode to the active area contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1A to 1D Cross-sectional views of various embodiments of an integrated circuit (IC) including a gate-to-contact (GC) structure are shown.

[0008] Figure 2A and Figure 2B Shown with Figure 1A The cross-section is orthogonal to Figure 1A Cross-sectional views of various embodiments of an IC.

[0009] Figure 3A and Figure 3B Shows Figure 1A Cross-sectional views of various alternative embodiments of an IC, wherein a GC structure is adjacent to a plurality of semiconductor devices and a plurality of AR contacts.

[0010] Figure 4A and Figure 4B Shows Figure 3A 1 and 2. An enlarged cross-sectional view of various embodiments of an IC in which a back-end of line (BEOL) region is located above a middle of line (MOL) region in which a GC structure is arranged.

[0011] FIG. 5A to FIG. 5D Shows Figure 3A Top layout of various embodiments of the IC.

[0012] Fig. 6A and Figure 6B A top layout of various embodiments of an IC including a plurality of GC structures adjacent to a plurality of AR contacts and a plurality of semiconductor devices configured as fin field effect transistors (finFETs) is shown.

[0013] Figure 7 Shows Fig. 6A Cross-sectional views of some embodiments of an IC.

[0014] Figure 8 Shows Fig. 6A Cross-sectional projections of some embodiments of ICs.

[0015] Figures 9 to 16 , Fig.17A , Fig. 17B and 18A to 18C A series of cross-sectional views illustrating various embodiments of a method for forming an IC including a GC structure are shown.

[0016] Fig.19 Shows Figures 9 to 16 , Fig.17A , Fig. 17B and 18A to 18C A block diagram of some embodiments of the method. DETAILED DESCRIPTION

[0017] The present invention provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0018] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or process of operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0019] In some embodiments, an integrated circuit (IC) includes a middle-of-line (MOL) region in which an active region (AR) contact and a gate contact are arranged. The AR contact extends from the gate contact to the source / drain region of the semiconductor device. The gate contact is located above the AR contact and the gate electrode of the semiconductor device and directly contacts the AR contact and the gate electrode of the semiconductor device. In some embodiments, a process for forming the AR contact and the gate contact includes: 1) depositing an interlayer dielectric (ILD) layer covering the semiconductor device; 2) performing a first etching on the ILD layer to form an AR opening exposing the source / drain region; 3) performing a second etching on the ILD layer to form a gate opening overlapping the AR opening and exposing the gate electrode; 4) depositing a metal layer filling the AR opening and the gate opening; and 5) performing planarization on the metal layer and the ILD layer until their top surfaces are substantially flush. The portion of the metal layer in the AR opening defines the AR contact, and the portion of the metal layer in the gate opening defines the gate contact.

[0020] The challenge with this process is that during the second etch, the source / drain regions may be exposed in the AR opening. This may result in oxide formation on the source / drain regions during the second etch. The oxide in turn increases the contact resistance between the AR contact and the source / drain regions, thus potentially shifting the operating parameters of the IC out of specification and / or causing failure.

[0021] Another challenge of this process is that the second etching process is subject to a large number of constraints on the gate opening. The gate opening must overlap with the AR opening and the gate electrode while maintaining sufficient spacing with other gate electrodes and other AR contacts. Therefore, this process depends on a high degree of coverage control and a high degree of size control. Failure to achieve a high degree of coverage and size control may result in high leakage current and / or an electrical short circuit from a gate contact to another gate electrode and / or another AR contact. In addition, failure to obtain a high degree of coverage and size control may result in the gate opening not being able to overlap with the AR opening, whereby the gate contact and the AR contact may not be electrically coupled to each other. In addition, failure to obtain a high degree of coverage and size control may result in the gate opening not being able to expose the gate electrode, whereby the gate contact and the gate electrode may not be electrically coupled to each other.

[0022] Various embodiments of the present application are directed to a via-first process for electrically coupling an AR contact and a gate electrode, and a gate-to-contact (GC) structure produced by the via-first process. According to some embodiments of the via-first process, an AR contact and a gate electrode are provided. The gate electrode is part of a semiconductor device and is located above the AR of the semiconductor device. The AR contact extends through a first ILD layer above the semiconductor device to a source / drain region of the semiconductor device or some other location in the AR. An etch stop layer (ESL) is deposited to cover the first ILD layer, and a second ILD layer is deposited to cover the ESL. A first etching is performed on the first and second ILD layers and the ESL to form a first opening exposing the gate electrode. A second etching is performed on the second ILD layer, and stops on the ESL to form a second opening overlapping the first opening on the AR contact. A third etching is performed on the ESL through the second opening to extend the second opening to the AR contact, and the bottom of the second opening is tilted downward from the AR contact to the first opening. A metal layer is deposited to fill the first opening and the second opening, and a top surface of the metal layer and a top surface of the second ILD layer are planarized until the top surfaces are substantially flush. The portion of the metal layer in the first opening defines a gate via. The portion of the metal layer in the second opening defines a gate contact located above the gate via. The gate via and the gate contact together define a GC structure.

[0023] Because the AR contact is formed before the via-first process, the AR is not exposed when the GC structure is formed, and therefore does not undergo oxidation when the GC structure is formed. Because the bottom of the second opening slopes downward from the AR contact to the first opening, the aspect ratio (e.g., the ratio of height to width) of the first opening is low, and there is less risk of seams and voids forming in the first opening when the metal layer is deposited. Such seams and voids increase the resistance from the gate contact to the gate electrode, and thus may cause operating parameters to shift out of specification and / or increase power consumption.

[0024] Because the through-hole first process forms the gate contact on the gate through-hole, coverage control and size control can be easier than the optional process of forming the gate contact directly on the gate electrode. Therefore, the process window (e.g., robustness) of the through-hole first process can be larger than the optional process. It is more secure to join the gate through-hole to the gate electrode than to join the gate contact directly to the gate electrode because the gate through-hole can be centered above the gate electrode and can be smaller than the gate contact. It is more secure to join the gate contact to the gate through-hole than to join the gate contact to the gate electrode because the gate through-hole vertically separates the gate contact from other gate electrodes. In this way, there is less risk of leakage current and / or electrical coupling with other gate electrodes. In addition, the first opening provides a buffer to laterally space the second opening from another AR contact located on the opposite side of the first opening from the AR contact. In this way, there is less risk of leakage current and / or electrical coupling with other AR contacts.

[0025] refer to Figure 1A , a cross-sectional view 100A of some embodiments of an IC including a GC structure 102 is provided. The GC structure 102 electrically couples a gate electrode 104 to an AR contact 106 adjacent to the gate electrode 104. The AR contact 106 may also be referred to as a metal-to-oxide diffusion (MD) contact or a first-level contact, for example. The GC structure 102 and the AR contact 106 are located in a MOL region 108 of the IC. The MOL region 108 provides local circuit routing to alleviate consumption of circuit routing resources in a back-end-of-line (BEOL) region (not shown) of the IC located above the MOL region 108.

[0026] The GC structure 102 includes a GC plug 110 and a GC barrier 112 that cups the bottom side of the GC plug 110. The GC barrier 112 blocks material from the GC plug 110 from diffusing out of the GC plug 110 to surrounding structures and / or blocks material from diffusing from surrounding structures into the GC plug 110. In some embodiments, the GC barrier 112 also serves as an adhesion layer for the GC plug 110. The GC barrier 112 can be or include, for example, titanium, titanium nitride, tantalum nitride, tantalum, some other suitable barrier material, or any combination of the foregoing. The GC plug 110 can be or include, for example, cobalt, ruthenium, tungsten, some other suitable metal, or any combination of the foregoing.

[0027] In some embodiments, the thickness T of the GC barrier 112 is b is greater at the bottom of the GC barrier 112 than at the sidewalls of the GC barrier 112. For example, the thickness T b The thickness T may be about 3-8 nm at the bottom and / or about 1-3 nm at the sidewalls. However, other thickness values ​​at the bottom of the GC barrier 112 and / or at the sidewalls of the GC barrier 112 are possible. If the thickness T bToo small (eg, less than about 1 nanometer or some other suitable value), the GC barrier 112 may not effectively prevent material diffusion, and / or the GC plug 110 may not bond to the GC barrier 112. b If the GC plug 112 is too large (e.g., greater than about 8 nm or some other suitable value), the resistance from the GC plug 110 to the gate electrode 104 may be high because the resistance of the GC barrier 112 may be higher than the resistance of the GC plug 110. The high resistance may in turn cause the operating parameters of the IC to shift out of specification and / or result in high power consumption.

[0028] The GC structure 102 defines a gate via 114 and a gate contact 116. The gate contact 116 is located above the gate via 114 and the AR contact 106, and further extends laterally from the gate via 114 to the AR contact 106. The gate contact 116 may also be referred to as a metal to polysilicon (MP) contact or a second level contact, for example. However, it is noted that the gate electrode 104 is not limited to polysilicon, and may be or include metal and / or other suitable materials. The gate via 114 extends downward from the gate contact 116 to the gate electrode 104.

[0029] The bottom surface 102b of the GC structure 102 is tilted downward from the AR contact 106 to the gate through hole 114 at an angle α relative to the sidewalls of the GC structure 102 located at the gate through hole 114. In the case of the GC structure 102 with a tilt, the opening in which the gate through hole 114 is formed has a low aspect ratio (e.g., a low ratio of height to width). If it were not for the tilt, the bottom surface 102b of the GC structure 102 could be substantially horizontal, and the opening could have a high aspect ratio. The high aspect ratio can cause material to gather around the top corners in the opening when the layers forming the GC structure 102 are deposited. The gathering may clamp the top of the opening before the opening is completely filled to form a gap or void. Therefore, by forming the GC structure 102 with a tilt, the possibility of gaps and voids at the gate through hole 114 is reduced. Such gaps and voids increase the resistance from the gate contact 116 to the gate electrode 104, and thus may cause the operating parameters of the IC to deviate out of the specification range and / or cause high power consumption.

[0030] In some embodiments, the angle α is about 30-70 degrees, about 30-50 degrees, about 50-70 degrees, or some other suitable value. If the angle α is too small (e.g., less than about 30 degrees or some other suitable value), the aspect ratio of the gate via 114 may be high. As such, the likelihood of voids occurring at the gate via 114 may be high. If the angle α is too large (e.g., greater than about 70 degrees or some other suitable value), the gate contact 116 may be too close to the substrate 126. This, in turn, may increase leakage current and / or electrical shorts from the gate contact 116 to adjacent structures (e.g., adjacent to the gate electrode).

[0031] In an embodiment, the angle α and the aspect ratio of the gate via 114 depend on the spacing S between the gate via 114 and the AR contact 106. For example, the angle α and the aspect ratio may increase as the spacing S decreases. In some embodiments, the spacing S is about 9-18 nanometers, about 9.0-13.5 nanometers, about 13.5-18.0 nanometers, or some other suitable value. If the spacing S is too small (e.g., less than about 9 nanometers or some other suitable value), the angle α may be larger and the aspect ratio of the gate via 114 may be higher. In this way, the possibility of gaps and voids appearing at the gate via 114 may be higher. At emerging and future process nodes, the spacing S may be, for example, limited by component density, so that the spacing S may be, for example, less than about 18 nanometers or some other suitable value. In some embodiments, the spacing S is about 9-18 nanometers and the angle α is about 45-60 degrees. However, other values ​​of the spacing S and the angle α are also possible.

[0032] In some embodiments, the gate via 114 has a width W of about 8-25 nm, about 8.0-16.5 nm, about 16.5-25.0 nm, or some other suitable value. gv If the width W gv If the width W is too small (e.g., less than about 8 nanometers or some other suitable value), the gate via 114 may have a high aspect ratio and thus may be susceptible to the formation of seams and voids. In addition, due to the small size, the formation of the gate via 114 may be challenging. gv If the gate via 114 is too large (eg, greater than about 25 nm or some other suitable value), there is a high risk that the gate via 114 may be too close to an adjacent AR contact (not shown), which in turn may result in leakage current and / or electrical coupling with an adjacent AR contact.

[0033] The gate electrode 104 is spaced apart above the substrate 118 by a gate dielectric layer 120 and is adjacent to the source / drain region 122. The substrate 118 may be, for example, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or some other suitable semiconductor substrate. The gate dielectric layer 120 may be or include, for example, silicon oxide, a high-k dielectric, some other suitable dielectric material, or any combination of the foregoing. The gate electrode 104 may be or include, for example, doped polysilicon, a metal, some other suitable conductive material, or any combination of the foregoing.

[0034] The source / drain region 122 is located at the opposite end of the channel region 118c from another source / drain region (not shown). The channel region 118c is located below the gate electrode 104 in the substrate 118 and is configured to change between a conductive state and a non-conductive state according to a bias voltage applied to the gate electrode 104. The source / drain region 122 may be or include, for example, a doped semiconductor region of the substrate 118 and / or an epitaxial layer grown on the substrate 118. In some embodiments, the substrate 118 is single crystal silicon, and the source / drain region 122 is silicon germanium or silicon carbide. However, other materials are also possible. The source / drain region 122, the channel region 118c, the gate electrode 104, and the gate dielectric layer 120 partially define a semiconductor device 124. The semiconductor device 124 may be, for example, a field effect transistor (FET), some other suitable transistor, a memory cell, or other suitable semiconductor device.

[0035] The AR contact 106 extends from the GC structure 102 to the source / drain region 122, and the AR contact 106 and the GC structure 102 together define a composite conductive structure that electrically couples the gate electrode 104 to the source / drain region 122. In an optional embodiment, the AR contact 106 extends to a body contact region (not shown) of the semiconductor device 124 or to some other location in the active region 126 of the semiconductor device 124. The active region 126 is a semiconductor region on which the semiconductor device 124 is formed, and is at least partially defined by the source / drain region 122 and the top of the substrate 118 located below the gate electrode 104. In some embodiments, the active region 126 also includes a body contact region. In some embodiments, the active region 126 is divided by a shallow trench isolation (STI) structure (not shown) and / or some other suitable trench isolation structure. The active region 126 may also be referred to as an oxide diffusion (OD) region and / or a device region, for example. The AR contact 106 includes an AR plug 128 and an AR stopper 130 that cups the bottom side of the AR plug 128 .

[0036] The AR barrier 130 blocks material from the AR plug 128 from diffusing out of the AR plug 128 into the surrounding structure and / or blocks material from the surrounding structure from diffusing into the AR plug 128. In some embodiments, the AR barrier 130 also serves as an adhesion layer for the AR plug 128. The AR barrier 130 can be or include, for example, titanium, titanium nitride, tantalum nitride, some other suitable barrier material, or any combination of the foregoing. The AR plug 128 can be or include, for example, cobalt, ruthenium, tungsten, some other suitable metal, or any combination of the foregoing. In some embodiments, the AR plug 128 and the GC plug 110 are or include the same material and / or define a composite plug. In some embodiments, the AR barrier 130 and the GC barrier 112 are or include the same material and / or define a composite barrier layer extending in a closed path around the AR plug 128.

[0037] A pair of interlayer dielectric (ILD) layers 132 and an etch stop layer 134 are stacked above the substrate 118 and accommodate the AR contact 106 and the GC structure 102. The etch stop layer 134 separates the ILD layers 132 from each other and is substantially flush with the bottom of the gate contact 116. The ILD layer 132 can be or include, for example, silicon oxide, silicon nitride, a low-k dielectric, some other suitable dielectric, or any combination of the foregoing. The etch stop layer 134 can be or include, for example, silicon nitride, silicon carbide, some other suitable dielectric, or any combination of the foregoing.

[0038] As will be seen below, the etch stop layer 134 provides control of the vertical separation from the gate contact 116 to the gate electrode 104 and to an adjacent gate electrode (not shown). In addition, as will be seen below, the GC structure 102 is formed after the AR contact 106. As such, the openings within which the AR contact 106 is formed are filled during the formation of the GC structure 102, and the source / drain regions 122 are not exposed through the openings during the formation of the GC structure 102. This, in turn, reduces the likelihood of oxide formation on the source / drain regions 122 and increases the resistance from the AR contact 106 to the source / drain regions 122. This increased resistance can cause the operating parameters of the IC to shift out of specification, reduce yield, increase power consumption, etc.

[0039] In addition, as will be seen below, the gate contact 116 formed spaced above the gate electrode 104 and electrically coupled to the gate electrode 104 through the gate via 114 has a larger process window (e.g., is more robust) than omitting the gate via 114 and forming the gate contact 116 directly on the gate electrode 104. Forming the gate contact 116 directly on the gate electrode 104 includes bonding the gate contact 116 on the gate electrode 104 and the AR contact 106 while maintaining sufficient spacing from adjacent structures to avoid leakage current and / or electrical coupling. Such adjacent structures may include, for example, an adjacent gate electrode (not shown) and an adjacent AR contact (not shown). Thus, bonding the gate contact 116 directly on the gate electrode 104 is subject to a large number of overlay and / or size constraints. In addition, due to the large size of the gate contact 116, the constraints are very strict to avoid leakage current and / or electrical coupling to adjacent structures.

[0040] In contrast, a gate contact 116 is formed spaced apart above the gate electrode 104 and electrically coupled to the gate electrode 104 through the gate via 114, including bonding the gate via 114 to the gate electrode 104 and bonding the gate contact 116 to the gate via 114. Bonding the gate via 114 to the gate electrode 104 is subject to fewer constraints than bonding the gate contact 116 to the gate electrode 104. The gate via 114 is not bonded to the AR contact 106, so the gate via 114 can be centered above the gate electrode 104. In addition, the gate via 114 is smaller than the gate contact 116, so there is less risk that the gate via 114 is too close to adjacent structures and causes leakage current and / or electrical coupling. In this way, coverage and / or size constraints can be less stringent.

[0041] Engaging the gate contact 116 on the gate via 114 is also subject to less stringent overlay and / or size constraints than engaging the gate contact 116 on the gate electrode 104. The gate contact 116 is vertically offset from the gate electrode 104 and the adjacent gate electrode (not shown), so there is less risk of leakage current and / or electrical coupling from the gate contact 116 to the adjacent gate electrode (not shown). In addition, the via opening in which the gate via 114 is formed provides a buffer laterally between the adjacent AR contact (not shown) and the contact opening in which the gate contact 116 is formed. The buffer reduces the likelihood of the contact opening, and therefore reduces the likelihood of the gate contact 116 being too close to the adjacent AR contact. This in turn reduces the likelihood of leakage current and / or electrical coupling from the gate contact 116 to the adjacent AR contact.

[0042] refer to Figure 1B , provides Figure 1A100B of some optional embodiments of an IC of the present invention, in which the GC barrier 112 is omitted. In this way, the GC structure 102 and the GC plug 110 are one and the same. Because the resistance of the GC barrier 112 can be, for example, higher than that of the GC plug 110, omitting the GC barrier 112 can reduce the resistance from the gate contact 116 to the gate electrode 104. This can reduce power consumption and / or improve the performance of the semiconductor device 124. The GC structure 102 and the GC plug 110 can, for example, be or include tungsten, ruthenium, cobalt, some other suitable conductive material, or any combination of the foregoing. In some embodiments, the GC structure 102 is a single material or consists essentially of a single material in the entirety of the GC structure 102. In some embodiments, the GC plug 110 and the AR plug 128 are the same material. In an optional embodiment, the GC plug 110 and the AR plug 128 are different materials.

[0043] refer to Figure 1C , provides Figure 1A 100C of some alternative embodiments of an IC, wherein the gate via 114 and the gate contact 116 (collectively referred to as the GC structure 102) share a plug 136 and a barrier 138 with the AR contact 106. The plug 136 may be, for example, Figure 1A GC plug 110 and / or Figure 1A The AR plug 128 is described above. In addition, the plug 136 can be or include, for example, cobalt, ruthenium, tungsten, some other suitable metal, or any combination of the foregoing. The barrier 138 can be, for example, Figure 1A GC blocker 112 and / or Figure 1A The AR barrier 130 is described above. In addition, the barrier 138 can be or include, for example, titanium, titanium nitride, tantalum nitride, tantalum, some other suitable barrier material, or any combination of the foregoing.

[0044] refer to Figure 1D , provides Figure 1A 100D of some alternative embodiments of the IC, wherein the blocking member 138 is omitted. Figure 1B As discussed, omitting the barrier 138 may reduce the resistance from the gate contact 116 to the gate electrode 104 .

[0045] refer to Figure 2A , provides Figure 1A 200A is a cross-sectional view of some embodiments of an IC, wherein the semiconductor device 124 is a planar FET. Figure 2A The cross-sectional view 200A and Figure 1A The cross-sectional view 100A is orthogonal, and Figure 1A The cross-sectional view 100A can be taken along Figure 2A The line A-A' in is intercepted. Therefore, Figure 1AThe cross-sectional view 100A extends into and out of the page.

[0046] The gate electrode 104 and the gate dielectric layer 120 have a substantially flat profile and are partially located above the trench isolation structure 202. The trench isolation structure 202 has a pair of segments on opposite sides of the channel region 118c, respectively, and divides the active region 126 of the semiconductor device 124. The trench isolation structure 202 may be, for example, or include silicon oxide and / or some other suitable dielectric material. In addition, the trench isolation structure 202 may be, for example, or include an STI structure or some other suitable trench isolation structure.

[0047] refer to Figure 2B , provides Figure 2A 200B of some alternative embodiments of an IC, wherein the semiconductor device 124 is a finFET. Figure 2A Similar, for example, Figure 1A The cross-sectional view 100A can be taken along Figure 2B The gate electrode 104 and the gate dielectric layer 120 wrap the top of the fin 118f of the substrate 118. The fin 118f protrudes upward and has a top surface elevated above the top surface of the trench isolation structure 202. In addition, the fin 118f at least partially defines the active area 126 of the semiconductor device 124.

[0048] Despite Figure 2A and Figure 2B 1 and 12 are shown as planar FETs and finFETs, respectively, but the semiconductor device 124 may be some other suitable type of transistor or semiconductor device. Figure 2A and Figure 2B 1 and 12. The semiconductor device 124 may be used with the embodiments shown in the drawings. For example, the semiconductor device 124 may be a gate-all-around (GAA) FET or some other suitable transistor. The GAA FET may, for example, employ circular / square nanowires, horizontal nanoplates, horizontal nanosheets, hexagonal nanowires, nanorings, or some other suitable nanostructures for separate channel regions. Figure 1A Describes Figure 2A and Figure 2B , Figure 2A and Figure 2B The teachings in this section apply to Figures 1B to 1D For example, Figure 1C Optionally, follow Figure 2A and Figure 2B As another example, in Figure 2A and Figure 2BIn alternative embodiments, the GC blocking member 112 may be omitted. In these alternative embodiments, Figure 1B and Figure 1D Any of them can be intercepted along line A-A'.

[0049] refer to Figure 3A , provides Figure 1A FIG. 3 is a cross-sectional view 300A of some alternative embodiments of an IC, wherein a GC structure 102 is adjacent to a plurality of semiconductor devices 124 and a plurality of AR contacts 106. Figure 1A 1 and 2 . As their counterparts, semiconductor devices 124 and AR contacts 106 are described in detail. For example, each of the semiconductor devices 124 includes a gate electrode 104, a gate dielectric layer 120, etc. As another example, each of the AR contacts 106 includes an AR plug 128 and an AR barrier 130. In addition, the semiconductor devices 124 share a source / drain region 122. In an alternative embodiment, at least one of the semiconductor devices 124 has a separate source / drain region.

[0050] The GC structure 102 is located above the first gate electrode 104a and is separated from the second gate electrode 104b by a distance D1. Because the gate contact 116 is elevated above the second gate electrode 104b through the gate via 114, the distance D1 is greater than the distance D1 if the gate contact 116 is directly located on the first gate electrode 104a. As such, the likelihood of leakage current and / or electrical coupling from the gate contact 116 to the second gate electrode 104b is low.

[0051] In some embodiments, the distance D1 is about 5-25 nanometers, about 5-15 nanometers, about 15-25 nanometers, about 10-25 nanometers, greater than about 10 nanometers, or some other suitable value. If the distance D1 is too small (e.g., less than about 5 nanometers or some other suitable value), the leakage current from the gate contact 116 to the second gate electrode 104b may be high, and / or the possibility of electrical coupling from the gate contact 116 to the second gate electrode 104b may be high. If the distance D1 is too large (e.g., greater than about 25 nanometers or some other suitable value), the aspect ratio of the gate through hole 114 may be high. As described above with respect to Figure 1A As discussed, the high aspect ratio at the gate via 114 increases the likelihood of seams or voids forming at the gate via 114. Such seams and voids will increase the resistance from the gate contact 116 to the first gate electrode 104a, and thus may shift the operating parameters of the IC out of specification and / or increase power consumption.

[0052] Continue to refer Figure 3A, an inner sidewall spacer 302 is formed on the sidewall of the gate electrode 104, and an outer sidewall spacer 304 is formed on the sidewall of the inner sidewall spacer 302. In addition, a silicide layer 306 separates the AR contact 106 from the source / drain region 122, and a source / drain extension 122e protrudes outward from the source / drain region 122. In an optional embodiment, the source / drain extension 122e is omitted. The source / drain extension 122e is located below the outer sidewall spacer 304 and can, for example, have a lower doping concentration than the remaining portion of the source / drain region 122. The inner sidewall spacer 302 and the outer sidewall spacer 304 can, for example, be or include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, some other suitable dielectric, or any combination of the foregoing. In some embodiments, the inner sidewall spacer 302 and the outer sidewall spacer 304 are different materials. In other embodiments, the inner sidewall spacer 302 and the outer sidewall spacer 304 are the same material.

[0053] refer to Figure 3B , provides Figure 3A 300B of some alternative embodiments of an IC, wherein, as Figure 1B The GC structure 102 is configured as shown, and the GC barrier 112 is omitted. Figure 3A In other optional embodiments of the IC, the GC structure 102 and / or the AR contact 106 are as shown in FIG. Figure 1C and Figure 1D Any one of them.

[0054] refer to Figure 4A , provides Figure 3A 400A is a cross-sectional view of some embodiments of an IC, wherein a BEOL region 402 is located above and electrically coupled to the MOL region 108. The BEOL region 402 is partially shown and includes a plurality of interconnect lines 404 and a plurality of interconnect vias 406 located in a plurality of additional ILD layers 408 and a plurality of additional etch stop layers 410.

[0055] The plurality of interconnect lines 404 are grouped into a plurality of line levels located above the substrate 118, and the plurality of interconnect vias 406 are grouped into a plurality of via levels located above the substrate 118. The plurality of line levels and the plurality of via levels are alternately stacked to define a conductive path leading out from the MOL region 108. In addition, the plurality of line levels include a first line level M1 and a second line level M2, and the plurality of via levels include a zeroth via level V0 and a first via level V1. In some embodiments, one or more additional line levels (not shown) and / or one or more additional via levels are located above the second line level M2 and electrically coupled to the second line level M2.

[0056] refer to Figure 4B , provides Figure 4A 400B of some optional embodiments of an IC, wherein the GC structure 102 is electrically isolated from the BEOL region 402. In other words, the GC structure 102 is completely separated from the interconnect vias in the zeroth via level V0. In some embodiments, the top surface of the GC structure 102 directly contacts the corresponding additional etch stop layer 410 over the entire top surface.

[0057] For example, when the GC structure 102 is used for a static random access memory (SRAM), etc., Figure 4B Embodiments, and for example when the GC structure 102 is used for logic, etc., may appear Figure 4A In addition, in Figure 4A and Figure 4B In an alternative embodiment of the present invention, the GC structure 102 and / or the AR contact 106 may be, for example, Figures 1B to 1D Any one of them.

[0058] refer to Figure 5A , provides Figure 3A The top layout 500A of some embodiments of the IC. For example, Figure 3A The IC can be along Figure 5A . The GC structure 102 has rounded edges and is formed by the overlap between the contact pattern 502 and the via pattern 504 as described later. The contact pattern 502 is used to form the gate contact 116 and is elongated along the line BB'. The via pattern 504 is used to form the gate via 114 and is rounded. However, other shapes of the contact pattern 502 and / or the via pattern 504 are also possible. The contact pattern 502 and the via pattern 504 overlap by a distance D2, and the contact pattern 502 is separated from the first AR contact 106a by a distance D3.

[0059] In some embodiments, distance D2 is about 5-25 nanometers, about 5-15 nanometers, about 15-25 nanometers, about 3-25 nanometers, greater than about 3 nanometers, or some other suitable value. If distance D2 is too small (e.g., less than about 3 nanometers or some other suitable value), the electrical coupling between gate contact 116 and gate via 114 may be poor and / or faulty. Such poor electrical coupling may, for example, limit the amount of current transmitted from gate contact 116 to gate via 114 and / or cause the operating parameters of the IC to shift out of specification. If distance D2 is too large (e.g., greater than about 25 nanometers or some other suitable value), contact pattern 502 may extend beyond via pattern 504, and distance D3 may be too small (see below).

[0060] In some embodiments, the distance D3 is about 5-25 nanometers, about 5-15 nanometers, about 15-25 nanometers, about 3-25 nanometers, greater than about 3 nanometers, or some other suitable value. If the distance D3 is too small (e.g., less than about 3 nanometers or some other suitable value), the leakage current between the gate contact 116 and the first AR contact 106a may be high, and / or the gate contact 116 and the first AR contact 106a may be electrically coupled. If the distance D3 is too large (e.g., greater than about 25 nanometers or some other suitable value), device scaling may be unnecessarily hindered, and / or the distance D2 may be too small.

[0061] Due to the gate via 114, the risk of distance D2 and distance D3 being too small and / or too large is reduced. During the formation of the GC structure 102, a via opening having a via pattern 504 is first formed, and then a contact opening having a contact pattern 502 overlapping the via opening is formed. Therefore, the via pattern 504 provides a buffer laterally between the contact pattern 502 and the first AR contact 106a. The buffer reduces the possibility of the contact pattern 502 being too close to the first AR contact 106a (e.g., see distance D3). In this way, the possibility of leakage current and / or electrical short circuit is reduced. In addition, compared with other methods, the buffer allows the contact pattern 502 to be closer to the first AR contact 106a. In this way, the coverage between the contact pattern 502 and the via pattern 504 (e.g., with distance D2) is firm (e.g., with a large coverage window).

[0062] refer to Figure 5B and Figure 5C , provides Figure 5A The top layouts 500B and 500C of some alternative embodiments of the IC are shown in which the edges of the GC structure 102 are substantially square. In addition, the contact pattern 502 and the via pattern 504 are rectangular or square. Figure 5B and Figure 5C Between the top layouts 500B and 500C, the width of the AR contact 106 is less than Figure 5B The width of the gate electrode 104 is greater than Figure 5C The width of the gate electrode 104 in .

[0063] refer to Figure 5D , provides Figure 5A 5 , wherein the GC structure 102 is at an angle Φ. The angle Φ is relative to a reference axis 506 that is perpendicular to the direction along which the gate electrode 104 and the AR contact 106 are elongated. The angle Φ may be, for example, less than about 30 degrees, less than about 20 degrees, less than about 10 degrees, or some other angle.

[0064] In some embodiments, by orienting the GC structure 102 at the angle Φ, the contact pattern 502 can extend a greater distance along its central axis 508 over the second AR contact 106 b without being too close to the second gate electrode 104 . For example, the distance D along the central axis 508 is Φ It can be equal to the distance D0 along the reference axis 506 divided by COS(Φ) (eg, D Φ =D0 / COS(Φ)), so that D Φ φ may be greater than D0. Because the contact pattern 502 may extend a greater distance above the second AR contact 106 b, the likelihood of the contact pattern 502, and therefore the gate contact 116, being bonded on the second AR contact 106 b may be increased. In some embodiments, by orienting the GC structure 102 at an angle φ, the likelihood of the contact pattern 502, and therefore the gate contact 116, being bonded on the gate via 114 may be increased. For example, this may be due to the same reasons described above.

[0065] Despite FIG. 5A to FIG. 5D Specific shapes of the GC structure 102, the contact pattern 502, and the via pattern 504 are shown in FIG. 1 , but in alternative embodiments, other shapes are also possible. FIG. 5A to FIG. 5D In an alternative embodiment of the present invention, the GC structure 102 and / or the AR contact 106 may be, for example, Figures 1B to 1D For example, in FIG. 5A to FIG. 5D In an alternative embodiment, the GC barrier 112 may be omitted.

[0066] refer to Fig. 6A , a top layout 600A of some embodiments of an IC including a plurality of GC structures 102 is provided, wherein the GC structures 102 are located on a plurality of AR contacts 106 and a plurality of semiconductor devices 124 configured as finFETs. The GC structures 102, AR contacts 106, and semiconductor devices 124 may be, for example, as in Figures 1A to 1D , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B and FIG. 5A to FIG. 5D In some embodiments, Figures 1A to 1D , Figure 2B , Figure 3A , Figure 3B , Figure 4A and Figure 4B Any one of which is taken along line C, and / or Figure 2B Taken along line D.

[0067] A plurality of fins 118f are defined by a substrate (eg, see Figure 2B118 in the figure), and the fins 118f are extended in parallel in a first direction. A plurality of gate electrodes 104 and a plurality of AR contacts 106 are extended in parallel in a second direction orthogonal to the first direction. The first direction and the second direction may be, for example, the X direction and the Y direction, respectively, or vice versa. The gate electrodes 104 are respectively located above the fins 118f (when viewed in cross section) and across the fins 118f. Similarly, the AR contacts 106 are respectively located above the fins 118f (when viewed in cross section) and / or across the source / drain regions (not shown; see, for example, Figure 1A In an alternative embodiment, at least one of the AR contacts 106 is located at another location in the active region for a corresponding one of the semiconductor devices 124 (eg, other than the source / drain region).

[0068] The fins 118f and the gate electrodes 104 partially define a semiconductor device 124. The GC structures 102 are located on the semiconductor device 124 and extend from the respective gate electrodes 104 to the respective AR contacts 106 to provide electrical coupling therebetween. The GC structures 102 include respective gate vias 114 and respective gate contacts 116. The gate vias 114 vertically separate the gate contacts 116 from the gate electrodes 104. As described above, the gate vias 114 allow the GC structures 102 to be formed more securely and reduce leakage current.

[0069] Continue to refer Fig. 6A , multiple AR vias 602 are located on some AR contacts 106. In addition, multiple additional gate vias 114 are separated from the GC structure 102 and are located on the gate electrode 104. In some embodiments, the AR vias 602 are always a single material, while the additional gate vias 114 include multiple materials. For example, the AR vias 602 may have no blocking members, while the additional gate vias 114 may include corresponding blocking members and corresponding plugs. See, for example Figure 1A 110 and 112.

[0070] refer to Figure 6B , provides Fig. 6A The top layout 600B of some alternative embodiments of the IC, wherein the GC structure 102 is oriented at an angle Φ. The angle Φ is relative to a reference axis that is parallel to the direction in which the fin 118f is elongated and / or perpendicular to the direction in which the gate electrode 104 and the AR contact 106 are elongated. Figure 5D As described and explained, the angle Φ may, for example, increase the likelihood of bonding the gate contact 116 to the corresponding AR contact 106 and / or the corresponding gate via 114. In other words, the angle Φ may increase the bonding window of the gate contact 116, for example.

[0071] refer to Figure 7 , along Fig. 6A Line C in provides Fig. 6A 700 of some embodiments of an IC. The semiconductor device 124 is located on the fin 118f of the substrate 118 and includes a corresponding gate electrode 104, a corresponding high-k dielectric layer 706, and a corresponding gate dielectric layer 120. Note that the high-k dielectric layer 706 can also be interpreted as a gate dielectric layer. The gate electrode 104 includes a corresponding metal plug 702 and a corresponding work function layer 704 that cups the bottom side of the metal plug 702. The high-k dielectric layer 706 cups the bottom side of the work function layer 704 and separates the work function layer 704 from the gate dielectric layer 120.

[0072] The GC structure 102 is located on a corresponding one of the semiconductor devices 124 and a corresponding one of the AR contacts 106. The GC structure 102 includes a GC plug 110 and a GC stopper 112 that cups the bottom side of the GC plug 110. In an alternative embodiment, as shown in FIG. Figure 1B GC barrier 112 is omitted. A corresponding one of the AR contacts 106 extends from the GC structure 102 to the silicide layer 306 on the source / drain region 122. Another AR contact 106 is located on the right side of the GC structure 102 and extends below the top surface of the fin 118f to the trench isolation structure 202. A capping layer 710 covers the semiconductor device 124 between the gate electrode 104 and an adjacent one of the ILD layers 132. The capping layer 710 may be or include, for example, silicon nitride and / or some other suitable dielectric.

[0073] refer to Figure 8 ,exist Fig. 6A Box E provides Fig. 6A The cross-sectional projection 800 of some embodiments of the IC. The cross-sectional projection 800 is within the frame E Fig. 6A The projection of the portion in FIG. 800 onto a two-dimensional (2D) plane in the direction indicated by the arrow on the frame E. Thus, the cross-sectional projection 800 is similar to Figure 7 700, in addition to illustrating overlap between features in different cross-sections. For example, the AR via 602 is shown adjacent to the GC structure 102 on a corresponding one of the AR contacts 106, even though the AR via 602 and the GC structure 102 may be in different cross-sections. As another example, the gate electrode 104 is shown extending below the top surface of the fin 118b in the same cross-section as the GC structure 102, even though the extension may be in a different cross-section.

[0074] refer to Figures 9 to 16 , Fig.17A and Fig. 17B, a series of cross-sectional views 900-1600, 1700A, and 1700B of some embodiments of methods for forming an IC including a GC structure are provided. The cross-sectional views 900-1600, 1700A, and 1700B correspond to Figure 3A The cross-sectional view 300A thus shows Figure 3A However, the method shown by the cross-sectional views 900-1600, 1700A and 1700B can also be used to form the IC and GC structure 102 in FIG. Figure 1A , Figure 2A , Figure 2B , Figure 4A , Figure 4B , FIG. 5A to FIG. 5D , Fig. 6A , Figure 6B , Figure 7 and Figure 8 Any one of the IC and / or GC structures 102.

[0075] like Fig. 9 As shown in cross-sectional view 900 of , a plurality of semiconductor devices 124 are provided or otherwise formed above a substrate 104. The semiconductor devices 124 include respective gate electrodes 104 and respective gate dielectric layers 120 separating the gate electrodes 104 and the substrate 118. In addition, the semiconductor devices 124 share respective source / drain regions 122 laterally located between the gate electrodes 104. In an alternative embodiment, at least one of the semiconductor devices 124 has a separate source / drain region. The source / drain region 122 may be, for example, a doped region of the substrate 118 and / or an epitaxial layer formed to be recessed into a top portion of the substrate 118. The source / drain region 122 and a top portion of the substrate 118 located below the semiconductor devices 124 at least partially define an active region 126.

[0076] In some embodiments, semiconductor devices 124 are planar FETs and / or each has Figure 2A For example, the cross-sectional profile of the semiconductor device taken along line FF' can be taken as its counterpart in Figure 2A In an alternative embodiment, semiconductor device 124 is a finFET and / or each has Figure 2B For example, the cross-sectional profile of the semiconductor device taken along line FF' can be taken as its counterpart in Figure 2B In other alternative embodiments, semiconductor device 124 is a GAA transistor, some other suitable transistor, a memory cell, or some other suitable semiconductor device.

[0077] Also through Fig. 9The cross-sectional view 900 shows that a plurality of inner sidewall spacers 302 and a plurality of outer sidewall spacers 304 are formed. The inner sidewall spacers 302 are respectively formed on the sidewalls of the gate electrode 104. The outer sidewall spacers 304 are respectively formed on the sidewalls of the inner sidewall spacers 302 and are respectively formed on the source / drain regions 122.

[0078] like Fig.10 As shown in the cross-sectional view 1000 of , the first ILD layer 132a is formed above the semiconductor device 124 and the substrate 118. In addition, the first ILD layer 132a is formed to have a flat or substantially flat top surface. The process for forming the first ILD layer 132a may, for example, include depositing the first ILD layer 132a, and then performing planarization on the top surface of the first ILD layer 132a. However, other processes are also possible. Planarization may, for example, be or include chemical mechanical polishing (CMP) and / or some other suitable planarization process.

[0079] like Fig.11 As shown in the cross-sectional view 1100 of FIG. 1 , a first etching is performed on the first ILD layer 132a to form a plurality of AR openings 1102. The AR openings 1102 expose at least some of the source / drain regions 122 and / or some other suitable locations in the active region 126. In some embodiments, the AR openings 1102 have a laterally elongated and / or top layout located above a plurality of fins of the finFET. For example, the AR openings 1102 may be formed by referring to FIG. Fig. 6A and / or Figure 6B A non-limiting example of such a top layout is found in the AR contact 106 in the AR opening 1102. In an optional embodiment, the AR opening 1102 has a top layout of a circle, a square, or other suitable shape. The process for performing the first etch may, for example, include: forming a first mask 1104 on the first ILD layer 132a; etching the first ILD layer 132a with the first mask 1104 in place; and removing the first mask 1104. However, other processes are also possible. The first mask 1104 may, for example, be a photoresist and / or some other suitable mask material.

[0080] like Fig.12 As shown in the cross-sectional view 1200 of FIG. 1 , a silicide layer 306 is formed on the active region 126 at the bottom of the AR opening 1102 (eg, see FIG. 1 ). Fig.11 ). For example, a silicide layer 306 may be formed on the source / drain region 122 in the AR opening 1102. The silicide layer 306 is or includes a metal silicide. The silicide layer 306 may be formed, for example, by a self-aligned silicide process or some other suitable process for forming a metal silicide.

[0081] Also through Fig.12The cross-sectional view 1200 shows that the AR contact 106 is formed to fill the AR opening 1102 above the silicide layer 306 (see, for example, Fig.11 ). The AR contact 106 includes a corresponding AR plug 128 and a corresponding AR barrier 130 that cups the bottom side of the AR plug 128. The process for forming the AR contact 106 may, for example, include: 1) depositing a barrier layer that covers the first ILD layer 132a and lines and partially fills the AR opening 1102; 2) depositing a plug layer that covers the barrier layer and fills the remaining portion of the AR opening 1102; and 3) performing planarization on the barrier layer, the plug layer, and the first ILD layer 132a until their top surfaces are substantially flat. However, other processes for forming the AR contact 106 are also possible. The planarization thins the first ILD layer 132a to a thickness T ild , and the plug layer and the barrier layer are respectively divided into an AR plug 128 and an AR barrier 130. In addition, the planarization may be or include, for example, CMP and / or some other suitable planarization process.

[0082] In some embodiments, the thickness T of the first ILD layer 132 a is ild About 8-25 nm, about 8-16.5 nm, about 16.5-25 nm, or some other suitable value above the gate electrode 104. If T ild If the thickness T is too small (e.g., less than about 8 nanometers or some other suitable value), the likelihood that a subsequently formed gate contact will become too close to an adjacent gate electrode becomes high. This, in turn, increases the likelihood of leakage currents and / or electrical shorts that may cause device failure. ild Too large (eg, greater than about 25 nanometers), and material is wasted.

[0083] like Fig.13 As shown in the cross-sectional view 1300 of FIG. 1 , an etch stop layer 134 and a second ILD layer 132b are deposited over the first ILD layer 132a and the AR contact 106. The etch stop layer 134 separates the first ILD layer 132a and the second ILD layer 132b from each other and, as described later, serves as an etch stop layer when forming a gate contact to provide control over the vertical spacing between the gate contact and the gate electrode 104.

[0084] like Fig.14 As shown in the cross-sectional view 1400 of FIG. 14, a second etching is performed on the first and second ILD layers 132a, 132b and the etch stop layer 134 to form a through hole opening 1402 exposing the first gate electrode 104a. The through hole opening 1402 may have, for example, FIG. 5A to FIG. 5D , Fig. 6A and Figure 6B The gate via 114 shown in FIG. FIG. 5A to FIG. 5DThe top layout is shown in FIG. 5A-5D . However, other top layouts are also possible.

[0085] In some embodiments, the via opening 1402 has a width W of about 8-25 nm, about 8.0-16.5 nm, about 16.5-25.0 nm, or some other suitable value. gv If the width W gv If the width W is too small (e.g., less than about 8 nanometers or some other suitable value), the via opening 1402 may have a high aspect ratio, and thus a gate via subsequently formed in the via opening 1402 may be easily formed with seams and voids. In addition, due to the small size, the formation of the via opening 1402 may be challenging. gv If the gate via is too large (e.g., greater than about 25 nm or some other suitable value), there is a high risk that the via opening 1402 may be too close to the first AR contact 106a to the right of the via opening 1402. As a result, the gate via may have a high leakage current and / or be electrically shorted to the first AR contact 106a.

[0086] The process for performing the second etch may, for example, include forming a second mask 1404 on the second ILD layer 132 b, etching the first and second ILD layers 132 a, 132 b and the etch stop layer 134 with the second mask 1404 in place, and removing the second mask 1404. However, other processes are also possible. The second mask 1404 may, for example, be a photoresist and / or some other suitable mask material.

[0087] like Fig.15 As shown in the cross-sectional view 1500 of FIG. 1 , a third etching is performed on the second ILD layer 132 b to form a contact opening 1502. The contact opening 1502 is located above the second AR contact 106 b on the left side of the via opening 1402. In addition, the contact opening 1502 overlaps the via opening 1402 by a distance D2 and is laterally separated from the first AR contact 106 a by a distance D3. The contact opening 1502 may have, for example, FIG. 5A to FIG. 5D The top layout is shown in FIG. 5 , with contact pattern 502 in FIG. However, other top layouts are also possible.

[0088] In some embodiments, distance D2 is about 5-25 nanometers, about 5-15 nanometers, about 15-25 nanometers, about 3-25 nanometers, greater than about 3 nanometers, or some other suitable value. If distance D2 is too small (e.g., less than about 3 nanometers or some other suitable value), the electrical coupling between the gate contact and gate via subsequently formed in contact opening 1502 and via opening 1402 may be poor and / or malfunction. If distance D2 is too large (e.g., greater than about 25 nanometers or some other suitable value), contact opening 1502 may extend beyond via opening 1402. This, in turn, increases the risk that distance D3 is too small (see below).

[0089] In some embodiments, the distance D3 is about 5-25 nanometers, about 5-15 nanometers, about 15-25 nanometers, about 3-25 nanometers, greater than about 3 nanometers, or some other suitable value. If the distance D3 is too small (e.g., less than about 3 nanometers or some other suitable value), leakage current between a gate contact subsequently formed in the contact opening 1502 and the first AR contact 106a may be high, and / or the gate contact and the first AR contact 106a may be electrically coupled. If the distance D3 is too large (e.g., greater than about 25 nanometers or some other suitable value), device scaling may be unnecessarily hindered and / or the distance D2 may be too small.

[0090] Due to the via opening 1402, the risk of distance D2 and distance D3 being too small and / or too large is reduced. The via opening 1402 provides a buffer laterally between the contact opening 1502 and the first AR contact 106a. The buffer reduces the possibility of the contact opening 1502 being too close to the first AR contact 106a (e.g., see distance D3). In this way, the possibility of leakage current and / or electrical short circuit is reduced. In addition, the buffer allows the contact opening 1502 to be closer to the first AR contact 106a than would otherwise be possible. In this way, the coverage between the contact opening 1502 and the via opening 1402 (e.g., distance D2) is secure (e.g., with a large process window).

[0091] The process for performing the third etch may, for example, include: forming a third mask 1504 on the second ILD layer 132b; etching the second ILD layer 132b with the third mask 1504 in place; and removing the third mask 1504. Other processes are also possible. In some embodiments, the third mask 1504 is a photoresist and / or some other suitable mask material. In some embodiments, the third mask 1504 partially fills the via opening 1402 to protect the first gate electrode 104a in the via opening 1402 and / or protects the width W of the via opening 1402. gvIn some embodiments, the etch stop layer 134 functions as an etch stop layer for etching, such that the etching stops on the etch stop layer 134 . In some embodiments, over-etching occurs during etching, and the contact opening 1502 extends into the etch stop layer 134 .

[0092] In some embodiments, etching is performed by dry etching to achieve high selectivity between the second ILD layer 132b and the etch stop layer 134 and minimize over-etching. In some embodiments, dry etching forms a plasma from an etching gas, which is or includes hexafluoro-1,3-butadiene gas (e.g., C4F6) to achieve high selectivity. However, other etching gases are also possible. In some embodiments where the etching gas is or includes hexafluoro-1,3-butadiene gas, the second ILD layer 132b is or includes silicon oxide, and the etch stop layer 134 is or includes silicon nitride. However, other materials of the second ILD layer 132b and the etch stop layer 134 are also possible, and / or other etching gases are also possible. In an optional embodiment, etching is performed by wet etching and / or some other suitable etching process. However, wet etching may not be able to achieve high selectivity between the second ILD layer 132b and the etch stop layer 134.

[0093] like Fig.16 As shown in the cross-sectional view of 1600 of FIG. 1 , a fourth etch is performed on the etch stop layer 134 to extend the contact opening 1502 to the second AR contact 106 b and to recess the bottom surface of the contact opening 1502 by a distance D4. In addition, the fourth etch corrodes a corner 1602 (shown in dotted lines) at the boundary between the via opening 1402 and the contact opening 1502, so that the bottom surface slopes downward from the second AR contact 106 b to the via opening 1402. The bottom surface is at an angle α relative to the sidewall of the via opening 1402, and the bottom surface and the sidewall are defined by the first ILD layer 132 a.

[0094] By forming the contact opening 1502 so that the bottom surface is tilted downward, the via opening 1402 and therefore the gate via subsequently formed in the via opening 1402 have a low aspect ratio (e.g., a low ratio of height to width). The low aspect ratio of the via opening 1402 prevents the material from gathering around the corner 1602 when the material forming the gate via is deposited. This gathering can then clamp the top of the via opening 1402 before the via opening 1402 is completely filled to form a gap or void. Such gaps and voids can increase the resistance of the gate via and / or may cause the operating parameters to shift out of the specification range. Therefore, by forming the contact opening 1502 so that the bottom surface is tilted downward, the possibility of gaps and voids at the via opening 1402 and therefore at the gate via is reduced.

[0095] In some embodiments, the angle α is about 30-70 degrees, about 30-50 degrees, about 50-70 degrees, or some other suitable value. If the angle α is too small (e.g., less than about 30 degrees or some other suitable value), the aspect ratio of the via opening 1402 may be high. As a result, the possibility of gaps and voids appearing at the gate vias subsequently formed in the via opening 1402 may be high. If the angle α is too large (e.g., greater than about 70 degrees or some other suitable value), over-etching of the first ILD layer 132a may occur, and the distance D1 from the contact opening 1502 to the second gate electrode 104b may also become too small. If the distance D1 is too small, leakage current and / or electrical short circuit may occur from the second gate electrode 104b to the gate contact subsequently formed in the contact opening 1502.

[0096] In some embodiments, the angle α and the aspect ratio of the gate opening 1402 depend on the spacing S between the via opening 1402 and the second AR contact 106b. For example, as the spacing S decreases, the angle α and the aspect ratio can increase. In some embodiments, the spacing S is about 9-18 nanometers, about 9.0-13.5 nanometers, about 13.5-18.0 nanometers, or some other suitable value. If the spacing S is too small (e.g., less than about 9 nanometers or some other suitable value), the angle α may be larger and the aspect ratio may be higher. In this way, the possibility of gaps and voids appearing at the gate via 114 may be higher. At emerging and future process nodes, the spacing S may be, for example, limited by component density, so that the spacing S may be, for example, less than about 18 nanometers or some other suitable value. In some embodiments, the spacing S is about 9-18 nanometers and the angle α is about 45-60 degrees. However, other values ​​of the spacing S and the angle α are also possible.

[0097] In some embodiments, the distance D4 is less than about 10 nanometers or some other suitable value. If the distance D4 is too large (e.g., greater than about 10 nanometers or other suitable values), the distance D1 from the contact opening 1502 to the second gate electrode 104b may become too small. In some embodiments, the distance D1 is about 5-25 nanometers, about 5-15 nanometers, about 15-25 nanometers, about 10-25 nanometers, greater than about 10 nanometers or some other suitable values. If the distance D1 is too small (e.g., less than about 5 nanometers or some other suitable values), leakage current and / or electrical short circuit may occur from the second gate electrode 104b to the gate contact subsequently formed in the contact opening 1502. If the distance D1 is too large (e.g., greater than about 25 nanometers or some other suitable values), the aspect ratio of the through-hole opening 1402 may be high. As described above, this increases the possibility of forming a gap or void at the through-hole opening 1402.

[0098] The process for performing the fourth etch may, for example, include etching the etch stop layer 134 and subsequently cleaning the etch residue. However, other processes are also possible. For example, the cleaning may be omitted. In some embodiments, the third etch (see, for example, Fig.15 ) and the fourth etch are performed in situ in a common etching process chamber, so that the substrate 118 is continuously in the common etching process chamber from the beginning of the third etch to the end of the fourth etch. In an alternative embodiment, the fourth etch is performed in an etching process chamber different from the third etch. In some embodiments, the first ILD layer 132a is used as an etch stop for the etching of the fourth etch, so that the etching stops on the first ILD layer 132a. In some embodiments, over-etching occurs during etching, so that the contact opening 1502 extends into the first ILD layer 132a.

[0099] In some embodiments, etching is performed by dry etching. Dry etching allows high selectivity between the etch stop layer 134 and the first ILD layer 132a to minimize over-etching and keep the distance D1 large. In addition, dry etching provides physical bombardment of ions, which corrode the corner 1602 and tilt the bottom surface of the contact opening 1502. As described above, tilting prevents the formation of voids and gaps at the through-hole opening 1402. In some embodiments, dry etching forms a plasma by an etching gas, which is or includes tetrafluoromethane gas (e.g., CF4) and / or hydrogen (e.g., H2). However, other etching gases are also possible. In some embodiments where the etching gas includes tetrafluoromethane gas and hydrogen, the ratio of hydrogen to tetrafluoromethane gas is greater than about 10. For example, the flow rate of hydrogen entering the process chamber where the dry etching is performed can be about 10 times greater than the flow rate of tetrafluoromethane gas. In some embodiments where the etching gas includes tetrafluoromethane gas and hydrogen, the etch stop layer 134 is or includes silicon nitride, and the first ILD layer 132a is or includes silicon oxide. However, other materials and gases are also possible. In alternative embodiments, etching is performed by wet etching and / or some other suitable etching process. However, wet etching may not achieve high selectivity between the etch stop layer 134 and the first ILD layer 132a, so over-etching may be high. This increases the possibility that the distance D1 becomes too small (as described above).

[0100] In some embodiments, cleaning is performed by or includes plasma treatment of exposed surfaces in the via opening 1402 and the contact opening 1502 using hydrogen (e.g., H2) and / or nitrogen (e.g., N2). However, other gases and / or other cleaning processes are also possible. The plasma treatment bombards the corner 1602 with ions and corrodes the corner 1602 to further tilt the bottom of the contact opening 1502. As described above, tilting prevents the formation of voids and gaps at the via opening 1402. In some embodiments, the cleaning corrodes the corner 1602 to a greater extent than etching, and / or the cleaning and etching are performed by dry etching and plasma treatment processes, respectively.

[0101] like Fig.17A As shown in the cross-sectional view 1700A of FIG. 1700A , a barrier layer 1702 is deposited to cover the second ILD layer 132 b and further deposited to line and partially fill the contact opening 1502 (see, for example, FIG. 1700B ). Fig.16 ) and through hole opening 1402 (see, for example, Fig.16 ). In addition, a plug layer 1704 is deposited to cover the barrier layer 1702 and fill the remaining portions of the contact opening 1502 and the via opening 1402. The barrier layer 1702 prevents material from diffusing through the barrier layer 1702 and / or diffusing through the barrier layer 1702 to the plug layer 1704. In addition, in some embodiments, the barrier layer 1702 serves as an adhesion layer for the plug layer 1704. The barrier layer 1702 can be or include, for example, titanium, titanium nitride, tantalum nitride, some other suitable barrier material, or any combination of the foregoing. The plug layer 1704 can be or include, for example, cobalt, ruthenium, tungsten, some other suitable metal, or any combination of the foregoing.

[0102] In some embodiments, the thickness T of the barrier layer 1702 is b The thickness T at the bottom of the barrier layer 1702 is greater than that at the sidewalls of the barrier layer 1702. For example, the thickness T at the bottom b It may be about 3-8 nm, and / or a thickness T at the sidewalls b It can be about 1-3 nanometers. However, other thickness values ​​are also possible. If the thickness T b If the thickness T is too small (eg, less than about 1 nanometer or some other suitable value), the barrier layer 1702 may not effectively prevent material diffusion, and / or the plug layer 1704 may not adhere to the barrier layer 1702. b If the thickness is too large (e.g., greater than about 8 nanometers or some other suitable value), the resistance from the plug layer 1704 to the first gate electrode 104a may be high because the barrier layer 1702 may have a high resistance relative to the plug layer 1704. The high resistance may, for example, cause the operation of the IC to deviate from the specification range.

[0103] The deposition of the barrier layer 1702 may be, for example, or include chemical vapor deposition (CVD), physical vapor deposition (PVD), some other suitable deposition process, or any combination thereof. The deposition of the plug layer 1704 may be, for example, or include CVD, PVD, chemical plating, electroplating, some other suitable deposition process, or any combination thereof.

[0104] like Fig. 17B As shown in the cross-sectional view 1700B, the barrier layer 1702 (for example, see Fig.17A ), plug layer 1704 (see, for example, Fig.17A ) and the second ILD layer 132b are planarized until their top surfaces are substantially flush. The planarization may be, for example, or include CMP and / or some other suitable planarization process. The planarization is performed on the contact opening 1502 (eg, see Fig.16 ) and through hole opening 1402 (see, for example, Fig.16 ) to form a GC structure 102.

[0105] The GC structure 102 electrically couples the first gate electrode 104a to the second AR contact 106b. The GC structure 102 includes a GC plug 110 and a GC barrier 112 formed by a plug layer 1704 and a barrier layer 1702, respectively. The GC barrier 112 cups the bottom side of the GC plug 110 and separates the GC plug 110 from the first gate electrode 104a and the second AR contact 106b. In addition, the GC structure 102 defines a gate via 114 and a gate contact 116. The bottom surface of the GC structure 102 is tilted downward from the second AR contact 106b to the gate via 114. As described above, the tilting reduces the aspect ratio of the gate via 114, thereby reducing the possibility of gaps and / or voids. The gaps and / or voids will increase the resistance from the gate contact 116 to the first gate electrode 104a, thereby possibly causing the operating parameters of the IC to deviate out of the specification range.

[0106] As seen in the previous figures (see, for example, Figures 14 to 16 , Fig.17A and Fig. 17B ), the GC structure 102 is formed after the AR contact 106. Because the GC structure 102 is formed after the AR contact 106, during the formation of the GC structure 102, the AR opening 1102 in which the AR contact 106 is formed is filled (see, for example, Fig.11). In addition, during the formation of the GC structure 102, the source / drain region 122 and / or other portions of the active region 126 in the AR opening 1102 are not exposed through the AR opening 1102. This in turn prevents oxidation of the source / drain region and / or the active region 126 during the formation of the GC structure 102. Such oxidation will increase the resistance from the AR contact 106 to the active region 126. Such increased resistance in turn may cause the operating parameters of the IC to shift out of specification, reduce yield, increase power consumption, etc.

[0107] In addition, as seen in the previous figures (see, for example, Figures 14 to 16 , Fig.17A and Fig. 17B ), the gate contact 116 is formed to be spaced above the first gate electrode 104a and electrically coupled to the first gate electrode 104a through the gate via 114. Such formation of the gate contact 116 has a larger process window (e.g., more robust) than omitting the gate via 114 and forming the gate contact 116 directly on the first gate electrode 104a. Forming the gate contact 116 directly on the gate electrode 104 includes bonding the contact opening 1502 on both the first gate electrode 104a and the second AR contact 106b (e.g., see Fig.16 ), while maintaining sufficient spacing from the second gate electrode 104b and the first AR contact 106a to avoid leakage current and / or electrical coupling. In this way, directly bonding the contact opening 1502 to the gate electrode 104 is subject to a large number of overlay and / or size constraints. In addition, due to the large size of the contact opening 1502, the constraints are very strict to avoid leakage current and / or electrical coupling.

[0108] In contrast, forming the gate contact 116 spaced apart above the gate electrode 104 and electrically coupled to the gate electrode 104 through the gate via 114 includes forming a via opening 1402 (see, e.g., Fig.16 ) is bonded on the gate electrode 104 and the contact opening 1502 is bonded on the via opening 1402. Compared with bonding the contact opening 1502 on the first gate electrode 104a, these two bonds individually or collectively have a larger process window (e.g., more secure). Bonding the via opening 1402 on the first gate electrode 104a is subject to fewer constraints than bonding the contact opening 1502 on the first gate electrode 104a. The via opening 1402 is not bonded on the second AR contact 106b, so the via opening 1402 can be centered above the first gate electrode 104a. In addition, the via opening 1402 is smaller than the contact opening 1502, so there is less risk that the via opening 1402 is too close to the first AR contact 106a and causes leakage current and / or electrical short circuits. In this way, coverage and / or size constraints may be less stringent.

[0109] Compared to bonding the contact opening 1502 on the first gate electrode 104a, bonding the contact opening 1502 on the via opening 1402 is subject to less stringent constraints. The contact opening 1502 is vertically offset from the second gate electrode 104b, so that there is less risk that the contact opening 1502 is too close to the second gate electrode 104b and causes leakage current and / or electrical short circuits. In addition, the via opening 1402 provides a buffer laterally between the contact opening 1502 and the first AR contact 106a. The buffer reduces the possibility that the contact opening 1502 is too close to the first AR contact 106a and causes leakage current and / or electrical short circuits with the first AR contact 106a.

[0110] exist Fig. 17B After forming the GC structure 102 in the embodiment of the present invention, a BEOL region (not shown) may be formed over the GC structure 102 and the second ILD layer 132 b. For an example of such a BEOL region, see Figure 4A and Figure 4B BEOL region 402 in the.

[0111] Although Fig.17A and Fig. 17B FIG. 1 shows the formation of the GC structure 102 with the GC stopper 112. In alternative embodiments, the GC stopper 112 may be omitted. In some embodiments where the GC stopper 112 is omitted, Fig.17A Then, the above-described method is performed without the barrier layer 1702. Fig. 17B In some embodiments where the GC blocker 112 is omitted, 18A to 18C The action (described below) is replaced by Fig.17A and Fig. 17B In other words, this method starts with Figures 9 to 16 Continue to 18A to 18C , while skipping Fig.17A and Fig. 17B .

[0112] refer to 18A to 18C , provides Fig.17A and Fig. 17B A series of cross-sectional views 1800A-1800C of some alternative embodiments of the series of cross-sectional views 1700A and 1700B. Figures 18A-18C Corresponds to Figure 3B The cross-sectional view 300B shows Figure 3B However, the method shown in the cross-sectional views 1800A-1800C can also be used to form 1B, Figure 2A , Figure 2B , Fig. 6A and Figure 6BThe IC and / or GC structures 102 in any one of them.

[0113] like Fig.18A As shown in the cross-sectional view 1800A, a first IC region I and a second IC region II are formed. Figures 9 to 16 The actions described and shown form the first IC region I minus the first plug layer 1802. Similarly, according to Figures 9 to 16 The above actions form the second IC region II. However, in Figures 9 to 16 The second IC region II is not shown in the figure. The second IC region II includes a peripheral opening 1804 located in the second ILD layer 132b and the etch stop layer 134. In addition, in some embodiments, the peripheral opening 1804 extends into the first ILD layer 132a due to over-etching. The peripheral opening 1804 can be, for example, Fig.15 and Fig.16 The contact opening 1502 at the same time is formed together.

[0114] Also through Fig.18A The cross-sectional view 1800A shows that from the contact opening 1502 (eg, see Fig.16 ) and through hole opening 1402 (see, for example, Fig.16 ) is used to grow the first plug layer 1802. Because the second AR contact 106b and / or the first gate electrode 104a serve as the seed material, the first plug layer 1802 grows to fill the contact opening 1502 and the via opening 1402. However, the first plug layer 1802 does not grow to fill the peripheral opening 1804 because the peripheral opening 1804 has no seed material.

[0115] In some embodiments, the seed material from which the first plug layer 1802 grows is a metal, and / or the peripheral opening 1804 is free of metal. In some embodiments, the first gate electrode 104a and the second AR contact 106b have different seed materials, and / or the different seed materials result in different growth rates at the first gate electrode 104a and the second AR contact 106b, respectively. In some embodiments, due to the different growth rates, the first plug layer 1802 has different thicknesses above the first gate electrode 104a and the second AR contact 106b, respectively. The second AR contact 106b and / or the first gate electrode 104a can be or include, for example, tungsten and / or cobalt, and the first plug layer 1802 can be or include, for example, tungsten. However, other materials are also possible. In addition, the first plug layer 1802 can be or include, for example, cobalt, ruthenium, tungsten, some other suitable metal, or any combination of the foregoing.

[0116] The first plug layer 1802 can be grown, for example, by CVD, chemical plating, electroplating, or some other suitable growth process. In some embodiments, the first plug layer 1802 is or includes tungsten and / or is grown by CVD using tungsten fluoride (e.g., WF6) and hydrogen (e.g., H2) precursors. However, other materials, growth processes, and precursors are also suitable for the first plug layer 1802.

[0117] like Fig.18B As shown in the cross-sectional view 1800B of FIG. 1800A , a barrier layer 1806 is deposited to cover the first plug layer 1802 and the second ILD layer 132 b. In addition, the barrier layer 1806 is deposited to partially fill and line the peripheral opening 1804 (see, for example, Fig.18A ). The barrier layer 1806 may be or include, for example, titanium, titanium nitride, tantalum nitride, some other suitable barrier material, or any combination of the foregoing. The deposition of the barrier layer 1806 may be or include, for example, CVD, PVD, some other suitable deposition process, or any combination of the foregoing.

[0118] Also through Fig.18B 1800B shows that a second plug layer 1808 is deposited to cover the barrier layer 1806 and fill the remaining portion of the peripheral opening 1804. The barrier layer 1806 prevents material from diffusing through the barrier layer 1806 and / or diffusing through the barrier layer 1806 from the second plug layer 1808. In addition, in some embodiments, the barrier layer 1806 serves as an adhesion layer for the second plug layer 1808. The second plug layer 1808 can be or include, for example, cobalt, ruthenium, tungsten, some other suitable metal, or any combination of the foregoing. The deposition of the second plug layer 1808 can be, for example, or include CVD, PVD, chemical plating, electroplating, some other suitable deposition process, or any combination of the foregoing.

[0119] like Fig.18C As shown in the cross-sectional view 1800C of FIG. 1 , the first and second plug layers 1802, 1808, the barrier layer 1806, and the second ILD layer 132b are planarized until their top surfaces are substantially flush. The planarization may be, for example, or include CMP and / or some other suitable planarization process. The planarization is performed on the contact opening 1502 (e.g., see FIG. 1 ). Fig.16 ) and through hole opening 1402 (see, for example, Fig.16 ) to form the GC structure 102, and further to form the GC structure 102 in the peripheral opening 1804 (eg, see Fig.18A ) is formed in the peripheral structure 1810. The peripheral structure 1810 includes a peripheral plug 1812 and a peripheral stopper 1814 that cups the bottom side of the peripheral plug 1812. The peripheral structure 1810 may be, for example, a test line, a dummy structure, or some other suitable structure.

[0120] Although various embodiments of the reference method are described Figures 9 to 16 , Fig.17A , Fig. 17B and 18A to 18C , it will be understood that Figures 9 to 16 , Fig.17A , Fig. 17B and 18A to 18C The structure shown in is not limited to this method, but can be independently independent of this method. Figures 9 to 16 , Fig.17A , Fig. 17B and 18A to 18C Although described as a series of actions, it will be appreciated that in other embodiments, the order of the actions may be changed. Figures 9 to 16 , Fig.17A , Fig. 17B and 18A to 18C A particular set of actions is shown and described, but some of the actions shown and / or described may be omitted in other embodiments. In addition, actions not shown and / or described may be included in other embodiments.

[0121] For example, Figures 9 to 16 , Fig.17A and Fig. 17B The illustrated embodiment of the method may be modified to include the GC structure 102 (see, e.g., Fig. 17B ) and a second AR structure 106b (see, for example, Fig. 17B ) are formed as they are Figure 1C or Figure 1D In the case of Figure 1C In some embodiments of the method, Fig.11 and Fig.12 The second AR contact 106b is not formed in Fig.16 and Fig.17A A fifth etching is performed to form an AR opening. In addition, the method is based on Fig.17A and Fig. 17B The operation of performing the second AR contact 106b in the AR opening is performed. Figure 1D In some embodiments of the method, the Figure 1C Same process, except Fig.17A The barrier layer 1702 is omitted.

[0122] Reference Fig.19 , provides Figures 9 to 16 , Fig.17A , Fig. 17B and 18A to 18C Block diagram 1900 of some embodiments of the method.

[0123] At 1902, a semiconductor device covered by a first ILD layer is formed on a substrate, wherein the substrate at least partially defines an active region of the semiconductor device. Fig. 9 and Fig.10 .

[0124] At 1904, an active region (AR) contact is formed that extends through the first ILD layer to a source / drain region of the semiconductor device at a location adjacent to a gate electrode of the semiconductor device. See, e.g. Fig.11 and Fig.12 In alternative embodiments, the AR contact extends to a body contact region of the semiconductor device or to some other location at an active region of the semiconductor device.

[0125] At 1906, an etch stop layer is deposited over the first ILD layer. See, e.g. Fig.13 .

[0126] At 1908, a second ILD layer is deposited over the etch stop layer. See, e.g. Fig.13 .

[0127] At 1910, a first etch is performed on the first ILD layer and the second ILD layer to form a via opening extending to the gate electrode. Fig.14 .

[0128] At 1912, a second etch is performed on the second ILD layer to form a contact opening located above the AR contact and overlapping the via opening, wherein the second etch stops on the etch stop layer. See, e.g. Fig.15 .

[0129] At 1914, a third etch is performed on the etch stop layer to extend the contact opening to the AR contact and to slope the bottom of the contact opening downward from the AR contact to the via opening. Fig.16 .

[0130] At 1916, a plug layer is deposited in the contact openings and the via openings. See, e.g. Fig.17A or Fig.18A .

[0131] At 1918, the plug layer and the second ILD layer are planarized to form a GC structure that is located above the gate electrode and electrically couples the gate electrode to the AR contact. See, e.g. Fig. 17B or Fig.18C. The GC structure defines a gate contact and a gate via that separates the gate contact from the gate electrode. Because the bottom of the contact opening is tilted, the via opening has a low aspect ratio. This reduces the possibility of forming gaps and / or voids in the plug layer during deposition, or otherwise prevents the formation of gaps and / or voids in the plug layer during deposition. Such gaps and / or voids increase the resistance from the gate contact to the gate electrode, which increases power consumption and potentially causes operating parameters to shift out of specification. Therefore, tilting the bottom of the contact opening can improve yield and / or reduce power consumption.

[0132] At 1920, a back-end of line (BEOL) region is formed above the GC structure. Non-limiting examples of such BEOL regions can be found by reference to Figure 4A and Figure 4B The BEOL region 402 is found in FIG.

[0133] Although here Fig.19 The block diagram 1900 is shown and described as a series of actions or events, but it will be understood that the order in which such actions or events are shown should not be interpreted in a limiting sense. For example, some actions may occur in a different order and / or occur simultaneously with other actions or events other than those shown and / or described herein. In addition, all of the actions shown may not be required to implement one or more aspects or embodiments described herein, and one or more actions described herein may be performed in one or more separate actions and / or stages.

[0134] In some embodiments, the present invention provides an IC, comprising: a substrate; a source / drain region located above and inserted into the top of the substrate; a gate electrode adjacent to the source / drain region above the substrate; a first-level contact located above and electrically coupled to the source / drain region; a second-level contact located above the first-level contact and the gate electrode; and a gate via extending from the second-level contact to the gate electrode, wherein the bottom surface of the second-level contact slopes downward from the first-level contact to the gate via. In some embodiments, the IC further comprises a metal plug and a metal barrier, the metal plug and the metal barrier defining the second-level contact and the gate via, wherein the metal barrier cups the bottom side of the metal plug and separates the metal plug from the first-level contact. In some embodiments, the IC further comprises: a first ILD layer located above the substrate; a second ILD layer located above the first ILD layer; and an etch stop layer located between the first ILD layer and the second ILD layer at the lower dielectric interface and the upper dielectric interface and directly contacting the first ILD layer and the second ILD layer, respectively, wherein the first level contact and the second level contact are directly contacting at an inner contact interface recessed relative to the lower dielectric interface. In some embodiments, the IC further comprises a first plug defining a second level contact and a gate via and being substantially composed of a single material, wherein the first level contact comprises a second plug and a diffusion barrier wrapping a bottom of the second plug, and wherein the first plug is located above a top surface of the diffusion barrier and a top surface of the second plug and directly contacts a top surface of the diffusion barrier and a top surface of the second plug. In some embodiments, the bottom surface of the second level contact is inclined downward from the first level contact to the gate via in a first direction, wherein the second level contact is laterally elongated in the first direction, and wherein the first level contact is laterally elongated in a second direction perpendicular to the first direction. In some embodiments, a bottom surface of the second level contact is at an angle of about 30-70 degrees relative to a sidewall of the gate via. In some embodiments, a top surface of the second level contact is completely spaced apart from the via and line above the second level contact.

[0135] In some embodiments, the present invention provides another IC, comprising: a substrate; a device located on the substrate and including a gate electrode, wherein the substrate at least partially defines an AR of the device; an AR contact extending from the AR along a sidewall of the gate electrode to a top surface of the AR contact, the AR contact being elevated above the top surface of the gate electrode; and a GC structure located on the AR contact and the gate electrode, wherein the GC structure extends from the top surface of the gate electrode to the top surface of the AR contact, wherein the GC structure defines a gate via extending to the top surface of the gate electrode and spaced apart from the AR contact, and wherein the width of the GC structure increases continuously from the top of the gate via to the top surface of the AR contact. In some embodiments, the device includes a source / drain region adjacent to the gate electrode in the AR, wherein the AR contact extends from the source / drain region to the top surface of the AR contact. In some embodiments, the width of the GC structure increases from the top surface of the gate electrode to the top of the gate via at a first rate, wherein the width of the GC structure increases from the top of the gate via to the top surface of the AR contact at a second rate greater than the first rate. In some embodiments, the bottom surface of the GC structure is angled upward from the first sidewall of the gate via to the second sidewall of the AR contact. In some embodiments, the IC further comprises: an ILD layer located below the GC structure and directly contacting the bottom surface of the GC structure; and an etch stop layer located above the ILD layer and directly contacting the ILD layer, wherein the etch stop layer laterally contacts the GC structure and is spaced apart from the AR contact. In some embodiments, the top surface of the GC structure has a first material across a majority of the top surface, wherein the bottom surface of the GC structure directly contacts the AR contact at an interface, and wherein the bottom surface of the GC structure has the first material at an interface. In some embodiments, the GC structure comprises: a metal plug; and a metal liner layer located on the sidewalls of the metal plug and on the bottom surface of the metal plug, wherein the metal liner layer separates the metal plug from the AR contact and the gate electrode.

[0136] In some embodiments, the present invention provides a method for forming an IC, the method comprising: forming an AR contact extending through a first ILD layer to an AR of a semiconductor device; depositing an etch stop layer (ESL) and a second ILD layer, the etch stop layer (ESL) and the second ILD layer covering the first ILD layer and the AR contact, wherein the ESL is located between the first ILD layer and the second ILD layer; performing a first etching on the ESL and the first ILD layer and the second ILD layer to form a first opening exposing a gate electrode of the semiconductor device; performing a second etching on the second ILD layer, the second etching stopping on the ESL to form a second opening located above the AR contact and overlapping the first opening; performing a third etching on the ESL through the second opening to expose the AR contact, wherein the third etching causes the bottom of the second opening to tilt downward from the AR contact to the first opening; and forming a GC structure, the GC structure filling the first opening and the second opening and electrically connecting the gate electrode to the AR contact. In some embodiments, the method further comprises performing a cleaning process between the execution of the third etching and the formation of the GC structure, wherein the cleaning process causes the bottom of the second opening to tilt further downward from the AR contact to the first opening. In some embodiments, the performing of the third etch includes: forming a plasma from a mixture of hydrogen gas and tetrafluoromethane gas; and applying the plasma to the ESL. In some embodiments, the hydrogen gas has a first flow rate during the third etch, wherein the tetrafluoromethane gas has a second flow rate during the third etch, and wherein the first flow rate is about 10 times greater than the second flow rate. In some embodiments, the forming of the GC structure includes: depositing a barrier layer, the barrier layer lining the first opening and the second opening and partially filling the first opening and the second opening; depositing a plug layer over the barrier layer, the plug layer filling the remaining portion of the first opening and the second opening; and performing planarization on the barrier layer and the plug layer until the top surfaces of the barrier layer and the plug layer are substantially flush with the top surface of the second ILD layer. In some embodiments, the forming of the GC structure includes: selectively growing a filling plug layer from a seed material of a gate electrode and a seed material of an AR contact, the plug layer filling the first opening and the second opening, wherein the plug layer directly contacts the sidewalls of the second ILD layer in the first opening and the second opening; and performing planarization on the plug layer so that the top surface of the plug layer is flush with the top surface of the second ILD layer.

[0137] The present invention summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a substrate to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also be aware that this equivalent configuration is not directed away from the spirit and scope of the present invention, and in the case of not directed away from the spirit and scope of the present invention, they can make multiple changes, replacements and changes herein.

Claims

1. An integrated circuit (IC), comprising: substrate; a source / drain region located above and inserted into the top portion of the substrate; a gate electrode adjacent to the source / drain region above the substrate; a first level contact located above the source / drain region and electrically coupled to the source / drain region; a second level contact located above the first level contact and the gate electrode and passing through the etch stop layer; as well as A gate through hole extending from the second level contact to the gate electrode, wherein the bottom surface of the second level contact is inclined downward from the first level contact to the gate through hole The bottom surface further has a first portion, the first portion and the gate through hole are respectively located on two opposite sides of the first level contact, and the first portion is lower than the bottom surface of the etching stop layer. The top surface of the first-level contact element contacts the bottom surface of the second-level contact element and is raised compared to the first portion.

2. The integrated circuit according to claim 1 , further comprising a metal plug and a metal barrier, the metal plug and the metal barrier defining the second level contact and the gate via, and wherein, The metal stopper cups a bottom side of the metal plug and separates the metal plug from the first-level contact.

3. The integrated circuit of claim 1 , further comprising: a first interlayer dielectric (ILD) layer disposed above the substrate; a second interlayer dielectric layer, located above the first interlayer dielectric layer; as well as An etch stop layer is located between the first interlayer dielectric layer and the second interlayer dielectric layer at a lower dielectric interface and an upper dielectric interface and directly contacts the first interlayer dielectric layer and the second interlayer dielectric layer, respectively, wherein the first level contact and the second level contact are in direct contact at an inner contact interface recessed relative to the lower dielectric interface.

4. The integrated circuit of claim 1 , further comprising a first plug defining the second level contact and the gate via and consisting of a single material, wherein The first-level contact includes a second plug and a diffusion barrier wrapping a bottom of the second plug, and wherein the first plug is located above and directly contacts a top surface of the diffusion barrier and a top surface of the second plug.

5. The integrated circuit according to claim 1, wherein: A bottom surface of the second level contact slopes downward from the first level contact to the gate via in a first direction, wherein the second level contact is laterally elongated in the first direction, and wherein the first level contact is laterally elongated in a second direction perpendicular to the first direction.

6. The integrated circuit of claim 1, wherein: A bottom surface of the second-level contact forms an angle of 30-70 degrees with respect to a sidewall of the gate through hole.

7. The integrated circuit according to claim 1, wherein: A top surface of the second level contact is completely spaced apart from vias and lines above the second level contact.

8. An integrated circuit (IC), comprising: substrate; a device located on the substrate and comprising a gate electrode, wherein the substrate at least partially defines an active region (AR) of the device; an active area contact extending from the active area along a sidewall of the gate electrode to a top surface of the active area contact, the active area contact being elevated above the top surface of the gate electrode; and a gate-to-contact (GC) structure located above the active area contact and the gate electrode and extending through the etch stop layer, wherein the gate-to-contact structure extends from a top surface of the gate electrode to a top surface of the active area contact, wherein the gate-to-contact structure defines a gate via extending to the top surface of the gate electrode and spaced apart from the active area contact, and wherein a width of the gate-to-contact structure increases continuously from a top of the gate via to a top surface of the active area contact, The bottom surface of the gate-to-contact structure contacts the top surface of the active region contact, and the bottom surface further has a first portion, and the first portion and the gate through hole are located on opposite sides of the active region contact. The first portion is lower than a bottom surface of the etching stop layer, and a top surface of the active area contact contacts a bottom surface of the gate-to-contact structure and is raised compared to the first portion.

9. The integrated circuit of claim 8, wherein: The device includes a source / drain region adjacent to the gate electrode in the active area, and wherein the active area contact extends from the source / drain region to a top surface of the active area contact.

10. The integrated circuit of claim 8, wherein: The width of the gate-to-contact structure increases at a first rate from a top surface of the gate electrode to a top of the gate via, and wherein the width of the gate-to-contact structure increases at a second rate greater than the first rate from a top of the gate via to a top surface of the active area contact.

11. The integrated circuit of claim 8, wherein: A bottom surface of the gate-to-contact structure is angled upward from a first sidewall of the gate via to a second sidewall of the active area contact.

12. The integrated circuit of claim 8, further comprising: an interlayer dielectric (ILD) layer underlying the gate-to-contact structure and directly contacting a bottom surface of the gate-to-contact structure; as well as An etch stop layer is located above the interlayer dielectric layer and directly contacts the interlayer dielectric layer, wherein the etch stop layer laterally contacts the gate-to-contact structure and is spaced apart from the active area contact.

13. The integrated circuit of claim 8, wherein: The top surface of the gate-to-contact structure has a first material over a majority thereof, wherein a bottom surface of the gate-to-contact structure directly contacts the active area contact at an interface, and wherein the bottom surface of the gate-to-contact structure has the first material at the interface.

14. The integrated circuit of claim 8, wherein: The gate-to-contact structure comprises: Metal plugs; and A metal liner layer is located on the sidewalls of the metal plug and on the bottom surface of the metal plug, wherein the metal liner layer separates the metal plug from the active region contact and the gate electrode.

15. A method for forming an integrated circuit (IC), comprising: forming an active region (AR) contact extending through the first interlayer dielectric (ILD) layer to an active region of the semiconductor device; Depositing an etch stop layer (ESL) and a second interlayer dielectric layer, the etch stop layer and the second interlayer dielectric layer covering the first interlayer dielectric layer and the active area contact, wherein the etch stop layer is located between the first interlayer dielectric layer and the second interlayer dielectric layer; Performing a first etching on the etch stop layer and the first and second interlayer dielectric layers to form a first opening exposing a gate electrode of the semiconductor device; performing a second etch on the second interlayer dielectric layer, the second etch stopping on the etch stop layer to form a second opening located above the active area contact and overlapping the first opening; Performing a third etching on the etch stop layer through the second opening to expose the active area contact, wherein the third etching causes the bottom of the second opening to tilt downward from the active area contact to the first opening, and the third etching causes the bottom surface of the second opening to be recessed and lower than the bottom surface of the etch stop layer, and the top surface of the active area contact exposed by the third etching is higher than the bottom surface of the second opening; and A gate-to-contact (GC) structure is formed that fills the first opening and the second opening and electrically connects the gate electrode to the active region contact.

16. The method according to claim 15, further comprising: A cleaning process is performed between the performing of the third etch and the forming of the gate-to-contact structure, wherein the cleaning process causes the bottom of the second opening to slope further downward from the active area contact to the first opening.

17. The method according to claim 15, wherein: The performing of the third etching comprises: forming a plasma from a mixture of hydrogen gas and tetrafluoromethane gas; and The plasma is applied to the etch stop layer.

18. The method according to claim 17, wherein: The hydrogen gas has a first flow rate during the third etching, wherein the tetrafluoromethane gas has a second flow rate during the third etching, and wherein the first flow rate is 10 times greater than the second flow rate.

19. The method according to claim 15, wherein: The formation of the gate-to-contact structure includes: depositing a barrier layer lining the first opening and the second opening and partially filling the first opening and the second opening; depositing a plug layer over the barrier layer, the plug layer filling remaining portions of the first opening and the second opening; and The barrier layer and the plug layer are planarized until top surfaces of the barrier layer and the plug layer are flush with a top surface of the second interlayer dielectric layer, respectively.

20. The method according to claim 15, wherein: The formation of the gate-to-contact structure includes: selectively growing a filling plug layer from the seed material of the gate electrode and the seed material of the active area contact, the plug layer filling the first opening and the second opening, wherein the plug layer directly contacts the sidewalls of the second interlayer dielectric layer in the first opening and the second opening; and The plug layer is planarized so that a top surface of the plug layer is flush with a top surface of the second interlayer dielectric layer.

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