Semiconductor device and method for manufacturing the same

Abstract

The present disclosure relates to semiconductor devices and methods for manufacturing the same. A device includes a transistor, an insulating structure, a buried conductive line, and a buried via. The transistor is above a substrate and includes a source / drain region and a source / drain contact above the source / drain region. The insulating structure is above the substrate and laterally surrounds the transistor. The buried conductive line is in the insulating structure and is spaced apart from the transistor. The buried via is in the insulating structure and interconnects the transistor and the buried conductive line. The height of the buried conductive line is greater than the height of the source / drain contact.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In the formation of integrated circuits, standard cells are often used as basic elements for building integrated circuits. Standard cells are arranged and wired to form functional circuits. In certain layouts of standard cells, power rails are located on the boundaries of the cells. When multiple standard cells are arranged in rows, the power rails of the standard cells in the same row are connected to each other to form a long power rail that can extend through, for example, thousands or more standard cells. The power rails in adjacent rows are merged to form a power rail that is twice as wide as the power rail width in independent standard cells. For example, the VDD power rail of one row is merged with another VDD power rail of an adjacent row, and the VSS power rail of one row is merged with another VSS power rail of an adjacent row. Therefore, using a circuit including multiple rows, the VDD power rail and the VSS power rail are arranged in an alternating pattern. Summary of the invention

[0003] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a transistor located above a substrate, wherein the transistor comprises: a source / drain region; and a source / drain contact located above the source / drain region; an insulating structure located above the substrate and laterally surrounding the transistor; a buried conductive line located in the insulating structure and spaced apart from the transistor; and a buried via located in the insulating structure and interconnecting the transistor and the buried conductive line, wherein a height of the buried conductive line is greater than a height of the source / drain contact.

[0004] According to another embodiment of the present disclosure, a semiconductor device is provided, including: a transistor located above a substrate; an insulating structure located above the substrate and laterally surrounding the transistor; a first conductive line located above the insulating structure and the transistor; and a second conductive line located above the substrate and partially buried in the insulating structure, wherein the first conductive line and the second conductive line extend along a first direction, the top surfaces of the first conductive line and the second conductive line are coplanar, and the height of the second conductive line is greater than the height of the first conductive line.

[0005] According to another embodiment of the present disclosure, a method for manufacturing a device is provided, comprising: forming a transistor above a substrate; forming a first trench in the substrate; forming an insulating structure above the substrate, surrounding the transistor and partially in the first trench; forming a second trench in the insulating structure, wherein the second trench does not expose the transistor; and forming a first buried conductive line in the second trench and adjacent to the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity.

[0007] Figure 1 is a schematic diagram of a perspective view of a layout structure corresponding to a semiconductor device according to some embodiments of the present disclosure.

[0008] Figure 2-12C A method for manufacturing a semiconductor device at various stages according to some embodiments of the present disclosure is shown.

[0009] Fig.13A is a perspective view of a semiconductor device according to some embodiments of the present disclosure.

[0010] Fig. 13B is along Fig.13A A cross-sectional view taken along line BB in FIG.

[0011] Fig.14A is a perspective view of a semiconductor device according to some embodiments of the present disclosure.

[0012] Fig. 14B is along Fig.14A A cross-sectional view taken along line BB in FIG.

[0013] Fig.15A is a perspective view of a semiconductor device according to some embodiments of the present disclosure.

[0014] Fig. 15B is along Fig.15A A cross-sectional view taken along line BB in FIG.

[0015] Fig.16A is a perspective view of a semiconductor device according to some embodiments of the present disclosure.

[0016] Fig. 16B is along Fig.16A A cross-sectional view taken along line BB in FIG.

[0017] Figures 17A-20CA method for manufacturing a semiconductor device at various stages according to some embodiments of the present disclosure is shown.

[0018] Fig.21A is a perspective view of a semiconductor device according to some embodiments of the present disclosure.

[0019] Fig. 21B is along Fig.21A A cross-sectional view taken along line BB in FIG.

[0020] Fig.22A is a perspective view of a semiconductor device according to some embodiments of the present disclosure.

[0021] Fig. 22B is along Fig.22A A cross-sectional view taken along line BB in FIG.

[0022] Fig.23A is a perspective view of a semiconductor device according to some embodiments of the present disclosure.

[0023] Fig. 23B is along Fig.23A A cross-sectional view taken along line BB in FIG.

[0024] Fig.24A is a perspective view of a semiconductor device according to some embodiments of the present disclosure.

[0025] Fig. 24B is along Fig.24A A cross-sectional view taken along line BB in FIG.

[0026] Figures 25A-28C A method for manufacturing a semiconductor device at various stages according to some embodiments of the present disclosure is shown.

[0027] Fig.29 is a perspective view of a semiconductor device according to some embodiments of the present disclosure.

[0028] Fig.30 is a perspective view of a semiconductor device according to some embodiments of the present disclosure.

[0029] Fig.31 is a perspective view of a semiconductor device according to some embodiments of the present disclosure.

[0030] Fig.32 is a perspective view of a semiconductor device according to some embodiments of the present disclosure.

[0031] Fig.33 is a flow chart of a method for forming a semiconductor device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0032] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which an additional feature is formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0033] Additionally, for ease of description, spatially relative terms, such as "under," "beneath," "below," "above," "above," etc., may be used herein to describe the relationship of one element or feature to another element (or elements) or feature (or features) as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0034] As used herein, "close to", "about", "approximately" or "substantially" shall generally refer to within 20%, or 10%, or 5% of a given value or range. The numerical values ​​given herein are approximate, meaning that if not explicitly stated, the term "close to", "about", "approximately" or "substantially" can be inferred.

[0035] The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Typically, double patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing for the creation of patterns having, for example, a pitch that is smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.

[0036] The gate all around (GAA) transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Typically, the double patterning or multi-patterning process combines photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, spacings smaller than those obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0037] Some embodiments of the present disclosure relate to semiconductor devices with (one or more) buried conductive lines to reduce chip size. Although some embodiments are shown below for FinFET, it should be understood that the concept is not limited to FinFET, but is also applicable to other types of devices, such as MOSFET, HGAA devices, etc.

[0038] Figure 1 is a schematic diagram of a perspective view of a layout structure corresponding to the semiconductor device 100 according to some embodiments of the present disclosure. In addition to the semiconductor device 100, Figure 1 The X-axis, Y-axis, and Z-axis directions are also depicted. Figure 1 A simplified version of semiconductor device 100 is depicted to illustrate the general spatial relationship between various features; Figure 2-32 Let's discuss the specific spatial relationships of various embodiments.

[0039] like Figure 1 As shown, semiconductor device 100 includes two transistors 110 and 120 with independent source and drain. Transistors 110 and 120 are adjacent to each other. In some embodiments, transistors 110 and 120 are arranged on a substrate (not shown) below transistors 110 and 120. In some embodiments, transistors 110 and 120 are planar structures. In some other embodiments, transistors 110 and 120 are FinFETs. In some other embodiments, transistors 110 and 120 can be formed at a stack of two nanosheets or two or more nanosheets (not shown) separated from each other along a vertical direction (e.g., along the Z-axis direction). In some embodiments, transistor 110 is a p-type FET, and transistor 120 is an n-type FET, and vice versa, so FET device 100 is a CFET device. The substrate below transistors 110 and 120 is any substrate suitable for epitaxial growth and / or is formed by any suitable crystalline material including, for example, silicon, silicon germanium (SiGe), etc.

[0040] In some embodiments, the term "p-type FET" as described above refers to a FET that includes p-type dopants (e.g., boron) in, for example, the doped source and drain regions of a p-type FET, and the term "n-type FET" as described above refers to a FET that includes n-type dopants (e.g., phosphorus or arsenic) in, for example, the doped source and drain regions of an n-type FET.

[0041] The term "nanosheet" refers to a substantially two-dimensional material that is a single monolayer thick or a few monolayers thick, so that in some embodiments the thickness is about 1 nanometer (nm) to about 100 nm, and the lateral dimensions range from, for example, hundreds of nanometers to tens of microns. In some embodiments, the nanosheet or nanosheet stack defines a defined (MD) segment of a metalloid.

[0042] exist Figure 1 , the transistor 110 includes a first source / drain 112, a gate 130, and a second source / drain 114 arranged in a horizontal direction (e.g., in a Y-axis direction). The gate 130 is arranged between the first source / drain 112 and the second source / drain 114 of the transistor 110, and extends in a predetermined direction (e.g., in an X-axis direction). The gate 130 is configured to control a channel 116 between the first source / drain 112 and the second source / drain 114 of the transistor 110. In some embodiments, the channel 116 and the first source / drain 112 and the second source / drain 114 are implemented by an active region formed by a dopant.

[0043] The transistor 120 includes a first source / drain 122, a gate 130, and a second source / drain 124 arranged along a horizontal direction (e.g., along the Y-axis direction). In other words, the gate 130 is arranged as a common gate corresponding to the transistors 110 and 120, and the transistors 110 and 120 share the gate 130. Similarly, the gate 130 is arranged between the first source / drain 122 and the second source / drain 124 of the transistor 120. The gate 130 is configured to control a channel 126 between the first source / drain 122 and the second source / drain 124 of the transistor 120. In some embodiments, the channel 126 and the first source / drain 122 and the second source / drain 124 are realized by an active region formed by a dopant. Note that, Figure 1 The configuration of transistors 110 and 120 in FIG. 1 is illustrative and should not limit the present disclosure. In some other embodiments, transistors 110 and 120 each include a gate.

[0044] In some embodiments, the term "source / drain" refers to a region that can be a source region or a drain region. Figure 1, when the first source / drain 112 of the transistor 110 is a source region, the second source / drain 114 of the transistor 110 is a drain region, and vice versa. Accordingly, when the first source / drain 122 of the transistor 120 is a source region, the second source / drain 124 of the transistor 120 is a drain region, and vice versa.

[0045] The semiconductor device 100 further includes source / drain contacts 142, 144, and 146. The source / drain contact 142 is coupled to the first source / drain 112 of the transistor 110, the source / drain contact 144 is coupled to the second source / drain 114 and 124, and the source / drain contact 146 is coupled to the first source / drain 122 of the transistor 120. The second source / drain 114 of the transistor 110 is electrically connected to the second source / drain 124 of the transistor 120 by means of the source / drain contact 144.

[0046] The semiconductor device 100 further includes buried conductive lines 162, 164, 166, and 168, buried vias 172 and 174, and insulating structures 152 and 154 on opposite sides of the transistors 110 and 120, respectively. The insulating structures 152 and 154 may be shallow trench isolation (STI) structures, interlayer dielectrics (ILDs), dielectric materials, or other suitable materials. The buried conductive lines 162 and 164 are embedded in the insulating structure 152, and the buried conductive lines 166 and 168 are embedded in the insulating structure 154. The buried conductive line 162 is above the buried conductive line 164, and the buried conductive line 166 is above the buried conductive line 168. The buried conductive line 162 is coupled to the gate 130 through the buried via 172, and the buried conductive line 166 is coupled to the source / drain contact 144 through the buried via 174. In some embodiments, buried conductive lines 164 and 168 may be omitted or connected to Figure 1 Other elements not shown.

[0047] The semiconductor device 100 also includes conductive lines 181, 183, 185, 187, and 189, and vias 192, 194, and 196. The conductive lines 181, 183, 185, 187, and 189 are above the transistors 110 and 120 and the buried conductive lines 162, 164, 166, and 168. The conductive lines 181 and 189 may be power lines, and the conductive lines 183, 185, and 187 may be signal lines, such that the width of each of the conductive lines 181 and 189 is greater than the width of each of the conductive lines 183, 185, and 187. In some embodiments, the conductive line 183 is coupled to the source / drain contact 144 through the via 192, the conductive line 187 is coupled to the gate 130 through the via 194, and the conductive line 189 is coupled to the source / drain contact 146 through the via 196.

[0048] The structure of the semiconductor device 100 as described above is given for illustrative purposes. Various structures of the semiconductor device 100 are within the intended scope of the present disclosure. For example, in various embodiments, the structure of the semiconductor device 100 is extended to omit some conductive lines and / or buried conductive lines. The interconnection between the (buried) conductive lines and the transistors can be adjusted according to different layout designs.

[0049] Using the structure of the semiconductor device 100 as described above, as Figure 1 As shown, buried conductive lines 162, 164, 166 and / or 168 can be formed in insulating structures 152 and 154 adjacent to transistors 110 and 120. This reduces the chip area of ​​semiconductor device 100. In addition, due to Figure 1 The buried conductive lines 162 , 164 , 166 and / or 168 shown in FIG. 1A and 1B enable the standard cell of the semiconductor device 100 to be scaled down.

[0050] Figure 1 The structure in can be applied to various types of devices to save chip area. Figure 2-12C A method for manufacturing a semiconductor device at various stages according to some embodiments of the present disclosure is shown. In some embodiments, Figure 2-12C The semiconductor device shown in may be an intermediate device fabricated during a process of an integrated circuit (IC) or a portion thereof, which may include static random access memory (SRAM), logic circuits, passive components (e.g., resistors, capacitors, and inductors), and / or active components (e.g., p-type field effect transistors (PFETs), n-type FETs (NFETs), multi-gate FETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors), other storage units, and combinations thereof.

[0051] refer to Figure 2 A substrate 210 is provided. The substrate 210 includes at least one N-type region 210n and at least one P-type region 210p. At least one N-type device will be formed on the N-type region 210n, and at least one P-type device will be formed on the P-type region 210p. For ease of explanation, it is assumed that Figure 2-12CIn the embodiment, the substrate 210 includes two N-type regions 210n and two P-type regions 210p adjacent to the N-type regions 210n. In some embodiments, the substrate 210 may include silicon (Si). Alternatively, the substrate 210 may include germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), or other suitable semiconductor materials. In some embodiments, the substrate 210 may include a semiconductor on insulator (SOI) structure, such as a buried dielectric layer. Furthermore, alternatively, the substrate 210 may include a buried dielectric layer, such as a buried oxide (BOX) layer, a buried dielectric layer formed by a method called separation by oxygen implantation (SIMOX) technology, wafer bonding, SEG, or other suitable methods. In various embodiments, the substrate 210 may include any of a variety of substrate structures and materials.

[0052] refer to Figure 3 A plurality of semiconductor fins 212 and a plurality of semiconductor fins 214 are formed over the N-type region 210n and the P-type region 210p of the substrate 210, respectively. The semiconductor fins 212 and 214 may serve as channel and source / drain features of the transistor. Note that Figure 3 The number of semiconductor fins 212 and 214 in the embodiment is illustrative and should not limit the scope of the claimed invention. In addition, one or more dummy fins may be provided near both sides of the semiconductor fins 212 and / or semiconductor fins 214 to improve pattern fidelity in the patterning process.

[0053] The semiconductor fins 212 and 214 can be formed, for example, by patterning and etching the substrate 210 using photolithography techniques. In some embodiments, a layer of photoresist material (not shown) is deposited over the substrate 210. The photoresist material layer is irradiated (exposed) according to the desired pattern (in this case, the semiconductor fins 212 and 214), and is developed to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material from subsequent process operations, such as etching. It should be noted that other masks, such as oxide or silicon nitride masks, may also be used in the etching process. The semiconductor fins 212 and 214 may be made of the same material as the substrate 210 and may extend or protrude continuously from the substrate 210. The semiconductor fins 212 and 214 may be intrinsic or appropriately doped with n-type impurities or p-type impurities.

[0054] In some other embodiments, semiconductor fins 212 and 214 may be epitaxially grown. For example, exposed portions of underlying materials, such as exposed portions of substrate 210, may be used in an epitaxial process to form semiconductor fins 212 and 214. Masks may be used during the epitaxial growth process to control the shape of semiconductor fins 212 and 214.

[0055] A plurality of isolation structures 220, such as shallow trench isolation (STI), are formed in the substrate 210 to separate various devices. The formation of the isolation structures 220 may include etching trenches in the substrate 210 and filling the trenches with an insulator material such as silicon oxide, silicon nitride, or silicon oxynitride. The filled trenches may have a multi-layer structure such as a thermal oxide liner layer, wherein silicon nitride fills the trenches. In some embodiments, the isolation structure 220 can be created using the following process sequence: growing a pad oxide, forming a low pressure chemical vapor deposition (LPCVD) nitride layer, patterning the STI openings using photoresist and masking, etching trenches in the substrate 210 (to form semiconductor fins 212 and 214), optionally growing a thermal oxide trench liner to improve the trench interface, filling the trenches with oxide, using chemical mechanical planarization (CMP) to remove excess oxide, and recessing the thermal oxide trench liner and oxide to form the isolation structure 220 so that the tops of the semiconductor fins 212 and 214 protrude from the top surface of the isolation structure 220.

[0056] refer to Figure 4 The interface layer 230 is conformally formed to cover the semiconductor fins 212, 214 and the isolation structure 220. In some embodiments, the interface layer 230 may include silicon dioxide, silicon nitride, a high-κ dielectric material, or other suitable materials. In various examples, the interface layer 230 may be deposited by an ALD process, a CVD process, a sub-atmospheric CVD (SACVD) process, a flowable CVD process, a PVD process, or other suitable processes. For example, the interface layer 230 may be used to prevent damage to the semiconductor fins 212 and 214 by subsequent processes (e.g., subsequent formation of a dummy gate structure).

[0057] A gate structure 240 is formed over the interface layer 230, the semiconductor fins 212, 214, and the isolation structure 220. In some embodiments, a gate layer (not shown) may be formed over the interface layer 230 and then patterned to form the gate electrode 240. In some embodiments, the gate electrode 240 may be made of polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe), or other suitable materials. If a gate-first technology is used, the gate structure 240 and the interface layer 230 are used as a gate electrode and a gate dielectric layer. Subsequently, as Figure 4 As shown, portions of the interface layer 230 not covered by the gate structure 240 are removed to expose portions of the semiconductor fins 212 and 214 .

[0058] refer to Figure 5The spacer structure 250 is formed at least on the opposite sides of the gate structure 240 and the interface layer 230. The spacer structure 250 may include a sealing spacer and a main spacer (not shown). The spacer structure 250 includes one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, SiCN, SiC x O y N z Or a combination thereof. The sealing spacer is formed on the sidewall of the gate structure 240, and the main spacer is formed on the sealing spacer. The spacer structure 250 can be formed using a deposition method such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD), etc. The formation of the spacer structure 250 can include blanket forming a spacer layer and then performing an etching operation to remove a horizontal portion of the spacer layer. The remaining vertical portion of the spacer layer forms the spacer structure 250.

[0059] Subsequently, the semiconductor fins 212 and 214 are etched (see Figure 4 ) A plurality of recesses 216 are formed on opposite sides of the gate structure 240. The gate structure 240 and the gate spacers 250 are used as etching masks in the formation of the recesses 216. The etching process includes a dry etching process, a wet etching process, or a combination thereof.

[0060] Then, semiconductor material is deposited in the recess 216 to form epitaxial structures 262 and 264 referred to as source / drain regions. Epitaxial structures 262 are formed respectively above the N-type region 210n, and epitaxial structures 264 are formed respectively above the P-type region 210p. Epitaxial structures 262 and 264 may alternatively be referred to as raised source and drain regions. Semiconductor materials include single element semiconductor materials (e.g., germanium (Ge) or silicon (Si)), compound semiconductor materials (e.g., gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs)), or semiconductor alloys (e.g., silicon germanium (SiGe) or gallium arsenide phosphide (GaAsP)). Epitaxial structures 262 and 264 have a suitable crystallographic orientation (e.g., (100), (110) or (111) crystallographic orientation). In some embodiments, epitaxial structures 262 and 264 include source / drain epitaxial structures. In some embodiments, where an N-type device is desired, the epitaxial structure 262 may include epitaxially grown silicon phosphide (SiP) or silicon carbide (SiC). In some embodiments, where a P-type device is desired, the epitaxial structure 264 may include epitaxially grown silicon germanium (SiGe). The epitaxial process includes CVD deposition techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and / or other suitable processes. During the epitaxial process, the desired p-type or n-type impurities may or may not be doped. Doping may be achieved by an ion implantation process, a plasma immersion ion implantation (PIII) process, a gas and / or solid source diffusion process, other suitable processes, or a combination thereof.

[0061] refer to Figure 6 A plurality of trenches 218 are formed in the isolation structure 220 and the substrate 210. For example, the trenches 218 are formed between the gate structures 240 and are substantially parallel to the semiconductor fins 212 and 214. In some embodiments, Figure 5 A mask layer is formed over the structures in the gate structures 240, and the mask layer is patterned to expose portions of the isolation structures 220 between the gate structures 240. These portions of the isolation structures 220 are then removed to expose portions of the substrate 210, and the exposed portions of the substrate are recessed to form trenches 218 therein. In some embodiments, a bottom surface 219 of the trench 218 is lower than a bottom surface 265 of the epitaxial structures 262 and / or 264. In some other embodiments, the bottom surface 219 of the trench 218 is higher than or substantially flush with the bottom surface 265 of the epitaxial structures 262 and / or 264.

[0062] refer to Fig. 7A and 7B ,in Figure 7B It is along Fig. 7A The contact etch stop layer (CESL) 270 is conformally formed on the Figure 6 In some embodiments, the CESL 270 may be one or more stress layers. In some embodiments, the CESL 270 has tensile stress and is formed of Si3N4. In some other embodiments, the CESL 270 includes a material such as oxynitride. In still other embodiments, the CESL 270 may have a composite structure including a plurality of layers, such as a silicon nitride layer covering a silicon oxide layer. The CESL 270 may be formed using plasma enhanced CVD (PECVD), however, other suitable methods may also be used, such as low pressure CVD (LPCVD), atomic layer deposition (ALD), etc.

[0063] Then, a first interlayer dielectric (ILD) 275 is formed on the CESL 270. The first ILD 275 may be formed by chemical vapor deposition (CVD), high-density plasma CVD, spin coating, sputtering, or other suitable methods. In some embodiments, the first ILD 275 includes silicon oxide. In some other embodiments, the first ILD 275 may include silicon oxynitride, silicon nitride, or a low-k material. A portion of the first ILD 275 is formed in the trench 218 (see FIG. 2 ). Figure 6 ).

[0064] Subsequently and optionally, a replacement gate (RPG) process scheme is optionally adopted. In the RPG process scheme, a dummy polysilicon gate (in this case Figure 6 The gate structure 240 in the embodiment of the present invention is then replaced by a metal gate. In some embodiments, the gate structure 240 is removed to form an opening, and the spacer structure 250 serves as a sidewall of the opening. In some other embodiments, the interface layer 230 (see Figure 4 ) are also removed. The gate structure 240 (and the interface layer 230) may be removed by dry etching, wet etching, or a combination of dry etching and wet etching.

[0065] A gate dielectric layer 282 is formed in the opening, and at least one metal layer is formed in the opening and on the gate dielectric layer 282. Subsequently, a chemical mechanical planarization (CMP) process is performed to planarize the metal layer and the gate dielectric layer 282 to form a metal gate structure 280 in the opening. The metal gate structure 280 spans the semiconductor fins 212 and 214. The metal gate structure 280 includes a gate dielectric layer 282 and a metal gate electrode 284 above the gate dielectric layer 282. The metal gate electrode 284 may include a metal layer 285 (e.g., (one or more) work function metal layers and (one or more) capping layers), (one or more) fill layers 286, and / or other suitable layers desired in the metal gate stack. The work function metal layer 285 may include n-type and / or p-type work function metals. Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN other suitable p-type work function materials or combinations thereof. The work function metal layer 285 may have multiple layers. (One or more) work function metal layers 285 may be deposited by CVD, PVD, electroplating and / or other suitable processes. In some embodiments, the cap layer may include a refractory metal and its nitride (e.g., TiN, TaN, W2N, TiSiN and TaSiN). The cap layer may be deposited by PVD, CVD, metal organic chemical vapor deposition (MOCVD) ALD, etc. In some embodiments, the filling layer 286 may include tungsten (W). The filling layer 286 may be deposited by ALD, PVD, CVD or other suitable processes.

[0066] exist Fig. 7A and Figure 7B In the embodiment, a plurality of devices are formed on the substrate 210. For example, the epitaxial structure 262, the semiconductor fin 212 (see Figure 3 ) and the metal gate structure 280 form an N-type device (transistor) TN, and the epitaxial structure 264, the semiconductor fin 214 (see Figure 3 ) and metal gate structure 280 form a P-type device (transistor) TP.

[0067] refer to Fig. 8A and Figure 8B ,in Figure 8B It is along Fig. 8ABB in FIG. 2 is a cross-sectional view taken along line BB in FIG. The first ILD 275 is etched by various methods (including dry etching, wet etching, or a combination of dry etching and wet etching) to form a plurality of contact openings 276, a plurality of trenches 277a, 277b, 277c, and a plurality of interconnect openings 278. The contact openings 276 extend substantially vertically through the first ILD 275 to expose the epitaxial structures 262 and 264. The trenches 277a, 277b, 277c extend substantially vertically through the first ILD 275, but do not extend to the bottommost surface of the first ILD 275. The trenches 277a, 277b, 277c do not expose the metal gate structure 280 and the epitaxial structures 262 and 264. The interconnect openings 278 extend from the trenches 277a to the corresponding contact openings 276. In some embodiments, the tops of the epitaxial structures 262 and 264 may be removed during the formation of the contact openings 276 and / or the interconnect openings 278. Multiple patterning processes may be performed to form the contact opening 276, the trenches 277a, 277b, 277c, and the interconnection opening 278. For example, different mask layers are used to pattern the contact opening 276, the trenches 277a, 277b, 277c, and the interconnection opening 278, respectively.

[0068] refer to Fig. 9A and Fig. 9B ,in Fig. 9B It is along Fig. 9A The source / drain contacts 292, the bottom buried conductive lines 294, 295, 296 and the buried vias 298 are formed in the contact openings 276, the trenches 277a, 277b, 277c and the interconnect openings 278, respectively (see FIG. Figures 8A-8B ). Each of the source / drain contacts 292, the bottom buried conductive lines 294, 295, 296, and the buried vias 298 includes an optional barrier layer 292a, 294a, 295a, 296a, and 298a and a filling material 292b, 294b, 295b, 296b, and 298b.

[0069] In some embodiments, barrier layers 292a, 294a, 295a, 296a, and 298a are formed in contact opening 276, trenches 277a, 277b, 277c, and interconnect opening 278, respectively (see Fig. 8A and Figure 8B). Barrier layers 292a, 294a, 295a, 296a, and 298a can improve the adhesion between the epitaxial structure 262 / 264 and the material formed thereon (e.g., a filling material). Barrier layers 292a, 294a, 295a, 296a, and 298a may include metal nitride materials. For example, barrier layers 292a, 294a, 295a, 296a, and 298a include Ti, TiN, or a combination thereof. In some embodiments, barrier layers 292a, 294a, 295a, 296a, and 298a include a single layer or multiple layers. For a multilayer structure, each layer includes a different metal nitride composition from each other. For example, barrier layers 292a, 294a, 295a, 296a, and 298a have a first metal nitride layer including Ti and a second metal nitride layer including TiN.

[0070] Filling materials 292b, 294b, 295b, 296b, and 298b are formed in contact openings 276, trenches 277a, 277b, 277c, and interconnect openings 278, and over barrier layers 292a, 294a, 295a, 295a, 296a, and 298a. Filling material 292b is electrically connected to epitaxial structures 262 and 264. In some embodiments, a metal material may be filled in the openings, and excess portions of the metal material and barrier layers may be removed by performing a planarization (e.g., CMP) process to form filling materials 292b, 294b, 295b, 296b, and 298b and barrier layers 292a, 294a, 295a, 296a, and 298a. Filling materials 292b, 294b, 295b, 296b, and 298b may be made of tungsten, aluminum, copper, or other suitable materials.

[0071] exist Fig. 9A and Fig. 9B In the embodiment of the present invention, an N-type device (transistor) TN and a P-type device (transistor) TP are formed above the N-type region 210n and the P-type region 210p of the substrate 210. The source / drain contact 292 is above the epitaxial structures 262 and 264 to interconnect the epitaxial structures 262 and 264. The bottom buried conductive line 294 is between the N-type device TN, and the N-type device TN and the P-type device TP are between the buried conductive lines 294 and 295 (or 296). The buried via 298 interconnects the bottom buried conductive line 294 and the two source / drain contacts 292, so that the bottom buried conductive line 294 is electrically connected to some of the epitaxial structures 262 and 264 of the N-type device TN and the P-type device TP. The first ILD 275 and the isolation structure 220 are referred to as an insulating structure. The bottom buried conductive lines 294 , 295 , and 296 and the buried via 298 are embedded in the insulating structure (ie, the first ILD 275 and the isolation structure 220 ).

[0072] exist Fig. 9B In the planarization process, due to the above-mentioned planarization process, the top surfaces of the source / drain contacts 292, the bottom buried conductive lines 294, 295, 296, the buried vias 298, and the first ILD 275 are substantially coplanar. In some embodiments, the bottom surface 294c of the bottom buried conductive line 294 is lower than the top surface 222 of the isolation structure 220. In addition, in some embodiments, the bottom surfaces 295c and 296c of the bottom buried conductive lines 295 and 296 are lower than the top surface 222 of the isolation structure 220. The height H1 of each of the bottom buried conductive lines 294, 295, and 296 is greater than the height H2 of each of the source / drain contacts 292 (the metal gate structure 280 may also have a height H2). The bottom surface 298c of each of the buried vias 298 and the top surface 262d of the epitaxial structure 262 (and / or the top surface of the epitaxial structure 264) may be substantially coplanar. In the planarization process, due to the above-mentioned planarization process, the top surfaces of the source / drain contacts 292, the bottom buried conductive lines 294, 295, 296, the buried vias 298 and the first ILD 275 may be substantially coplanar. In the planarization process, due to the above-mentioned planarization process, the top surfaces of the source / drain contacts 292, the bottom buried conductive lines 294, 295, 296, the buried vias 298 and the top surface 262d of the epitaxial structure 262 (and / or the top surface of the epitaxial structure 264) may be substantially coplanar. Fig. 9B In the embodiment, the barrier layers 292a, 294a and 298a are connected to each other, and the filling materials 292b, 294b and 298b are connected to each other, so that Fig. 9B The source / drain contacts 292 , bottom buried conductive lines 294 , and buried vias 298 are shown electrically connected to one another.

[0073] Note that the source / drain contacts 292, the bottom buried conductive lines 294, 295, 296, and the buried vias 298 may be formed in different processes. For example, the source / drain contacts 292 may be formed before forming the bottom buried conductive lines 294, 295, 296. Alternatively, the buried vias 298 may be formed after forming the source / drain contacts 292 and the bottom buried conductive lines 294, 295, 296.

[0074] refer to Fig. 10A and Fig. 10B ,in Fig. 10B It is along Fig. 10A The cross-sectional view is taken along the line BB in FIG. Fig. 9A A second interlayer dielectric (ILD) 310 is formed on the structure of the substrate. The second ILD 310 may be formed by chemical vapor deposition (CVD), high-density plasma CVD, spin coating, sputtering, or other suitable methods. In some embodiments, the second ILD 310 includes silicon oxide. In some other embodiments, the second ILD 310 may include silicon oxynitride, silicon nitride, or a low-k material.

[0075] Subsequently, the second ILD 310 is etched by various methods (including dry etching, wet etching, or a combination of dry etching and wet etching) to form a plurality of gate openings 314, a plurality of contact openings 316, a plurality of trenches 317a, 317b, 317c, and a plurality of interconnect openings 318, 312. The gate openings 314 extend substantially vertically through the second ILD 310 to expose the metal gate structures 280, respectively. The contact openings 316 extend substantially vertically through the second ILD 310 to expose the source / drain contacts 292, respectively. The trenches 317a, 317b, 317c extend substantially vertically through the second ILD 310, but do not extend to the bottommost surface 311 of the second ILD 310. The trenches 317a, 317b, 317c may be located directly above the bottom buried conductive lines 294, 295, and 296. The interconnect opening 318 extends from the trench 317b to the corresponding contact opening 316, and the interconnect opening 312 is below the trench 317b and exposes the buried conductive line 295. Multiple patterning processes may be performed to form the gate opening 314, the contact opening 316, the trenches 317a, 317b, 317c, and the interconnect openings 312, 318. For example, the gate opening 314, the contact opening 316, the trenches 317a, 317b, 317c, and the interconnect openings 312, 318 are patterned respectively using different mask layers.

[0076] refer to Fig.11A and Fig. 11B ,in Fig. 11B It is along Fig.11A The gate via 321, the source / drain contact 322, the top buried conductive lines 324, 325, 326 and the buried vias 328 and 329 are formed in the gate opening 314, the contact opening 316, the trenches 317a, 317b, 317c and the interconnection openings 312, 318 (see FIG. Figures 10A-10B Each of the gate via 321, the source / drain contacts 322, the top buried conductive lines 324, 325, 326, and the buried vias 328 and 329 includes an optional barrier layer 321a, 322a, 324a, 325a, 326a, 328a, and 329a and a filling material 321b, 322b, 324b, 325b, 326b, 328b, and 329b.

[0077] In some embodiments, barrier layers 321a, 322a, 324a, 325a, 326a, 328a, and 329a are formed in gate opening 314, contact opening 316, trenches 317a, 317b, 317c, and interconnect openings 312, 318, respectively (see Fig. 10A and Fig. 10B). Barrier layers 321a, 322a, 324a, 325a, 326a, 328a, and 329a may include metal nitride materials. For example, barrier layers 321a, 322a, 324a, 325a, 326a, 328a, and 329a include Ti, TiN, or a combination thereof. In some embodiments, barrier layers 321a, 322a, 324a, 325a, 326a, 328a, and 329a include a single layer or multiple layers. For a multilayer configuration, each layer includes a different metal nitride composition from each other. For example, barrier layers 321a, 322a, 324a, 325a, 326a, 328a, and 329a have a first metal nitride layer including Ti and a second metal nitride layer including TiN.

[0078] Filling materials 321b, 322b, 324b, 325b, 326b, 328b, and 329b are formed in contact openings 276, trenches 277a, 277b, 277c, and interconnect openings 278, and over barrier layers 321a, 322a, 324a, 325a, 326a, 328a, and 329a. Filling material 321b is electrically connected to metal gate structure 280, and filling material 322b is electrically connected to source / drain contacts 292. In some embodiments, a metal material may be filled in the openings, and excess portions of the metal material and the barrier layer may be removed by performing a planarization (e.g., CMP) process to form filling materials 321b, 322b, 324b, 325b, 326b, 328b, and 329b and barrier layers 321a, 322a, 324a, 325a, 326, 328a, and 329a. The filling materials 321b, 322b, 324b, 325b, 326b, 328b, and 329b may be made of tungsten, aluminum, copper, or other suitable materials.

[0079] exist Fig. 11B In FIG. 1 , due to the above-mentioned planarization process, the top surfaces of the gate via 321, the source / drain contacts 322, the top buried conductive lines 324, 325, 326, and the buried via 328 are substantially coplanar. The height H3 of each of the top buried conductive lines 324, 325, and 326 is less than the height H4 of each of the source / drain contacts 322. Fig. 11B In the embodiment, the barrier layers 322a, 325a, 328a and 329a are connected to each other, and the filling materials 322b, 325b, 328b and 329a are connected to each other, so that Fig. 11B One of the source / drain contacts 322 , the top buried conductive line 325 , the buried vias 328 , 329 , one of the source / drain contacts 292 , and the bottom buried conductive line 295 are shown electrically connected to one another.

[0080] refer to Figures 12A-12C ,in Fig. 12B It is along Fig. 12A The cross-sectional view taken along line BB in FIG. Fig. 12C It is along Fig. 12A Then, in Fig.11A The third ILD 330 is formed on the structure of the substrate. The third ILD 330 may be formed by chemical vapor deposition (CVD), high-density plasma CVD, spin coating, sputtering, or other suitable methods. In some embodiments, the third ILD 330 includes silicon oxide. In some other embodiments, the third ILD 330 may include silicon oxynitride, silicon nitride, or a low-k material.

[0081] A plurality of conductive lines 341, 343, 345, 347, and 349 are formed over the third ILD 330. In some embodiments, the formation of the conductive lines 341, 343, 345, 347, and 349 includes a damascene process, and may be electrically connected to the N-type device TN and / or the P-type device TP by forming vias in the third ILD 330. For example, the conductive line 345 is coupled to the gate structure 280 through the via 352 and the gate via 321, and / or the conductive line 347 is coupled to the epitaxial structures 262 and 264 through the via 354 and the source / drain contacts 322 and 292. Note that the formation and / or construction of the conductive lines 341, 343, 345, 347, and 349 are examples and should not limit the present disclosure. In some embodiments, each of the conductive lines 341, 343, 345, 347, and 349 includes a barrier layer and a filling material over the barrier layer. In some embodiments, conductive lines 341 and 349 may be power lines, and conductive lines 343, 345, and 347 may be signal lines. In some embodiments, the width W1 of conductive line 349 is greater than the width W2 of conductive line 347 (or 345 or 343). Conductive line 341 may be connected to Figures 12A-12C The structure shown in FIG. 3 is shared by adjacent cells, so that conductive line 341 may have a width substantially the same as width W1 of conductive line 349 .

[0082] exist Figures 12A-12CIn the embodiment, since the semiconductor device includes top and / or bottom buried conductive lines 324, 325, 326, 294, 295, and / or 296, internal electrical connection between the N-type device TN and the P-type device TP can be achieved by using the top and / or bottom buried conductive lines 324, 325, 326, 294, 295, and / or 296. The top and / or bottom buried conductive lines 324, 325, 326, 294, 295, and / or 296 are directly below the conductive lines 341 and 349 (e.g., power lines), so that the top and / or bottom buried conductive lines 324, 325, 326, 294, 295, and / or 296 do not occupy the layout area of ​​the semiconductor device. With this configuration, the number of conductive lines (e.g., conductive lines 341, 343, 345, 347, and 349) above the third ILD 330 can be reduced, and the cell height H5 of the semiconductor device can be reduced. In addition, the buried conductive lines 294, 295, and / or 296 have the benefit of relieving the pressure or tension of the first ILD 275 (and the isolation structure 220).

[0083] Fig.13A is a perspective view of a semiconductor device according to some embodiments of the present disclosure, and Fig. 13B It is along Fig.13A A cross-sectional view taken along line BB in FIG. Figures 13A-13B and Figures 12A-12C The difference between the semiconductor devices in FIG. 3 relates to the configuration of conductive lines 341 and 349. Fig.13A and Fig. 13B In the embodiment, the top buried conductive lines 324, 325 and 326 are omitted (see Fig. 12B ), and the conductive lines 341 and 349 extend into the second ILD 310. That is, the height H6 of each of the conductive lines 341 and 349 is greater than the height H7 of each of the conductive lines 343, 345, and 347. Top surfaces 341d, 343d, 345d, 347d, and 349d of the conductive lines 341, 343, 345, 347, and 349 are substantially coplanar, bottom surfaces 341c and 349c of the conductive lines 341 and 349 are substantially coplanar, and the bottom surfaces 341c and 349c of the conductive lines 341 and 349 are lower than the bottom surface 343c of the conductive line 343 (and the bottom surfaces of the conductive lines 345 and 347). The buried conductive line 294 is directly below the conductive line 349, and the buried conductive lines 295 and 296 are directly below the conductive line 341, respectively, so that the buried conductive lines 294, 295, and 296 do not occupy the layout area of ​​the semiconductor device. In some embodiments, a buried via (e.g., Fig. 12B The buried via 328 in the embodiment of the present invention is used to interconnect the conductive line 341 (or 349) and the source / drain contact 322 (or Fig. 12CIn some embodiments, another buried via (eg, gate via 321 in the second ILD 310) may be formed in the second ILD 310. Fig. 12B The buried via 329 in the middle is used to interconnect the conductive line 341 (or 349) and the bottom buried conductive line 295 (or 294 or 296). Fig.13A and Fig. 13B In the embodiment, since the conductive lines 341 and 349 extend into the second ILD 310, the conductivity thereof can be increased, and the width W1′ of the conductive lines 341 and 349 can be reduced. In some embodiments, the width W1′ of the conductive lines 341 and 349 is not greater than the width W2 of the conductive lines 343, 345, and / or 347. With this structure, the cell height H5′ of the semiconductor device can be further reduced. Fig.13A and 13B Other relevant structural details of the semiconductor device in Figures 12A-12C The semiconductor devices in the embodiment are basically the same or similar, so the description in this regard will not be repeated below.

[0084] Fig.14A is a perspective view of a semiconductor device according to some embodiments of the present disclosure, and Fig. 14B It is along Fig.14A A cross-sectional view taken along line BB in FIG. Figures 14A-14B and Figures 12A-12C The difference between the semiconductor devices in FIG. 3 relates to the presence of the second ILD 310, the top buried conductive lines 324, 325 and 326, and the source / drain contacts 322. Fig.14A and Fig. 14B , the second ILD 310, the top buried conductive lines 324, 325 and 326, and the source / drain contacts 322 are omitted (see Fig. 12B ), and the third ILD 330 is in direct contact with the first ILD 275. That is, there is only one level of buried conductive lines. Fig.14A and Fig. 14B Other relevant structural details of the semiconductor device in Figures 12A-12C The semiconductor devices in the embodiment are basically the same or similar, so the description in this regard will not be repeated below.

[0085] Note that the above-mentioned layer for burying the conductive line (eg, Figures 12A-12C The two layers in Figures 14A-14B In some other embodiments, the semiconductor device may include more than two layers of buried conductive lines.

[0086] Fig.15A is a perspective view of a semiconductor device according to some embodiments of the present disclosure, and Fig. 15B It is along Fig.15AA cross-sectional view taken along line BB in FIG. Figures 15A-15B and Figures 14A-14B The difference between the semiconductor devices in FIG. 3 relates to the configuration of conductive lines 341 and 349. Fig.15A In the same embodiment as in FIG15B, the bottom buried conductive lines 294, 295 and 296 are omitted (see Fig. 14B ), and the conductive lines 341 and 349 extend into the first ILD 275. That is, the height H6' of each of the conductive lines 341 and 349 is greater than the height H7' of each of the conductive lines 343, 345, and 347. The top surfaces of the conductive lines 341, 343, 345, 347, and 349 are substantially coplanar, and the bottom surfaces 341c and 349c of the conductive lines 341 and 349 are lower than the bottom surface 343c of the conductive line 343 (and the bottom surfaces of the conductive lines 345 and 347). In some embodiments, a buried via (e.g., Fig. 12B The buried via 298 in the embodiment of the present invention is used to interconnect the conductive line 341 (or 349) and the source / drain contact 292 (or Fig. 7A The metal gate structure 280 in FIG. Fig.15A and Fig. 15B In the embodiment, since the conductive lines 341 and 349 extend into the first ILD 275, the conductivity thereof can be increased, and the width W1' of the conductive lines 341 and 349 can be reduced. With this configuration, the cell height H5' of the semiconductor device can be reduced. Fig.15A and Fig. 15B Other relevant structural details of the semiconductor device in Fig.14A and Fig. 14B The semiconductor devices in the embodiment are basically the same or similar, so the description in this regard will not be repeated below.

[0087] Fig.16A is a perspective view of a semiconductor device according to some embodiments of the present disclosure, and Fig. 16B It is along Fig.16A A cross-sectional view taken along line BB in FIG. Figures 16A-16B and Figures 12A-12C The difference between the semiconductor devices in FIG. 1 relates to the depth of the bottom buried conductive lines 294, 295, and 296. Fig.16A and Fig. 16B In, omitted Figure 6 The etching process shown in FIG. 2 forms bottom buried conductive lines 294 , 295 , and 296 over the isolation structure 220 . Fig.16A and Fig. 16B Other relevant structural details of the semiconductor device in Figures 12A-12C The semiconductor devices in the embodiment are basically the same or similar, so the description in this regard will not be repeated below.

[0088] Figures 17A-20C A method for manufacturing a semiconductor device at various stages according to some embodiments of the present disclosure is shown. In some embodiments, Figures 17A-20C The semiconductor device shown in the figure may be an intermediate device manufactured during the process of an integrated circuit (IC) or a part thereof, which may include static random access memory (SRAM), logic circuits, passive components (such as resistors, capacitors and inductors), and / or active components (for example, p-type field effect transistors (PFETs), n-type FETs (NFETs), multi-gate FETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors), other storage units and combinations thereof.

[0089] refer to Figures 17A-17C ,in Fig. 17B It is along Fig.17A A cross-sectional view taken along line BB in FIG. Fig. 17C It is along Fig.17A At least one N-type device TN and at least one P-type device TP are formed on the substrate 410. Figures 17A-17C In the embodiment, the N-type device TN and the P-type device TP are planar FETs. Specifically, the substrate 410 includes at least one N-type region 410n and at least one P-type region 410p. The N-type device TN is formed on the N-type region 410n, and the P-type device TP is formed on the P-type region 410p. For ease of explanation, it is assumed that Figures 17A-20C In the embodiment, the substrate 410 includes two N-type regions 410n and two P-type regions 410p.

[0090] In some embodiments, the substrate 410 and Figure 2 The substrate 210 in the embodiment may have the same or similar materials, and therefore, the description of this aspect will not be repeated below. In some embodiments, an isolation structure 420 is formed in the substrate 410 to separate various devices. The isolation structure 420 and Figure 3 The isolation structure 220 in the embodiment may have the same or similar material, and therefore, the description in this regard will not be repeated below.

[0091] Each of the N-type device TN and the P-type device TP includes active regions 412 and 414 as channels of the N-type device TN and the P-type device TP. The isolation structure 420 defines the active regions 412 and 414 in the substrate 410. For example, the isolation structure 420 surrounds the active regions 412 and 414, and the active regions 412 and 414 are separated from each other by the isolation structure 420. The active region 412 is formed in the N-type region 410p, and the active region 414 is formed in the P-type region 410n. Note that Figures 17A-17CThe arrangement of active regions 412 and 414 in FIG. 4 is illustrative and should not limit the scope of the present disclosure.

[0092] The gate structure 480 is formed over the substrate 410 and the active regions 412 and 414. The spacer structure 450 is disposed on the opposite side of the gate structure 480. In some embodiments, the spacer structure 450 and Figure 5 The spacer structure 250 in the embodiment may have the same or similar materials, and therefore, the description in this regard will not be repeated below. The gate structure 480 includes a high-k gate dielectric layer 482, one or more work function metal layers 485, and a filling layer 486. The work function metal layer 485 and the filling layer 486 are referred to as a gate electrode 484. In some embodiments, the high-k gate dielectric layer 482 includes a material such as hafnium oxide (HfO2), zirconium oxide (ZrO2), or lanthanum oxide (La2O3). In some embodiments, the high-k gate dielectric layer 482 can be formed by performing an ALD process or other suitable process.

[0093] The work function metal layer 485 is conformally formed on the high-k gate dielectric layer 482. The work function metal layer 485 may include materials such as TiN, TaN, TiAlSi, TiSiN, TiAl, TaAl, or other suitable materials. In some embodiments, the work function metal layer 485 may be formed by performing an ALD process or other suitable process. A fill layer 486 is formed over the work function metal layer 485. The fill layer 486 may include materials such as tungsten or aluminum.

[0094] The epitaxial structures 462 and 464 are formed on opposite sidewalls of the gate structure 480 by performing, for example, a selective growth process, and are respectively formed over the N-type region 410n and the P-type region 410p. In some embodiments, the epitaxial structures 462 and 464 are Figure 5 The epitaxial structures 262 and 264 in the embodiment may have the same or similar materials, and therefore, the description in this regard will not be repeated below.

[0095] In some embodiments, a trench 418 is formed in the isolation structure 420 and the substrate 410, and a contact etch stop layer (CESL) 470 and a first interlayer dielectric (ILD) 475 are sequentially formed on the isolation structure 420, the epitaxial structures 462 and 464, and surround the gate structure 480. In some embodiments, the first ILD 475 and Figure 7A-7B The first ILD 275 in the embodiment may have the same or similar materials, and the CESL 470 and Figure 7A-7B The CESL 270 in the embodiment may have the same or similar materials, and therefore, the description in this regard will not be repeated below.

[0096] refer to Fig.18A and Fig.18B ,in Fig.18B It is along Fig.18A The first ILD 475 is etched to form a plurality of contact openings 476, a plurality of trenches 477a, 477b, 477c and a plurality of interconnection openings 478, and source / drain contacts 492, bottom buried conductive lines 494, 495, 496, and buried vias 498 are formed in the contact openings 476, the trenches 477a, 477b, 477c and the interconnection openings 478, respectively. The aforementioned process may be performed with Figures 8A-9B The processes shown are the same or similar, and therefore, the description in this regard will not be repeated below.

[0097] refer to Fig.19A and Fig.19B ,in Fig.19B It is along Fig.19A The cross-sectional view is taken along the line BB in FIG. Fig.18A A second interlayer dielectric (ILD) 510 is formed on the structure. Subsequently, the second ILD 510 is etched to form a plurality of gate openings 514, a plurality of contact openings 516, a plurality of trenches 517a, 517b, 517c, and a plurality of interconnect openings 518, 512. Gate vias 521, source / drain contacts 522, top buried conductive lines 524, 525, 526, and buried vias 528 and 529 are formed in the gate openings 514, the contact openings 516, the trenches 517a, 517b, 517c, and the interconnect openings 512, 518, respectively. The aforementioned process may be performed with Figures 10A-11B The processes shown are the same or similar, and therefore, the description in this regard will not be repeated below.

[0098] refer to Figures 20A-20C ,in Fig. 20B It is along Fig. 20A A cross-sectional view taken along line BB in FIG. Fig. 20C It is along Fig. 20A Then in Fig.19A A third ILD 530 is formed on the structure. A plurality of conductive lines 541, 543, 545, 547, and 549 are formed over the third ILD 530. In some embodiments, the conductive line 545 is coupled to the gate structure 480 through the via 552 and the gate via 521, and / or the conductive line 547 is coupled to the epitaxial structures 462 and 464 through the via 554 and the source / drain contacts 522 and 492. The aforementioned process may be performed with Figures 12A-12B The processes shown are the same or similar, and therefore, the description in this regard will not be repeated below.

[0099] Fig.21Ais a perspective view of a semiconductor device according to some embodiments of the present disclosure, and Fig. 21B It is along Fig.21A A cross-sectional view taken along line BB in FIG. Figures 21A-21B and Figures 20A-20C The difference between the semiconductor devices in FIG. 5 relates to the configuration of conductive lines 541 and 549. Fig.21A and Fig. 21B In the embodiment, the top buried conductive lines 524, 525 and 526 are omitted (see Fig. 20B ), and the conductive lines 541 and 549 extend into the second ILD 510. Fig.21A and Fig. 21B In the embodiment, since the conductive lines 541 and 549 extend into the second ILD 510, the conductivity thereof can be increased, and the width W1' of the conductive lines 541 and 549 can be reduced. With this configuration, the cell height H5' of the semiconductor device can be reduced. Fig.21A and Fig. 21B Other relevant structural details of the semiconductor device in Fig. 20A and Fig. 20B The semiconductor devices in the embodiment are basically the same or similar, so the description in this regard will not be repeated below.

[0100] Fig.22A is a perspective view of a semiconductor device according to some embodiments of the present disclosure, and Fig. 22B It is along Fig.22A A cross-sectional view taken along line BB in FIG. Figures 22A-22B and Figures 20A-20C The difference between the semiconductor devices in FIG. 5 relates to the presence of the second ILD 510, the top buried conductive lines 524, 525 and 526, and the source / drain contacts 522. Fig.22A and Fig. 22B , the second ILD 510, the top buried conductive lines 524, 525 and 526, and the source / drain contacts 522 are omitted (see Fig. 20B ), and the third ILD 530 is in direct contact with the first ILD 475. That is, there is only one layer of buried conductive lines. Fig.22A and Fig. 22B Other relevant structural details of the semiconductor device in Figures 20A-20C The semiconductor devices in the embodiment are basically the same or similar, so the description in this regard will not be repeated below.

[0101] Fig.23A is a perspective view of a semiconductor device according to some embodiments of the present disclosure, and Fig. 23B It is along Fig.23A A cross-sectional view taken along line BB in FIG. Figures 23A-23B and Figures 22A-22BThe difference between the semiconductor devices in FIG. 5 relates to the configuration of conductive lines 541 and 549. Fig.23A and Fig. 23B In the embodiment, the bottom buried conductive lines 494, 495 and 496 are omitted (see Fig. 22B ), and the conductive lines 541 and 549 extend into the first ILD 475. Fig.23A and Fig. 23B In the embodiment, since the conductive lines 541 and 549 extend into the first ILD 475, the conductivity thereof can be increased, and the width W1' of the conductive lines 541 and 549 can be reduced. With this configuration, the cell height H5' of the semiconductor device can be reduced. Fig.23A and Fig. 23B Other relevant structural details of the semiconductor device in Fig.22A and Fig. 22B The semiconductor devices in the embodiment of the present invention are substantially the same or similar. Therefore, the description in this regard will not be repeated below.

[0102] Fig.24A is a perspective view of a semiconductor device according to some embodiments of the present disclosure, and Fig. 24B is along Fig.24A A cross-sectional view taken along line BB in FIG. Figures 24A-24B and Figures 20A-20C The difference between the semiconductor devices in FIG. 4 relates to the depth of the bottom buried conductive lines 494, 495, and 496. Fig.24A and Fig. 24B In the embodiment, the etching process of the isolation structure 420 is omitted, so that bottom buried conductive lines 494 , 495 , and 496 are formed above the isolation structure 420 . Fig.24A and Fig. 24B Other relevant structural details of the semiconductor device shown in Figures 20A-20C The semiconductor devices shown are substantially the same or similar, and therefore, descriptions in this regard will not be repeated below.

[0103] Figures 25A-28C A method for manufacturing a semiconductor device at various stages according to some embodiments of the present disclosure is shown. In some embodiments, Figures 25A-28C The semiconductor device shown in the figure may be an intermediate device manufactured during the process of an integrated circuit (IC) or a part thereof, which may include static random access memory (SRAM), logic circuits, passive components (such as resistors, capacitors and inductors), and / or active components (such as p-type field effect transistors (PFETs), n-type FETs (NFETs), multi-gate FETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors), other memory cells and combinations thereof.

[0104] refer to Figures 25A-25C ,in Fig.25B It is along Fig.25A A cross-sectional view taken along line BB in FIG. Fig.25C It is along Fig.25A At least one N-type device TN and at least one P-type device TP are formed on the substrate 610. Figures 25A-25C In the embodiment, the N-type device TN and the P-type device TP are horizontal gate-all-around (HGAA) FETs. Specifically, the substrate 610 includes at least one N-type region 610n and at least one P-type region 610p. The N-type device TN is formed on the N-type region 610n, and the P-type device TP is formed on the P-type region 610p. For ease of explanation, it is assumed that Figures 25A-28C In FIG. 6 , the substrate 610 includes a single N-type region 610n and a single P-type region 610p. The substrate 610 also includes a base 606 extending upward, and the base 606 may be a fin structure.

[0105] In some embodiments, the substrate 610 and Figure 2 The substrate 210 in the embodiment may have the same or similar materials, and therefore, the description of this aspect will not be repeated below. In some embodiments, an isolation structure 620 is formed in the substrate 610 to separate various devices. The isolation structure 620 and Figure 3 The isolation structure 220 in the embodiment may have the same or similar material, and therefore, the description in this regard will not be repeated below.

[0106] Each of the N-type device TN and the P-type device TP includes a semiconductor layer (or nanosheet or nanorod or nanocolumn) 602 as a channel of the N-type device TN and the P-type device TP. The semiconductor layers 602 are above the substrate 610 and are spaced apart from each other. In some embodiments, the semiconductor layer 602 may be a pure silicon layer without germanium. The semiconductor layer 602 may also be a substantially pure silicon layer, for example, the germanium percentage is less than about 1%. In addition, the semiconductor layer 602 may be intrinsic, which is not doped with p-type and n-type impurities. There may be two, three, four or more semiconductor layers 602. However, in some other embodiments, the semiconductor layer 602 may be silicon germanium or germanium for a p-type semiconductor device, or may be a III-V group material, such as InAs, InGaAs, InGaAsSb, GaAs, InPSb or other suitable materials.

[0107] In some embodiments, a bottom insulating layer 604 is formed between the bottommost semiconductor layer 602 and the base 606 of the substrate 610 to prevent current from leaking from the semiconductor layer 602 to the substrate 610. The bottom insulating layer 604 may be made of silicon nitride, oxide, metal oxide, or other dielectrics (e.g., SiC xO y N z In some embodiments, the bottom insulating layer 604 may be formed by performing an ALD process or other suitable processes.

[0108] The gate structure 680 is formed over the substrate 610 and surrounds (wraps) the semiconductor layer 602. The spacer structure 650 is disposed on the opposite side of the gate structure 680. In some embodiments, the spacer structure 650 and Figure 5 The spacer structure 250 in the embodiment may have the same or similar materials, and therefore, the description in this regard will not be repeated below. The gate structure 680 includes a high-k gate dielectric layer 682, one or more work function metal layers 685, and a filling layer 686. The work function metal layer 685 and the filling layer 686 are referred to as a gate electrode 684. The high-k gate dielectric layer 682 conformally wraps the semiconductor layer 602. In some embodiments, the high-k gate dielectric layer 682 includes a material such as hafnium oxide (HfO2), zirconium oxide (ZrO2), or lanthanum oxide (La2O3). In some embodiments, the high-k gate dielectric layer 682 can be formed by performing an ALD process or other suitable process.

[0109] In some embodiments, the work function metal layer 685 is conformally formed on the high-k gate dielectric layer, and the work function metal layer 685 surrounds the semiconductor layer 602. The work function metal layer 685 may include materials such as TiN, TaN, TiAlSi, TiSiN, TiAl, TaAl, or other suitable materials. In some embodiments, the work function metal layer 685 may be formed by performing an ALD process or other suitable process. A filling layer 686 is formed above the work function metal layer 685. The filling layer 686 may include materials such as tungsten or aluminum.

[0110] The epitaxial structures 662 and 664 are formed on opposite sidewalls of the semiconductor layer 602 by performing, for example, a selective growth process, and are respectively formed on the N-type region 610n and the P-type region 610p. In some embodiments, the epitaxial structures 662 and 664 and Figure 5 The epitaxial structures 262 and 264 in the embodiment may have the same or similar materials, and therefore, the description in this regard will not be repeated below.

[0111] In some embodiments, the inner sidewall spacer 608 is formed between the gate structure 680 and the epitaxial structure 662 (664) to isolate the gate structure 680 from the epitaxial structure 662 (664). The inner sidewall spacer 608 can be made of silicon nitride, oxide, metal oxide or other dielectrics (e.g., SiC x O y N z). In some embodiments, the sidewall spacer 608 is formed by performing an ALD process or other suitable process. In some embodiments, a trimming process may be performed after the sidewall spacer 608 is deposited to remove a portion of the sidewall spacer 608 outside the gate spacer 420.

[0112] A first interlayer dielectric (ILD) 675 is formed on the isolation structure 620, the epitaxial structures 662 and 664, and surrounds the gate structure 680. In some embodiments, the first ILD 675 and Figure 7A-7B The first ILD 275 in the embodiment may have the same or similar materials, and thus, the description in this regard will not be repeated below. In some other embodiments, a contact etch stop layer (CESL) 670 may be formed before forming the first ILD 675 .

[0113] refer to Fig.26 The first ILD 675 is etched to form a plurality of contact openings 676, a plurality of trenches 677a, 677b and at least one interconnect opening 678. Source / drain contacts 692, bottom buried conductive lines 694, 695 and at least one buried via 698 are formed in the contact openings 676, the trenches 677a, 677b and the interconnect opening 678, respectively. The aforementioned process may be performed with Figures 8A-9B The processes shown are the same or similar, and therefore, the description in this regard will not be repeated below.

[0114] refer to Fig. 27 Then, in Fig.26 A second interlayer dielectric (ILD) 710 is formed on the structure. Subsequently, the second ILD 710 is etched to form a plurality of gate openings 714, a plurality of contact openings 716, a plurality of trenches 717a, 717b and at least one interconnect opening 712. Gate vias 721, source / drain contacts 722, top buried conductive lines 724, 725 and buried vias 729 are formed in the gate openings 714, the contact openings 716, the trenches 717a, 717b and the interconnect openings 712, respectively. The aforementioned process may be performed with Figures 10A-11B The processes shown are the same or similar, and therefore, the description in this regard will not be repeated below.

[0115] refer to Figures 28A-28C ,in Fig.28B It is along Fig.28A A cross-sectional view taken along line BB in FIG. Fig.28C It is along Fig.28A Then, in Fig. 27 A third ILD 730 is formed on the structure. A plurality of conductive lines 741, 743, 745, 747 and 749 are formed over the third ILD 730. The aforementioned process may be Figures 12A-12BThe processes shown are the same or similar. Therefore, the description of this aspect will not be repeated below.

[0116] In some embodiments, conductive lines 741 and 749 are power lines, and conductive lines 743, 745, and 747 are signal lines. Conductive lines 741 and 749 may be connected to Fig.28A The structure shown is shared by adjacent cells. The conductive lines 741 , 743 , 745 , 747 , and 749 may be electrically connected to the N-type device TN and / or the P-type device TP through vias (eg, via 752 ) in the third ILD 730 .

[0117] Fig.29 is a perspective view of a semiconductor device according to some embodiments of the present disclosure. Fig.29 and Figures 28A-28C The difference between the semiconductor devices in FIG. 7 is the configuration of the conductive lines 741 and 749. Fig.29 In the embodiment, the top buried conductive lines 724 and 725 are omitted (see Fig.28B ), and the conductive lines 741 and 749 extend into the second ILD 710. Fig.29 In the embodiment, since the conductive lines 741 and 749 extend to the second ILD 710, the conductivity thereof can be increased, and the width W1' of the conductive lines 741 and 749 can be reduced. With this configuration, the cell height H5' of the semiconductor device can be reduced. Fig.29 Other relevant structural details of the semiconductor device in Figures 28A-28C The semiconductor devices in the embodiment of the present invention are substantially the same or similar. Therefore, the description in this regard will not be repeated below.

[0118] Fig.30 is a perspective view of a semiconductor device according to some embodiments of the present disclosure. Fig.30 and Figures 28A-28C The difference between the semiconductor devices in FIG. 7 is the presence of the second ILD 710, the top buried conductive lines 724 and 725, and the source / drain contacts 722. Fig.30 , the second ILD 710, the top buried conductive lines 724 and 725, and the source / drain contacts 722 are omitted (see Fig.28B ), and the third ILD 730 is in direct contact with the first ILD 675. That is, there is only one layer of buried conductive lines. Fig.30 Other relevant structural details of the semiconductor device in Figures 28A-28C The semiconductor devices in the embodiment of the present invention are substantially the same or similar. Therefore, the description in this regard will not be repeated below.

[0119] Fig.31 is a perspective view of a semiconductor device according to some embodiments of the present disclosure. Fig.31 and Fig.30The difference between the semiconductor devices in FIG. 7 is the configuration of the conductive lines 741 and 749. Fig.31 In the embodiment, the bottom buried conductive lines 694 and 695 are omitted (see Fig.30 ), and the conductive lines 741 and 749 extend into the first ILD 675. Fig.31 In the embodiment, since the conductive lines 741 and 749 extend into the first ILD 675, the conductivity thereof can be increased, and the width W1' of the conductive lines 741 and 749 can be reduced. With this configuration, the cell height H5' of the semiconductor device can be reduced. Fig.31 Other relevant structural details of the semiconductor device in Fig.30 The semiconductor devices in the embodiment are basically the same or similar, so the description in this regard will not be repeated below.

[0120] Fig.32 is a perspective view of a semiconductor device according to some embodiments of the present disclosure. Fig.32 and Figures 28A-28C The difference between the semiconductor devices in FIG. 1 is the depth of the bottom buried conductive lines 694 and 695. Fig.32 In FIG. 6 , the etching process of the isolation structure 620 is omitted, so that the bottom buried conductive lines 694 and 695 are formed above the isolation structure 620 . Fig.32 Other relevant structural details of the semiconductor device in Figures 28A-28C The semiconductor devices in the embodiment are basically the same or similar, so the description in this regard will not be repeated below.

[0121] Fig.33 is a flow chart of a method M1 for forming a semiconductor device according to some embodiments of the present disclosure. Although method M1 is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the order or actions shown. Therefore, in some embodiments, the actions may be performed in an order different from the order shown, and / or the actions may be performed simultaneously. In addition, in some embodiments, the actions or events shown may be subdivided into multiple actions or events, which may be performed at independent times or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown may be omitted, and other actions or events not shown may be included.

[0122] In block S12 , at least one device is formed over the substrate, wherein a first ILD horizontally surrounds the device. Fig. 7A , Fig.17A and Fig.25A A perspective view of some embodiments corresponding to the actions in block S12 is shown. In some embodiments, the device may be a transistor, such as Fig. 7A , Fig.17A and Fig.25A N-type devices in TN and / or Fig. 7A , Fig.17A and Fig.25A In block S14, at least one buried conductive line is formed in the first ILD, such that the buried conductive line and the device are electrically connected. Fig. 9A , Fig.18A and Fig.26 A perspective view of some embodiments corresponding to the actions in block S 14 is shown. In block S 16, at least one conductive line is formed over the device and the buried conductive line such that the conductive line and the device are electrically connected. Fig. 12A , Fig. 20A and Fig.28A A perspective diagram of some embodiments corresponding to the actions in block S16 is shown.

[0123] Based on the above discussion, it can be seen that the present disclosure provides advantages. However, it should be understood that other embodiments may provide additional advantages, and it is not necessary to disclose all advantages here, and no specific advantages are required for all embodiments. One advantage is that since the semiconductor device includes top and / or bottom buried conductive lines, internal electrical connections between transistors can be achieved by using top and / or bottom buried conductive lines. Another advantage is that the top and / or bottom buried conductive lines are directly below the power line, the top and / or bottom buried conductive lines do not occupy the layout area of ​​the semiconductor device, and the cell height of the semiconductor device can be reduced. In addition, when the power line extends to the ILD below, the cell height can be further reduced.

[0124] According to some embodiments, a device includes a transistor, an insulating structure, a buried conductive line, and a buried via. The transistor is above a substrate and includes a source / drain region and a source / drain contact above the source / drain region. The insulating structure is above the substrate and laterally surrounds the transistor. The buried conductive line is in the insulating structure and is spaced apart from the transistor. The buried via is in the insulating structure and interconnects the transistor and the buried conductive line. The height of the buried conductive line is greater than the height of the source / drain contact.

[0125] According to some embodiments, a device includes a transistor, an insulating structure, a first conductive line, and a second conductive line. The transistor is above a substrate. The insulating structure is above the substrate and laterally surrounds the transistor. The first conductive line is above the insulating structure and the transistor. The second conductive line is above the substrate and partially buried in the insulating structure. The first and second conductive lines extend in a first direction. Top surfaces of the first and second conductive lines are substantially coplanar. The height of the second conductive line is greater than the height of the first conductive line.

[0126] According to some embodiments, a method for manufacturing a device includes forming a transistor above a substrate. A first trench is formed in the substrate. An insulating structure is formed above the substrate, surrounding the transistor and partially in the first trench. A second trench is formed in the insulating structure. The second trench does not expose the transistor. A first buried conductive line is formed in the first trench and adjacent to the transistor.

[0127] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0128] Example 1. A semiconductor device, comprising: a transistor located above a substrate, wherein the transistor comprises: a source / drain region; and a source / drain contact located above the source / drain region; an insulating structure located above the substrate and laterally surrounding the transistor; a buried conductive line located in the insulating structure and spaced apart from the transistor; and a buried via located in the insulating structure and interconnecting the transistor and the buried conductive line, wherein a height of the buried conductive line is greater than a height of the source / drain contact.

[0129] Example 2. The semiconductor device of Example 1, wherein the source / drain contacts are spaced apart from the buried conductive line.

[0130] Example 3. The semiconductor device of Example 1, wherein the buried via is in direct contact with the buried conductive line and the source / drain contact.

[0131] Example 4. The semiconductor device of Example 2, wherein a bottom surface of the buried conductive line is lower than a bottom surface of the source / drain contact.

[0132] Example 5. The semiconductor device of Example 2, wherein a top surface of the buried conductive line is higher than a top surface of the source / drain contact.

[0133] Example 6. The semiconductor device of Example 1, wherein the transistor further comprises a gate structure, and the buried via is in direct contact with the buried conductive line and the gate structure.

[0134] Example 7. The semiconductor device of Example 6, wherein the gate structure and the buried conductive line extend in different directions.

[0135] Example 8. The semiconductor device of Example 1, wherein the insulating structure comprises: an isolation structure located above the substrate; and an interlayer dielectric located above the isolation structure.

[0136] Example 9. The semiconductor device of Example 8, wherein a bottom surface of the buried conductive line is lower than a top surface of the isolation structure.

[0137] Example 10. The semiconductor device of Example 8, wherein a top surface of the buried conductive line and a top surface of the interlayer dielectric are coplanar.

[0138] Example 11. A semiconductor device, comprising: a transistor located above a substrate; an insulating structure located above the substrate and laterally surrounding the transistor; a first conductive line located above the insulating structure and the transistor; and a second conductive line located above the substrate and partially buried in the insulating structure, wherein the first conductive line and the second conductive line extend along a first direction, the top surfaces of the first conductive line and the second conductive line are coplanar, and the height of the second conductive line is greater than the height of the first conductive line.

[0139] Example 12. The semiconductor device of Example 11, wherein a width of the second conductive line is not greater than a width of the first conductive line.

[0140] Example 13. The semiconductor device of Example 11, wherein the insulating structure comprises: an isolation structure located above the substrate; and an interlayer dielectric located above the isolation structure, and a portion of the interlayer dielectric is lower than the isolation structure.

[0141] Example 14. The semiconductor device of Example 11, wherein a bottom surface of the second conductive line is lower than a bottom surface of the insulating structure.

[0142] Example 15 The semiconductor device of Example 11, further comprising a buried conductive line directly below the second conductive line, wherein the buried conductive line is adjacent to the transistor.

[0143] Example 16. A method for manufacturing a device, comprising: forming a transistor above a substrate; forming a first trench in the substrate; forming an insulating structure above the substrate, surrounding the transistor and partially in the first trench; forming a second trench in the insulating structure, wherein the second trench does not expose the transistor; and forming a first buried conductive line in the second trench and adjacent to the transistor.

[0144] Example 17. The method of Example 16, wherein the first buried conductive line is formed directly over a portion of the insulating structure in the first trench.

[0145] Example 18. The method of Example 16, further comprising: forming a first dielectric layer over the first buried conductive line; and forming a power line over the dielectric layer and directly over the first buried conductive line.

[0146] Example 19. The method of Example 18, further comprising: forming a second dielectric layer above the buried conductive line before forming the first dielectric; and forming a second buried conductive line in the second dielectric layer and directly above the first buried conductive line.

[0147] Example 20. The method of Example 16, further comprising: forming an opening in the insulating structure; and forming a buried via in the insulating structure, such that the buried via interconnects the first buried conductive line and the transistor.

Claims

1. A semiconductor device, comprising: A transistor is located above the substrate, wherein the transistor comprises: source / drain regions; and a source / drain contact located above the source / drain region; an insulating structure located above the substrate and laterally surrounding the transistor; a buried conductive line located in the insulating structure and spaced apart from the transistor; and A buried via is located in the insulating structure and interconnects the transistor and the buried conductive line, wherein the height of the buried conductive line is greater than the height of the source / drain contact, and the top surface of the buried conductive line is coplanar with the top surface of the buried via.

2. The semiconductor device according to claim 1, wherein The source / drain contacts are spaced apart from the buried conductive line.

3. The semiconductor device according to claim 1, wherein The buried via is in direct contact with the buried conductive line and the source / drain contacts.

4. The semiconductor device according to claim 2, wherein: A bottom surface of the buried conductive line is lower than a bottom surface of the source / drain contact.

5. The semiconductor device according to claim 2, wherein: A top surface of the buried conductive line is higher than a top surface of the source / drain contact.

6. The semiconductor device according to claim 1, wherein The transistor also includes a gate structure, and the buried via is in direct contact with the buried conductive line and the gate structure.

7. The semiconductor device according to claim 6, wherein: The gate structure and the buried conductive line extend in different directions.

8. The semiconductor device according to claim 1, wherein The insulating structure comprises: an isolation structure located above the substrate; and An interlayer dielectric is located above the isolation structure.

9. The semiconductor device according to claim 8, wherein: A bottom surface of the buried conductive line is lower than a top surface of the isolation structure.

10. The semiconductor device according to claim 8, wherein A top surface of the buried conductive line is coplanar with a top surface of the interlayer dielectric.

11. A semiconductor device comprising: transistors, located above the substrate; an insulating structure located above the substrate and laterally surrounding the transistor, wherein the insulating structure comprises: an isolation structure located above the substrate; and an interlayer dielectric located above the isolation structure, and a portion of the interlayer dielectric is below the isolation structure; A first conductive line located above the insulating structure and the transistor; and A second conductive line is located above the substrate and is partially buried in the insulating structure, wherein the first conductive line and the second conductive line extend along a first direction, the top surfaces of the first conductive line and the second conductive line are coplanar, and the height of the second conductive line is greater than the height of the first conductive line.

12. The semiconductor device according to claim 11, wherein The width of the second conductive line is not greater than the width of the first conductive line.

13. The semiconductor device according to claim 11, wherein A bottom surface of the second conductive line is lower than a bottom surface of the insulating structure.

14. The semiconductor device according to claim 11, further comprising a buried conductive line located directly below the second conductive line, wherein The buried conductive line is adjacent to the transistor.

15. A method for manufacturing a device, comprising: forming a transistor over the substrate; forming a first trench in the substrate; forming an insulating structure over the substrate, surrounding the transistor and partially in the first trench; forming a second trench and a contact opening in the insulating structure, wherein the second trench does not expose the transistor and the contact opening exposes a source / drain region of the transistor; as well as After forming the second trench and the contact opening, the second trench and the contact opening are filled with a conductive material to form a first buried conductive line in the second trench and adjacent to the transistor and to form a source / drain contact over a source / drain region of the transistor.

16. The method according to claim 15, wherein: The first buried conductive line is formed directly over a portion of the insulating structure in the first trench.

17. The method according to claim 15, further comprising: forming a first dielectric layer over the first buried conductive line; as well as A power supply line is formed over the dielectric layer and directly above the first buried conductive line.

18. The method according to claim 17, further comprising: before forming the first dielectric, forming a second dielectric layer over the buried conductive line; as well as A second buried conductive line is formed in the second dielectric layer and directly above the first buried conductive line.

19. The method according to claim 15, further comprising: forming an opening in the insulating structure; as well as A buried via is formed in the insulating structure such that the buried via interconnects the first buried conductive line and the transistor.

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