Integrated circuit chip and method for forming an integrated circuit chip

Abstract

Various embodiments of the present application are directed to integrated circuit (IC) chips including a semiconductor through-silicon via (TSV) on a front-end-of-line (FEOL) substrate and methods for forming the same. In some embodiments, a semiconductor layer is on the substrate. The semiconductor layer may, for example, be or include a group III-V semiconductor and / or some other suitable semiconductor. A semiconductor device is on the semiconductor layer, and a FEOL layer is on the semiconductor device. A FEOL TSV extends through the FEOL layer and the semiconductor layer to the substrate at a periphery of the IC chip. An inter-metal dielectric (IMD) layer is on the FEOL TSV and the FEOL layer, and an alternating stack of wires and vias is in the IMD layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to integrated circuit chips and methods for forming integrated circuit chips. BACKGROUND

[0002] Over the past several decades, silicon-based semiconductor devices have been the standard. However, semiconductor devices based on alternative materials are receiving increasing attention for their advantages over silicon-based semiconductor devices. For example, semiconductor devices based on gallium nitride (e.g., GaN) and other III-V semiconductor materials are receiving increasing attention due to high electron mobility and wide bandgaps, as compared to silicon-based semiconductor devices. Such high electron mobility and wide bandgaps allow for improved performance and high temperature applications. SUMMARY

[0003] According to one embodiment of the present application, an integrated circuit (IC) chip is provided, comprising: a substrate; a semiconductor layer on the substrate; a front end of line (FEOL) layer on the semiconductor layer; a through via extending through the FEOL layer and the semiconductor layer to the substrate at a periphery of the IC chip; and an alternating stack of a wire and a via over the through via.

[0004] According to another embodiment of the present application, an integrated circuit (IC) chip is provided, comprising: a substrate; a semiconductor layer on the substrate; a semiconductor device on the semiconductor layer; an interconnect structure on the semiconductor device; a contact extending from the interconnect structure to the semiconductor device; and a through via extending through the semiconductor layer to the substrate and having a top surface that is approximately flush with or recessed relative to a top surface of the contact.

[0005] According to yet another embodiment of the present application, a method for forming an integrated circuit (IC) chip is provided, the method comprising: depositing a semiconductor layer over a substrate; forming a semiconductor device on the semiconductor layer; forming a front end of line (FEOL) layer over the semiconductor device; patterning the FEOL layer and the semiconductor layer to form a trench extending through the FEOL layer and the semiconductor layer to the substrate at a periphery of the IC chip; filling the trench with a dielectric and / or conductive material to form a through via; and forming an intermetallic dielectric (IMD) layer over the through via and the FEOL layer, while forming an alternating stack of a wire and a via in the IMD layer.

[0006] Embodiments of the present application provide semiconductor through vias (TSVs) on front end of line (FEOL) substrates. BRIEF DESCRIPTION OF DRAWINGS

[0007] The various aspects of the application can best be understood with reference to the following detailed description when read with the accompanying drawings in which: It should be noted that the various components are not necessarily drawn to scale. Indeed, the dimensions of the various components can be arbitrarily increased or decreased for the sake of discussion. It is also to be understood that the specific devices illustrated are intended to represent only a general class of such devices. For example, the various components can be implemented in hardware, software or a combination thereof.

[0008] Figure 1 Cross-sectional views illustrating some embodiments of an integrated circuit (IC) chip including through semiconductor vias (TSVs) on a front end of line (FEOL) substrate.

[0009] Figure 2 Top layout views illustrating some embodiments of FEOL TSVs. Figure 1

[0010] Figures 3A-3E Cross-sectional views illustrating some different alternative embodiments of an IC chip of Figure 1

[0011] Cross-sectional views illustrating some embodiments of an IC chip of Figure 4 Figure 1

[0012] Figure 5 Cross-sectional views illustrating some alternative embodiments of an IC chip of Figure 1

[0013] Top layout views illustrating some embodiments of FEOL TSVs. Figure 6 Figure 5

[0014] Figures 7A-7C Cross-sectional views illustrating some different alternative embodiments of an IC chip of Figure 5

[0015] Figure 8 Cross-sectional views illustrating some embodiments of an IC chip of Figure 5

[0016] Figures 9-15 A series of cross-sectional views illustrating some embodiments of a method for forming an IC chip including FEOL TSVs.

[0017] Figure 16 Block diagrams illustrating some embodiments of a method of Figures 9-15

[0018] Figure 17 and Figure 18 respectively illustrate Figure 12 and Figure 13 ​​​​​​​​some alternative embodiments of the IC chip in FIG. 1.

[0019] Figures 19-26 A series of cross-sectional views showing some embodiments of a method for forming an IC chip including FEOL TSVs that provide electrical coupling to a substrate.

[0020] Figure 27 A block diagram showing some embodiments of a method of Figures 19-26 DETAILED DESCRIPTION

[0021] The present application provides many different embodiments or examples, but specific examples are provided in the description below to provide a thorough description of embodiments of the application. Of course, it will be apparent that specific examples can not include all features of the application. For example, some embodiments can not include features of one or more examples provided in the description below. Each feature and example can be implemented in its own embodiment and each description articulates a representative embodiment. After considering this discussion, it will be apparent to one skilled in the art how to implement the application in various embodiments and examples. It should be noted that, in this Discussion, references to examples can include one or more embodiments of the application, and that features discussed in relation to a particular example can be combined with any other example described or otherwise disclosed herein.

[0022] Furthermore, spatial or directional terms, such as "below", "above", "lower", "upper", and the like can be used in this description in relation to the illustrated orientation of the device as shown in the figures. The spatial or directional terms are used in relation to the device's use or operation as intended and can be interpreted differently depending on the orientation of the device in use or operation. The device can be positioned in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptions contained herein can be interpreted accordingly.

[0023] Some integrated circuit (IC) chips include a substrate and a III-V layer on the substrate. A front end of line (FEOL) layer and a semiconductor device are on the III-V layer, where the semiconductor device is buried in the FEOL layer. A plurality of interlayer dielectric (ILD) layers are stacked on the FEOL layer, and a back end of line (BEOL) interconnect structure is on the ILD layers. The BEOL interconnect structure includes an intermetal dielectric (IMD) layer and a plurality of wires and vias stacked in the IMD layer. A back end of line (BEOL) III-V through via (TGV) is at a periphery of the IC chip and extends through the BEOL interconnect structure, the ILD layers, the FEOL layer, and the III-V layer to the substrate. The BEOL TGV can be used as a seal ring or to electrically couple to the substrate, for example.

[0024] ​Methods for forming BEOL TGVs include etching through the IMD layer, the ILD layer, the FEOL layer, and the Group III-V layer to form a trench in which the BEOL TGV is formed. A challenge of this method is that the IMD and ILD layers are thick, and thus the etch depth is large. For example, the thickness of the IMD and ILD layers can be about 12-13 microns or some other suitable value. Because the etch depth is large, the etch takes a large amount of time, and the production rate for batch production is low. For example, etching through the IMD and ILD layers can take about 40 minutes or some other suitable value. Furthermore, because the etch depth is large, the etch can be divided into multiple etches using different photoresist masks formed by lithography. Because lithography is expensive, using multiple photoresist masks can result in high cost. Furthermore, because the etch depth is large, the trench can have a high aspect ratio (e.g., high height-to-width ratio). As such, the material deposited in the trench to form the BEOL TGV is likely to be deposited with voids. At least when the BEOL TGV is used to electrically couple with the substrate, the voids increase the electrical resistance of the BEOL TGV, thereby degrading the performance of the BEOL TGV. Thus, the high likelihood of deposition with voids can increase the likelihood that the BEOL TGV falls outside of design specifications, thereby potentially degrading yield.

[0025] Various embodiments of the present disclosure are directed to methods for forming an IC chip including a semiconductor through-silica via (TSV) on a FEOL substrate and the IC chip obtained from the method. In some embodiments of the method, a semiconductor layer is deposited over the substrate. The semiconductor layer can be, for example, or include, a Group III-V semiconductor and / or some other suitable semiconductor. FEOL layers and semiconductor devices are formed on the semiconductor layer, with the semiconductor devices being buried in the FEOL layers. A lithography / etching process is performed to form a trench at a periphery of the IC chip and extending through the FEOL layers and the semiconductor layer to the substrate. A FEOL TSV is formed to fill the trench, and a plurality of ILD layers are formed on the FEOL layers. In some embodiments, the ILD layers partially define the FEOL TSV. In alternative embodiments, the ILD layers cover and are independent of the FEOL TSV. A BEOL interconnect structure is formed on the ILD layers and includes a plurality of wires, a plurality of vias, and an IMD layer housing the wires and the vias.

[0026] Because the trenches are formed prior to deposition of the ILD and IMD layers, the etching that forms the trenches does not extend through the ILD and IMD layers. As a result, the etching depth is small. Because the etching depth is small, the etching takes less time and the production rate for batch production is high. In addition, because the etching depth is small, the etching can be performed with a single photoresist mask formed by photolithography. Because photolithography is expensive, the use of a single photoresist mask can result in low cost. In addition, because the etching depth is small, the trenches can have a small aspect ratio. In this way, the material deposited in the trenches to form the FEOL TSVs can have a low likelihood of being deposited with voids. At least when the FEOL TSVs are used to electrically couple with the substrate, voids increase the electrical resistance of the FEOL TSVs, thereby degrading the performance of the FEOL TSVs. Thus, the low likelihood of being deposited with voids can reduce the likelihood of the FEOL TSVs falling outside of design specifications, thereby increasing the yield.

[0027] Reference Figure 1 A cross-sectional view 100 of some embodiments of an IC chip including FEOL TSVs 102 is provided. The FEOL TSVs 102 are on a substrate 104 in a peripheral region P of the IC chip and extend through a semiconductor layer 106 and a FEOL layer 108 to the substrate 104. The semiconductor layer 106 is on the substrate 104 and the FEOL layer 108 is on the semiconductor layer 106. The semiconductor FEOL TSVs 102 are defined by a first ILD layer 110, a second ILD layer 112, and a gap fill layer 114. In alternative embodiments, the first ILD layer 110 and / or the second ILD layer 112 are omitted. The first ILD layer 110 is on the FEOL layer 108, the second ILD layer 112 is on the first ILD layer 110, and the gap fill layer 114 is on the second ILD layer 112.

[0028] The contacts 116 are located in the first and second ILD layers 110, 112 and the FEOL layer 108 at locations laterally offset from the FEOL TSVs 102. In alternative embodiments, the contacts 116 are omitted. Further, the BEOL interconnect structure 118 covers the FEOL TSVs 102, the second ILD layer 112, and the contacts 116. The BEOL interconnect structure 118 includes IMD layers 120 and a passivation layer 122 located on the IMD layers 120. Further, the BEOL interconnect structure 118 includes a plurality of wires 124, a plurality of vias 126, and pads 128. The wires 124 and the vias 126 are alternately stacked in the IMD layers 120 and are located on the contacts 116. The pads 128 are located on the wires 124 and the vias 126 between the IMD layers 120 and the passivation layer 122. Further, the pads 128 are exposed through pad openings 130 defined by the passivation layer 122. In alternative embodiments, the pad openings 130 are omitted. The contacts 116, the wires 124, the vias 126, and the pads 128 collectively define a conductive seal structure 132.

[0029] Because the FEOL TSVs 102 are located below the IMD layers 120 and are defined by the first and second ILD layers 110, 112, trenches accommodating the FEOL TSVs 102 are formed prior to the first and second ILD layers 110, 112 and the IMD layers 120. As such, the etching forming the trenches does not extend through the first and second ILD layers 110, 112 and the IMD layers 120. The first and second ILD layers 110, 112 and the IMD layers 120 have a large thickness such that if the etching extended through the first and second ILD layers 110, 112 and the IMD layers 120, the etching would have a large etch depth. However, because the etching does not extend through the first and second ILD layers 110, 112 and the IMD layers 120, the etching has a small etch depth. Because the etching has a small etch depth, the etching takes a small amount of time and has a high production rate for batch production. For example, the etching can be about 50% or some other suitable percentage faster when not etching through the first and second ILD layers 110, 112 and the IMD layers 120. Further, because the etching has a small etch depth, the etching can be performed with a single photoresist mask formed with photolithography. Because photolithography is expensive, using a single photoresist mask can result in a low cost.

[0030] The conductive seal structure 132 and the FEOL TSV 102 cooperate to seal the peripheral region P of the IC chip, thereby protecting an interior region (not shown) of the IC chip. For example, the conductive seal structure 132 and the FEOL TSV 102 can prevent moisture and / or vapor from entering the IC chip at the peripheral region P of the IC chip. Moisture and / or vapor that enters the IC chip can corrode conductive components and / or semiconductor devices in the IC chip. As another example, the conductive seal structure 132 and the FEOL TSV 102 can prevent cracks caused by a die cutter during singulation of the IC chip from a wafer from propagating through the IC chip. Cracks that propagate through the IC chip can cause delamination of layers and / or structures in the IC chip.

[0031] As described above, the etching used to form the trench that houses the FEOL TSV 102 can have a small etch depth. Because the etching has a small etch depth, the trench can have a small aspect ratio (e.g., a small height-to-width ratio). As such, the first and second ILD layers 110, 112 and the gap fill layer 114 can have a low likelihood of being deposited with voids. Voids can impede the FEOL TSV 102 from protecting the interior region of the IC chip. For example, voids can impede the FEOL TSV 102 from preventing moisture and / or vapor from entering the IC chip, and / or can impede the FEOL TSV 102 from preventing the propagation of cracks caused by a die cutter. Thus, the low likelihood of being deposited with voids can reduce the likelihood of the FEOL TSV falling outside of design specifications, which can improve yield.

[0032] Referring again to the FEOL layer 108, the FEOL layer 108 is between the semiconductor layer 106 and the first ILD layer 110 and is composed of multiple layers (not shown individually) deposited during FEOL processing. Further, the FEOL layer 108 covers semiconductor devices (not shown) on the semiconductor layer 106 and, in some embodiments, at least partially defines the semiconductor devices. The layers that compose the FEOL layer 108 can include, for example, ILD layers, pad oxide layers, pad nitride layers, contact etch stop layers (CESLs), gate dielectric layers, some other suitable layer, or any combination of the above. In some embodiments, the FEOL layer 108 is limited to dielectric oxides and / or other suitable dielectrics. Further, in some embodiments, the FEOL layer 108 has a thickness of about 3.5-4.0 kilo Angstroms (kA), about 4.0-4.5 kA, about 3.5-4.5 kA, or some other suitable value.

[0033] In some embodiments, the semiconductor layer 106 is or includes a III-V material. For example, the semiconductor layer 106 can be or include gallium nitride (e.g., GaN), gallium arsenide (e.g., GaAs), indium phosphide (InP), some other suitable III-V material, or any combination thereof. In alternative embodiments, the semiconductor layer 106 is or includes a II-VI material, a IV-IV material, or some other suitable semiconductor material. In some embodiments, the semiconductor layer 106 is composed of multiple layers (not shown separately) that define a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG) along a heterojunction. For example, the semiconductor layer 106 can include a layer of aluminum gallium nitride and a layer of gallium nitride in direct contact to define a heterojunction and a 2DEG along the heterojunction. In some embodiments, the semiconductor layer 106 has a thickness of about 45-55 kA, about 55-65 kA, about 45-65 kA, about 58 kA, about 50 kA, or some other suitable value.

[0034] In some embodiments, the substrate 104 is or includes a bulk substrate of single-crystal silicon, a bulk substrate of silicon carbide, a silicon-on-insulator (SOI) substrate, or some other suitable type of semiconductor substrate.

[0035] In some embodiments, each of the first ILD layer 110, the second ILD layer 112, and the IMD layer 120 is a dielectric oxide and / or some other suitable dielectric. In some embodiments, the gap fill layer 114 is or includes a dielectric oxide and / or some other suitable dielectric. In alternative embodiments, the gap fill layer 114 is or includes a conductive material and / or some other suitable material. In some embodiments, the first ILD layer 110 and the second ILD layer 112 are different dielectrics, the second ILD layer 112 and the gap fill layer 114 are different materials, the second ILD layer 112 and the IMD layer 120 are different dielectrics, or any combination of the above. In some embodiments, any one or combination of the first ILD layer 110, the second ILD layer 112, and the gap fill layer 114 has a lower moisture and / or vapor permeability than the FEOL layer 108 to prevent moisture and / or vapor from the surrounding environment of the IC chip from entering the FEOL layer 108. Such moisture and / or vapor can corrode and thus damage the semiconductor devices (not shown) in the FEOL layer 108. In some embodiments, the gap fill layer 114 has a lower permeability to moisture and / or vapor than the first and / or second ILD layers 110, 112 and / or the second ILD layer 112 has a lower permeability to moisture and / or vapor than the first ILD layer 110. In some embodiments, the first ILD layer 110, the second ILD layer 112, and the IMD layer 120 have a combined thickness of about 120-140 kA, about 120-130 kA, about 130-140 kA, about 125 kA, about 126 kA, or some other suitable value.

[0036] In some embodiments, the contacts 116 are or include tungsten and / or some other suitable metal. In some embodiments, the leads 124, the vias 126, and the pads 128 are or include copper, aluminum copper, aluminum, some other suitable metal, or any combination thereof.

[0037] Referring to Figure 2 , a top layout view 200 of some embodiments of the IC chip of Figure 1 is provided. For example, Figure 1 the cross-sectional view 100 can be taken along line A, although other suitable locations are possible. The FEOL TSVs 102 and the conductive seal structure 132 extend in a single closed path along the peripheral region P of the IC chip to enclose the interior region I of the IC chip. The closed path is a rectangular ring, although it can be a circular ring, a square ring, or other suitable shape. Moreover, the conductive seal structure 132 is between the FEOL TSVs 102 and the interior region I of the IC chip. As will be seen below, the interior region I of the IC chip houses semiconductor devices (not shown) and conductive interconnects (not shown) that define circuitry.

[0038] The FEOL TSVs 102 and the conductive seal structure 132 cooperate to seal the peripheral region P of the IC chip, thereby protecting the interior region I of the IC chip. For example, the FEOL TSVs 102 and the conductive seal structure 132 can prevent moisture and / or vapor from entering the IC chip at the peripheral region P of the IC chip. As another example, the FEOL TSVs 102 and the conductive seal structure 132 can prevent cracks caused by a die cutter during singulation of the IC chip from a wafer from propagating through the IC chip.

[0039] Referring to Figures 3A-3E , cross-sectional views 300A-300E of some different alternative embodiments of the IC chip of Figure 1 are provided.

[0040] In Figure 3A , the top surface of the gap fill layer 114 has an indentation 302. For example, the indentation 302 can result from deposition of the gap fill layer 114 in the trench and subsequent planarization that does not extend far enough to completely remove the indentation 302.

[0041] In Figure 3B , the gap fill layer 114 is omitted, and the second ILD layer 112 occupies the space previously occupied by the gap fill layer 114. For example, this can be accomplished by depositing the second ILD layer 112 in the trench with a thickness great enough to completely fill the trench, and then planarizing the second ILD layer 112 to thin the second ILD layer 112.

[0042] InFigure 3C In some embodiments, the second ILD layer 112 is omitted, and the space occupied by the second ILD layer 112 is occupied by the first ILD layer 110.

[0043] In Figure 3D In some embodiments, the first and second ILD layers 110, 112 and the gap fill layer 114 have less uniform dimensions, and also have curved edges and sidewalls. In addition, the semiconductor layer 106 includes multiple layers (e.g., 106a and 106b), and the FEOL layer 108 includes multiple layers (e.g., 108a and 108b). For example, the first layer 106a of the semiconductor layer 106 can be or include gallium nitride, and the second layer 106b of the semiconductor layer 106 can be or include aluminum gallium nitride, or vice versa. However, other suitable materials are possible in addition to the materials in the examples.

[0044] In Figure 3E In some embodiments, the gap fill layer 114 completely defines the FEOL TSV 102, and extends through both the first and second ILD layers 110, 112 to the substrate 104. Because the FEOL TSV 102 is located under the IMD layer 120, the trench that houses the FEOL TSV 102 is formed before the IMD layer 120. As such, the etch that forms the trench does not extend through the IMD layer 120. The IMD layer 120 has a greater thickness, such that if the etch extended through the IMD layer 120, the etch would have a greater etch depth. However, because the etch does not extend through the IMD layer 120, the etch has a smaller etch depth. Note that the smaller etch depth is not as small as in Figure 1 In some embodiments, the gap fill layer 114 completely defines the FEOL TSV 102, and extends through both the first and second ILD layers 110, 112 to the substrate 104. Because the FEOL TSV 102 is located under the IMD layer 120, the trench that houses the FEOL TSV 102 is formed before the IMD layer 120. As such, the etch that forms the trench does not extend through the IMD layer 120. The IMD layer 120 has a greater thickness, such that if the etch extended through the IMD layer 120, the etch would have a greater etch depth. However, because the etch does not extend through the IMD layer 120, the etch has a smaller etch depth. Note that the smaller etch depth is not as small as in

[0045] Referring to Figure 4 , there is provided an enlarged cross-sectional view 400 of some embodiments of the IC chip of Figure 1 , in which the FEOL TSV 102 and the conductive seal structure 132 surround the inner region I of the IC chip at the peripheral region P of the IC chip. The FEOL TSV 102 has a pair of segments that are located on opposite sides of the inner region I of the IC chip, respectively. Similarly, the conductive seal structure 132 has a pair of segments that are located on opposite sides of the inner region I of the IC chip, respectively. In addition, the segments of the conductive seal structure 132 are located between the segments of the FEOL TSV 102.

[0046] In some embodiments, the FEOL TSVs 102 and the electrically conductive encapsulation structure 132 extend in separate closed paths to surround the interior region I of the IC chip when viewed from top to bottom. Further, in some embodiments, the IC chip has a top layout as in Figure 2 For example, the enlarged cross-sectional view 400 can be taken along line B in Figure 2 In alternative embodiments, the IC chip has some other suitable top layout.

[0047] The interior region I of the IC chip houses a plurality of semiconductor devices 402 interconnected by the contacts 116 and the BEOL interconnect structure 118 to define an electrical circuit. Note that while not shown, there can be additional pads (see, e.g., the pads 128) that electrically couple the electrical circuit to external devices and / or electrical circuits.

[0048] The semiconductor devices 402 are located between the semiconductor layer 106 and the FEOL layer 108, and can be, for example, high electron mobility transistors (HEMTs), metal-oxide semiconductor (MOS) HEMTs, metal-insulator semiconductor field effect transistors (MISFETs), some other suitable type of semiconductor device, or any combination thereof. The semiconductor devices 402 are defined in part by the semiconductor layer 106, and in some embodiments, are defined in part by the FEOL layer 108. For example, the semiconductor layer 106 can define a 2DEG of the semiconductor devices 402, and / or the FEOL layer 108 can define a gate dielectric layer of the semiconductor devices 402. As noted above, the semiconductor layer 106 can be composed of multiple layers and / or can be or include a III-V material, a II-VI material, a IV-IV material, some other suitable semiconductor material, or any combination thereof.

[0049] While embodiments utilizing the FEOL TSVs 102 in Figure 1 illustrate the IC chip of Figure 4 , the IC chip of Figure 4 may instead use embodiments of the FEOL TSVs 102 of any one of Figures 3A-3E . Similarly, while embodiments utilizing the embodiments of the semiconductor layer 106 in Figure 1 and the embodiments of the FEOL layer 108 illustrate the IC chip of Figure 4 , the IC chip of Figure 4 may instead use embodiments of the semiconductor layer 106 in Figure 3D and / or can instead use embodiments of the FEOL layer 108 in Figure 3D .

[0050] With reference to Figure 5 , there is provided Figure 1Cross-sectional view 500 of some alternative embodiments of the IC chip, wherein the FEOL TSV 102 provides electrical coupling to the substrate 104. For example, the electrical coupling can be used to ground or otherwise bias the substrate 104. The FEOL TSV 102 is defined by a gap-filling layer 114 and a sidewall spacer structure 502. The gap-filling layer 114 is conductive and extends through the FEOL layer 108 and the semiconductor layer 106 to the substrate 104. The gap-filling layer 114 may be, for example, a metal and / or some other suitable conductive material. The sidewall spacer structure 502 is a dielectric and separates the gap-filling layer 114 from the FEOL layer 108 and the semiconductor layer 106. The sidewall spacer structure 502 may be, for example, silicon oxide, silicon nitride, silicon oxynitride, some other suitable dielectric, or any combination thereof.

[0051] The first and second ILD layers 110 and 112 are located above FEOL TSV 102 and are adjacent to it. Figure 1 Conversely, independent of FEOLTSV 102, contact 116 is located in the first and second ILD layers 110, 112, and BEOL interconnect structure 118 is located above the second ILD layer 112 and contact 116. At least one of contact 116 and BEOL interconnect structure 118 defines a conductive path extending from FEOL TSV 102. This conductive path can, for example, electrically couple FEOL TSV 102 to ground pad 128g or other suitable pad. Alternatively, the conductive path can, for example, electrically couple FEOL TSV 102 to circuitry (not shown) in an internal region of the IC chip. Furthermore, as... Figure 1 As shown, at least one of the contact 116 and the BEOL interconnect structure 118 defines a conductive sealing structure 132.

[0052] refer to Figure 6 Provided Figure 5 The top layout 600 of some embodiments of the IC chip. For example, Figure 5The cross-sectional view 500 can be taken along line C, but other suitable locations are also possible. The conductive sealing structure 132 and the FEOL TSV 102 are located at the peripheral region P of the IC chip. The conductive sealing structure 132 extends in a closed path to surround the FEOL TSV 102 and the internal region I of the IC chip. The closed path is a rectangular ring, but can be a circular ring, a square ring, or other suitable shape. Furthermore, the conductive sealing structure 132 seals the periphery of the IC chip to protect the internal region I of the IC chip. The FEOL TSV 102 is linear and located on one side of the IC chip. In alternative embodiments, the FEOL TSV 102 is located on multiple sides of the IC chip and / or has other suitable shapes. Additionally, the FEOL TSV 102 is located between the conductive sealing structure 132 and the internal region I of the IC chip.

[0053] refer to Figures 7A-7C Provided Figure 5 Cross-sectional views 700A-700C show some different alternative embodiments of the IC chip.

[0054] exist Figure 7A In this structure, FEOL TSV 102 extends from BEOL interconnect structure 118 through both the first and second ILD layers 110 and 112 to substrate 104. Furthermore, FEOL TSV 102 is electrically coupled to BEOL interconnect structure 118 at bottom lead 124b.

[0055] exist Figure 7B In this configuration, the first and second ILD layers 110 and 112 separate the gap-filling layer 114 from the FEOL layer 108 and the semiconductor layer 106. Furthermore, the sidewall spacer structure 502 is omitted, and the FEOL TSV 102 is electrically coupled to the BEOL interconnect structure 118 at the bottom lead 124b.

[0056] exist Figure 7C In this paper, the second ILD layer 112 is omitted, and the space occupied by the second ILD layer 112 is occupied by the first ILD layer 110.

[0057] refer to Figure 8 Provided Figure 5 An enlarged cross-sectional view 800 of some embodiments of an IC chip shows a conductive sealing structure 132 surrounding a FEOL TSV 102 and an internal region I of the IC chip. Furthermore, the FEOL TSV 102 is located on one side of the IC chip and between the conductive sealing structure 132 and the internal region I. In some embodiments, the FEOL TSV 102 is linear when viewed from top to bottom, and / or the conductive sealing structure 132 extends in a closed path to surround the internal region I of the IC chip when viewed from top to bottom. Additionally, in some embodiments, the IC chip has...Figure 6 The top layout is shown. For example, the enlarged cross-sectional view 800 can be along... Figure 6 Line D is cut off in the middle. In an alternative embodiment, the IC chip has some other suitable top layout.

[0058] Internal region I houses a plurality of semiconductor devices 402 interconnected by contact 116 and BEOL interconnect structure 118 to define a circuit. Note that, although not shown, additional pads (e.g., see pad 128) may be present to electrically couple the circuit to external devices and / or circuitry. Internal region I and semiconductor devices 402 may, for example, be as described with respect to Figure 4 As described.

[0059] Despite using Figure 5 An embodiment of FEOL TSV 102 is shown in the figure. Figure 8 IC chips, but Figure 8 IC chips can be used as alternatives. Figures 7A-7C Any of the FEOL TSV 102 embodiments. Similarly, although utilizing Figure 5 Embodiments of semiconductor layer 106 and FEOL layer 108 are shown. Figure 8 IC chips, but Figure 8 IC chips can be used as alternatives. Figure 3D Embodiments of semiconductor layer 106 and / or alternatively using Figure 3D An embodiment of the FEOL layer 108 in the example.

[0060] refer to Figures 9-15 A series of cross-sectional views 900-1500 are provided for some embodiments of a method for forming an IC chip including a FEOL TSV. For example, this method can be used to form... Figure 1 , Figure 2 and Figure 4 Any one or a combination of IC chips or forming some other suitable IC chips.

[0061] like Figure 9As shown in cross-sectional view 900, a semiconductor layer 106 is deposited on substrate 104 at the peripheral region P and the internal region I of the formed IC chip. In some embodiments, the semiconductor layer 106 comprises a multilayer (not shown separately) defining a heterojunction. In some embodiments, the multilayer further defines a 2DEG or DHG along the heterojunction. In some embodiments, the semiconductor layer 106 is or comprises a III-V material. For example, the semiconductor layer 106 may be, for example, gallium nitride (e.g., GaN), gallium arsenide (e.g., GaAs), indium phosphide (InP), some other suitable III-V materials, or any combination thereof. In alternative embodiments, the semiconductor layer 106 is or comprises a II-VI material, a IV-IV material, or some other suitable semiconductor material. In some embodiments, the thickness T of the semiconductor layer 106 is... g It is approximately 45-55kA, approximately 55-65kA, approximately 45-65kA, approximately 58kA, approximately 50kA, or some other suitable value.

[0062] Also through Figure 9 Cross-sectional view 900 shows that a FEOL process is performed to form a plurality of semiconductor devices 402 and a FEOL layer 108. The plurality of semiconductor devices 402 are formed on the semiconductor layer 106 in the inner region I but not in the outer region P. On the other hand, the FEOL layer 108 is formed in both the outer region P and the inner region I. In some embodiments, the outer region P and the inner region I have as follows: Figure 2 The top layout shown is acceptable, but other suitable top layouts are also possible. In some embodiments, the thickness T of the FEOL layer 108 is... f It is approximately 3.5-4.0 kiloangs (kA), approximately 4.0-4.5 kA, approximately 3.5-4.5 kA, or some other suitable value.

[0063] The FEOL layer 108 comprises multiple layers (not shown separately) deposited during the FEOL process. Furthermore, the FEOL layer 108 covers the semiconductor device 402 on the semiconductor layer 106 and, in some embodiments, at least partially defines the semiconductor device 402. The layers constituting the FEOL layer 108 may include, for example, an ILD layer, a pad oxide layer, a pad nitride layer, a CESL, a gate dielectric layer, some other suitable layer, or any combination of the above layers. In some embodiments, the FEOL layer 108 is limited to dielectric oxides and / or other suitable dielectrics.

[0064] Semiconductor device 402 is located between semiconductor layer 106 and FEOL layer 108, and may be, for example, HEMT, MOSHEMT, MISFET, some other suitable type of semiconductor device, or any combination thereof. Furthermore, semiconductor device 402 is partially defined by semiconductor layer 106, and in some embodiments, is partially defined by FEOL layer 108.

[0065] like Figure 10 As shown in cross-sectional view 1000, the FEOL layer 108 and semiconductor layer 106 are patterned to form a trench 1002 at the peripheral region P. The trench 1002 extends through the FEOL layer 108 and semiconductor layer 106 to the substrate 104. In some embodiments, the trench 1002 extends in a closed path to surround the inner region I. For example, the trench 1002 may only be present in the inner region P. Figure 10 The cross-sectional view 1000 is partially shown, and it may have a square ring top layout, a circular ring top layout, or some other suitable top layout extending in a closed path. In some embodiments, the trench 1002 has a... Figure 2 The top layout is the same as that of FEOL TSV 102, while the inner area I has the same top layout as... Figure 2 The top layout shown.

[0066] Patterning to form trench 1002 may include, for example,: 1) forming a mask 1004 over FEOL layer 108; 2) etching FEOL layer 108 and semiconductor layer 106 at appropriate locations using mask 1004 to form trench 1002; and 3) removing mask 1004. However, other suitable patterning processes are also possible. For example, mask 1004 may be a photoresist mask formed by photolithography or some other suitable type of mask. Etching may be performed, for example, by dry etching, but other suitable types of etching are also possible. In some embodiments, etching takes about 25-35 minutes, about 30 minutes, or some other suitable amount of time. As described below, because the etching does not penetrate the ILD and IMD layers subsequently formed over FEOL layer 108, the etching time can be significantly reduced. For example, when etching does not penetrate the ILD and IMD layers, the etching can be about 50% faster or some other suitable percentage.

[0067] like Figure 11As shown in cross-sectional view 1100, a first ILD layer 110 and a second ILD layer 112 are deposited over the FEOL layer 108 and further deposited to line and partially fill the trench 1002. Additionally, the second ILD layer 112 is deposited over the first ILD layer 110. In an alternative embodiment, the first ILD layer 110 and / or the second ILD layer 112 are not deposited. The first ILD layer 110 and the second ILD layer 112 can be deposited sequentially using corresponding deposition processes. Deposition can be performed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), some other suitable deposition process, or any combination thereof.

[0068] In some embodiments, the first ILD layer 110 is a dielectric oxide and / or some other suitable dielectric. Similarly, in some embodiments, the second ILD layer 112 is a dielectric oxide and / or some other suitable dielectric. In some embodiments, the first ILD layer 110 and the second ILD layer 112 are different dielectrics. In some embodiments, the first ILD layer 110 and / or the second ILD layer 112 have lower moisture and / or vapor permeability than the FEOL layer 108 to prevent moisture and / or vapor from entering the FEOL layer 108 from the surrounding environment of the IC chip. Such moisture and / or vapor can corrode and thus damage the semiconductor device 402 (not shown). In some embodiments, the second ILD layer 112 has lower moisture and / or vapor permeability than the first ILD layer 110, and vice versa.

[0069] like Figure 12 As shown in cross-sectional view 1200, an interstitial filling layer 114 is deposited above the second ILD layer 112 and fills the remaining portion of the trench 1002 (see, for example, [reference]). Figure 10 Deposition can be performed, for example, by CVD, PVD, some other suitable deposition process, or any combination thereof.

[0070] In some embodiments, the gap filling layer 114 is or includes a dielectric oxide and / or some other suitable dielectric. In alternative embodiments, the gap filling layer 114 is or includes a conductive material and / or some other suitable material. In some embodiments, the second ILD layer 112 and the gap filling layer 114 are different materials. In some embodiments, the gap filling layer 114 has lower moisture and / or vapor permeability than the FEOL layer 108 to prevent moisture and / or vapor from entering the FEOL layer 108 from the surrounding environment of the IC chip. Such moisture and / or vapor may corrode and thus damage the semiconductor device 402 (not shown). In some embodiments, the gap filling layer 114 has lower moisture and / or vapor permeability than the first and / or second ILD layers 110, 112.

[0071] The gap fill layer 114, along with the first and second ILD layers 110, 112, collectively define the FEOL TSVs 102 in the trench 1002. For example, since formation begins with the Figure 9 last FEOL processing described, the FEOL TSVs 102 can be referred to as “FEOL” TSVs. In some embodiments, the FEOL TSVs 102 have a top layout as shown in Figure 2 but other suitable top layouts are possible. In some embodiments, the FEOL TSVs 102 protect the inner region I. For example, the FEOL TSVs 102 can prevent moisture and / or vapor from entering the peripheral region P and diffusing or otherwise moving to the inner region I. As another example, the FEOL TSVs 102 can prevent cracks caused by a die cutter during singulation of the IC chip from the wafer from propagating from the peripheral region P to the inner region I.

[0072] As seen below, the trench 1002 in which the FEOL TSVs 102 are formed (e.g., see Figure 10 ) can have a small aspect ratio (e.g., Figure 10 the ratio of the height H in Figure 10 to the width W in ) because the trench 1002 is formed prior to deposition of the first and second ILD layers 110, 112 and the IMD layer formed thereafter. Due to the low aspect ratio, the first and second ILD layers 110, 112 and / or the gap fill layer 114 can have a low likelihood of being deposited with voids. Voids would impede the FEOL TSVs 102 from protecting the inner region I from cracks, moisture, vapor, or any combination thereof. Thus, the low likelihood of being deposited with voids can reduce the likelihood of failure of the FEOL TSVs 102 to protect the inner region, which can improve yield.

[0073] Figure 13 As shown in the cross-sectional view 1300 of , planarization is performed on the gap fill layer 114 to remove the gap fill layer 114 from the top of the second ILD layer 112. In addition, the planarization flattens the top surface of the gap fill layer 114. In some embodiments, the planarization also makes the top surface of the gap fill layer 114 coplanar with the top surface of the second ILD layer 112 and / or thins the second ILD layer 112. For example, the planarization can be performed by chemical mechanical polishing (CMP) or some other suitable planarization process.

[0074] Figure 14As shown in cross-sectional view 1400, contacts 116 are formed in the first and second ILD layers 110, 112 and the FEOL layer 108. Sealing contacts 116s are formed at the peripheral region P and between the FEOL TSV 102 and the semiconductor device 402. Furthermore, device contacts 116d are formed at the internal region I of one of the semiconductor devices 402. In an alternative embodiment, the sealing contacts 116s are omitted. Contacts 116 may be, for example, tungsten and / or some other suitable conductive material.

[0075] like Figure 15 As shown in cross-sectional view 1500, a BEOL process is performed to form and electrically couple a BEOL interconnect structure 118 over and to the contact 116. The BEOL interconnect structure 118 includes multiple leads 124 stacked over and electrically coupled to the contact 116, multiple vias 126, and pads 128. In some embodiments, an additional pad (not shown) is present in the inner region I and configured identically to the pad 128. The leads and vias at the peripheral region P are stacked together with the pads 128 and the sealing contacts 116s to define a conductive sealing structure 132 with the sealing contacts 116s. In some embodiments, the conductive sealing structure 132 has as shown in the figure. Figure 2 The top layout shown is acceptable, but other suitable top layouts are also possible. Furthermore, leads and vias at internal region I are stacked with device contacts 116d to define interconnect semiconductor devices 402 and define conductive paths for the circuit.

[0076] Multiple leads 124 and multiple vias 126 are stacked in an IMD layer 120 located on a second ILD layer 112. Furthermore, pads 128 are located in a passivation layer 122 between the IMD layer 120 and a passivation layer 122. The passivation layer 122 is located on the IMD layer 120 and defines pad openings 130 that expose the pads 128. In an alternative embodiment, the pads 128 and / or pad openings 130 are omitted. The IMD layer 120 consists of multiple layers (not shown separately) deposited during the formation of the leads 124 and vias 126, and the passivation layer 122 is deposited after the formation of the leads 124 and vias 126. In some embodiments, the IMD layer 120 is a dielectric oxide and / or some other suitable dielectric. In some embodiments, the second ILD layer 112 and the IMD layer 120 are different dielectrics. The first and second ILD layers 110, 112 and the IMD layer 120 have a large combined thickness T. c In some embodiments, a larger thickness T c It is approximately 120-140kA, approximately 120-130kA, approximately 130-140kA, approximately 125kA, approximately 126kA, or some other suitable value.

[0077] For example, through comparison Figure 10With Figure 15 As seen, prior to depositing the first and second ILD layers 110, 112 (see, e.g., Figure 15 ) and the IMD layer 120 (see, e.g., Figure 15 ), an etch is performed through the FEOL layers 108 and the semiconductor layer 106 to form the trench 1002 (see, e.g., Figure 10 ). As such, the etch does not extend through the first and second ILD layers 110, 112 and the IMD layer 120. Moreover, because the first and second ILD layers 110, 112 and the IMD layer 120 have a large combined thickness T c , if the etch extended through the first and second ILD layers 110, 112 and the IMD layer 120, the etch would have a large etch depth. However, because the etch does not extend through the first and second ILD layers 110, 112 and the IMD layer 120, the etch has a small etch depth.

[0078] Because the etch has a small etch depth, the etch takes a small amount of time and has a high production rate for batch production. For example, when not etching through the first and second ILD layers 110, 112 and the IMD layer 120, the etch can be about 50% or some other suitable percentage faster. Moreover, because the etch has a small etch depth, the etch can be performed with a single photoresist mask (e.g., Figure 10 1004) formed by photolithography. Because photolithography is expensive, using a single photoresist mask can result in low cost. Moreover, because the etch has a small etch depth, the trench 1002 can have a small aspect ratio (e.g., Figure 10 the ratio of the height H in Figure 10 to the width W in ). As such, the FEOL TSV 102 can be formed with a lower likelihood of voids. This can reduce the likelihood of FEOL TSV 102 failure to protect the internal region, which can improve yield.

[0079] Figures 9-15 As seen by reviewing , forming the FEOL TSV 102 at the end of the FEOL processing instead of at the end of the BEOL processing does not change the film scheme of the internal region I. In other words, the film scheme of the internal region I is the same whether the FEOL TSV 102 is formed or the BEOL TSV is formed. The film scheme can correspond, for example, to the layout of the first and second ILD layers 110, 112 and the IMD layer 120. Because the film scheme at the internal region I is not changed, the FEOL TSV 102 can replace the BEOL TSV at low cost.

[0080] Figures 9-15 Although described with reference to a method, Figures 9-15The illustrated structure is not limited to this method, but can stand alone from this method. Although Figures 9-15 are described as a series of acts, it is to be understood that the order of the acts can be changed. For example, Figures 9-15 are shown and described as a particular set of acts, but other embodiments can omit some acts shown and / or described herein. Additionally, acts not shown and / or described herein can be included in other embodiments.

[0081] Referring to Figure 16 , a block diagram 1600 of some embodiments of a method of Figures 9-15 is provided.

[0082] At 1602, a semiconductor layer is deposited over a substrate. For example, see Figure 9 .

[0083] At 1604, a semiconductor device and a FEOL layer are formed over the semiconductor layer, wherein the semiconductor device is located between the semiconductor layer and the FEOL layer. For example, see Figure 9 .

[0084] At 1606, the FEOL layer and the semiconductor layer are patterned to form a trench extending through the FEOL layer and the semiconductor layer to the substrate, wherein the trench surrounds the semiconductor device. For example, see Figure 10 .

[0085] At 1608, a first ILD layer is deposited over the FEOL layer and further lines and partially fills the trench. For example, see Figure 11 .

[0086] At 1610, a second ILD layer is deposited over the first ILD layer and further lines and partially fills the trench. For example, see Figure 11 .

[0087] At 1612, a gap fill layer is deposited over the second ILD layer and fills a remaining portion of the trench. For example, see Figure 12 .

[0088] At 1614, planarization is performed on the gap fill layer to remove the gap fill layer from a top of the second ILD layer. For example, see Figure 13 .

[0089] At 1616, a contact is formed in the first and second ILD layers, wherein the contact includes a sealed contact laterally located between the trench and the semiconductor device. For example, see Figure 14 .

[0090] At 1618, a BEOL interconnect structure is formed over and electrically coupled with the contacts, where the BEOL interconnect structure includes vias and wires stacked in the IMD layers and defining, along with the sealed contacts, electrically conductive sealed structures. See, e.g., Figure 15 .

[0091] Although the block diagram 1600 is illustrated and described herein as a series of actions or events, it will be understood that the order of these steps or events shown is not to be construed as a limitation. Figure 16 For example, some steps can occur in different orders and / or concurrently with other actions or events besides those shown and / or described herein. In addition, not all illustrated steps can be required to implement one or more aspects or embodiments described herein, and one or more steps shown can be performed in one or more separate actions and / or stages.

[0092] Referring to Figure 17 and Figure 18 , cross-sectional views 1700, 1800 are provided of some alternative embodiments of IC chips of Figure 12 and Figure 13 , respectively. Figure 17 Corresponding to Figure 12 , some alternative embodiments of IC chips are shown during deposition of the gap fill layer 114. Figure 18 Corresponding to Figure 11 , some alternative embodiments of IC chips are shown during planarization.

[0093] In both Figure 17 and Figure 18 , the first and second ILD layers 110, 112 and the gap fill layer 114 have less uniform dimensions and also have curved edges and sidewalls. In addition, the semiconductor layer 106 includes multiple layers (e.g., 106a and 106b) and the FEOL layer 108 includes multiple layers (e.g., 108a and 108b). For example, the first layer 106a of the semiconductor layer 106 can be or include gallium nitride and the second layer 106b of the semiconductor layer 106 can be or include aluminum gallium nitride, or vice versa. However, other suitable materials are possible in addition to the materials in the examples.

[0094] Referring to Figures 19-25 , a series of cross-sectional views 1900-2500 are provided of a method for forming an IC chip including a FEOL TSV that provides electrical coupling with a substrate. For example, the method can be employed to form an IC chip of any one or combination of Figure 5 , Figure 6 and Figure 8 or to form some other suitable IC chip.

[0095] As Figure 19 shown in cross-sectional view 1900, the actions described with respect to Figure 9 and Figure 10 are performed. As described with respect to Figure 9 , a semiconductor layer 106 is deposited over the substrate 104 at the peripheral region P and the inner region I. Further, as described with respect to Figure 9 , FEOL processing is performed to form a plurality of semiconductor devices 402 and a FEOL layer 108. Then as shown with respect to Figure 10 , the FEOL layer 108 and the semiconductor layer 106 are patterned to form a trench 1002 at the peripheral region P. The trench 1002 extends through the FEOL layer 108 and the semiconductor layer 106 to the substrate. In some embodiments, the trench 1002 is on a single side of the inner region I and / or is linear when viewed from above. In alternative embodiments, the trench 1002 is on multiple sides of the inner region I and / or has other suitable shapes when viewed from above. In some embodiments, the trench 1002 has the same top layout as the FEOL TS V 102 in Figure 6 , while the inner region I has a top layout as shown in Figure 6 .

[0096] As shown in cross-sectional view 2000 of Figure 20 , a spacer layer 2002 is deposited over the FEOL layer 108 and further lines and partially fills the trench 1002. The spacer layer 2002 may, for example, be or include silicon oxide, silicon nitride, silicon oxynitride, some other suitable dielectric, or any combination thereof.

[0097] As shown in cross-sectional view 2100 of Figure 21 , the spacer layer 2002 is etched back (e.g., see Figure 20 ) to form sidewall spacer structures 502 on sidewalls of the trench 1002 (e.g., see Figure 20 ) and expose the substrate 104 at a bottom of the trench 1002. The etching back removes the spacer layer 2002 from a top of the FEOL layer 108 and further removes a horizontal section of the spacer layer 2002 at the bottom of the trench 1002.

[0098] As shown in cross-sectional view 2200 of Figure 22 , a gap fill layer 114 is deposited over the FEOL layer 108 and fills a remaining portion of the trench 1002 (e.g., see Figure 21The gap-filling layer 114 is conductive and electrically coupled to the substrate 104. The gap-filling layer 114 may be, for example, a metal and / or some other suitable conductive material. Deposition may be performed, for example, by CVD, PVD, electroless plating, electroplating, some other suitable deposition process, or any combination thereof.

[0099] The gap-filling layer 114 and the sidewall spacer structure 502 together define the FEOL TSV 102 in the trench 1002. In some embodiments, the FEOL TSV 102 has as follows Figure 6 The top layout shown is correct, but other suitable top layouts are also possible. In some embodiments, as seen below, the FEOL TSV 102 provides electrical coupling between the substrate 104 and the subsequently formed BEOL interconnect structure. This electrical coupling can be used, for example, to electrically couple the substrate 104 to ground or to circuitry in the inner region I.

[0100] like Figure 23 As shown in cross-sectional view 2300, planarization is performed on the gap filler layer 114 to remove the gap filler layer 114 from the top of the FEOL layer 108. Furthermore, planarization flattens the top surface of the gap filler layer 114. In some embodiments, planarization also makes the top surface of the gap filler layer 114 coplanar with the top surface of the FEOL layer 108 and / or thins the FEOL layer 108. For example, planarization can be performed by CMP or some other suitable planarization process.

[0101] like Figure 24 As shown in cross-sectional view 2400, the first ILD layer 110 and the second ILD layer 112 are deposited above the FEOL layer 108, as per the description. Figure 11 As stated above. However, with Figure 11 Conversely, the first and second ILD layers 110 and 112 are independent of FEOL TSV 102.

[0102] like Figure 25 As shown in cross-sectional view 2500, contacts 116 are formed in the first and second ILD layers 110, 112 and the FEOL layer 108. Sealing contacts 116s are formed at the peripheral region P. In an alternative embodiment, the sealing contacts 116s are omitted. At the peripheral region P and between the sealing contacts 116s and the inner region I, TSV contacts 116v are formed on the FEOL TSV 102. Device contacts 116d are formed at the inner region I of one of the semiconductor devices 402. Contacts 116 may be, for example, tungsten and / or some other suitable conductive material.

[0103] As shown in the cross-sectional view of Figure 2600, a BEOL process is performed to form a BEOL interconnect structure 118 on the contact 116 and electrically couple it thereto, as per [reference to...].Figure 15 The BEOL interconnect structure 118 includes multiple leads 124, multiple vias 126, and multiple pads 128 stacked above and electrically coupled to contacts 116. The leads and vias at the peripheral region P are stacked together with the sealing pads 128 and sealing contacts 116s to define a conductive sealing structure 132. In some embodiments, the conductive sealing structure 132 has, as described above... Figure 6 The top layout shown is shown, but other suitable top layouts are also possible. Additional leads and vias at the peripheral region P are stacked with TSV contact 116v to define a conductive path from FEOL TSV 102 to ground pad 128g or some other suitable pad. Leads and vias at the internal region I are stacked with device contact 116d to define interconnect semiconductor device 402 and define a conductive path for the circuit.

[0104] Multiple leads 124 and multiple vias 126 are stacked in an IMD layer 120 located on a second ILD layer 112. Furthermore, multiple pads 128 are located in a passivation layer 122 between the IMD layer 120 and a passivation layer 122. The passivation layer 122 is located on the IMD layer 120 and defines pad openings 130 that expose the pads 128. In an alternative embodiment, the sealing pads 128s and / or the corresponding pad openings are omitted. The first and second ILD layers 110, 112 and the IMD layer 120 have a large combined thickness T. c In some embodiments, a larger thickness T c It is approximately 120-140kA, approximately 120-130kA, approximately 130-140kA, approximately 125kA, approximately 126kA, or some other suitable value.

[0105] For example, through comparison Figure 19 and Figure 26 As seen, in the deposition of the first and second ILD layers 110, 112 (e.g., see...) Figure 26 ) and IMD layer 120 (for example, see Figure 26 Prior to this, etching is performed through the FEOL layer 108 and the semiconductor layer 106 to form the trench 1002 (see, for example, see...). Figure 19 Thus, the etching does not extend through the first and second ILD layers 110, 112 and the IMD layer 120. Therefore, the etching has a small etch depth. Because of the small etch depth, the etching takes less time and results in high productivity for mass production. Furthermore, a single photoresist mask formed by photolithography can be utilized (e.g., Figure 19 The etching is performed using 1004 (a type of 4004), which reduces costs. Furthermore, the trenches can have a smaller aspect ratio (e.g., 1004). Figure 19 The height H in the middle and Figure 19the ratio of the width W in the FEOL TSV 102 is small), which reduces the likelihood of voids forming in the FEOL TSV 102. Voids increase the resistance of the FEOL TSV 102, and thus reduce the performance of the FEOL TSV 102. Thus, the low likelihood of the FEOL TSV 102 forming voids can reduce the likelihood of the FEOL TSV 102 falling outside of design specifications, which can improve yield.

[0106] By way of review Figures 19-26 It can be seen that forming the FEOL TSV 102 at the end of the FEOL processing, rather than at the end of the BEOL processing, does not change the film scheme of the inner region I. In other words, the film scheme of the inner region I is the same whether the FEOL TSV 102 is formed or the BEOL TSV is formed. In this way, the FEOL TSV 102 can replace the BEOL TSV at a low cost.

[0107] Although the method is described with reference to Figures 19-26 it should be understood that Figures 19-26 the structure shown is not limited to the method, but can be separate from the method. Although Figures 19-26 is described as a series of acts, it should be understood that the order of the acts can change in other embodiments. Although Figures 19-26 is shown and described as a particular set of acts, some of the acts shown and / or described can be omitted in other embodiments. Further, acts not shown and / or described can be included in other embodiments.

[0108] With reference to Figure 27 a block diagram 2700 of some embodiments of the method of Figures 19-26 is provided.

[0109] At 2702, a semiconductor layer is deposited over a substrate. For example, see Figure 19 .

[0110] At 2704, a semiconductor device and a FEOL layer are formed over the semiconductor layer, where the semiconductor device is between the semiconductor layer and the FEOL layer. For example, see Figure 19 .

[0111] At 2706, the FEOL layer and the semiconductor layer are patterned to form a trench that extends through the FEOL layer and the semiconductor layer to the substrate. For example, see Figure 19 .

[0112] At 2708, a sidewall spacer structure is formed that partially fills the trench on sidewalls of the trench. For example, see Figure 20 and Figure 21 .

[0113] At 2710, a gap-filling layer is deposited over the FEOL layer and fills the remainder of the trench, wherein the gap-filling layer is conductive, and wherein the sidewall spacer structure and the gap-filling layer define the FEOL TSV. See, for example, [link to relevant documentation]. Figure 22 .

[0114] At 2712, planarization is performed on the gap fill layer to remove it from the top of the FEOL layer. See, for example, [link to example]. Figure 23 .

[0115] At position 2714, the first ILD layer is deposited above the FEOL layer and the FEOL TSV. See, for example. Figure 24 .

[0116] At position 2716, a second ILD layer is deposited above the first ILD layer. See, for example, [link to example]. Figure 24 .

[0117] At 2718, contacts are formed in the first and second ILD layers, wherein the contacts include sealing contacts and TSV contacts, and wherein the TSV contacts are located on the FEOL TSV and between the sealing contacts and the semiconductor device. See, for example. Figure 25 .

[0118] At 2820, a BEOL interconnect structure is formed above and electrically coupled to the contact, wherein the BEOL interconnect structure includes leads and vias stacked in the IMD layer and defining a conductive sealing structure together with the sealing contact. See, for example, [link to example]. Figure 26 .

[0119] Although this article will Figure 27 Block diagram 2700 illustrates and describes a series of actions or events; however, it should be understood that the order of these steps or events shown should not be interpreted as limiting. For example, some steps may occur in a different order and / or simultaneously with other actions or events besides those shown and / or described herein. Furthermore, it is not required that all actions shown are used to implement one or more aspects or embodiments described herein, and one or more actions shown herein may be performed in one or more separate actions and / or phases.

[0120] In some embodiments, the disclosure provides an IC chip comprising: a substrate; a semiconductor layer on the substrate; a FEOL layer on the semiconductor layer; a through via extending through the FEOL layer and the semiconductor layer to the substrate at a periphery of the IC chip; and an alternating stack of leads and vias over the through via. In some embodiments, the IC chip further comprises an ILD layer on the FEOL layer and under the alternating stack, wherein the ILD layer has a portion extending through the semiconductor layer to the substrate and partially defining the through via. In some embodiments, the through via is dielectric. In some embodiments, the IC chip further comprises a semiconductor device on the semiconductor layer, wherein the through via extends in a closed path along the periphery of the IC chip to surround the semiconductor device. In some embodiments, the alternating stack defines a conductive seal extending in a closed path along the periphery of the IC chip, wherein the through via is between an outermost sidewall of the IC chip and the conductive seal. In some embodiments, the IC chip further comprises an ILD layer on the FEOL layer and the through via and also under the alternating stack, wherein the ILD layer is independent of the through via. In some embodiments, the through via is conductive. In some embodiments, a top layout of the through via is linear and on a single side of the IC chip at the periphery of the IC chip. In some embodiments, the IC chip further comprises: a pad over the alternating stack; and a contact on the through via; wherein the alternating stack and the contact define a conductive path from the through via to the pad.

[0121] In some embodiments, the disclosure provides another IC chip comprising: a substrate; a semiconductor layer on the substrate; a semiconductor device on the semiconductor layer; an interconnect structure on the semiconductor device; a contact extending from the interconnect structure to the semiconductor device; and a through via extending through the semiconductor layer to the substrate and having a top surface that is approximately flush with a top surface of the contact or recessed relative to the top surface of the contact. In some embodiments, the interconnect structure comprises a plurality of leads and a plurality of vias defining a conductive seal, wherein the conductive seal extends in a closed path around the semiconductor device and the through via at a periphery of the IC chip. In some embodiments, the IC chip further comprises: a first oxide layer on the semiconductor device; and a second oxide layer on the first oxide layer and under the interconnect structure, wherein the first and second oxide layers are different oxides, and wherein the contact and the through via extend through the first and second oxide layers. In some embodiments, the through via comprises a conductive gap fill layer, wherein the IC chip further comprises a second contact on the conductive gap fill layer and directly contacting the conductive gap fill layer. In some embodiments, the semiconductor layer comprises a III-V material, wherein the substrate comprises silicon.

[0122] In some embodiments, the disclosure provides a method for forming an IC chip, the method comprising: depositing a semiconductor layer over a substrate; forming a semiconductor device on the semiconductor layer; forming a FEOL layer over the semiconductor device; patterning the FEOL layer and the semiconductor layer to form a trench at a periphery of the IC chip that extends through the FEOL layer and the semiconductor layer to the substrate; filling the trench with a dielectric and / or conductive material to form a via; and forming an IMD layer over the via and the FEOL layer, while forming an alternating stack of leads and vias in the IMD layer. In some embodiments, the method further comprises forming a conductive contact in the FEOL layer between the filling and the formation of the IMD layer. In some embodiments, the patterning is performed by a single lithography / etch process. In some embodiments, the filling comprises: depositing an ILD layer on the FEOL layer, and further lining and partially filling the trench; depositing a gap fill layer on the ILD layer, and further filling a remaining portion of the trench on the ILD layer; and then performing a planarization on the gap fill layer to remove the gap fill layer from a top of the ILD layer. In some embodiments, the filling comprises: forming a sidewall spacer structure that partially fills sidewalls of the trench on the sidewalls; depositing a gap fill layer on the FEOL layer, and further filling a remaining portion of the trench, wherein the gap fill layer is conductive; and performing a planarization on the gap fill layer to remove the gap fill layer from a top of the FEOL layer. In some embodiments, the method further comprises: depositing a first ILD layer that covers the via; and depositing a second ILD layer that comprises a different material than the first ILD layer and covers the first ILD layer, wherein the IMD layer is deposited over the second ILD layer, and wherein the leads and vias are confined to the IMD layer.

[0123] According to one embodiment of the present application, an integrated circuit (IC) chip is provided, comprising: a substrate; a semiconductor layer on the substrate; a front-end-of-line (FEOL) layer on the semiconductor layer; a through-hole extending through the FEOL layer and the semiconductor layer to the substrate at a periphery of the IC chip; and an alternating stack of wires and vias over the through-hole. In some embodiments, the integrated circuit chip further comprises: an inter-layer dielectric (ILD) layer on the FEOL layer and under the alternating stack, wherein the ILD layer has a portion extending through the semiconductor layer to the substrate and partially defining the through-hole. In some embodiments, the through-hole is dielectric. In some embodiments, the integrated circuit chip further comprises: a semiconductor device on the semiconductor layer, wherein the through-hole extends in a closed path around the semiconductor device along the periphery of the IC chip. In some embodiments, the alternating stack defines a conductive seal structure extending in a closed path around the semiconductor device along the periphery of the IC chip, and wherein the through-hole is between an outermost sidewall of the IC chip and the conductive seal structure. In some embodiments, the IC chip further comprises: an inter-layer dielectric (ILD) layer on the FEOL layer and the through-hole and also under the alternating stack, wherein the ILD layer is independent of the through-hole. In some embodiments, the through-hole is conductive. In some embodiments, a top layout of the through-hole is linear and is on a single side of the IC chip at the periphery of the IC chip. In some embodiments, the IC chip further comprises: a pad over the alternating stack; and a contact on the through-hole; wherein the alternating stack and the contact define a conductive path from the through-hole to the pad.

[0124] According to another embodiment of the present application, an integrated circuit (IC) chip is provided, comprising: a substrate; a semiconductor layer on the substrate; a semiconductor device on the semiconductor layer; an interconnect structure on the semiconductor device; a contact extending from the interconnect structure to the semiconductor device; and a through-hole extending through the semiconductor layer to the substrate and having a top surface that is approximately flush with or recessed relative to a top surface of the contact. In some embodiments, the interconnect structure comprises a plurality of wires and a plurality of vias defining a conductive seal structure, and wherein the conductive seal structure extends in a closed path around the semiconductor device and the through-hole along a periphery of the IC chip. In some embodiments, the IC chip further comprises: a first oxide layer on the semiconductor device; and a second oxide layer on the first oxide layer and under the interconnect structure, wherein the first and second oxide layers are different oxides, and wherein the contact and the through-hole extend through the first and second oxide layers. In some embodiments, the through-hole comprises a conductive gap fill layer, and wherein the IC chip further comprises: a second contact on the conductive gap fill layer and directly contacting the conductive gap fill layer. In some embodiments, the semiconductor layer comprises a III-V material, and wherein the substrate comprises silicon.

[0125] According to yet another embodiment of the present application, a method for forming an integrated circuit (IC) chip is provided, the method comprising: depositing a semiconductor layer over a substrate; forming a semiconductor device on the semiconductor layer; forming a front end of line (FEOL) layer over the semiconductor device; patterning the FEOL layer and the semiconductor layer to form a trench at a periphery of the IC chip that extends through the FEOL layer and the semiconductor layer to the substrate; filling the trench with a dielectric and / or conductive material to form a via; and forming an intermetal dielectric (IMD) layer over the via and the FEOL layer, while forming an alternating stack of wires and vias in the IMD layer. In some embodiments, the method for forming an integrated circuit chip further comprises: forming a conductive contact in the FEOL layer between the filling and the formation of the IMD layer. In some embodiments, the patterning is performed by a single lithography / etch process. In some embodiments, the filling comprises: depositing an interlayer dielectric (ILD) layer on the FEOL layer, and further lining and partially filling the trench; depositing a gap fill layer on the ILD layer, and further filling a remaining portion of the trench above the ILD layer; and performing a planarization on the gap fill layer to remove the gap fill layer from a top of the ILD layer. In some embodiments, the filling comprises: forming a sidewall spacer structure that partially fills sidewalls of the trench on the sidewalls; depositing a gap fill layer on the FEOL layer, and further filling a remaining portion of the trench, wherein the gap fill layer is conductive; and performing a planarization on the gap fill layer to remove the gap fill layer from a top of the FEOL layer. In some embodiments, the method for forming an integrated circuit (IC) chip further comprises: depositing a first interlayer dielectric (ILD) layer that covers the via; and depositing a second ILD layer that comprises a different material than the first ILD layer and covers the first ILD layer, wherein the IMD layer is deposited over the second ILD layer, and wherein the wires and vias are confined to the IMD layer.

[0126] The components of the several embodiments discussed above are to better enable those skilled in the art to understand the various embodiments of the present application. Those skilled in the art should understand that other processes and structures can readily be devised which will be functionally equivalent to those described herein without departing from the spirit of the present application. Those skilled in the art should appreciate that the present application can be used with any number of electrical devices, and that the present application is applicable to an electrical device of any size and shape.

Claims

1. An integrated circuit chip comprising: a substrate; a semiconductor layer on the substrate; a front-of-line layer on the semiconductor layer; a through via extending through the front-of-line layer and the semiconductor layer to the substrate at a periphery of the integrated circuit chip; and an alternating stack of leads and vias over the through via; an interlayer dielectric layer on the front-of-line layer and under the alternating stack, wherein the interlayer dielectric layer has a portion extending through the semiconductor layer to the substrate and partially defining the through via; wherein the alternating stack and a sealing contact under the alternating stack define a conductive seal structure, wherein the conductive seal structure and the through via extend in a closed path along a periphery of the integrated circuit chip, and wherein the through via is between an outermost sidewall of the integrated circuit chip and the conductive seal structure, wherein the interlayer dielectric layer defining the through via has a lower moisture and / or vapor permeability than the front-of-line layer, wherein the sealing contact at the periphery of the integrated circuit chip penetrates the interlayer dielectric layer extending out of the through via, and the sealing contact laterally overlaps the through via. The front-of-line layer comprises multiple layers.

2. The integrated circuit chip of claim 1, wherein, The through via is dielectric.

3. The integrated circuit chip of claim 1, wherein, 4. The integrated circuit chip of claim 1, further comprising: a semiconductor device on the semiconductor layer, wherein the through via extends in a closed path along a periphery of the integrated circuit chip to surround the semiconductor device. The semiconductor layer consists of multiple layers defining a two-dimensional electron gas or a two-dimensional hole gas along a heterojunction.

5. The integrated circuit chip of claim 1, wherein, The interlayer dielectric layer is independent of the through via.

6. The integrated circuit chip of claim 1, wherein, The through via is conductive.

7. The integrated circuit chip of claim 1, wherein, A top layout of the through via is linear and is on a single side of the integrated circuit chip at a periphery of the integrated circuit chip.

8. The integrated circuit chip of claim 1, wherein, 9. The integrated circuit chip of claim 1, further comprising: a pad over the alternating stack; and a contact on the through via; wherein the alternating stack and the contact define a conductive path from the through via to the pad.

10. An integrated circuit chip comprising: a substrate; a semiconductor layer on the substrate; a semiconductor device on the semiconductor layer; an interconnect structure on the semiconductor device; a sealing contact extending from the interconnect structure to the semiconductor device; a through via extending through the semiconductor layer to the substrate and having a top surface that is approximately flush with or recessed relative to a top surface of the sealing contact; a front-of-line layer on the semiconductor layer; an interlayer dielectric layer on the front-of-line layer and under the interconnect structure, wherein the interlayer dielectric layer has a portion extending through the semiconductor layer to the substrate and partially defining the through via; wherein the interconnect structure comprises a plurality of leads and a plurality of vias, the sealing contact, the plurality of leads, and the plurality of vias define a conductive seal structure, ​ ​ ​ and wherein the conductive seal structure and the through via extend in a closed path around the semiconductor device at a periphery of the integrated circuit chip, the through via being located between an outermost sidewall of the integrated circuit chip and the conductive seal structure, wherein the interlayer dielectric layer defining the through via has a lower moisture and / or vapor permeability than the front end of line layer, wherein the seal contact located at a periphery of the integrated circuit chip penetrates through the interlayer dielectric layer extending out of the through via, and the seal contact laterally overlaps the through via.

11. The integrated circuit chip of claim 10, wherein, The semiconductor layer has a thickness in a range of 45-55 kA.

12. The integrated circuit chip of claim 10, the interlayer dielectric layer comprising: a first oxide layer located on the front end of line layer; and a second oxide layer located on the first oxide layer and under the interconnect structure, wherein the first and second oxide layers are different oxides, and wherein the seal contact and the through via extend through the first and second oxide layers. The through via includes a conductive gap fill layer, and wherein the integrated circuit chip further comprises:

13. The integrated circuit chip of claim 10, wherein, a second contact located on and directly contacting the conductive gap fill layer. The semiconductor layer includes a III-V material, and wherein the substrate includes silicon.

14. The integrated circuit chip of claim 10, wherein, 15. A method for forming an integrated circuit chip, the method comprising: depositing a semiconductor layer over a substrate; forming a semiconductor device on the semiconductor layer; forming a front end of line layer over the semiconductor device; patterning the front end of line layer and the semiconductor layer to form a trench extending through the front end of line layer and the semiconductor layer to the substrate at a periphery of the integrated circuit chip; filling the trench with a dielectric and / or conductive material to form a through via; and forming an intermetal dielectric layer over the through via and the front end of line layer while forming an alternating stack of leads and vias in the intermetal dielectric layer; the filling comprising: depositing an interlayer dielectric layer on the front end of line layer and further lining and partially filling the trench; wherein the alternating stack and a conductive seal contact located under the alternating stack define a conductive seal structure, the conductive seal contact penetrating through the interlayer dielectric layer extending out of the trench being formed after depositing the interlayer dielectric layer, the conductive seal contact being located at a periphery of the integrated circuit chip and laterally overlapping the through via, wherein the conductive seal structure and the through via extend in a closed path along a periphery of the integrated circuit chip, and wherein the through via is located between an outermost sidewall of the integrated circuit chip and the conductive seal structure, wherein the interlayer dielectric layer defining the through via has a lower moisture and / or vapor permeability than the front end of line layer.

16. The method of claim 15, further comprising: forming the conductive seal contact in the front end of line layer between the filling and the forming of the intermetal dielectric layer. ​ 17. The method of claim 15, wherein, The patterning is performed by a single lithography / etching process.

18. The method of claim 15, wherein, The filling comprises: depositing a gap fill layer on the interlayer dielectric layer and further filling a remaining portion of the trench above the interlayer dielectric layer; and performing planarization on the gap fill layer to remove the gap fill layer from a top of the interlayer dielectric layer.

19. The method of claim 15, wherein, The semiconductor layer has a thickness in the range of 45-55 kA.

20. The method of claim 19, wherein, The semiconductor layer comprises a III-V material, and wherein the substrate comprises silicon.

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