Semiconductor Structure, Semiconductor Device and Method for Manufacturing the Same

Abstract

The structure includes: a core substrate attached to a first side of a redistribution structure, wherein the first redistribution structure includes a first conductive component and a first dielectric layer, wherein each core substrate includes conductive pillars, and the conductive pillars of the core substrate physically and electrically contact the first conductive component; a sealant extending over the first side of the redistribution structure, wherein the sealant extends along the sidewalls of each core substrate; and an integrated device package connected to a second side of the first redistribution structure. Embodiments of the present application also relate to semiconductor structures, semiconductor devices, and methods of manufacturing the same.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures, semiconductor devices, and methods of manufacturing the same. Background Art

[0002] The semiconductor industry continuously improves the integration density of individual electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum component size, which allows more components (and thus more functions) to be integrated into a given area. Integrated circuits with high functionality require many input / output pads. However, for applications where miniaturization is important, small packages may be required.

[0003] With the growing demand for shrinking electronic devices, there has been a need for smaller and more innovative semiconductor die packaging technologies. An example of such a packaging system is the Package-on-Package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology is generally capable of producing semiconductor devices with enhanced functionality and small footprint on a printed circuit board (PCB). Summary of the Invention

[0004] Some embodiments of the present application provide a semiconductor device, comprising: a first interconnect structure including conductive pillars located on a first side of the first interconnect structure; a second interconnect structure including conductive pillars located on a first side of the second interconnect structure, wherein the second interconnect structure is laterally adjacent to the first interconnect structure; an underfill material extending above the first side of the first interconnect structure, above the first side of the second interconnect structure, and between the first interconnect structure and the second interconnect structure; a first redistribution structure extending above the first side of the first interconnect structure and above the first side of the second interconnect structure, wherein the first redistribution structure is electrically connected to the conductive pillars of the first interconnect structure and the conductive pillars of the second interconnect structure; and an integrated device package attached to the first redistribution structure.

[0005] Some other embodiments of the present application provide a semiconductor structure, comprising: a plurality of core substrates attached to a first side of a first redistribution structure, wherein the first redistribution structure includes a plurality of first conductive components and a plurality of first dielectric layers, wherein each core substrate of the plurality of core substrates includes a conductive pillar, and wherein the conductive pillars of the plurality of core substrates physically and electrically contact a first conductive component of the plurality of first conductive components; a sealant extending above the first side of the first redistribution structure, wherein the sealant extends along sidewalls of each core substrate of the plurality of core substrates; and an integrated device package connected to a second side of the first redistribution structure.

[0006] Some further embodiments of the present application provide a method of manufacturing a semiconductor device, including: attaching an interconnect structure to a carrier, wherein each of the interconnect structures includes a conductive pillar; forming a sealant over the interconnect structure, wherein the sealant extends between adjacent ones of the interconnect structures; performing a planarization process on the sealant to expose the conductive pillars, wherein after performing the planarization process, the sealant and the conductive pillars have coplanar surfaces; and forming a first redistribution layer over the sealant and the conductive pillars, wherein a bottom redistribution layer of the first redistribution layer is electrically connected to the conductive pillars. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 A cross-sectional view of an interconnect structure in accordance with some embodiments is shown.

[0009] Figure 2A , Figure 2B and Figure 2C A cross-sectional view and a plan view of an intermediate step of forming a structure on a carrier substrate in accordance with some embodiments are shown.

[0010] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Figure 9 A cross-sectional view of an intermediate step of forming a package structure in accordance with some embodiments is shown.

[0011] Figure 10 A plan view of an intermediate step of forming a package structure in accordance with some embodiments is shown.

[0012] Figure 11 A cross-sectional view of an intermediate step of forming a package structure in accordance with some embodiments is shown.

[0013] Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 and Figure 18 A cross-sectional view of an intermediate step of forming a package structure in accordance with some embodiments is shown.

[0014] Figure 19A cross-sectional view showing an intermediate step of forming a packaging structure according to some embodiments. Detailed Description

[0015] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first component and the second component are in direct contact, and may also include embodiments where additional components may be formed between the first component and the second component such that the first component and the second component are not in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Moreover, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientation shown in the figures, the spatially relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0017] In the present invention, various aspects of a packaging structure and its formation are described. The techniques described herein allow for the formation of a packaging structure having multiple interconnect structures with reduced warpage, which can improve the joints of components that attach a device (e.g., an integrated circuit package) to the packaging structure. The techniques described herein can reduce warpage or cracks, particularly when multiple interconnects or integrated circuit dies are attached to a redistribution structure. Reducing the stress within the package in this manner can improve performance and yield. One or more redistribution structures can be formed above the multiple interconnect structures and electrically connected to the interconnect structures through conductive pillars passing through the interconnect structures. This can allow for improved planarity of the redistribution structures. A second redistribution structure including fine conductive components can be formed, which can allow for improved device performance. In addition, the techniques described herein can reduce the cost or processing time of the packaging structure.

[0018] Figure 1 An exemplary interconnect structure 100 is shown according to some embodiments. It can be in a packaging structure 200 (see Figure 9)One or more interconnect structures 100 are incorporated therein to provide electrical wiring and structural stability for the encapsulation structure 200. In some embodiments, the interconnect structure 100 can be, for example, an interposer or a “semi-finished substrate” and can be without active devices. The interconnect structure 100 can have a thickness between about 200 μm and about 3000 μm, but other thicknesses are possible.

[0019] In some embodiments, the interconnect structure 100 can include wiring layers (e.g., wiring structures 112 and 113) formed on a core substrate 102. The core substrate 102 can include materials such as an Ajinomoto build-up film (ABF), pre-impregnated composite fiber (“prepreg”) material, epoxy resin, molding compound, epoxy molding compound, glass fiber reinforced resin material, printed circuit board (PCB) material, silica filler, polymer material, polyimide material, paper, glass fiber, non-woven glass fabric, glass, ceramic, other laminate, etc. or combinations thereof. In some embodiments, the core substrate can be a copper-clad laminate (CCL) substrate, etc. The core substrate 102 can have a thickness between about 30 μm and about 2000 μm, but other thicknesses are possible.

[0020] The interconnect structure 100 can have one or more wiring structures 112 / 113 formed on each side of the core substrate 102 and vias 110 extending through the core substrate 102. The wiring structures 112 / 113 and the vias 110 provide electrical wiring and interconnection. The vias 110 can, for example, interconnect the wiring structure 112 and the wiring structure 113. Each of the wiring structures 112 / 113 can include one or more wiring layers 108 / 109 and one or more dielectric layers 118 / 119. In some embodiments, the wiring layer 108 / 109 and / or the vias 110 can include one or more layers of copper, nickel, aluminum, other conductive materials, etc. or combinations thereof. In some embodiments, the dielectric layers 118 / 119 can include materials such as build-up material, ABF, prepreg material, laminate material, another material similar to those described above for the core substrate 102, etc. or combinations thereof. In other embodiments, the interconnect structure 100 can include only one wiring structure (e.g., 112 or 113), or each of the wiring structures 112 / 113 can include more or fewer wiring layers. Each wiring layer of the wiring structures 112 / 113 can have a thickness between about 5 μm and about 50 μm, and each of the wiring structures 112 / 113 can have a total thickness between about 2 μm and about 50 μm, but other thicknesses are possible.

[0021] In some embodiments, the opening for the via 110 in the core substrate 102 may be filled with a filling material 111. The filling material 111 may provide structural support and protection for the conductive material of the via 110. In some embodiments, the filling material 111 may be a material such as a molding material, an epoxy resin, an epoxy molding compound, a resin, a material including monomers or oligomers (such as acrylated urethane, rubber-modified acrylated epoxy resin or polyfunctional monomers), etc. or a combination thereof. In some embodiments, the filling material 111 may include pigments or dyes (e.g., for color) or other fillers and additives that change rheology, improve adhesion, or affect other properties of the filling material 111. In some embodiments, the conductive material of the via 110 may completely fill the via 110, thereby omitting the filling material 111.

[0022] In some embodiments, the interconnect structure 100 may include a passivation layer 107 formed over one or more sides of the interconnect structure 100. The passivation layer 107 may be a material such as a nitride, an oxide, a polyimide, a low-temperature polyimide, a solder mask, a combination thereof, etc. Once formed, the passivation layer 107 may be patterned (e.g., using suitable lithography and etching processes) to expose portions of the wiring layers 108 / 109 of the wiring structure 112 / 113. Conductive pillars 105 may be formed on the portions of the wiring layers exposed by the openings.

[0023] In some embodiments, conductive pillars 105 are formed on one or both of the wiring structures 112 / 113 of the interconnect structure 100. For example, Figure 1 illustrates a conductive pillar 105 formed on the outermost wiring layer 108 of the wiring structure 112. The conductive pillar 105 provides an electrical connection between the wiring structure 112 and a subsequently formed redistribution structure 208 (see Figure 7 ). In some embodiments, the conductive pillar 105 includes a metal rod or metal column in an opening in the passivation layer 107 that exposes a portion of the wiring layer (e.g., 108 or 109) of the wiring structure (e.g., 112 or 113). The conductive pillar 105 may be formed by suitable processes such as sputtering, printing, electroplating, electroless plating, CVD, etc. The conductive pillar 105 may include one or more conductive materials such as copper, titanium, tungsten, aluminum, another metal, an alloy, etc. or a combination thereof. The conductive pillar 105 may be solderless. The conductive pillar 105 may be formed to have a substantially vertical sidewall or a tapered sidewall.

[0024] As an example of forming the conductive pillar 105, a seed layer (not shown) is formed over the passivation layer 107 and the portion of the wiring layers 108 / 109 exposed by the opening in the passivation layer 107. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sub-layers formed of different materials. In a particular embodiment, the seed layer includes a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using, for example, PVD. A photoresist is formed and patterned over the seed layer. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to the conductive pillar 105. An opening is patterned through the photoresist to expose the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating (such as electroplating, electroless plating, etc.). The conductive material can include metals such as copper, titanium, tungsten, aluminum, etc. The portions of the photoresist and the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as wet etching or dry etching. The remaining portions of the seed layer and the conductive material form the conductive pillar 105.

[0025] In some embodiments, the conductive pillar 105 includes a metal capping layer formed on top of the metal pillar. The metal capping layer can include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc. or a combination thereof and can be formed by a plating process. Subsequently, the conductive pillar 105 can be planarized (see Figure 4 ). Using the conductive pillar 105 as described herein can improve the planarity of the subsequently formed redistribution structure 208 (see Figure 7 ) and reduce warping, which can reduce the chance of joint failure or delamination within the package structure (e.g., Figure 9 the package structure 200 shown, etc.). In addition, the planarization process can be used to reduce the impact of thickness variations of the interconnect structure 100.

[0026] In some embodiments, the conductive pillar 105 can be formed to have a height H1 in the range of about 10 μm to about 500 μm, but other heights are also possible. After planarization (see Figure 4 ), the height of the conductive pillar 105 can be reduced. In some embodiments, the conductive pillar 105 can be formed to have a width W1 in the range of about 20 μm to about 800 μm, but other widths are also possible. In some cases, conductive pillars with a larger width can provide better electrical contacts to the overlying redistribution structure (e.g., the redistribution structure 208). In some embodiments, the conductive pillar 105 can be formed to have a pitch P1 in the range of about 50 μm to about 1,000 μm, but other pitches are also possible.

[0027] Figures 2A to 10 illustrates an intermediate step in forming an encapsulation structure 200 (see Figure 10 ). Figure 10 illustrates a schematic plan view of the encapsulation structure 200, and Figures 3 to 9 illustrates a cross-sectional view taken through Figure 10 the reference cross-section A-A shown. The encapsulation structure 200 includes a redistribution structure 208 formed over a plurality of interconnect structures 100 denoted as interconnect structures 100A and 100B. The interconnect structures 100A - 100B may be similar to Figure 1 the interconnect structure 100 shown, and the interconnect structures 100A and 100B may be different from each other. The number, arrangement, or size of the interconnect structures within the encapsulation structure may be different from that shown.

[0028] Figures 2A to 7 illustrates the formation of a redistribution structure 208 including a plurality of wires 205A - 205F, a plurality of dielectric layers 206A - 206G, and a plurality of conductive vias 207A - 207F. The redistribution structure 208 is shown as an illustrative example, and more or fewer wires, dielectric layers, and / or conductive vias may be used in other embodiments. The redistribution structure 208 may be formed using materials and / or techniques different from those described below.

[0029] Turning to Figure 2A , according to some embodiments, the interconnect structures 100A - 100B are attached to a carrier substrate 202. In some embodiments, the interconnect structure 100 may be attached to a release layer 203 formed on the carrier substrate 202, etc. In some embodiments, the interconnect structure 100 attached to the carrier substrate 202 may have a length L1 in the range of about 15 mm to about 500 mm, but other lengths are possible. In some embodiments, adjacent interconnect structures 100 may be separated by a lateral distance D1 in the range of about 40 μm to about 5000 μm, but other separation distances are possible.

[0030] The carrier substrate 202 may include, for example, a silicon-based material (such as a silicon substrate (e.g., a silicon wafer), a glass material, silicon oxide) or other materials (such as alumina), etc., or a combination thereof. Figure 2B illustrates an illustrative example where the carrier substrate 202 is a silicon wafer. In some embodiments, the carrier substrate 202 may be a panel structure, which may be, for example, a support substrate formed of a suitable dielectric material (such as a glass material, a plastic material, or an organic material). The panel structure may be, for example, a rectangular panel. Figure 2C illustrates an illustrative example where the carrier substrate 202 is a panel structure. Figures 2B to 2CShows multiple sets of interconnect structures 100A - 100B attached to a carrier substrate 202. In this way, multiple structures can be formed simultaneously on the carrier substrate 202. Subsequently, the structures formed on the carrier substrate 202 can be divided as part of the process of forming a single package structure 200 (see Figure 9 ).

[0031] Returning to Figure 2A , a release layer 203 can be formed on the top surface of the carrier substrate 202 to assist in subsequently peeling off the carrier substrate 202. The release layer 203 can be formed of a polymer - based material, which can be removed from the overlying structures to be formed in subsequent steps together with the carrier substrate 202. In some embodiments, the release layer 203 is a thermally - releasable epoxy - based material that loses its adhesiveness when heated, such as a light - to - heat conversion (LTHC) release coating. In other embodiments, the release layer 203 can be an ultraviolet (UV) glue that loses its adhesiveness when exposed to UV light. The release layer 203 can be dispensed in liquid form and cured, can be a laminated film laminated onto the carrier substrate 202, or the like. The top surface of the release layer 203 can be flush and can have a high degree of planarity. In some embodiments, a die attach film (DAF) (not shown) can be used instead of or in addition to the release layer 203.

[0032] In Figure 3 , a bottom fill 224 is deposited along the sidewalls of the interconnect structures 100A - 100B and in the gaps between the interconnect structures 100A - 100B. The bottom fill 224 can cover the conductive pillars 105, as Figure 3 shown. The bottom fill 224 can be a material such as molding compound, sealant, epoxy resin, underfill, molded underfill (MUF), resin, etc. The bottom fill material 224 can protect the conductive pillars 105 and provide structural support for the package structure 200 (see Figure 9 ). In some embodiments, the bottom fill 224 can be applied using a compression molding process, a transfer molding process, etc. In some embodiments, the bottom fill 224 can be applied in liquid or semi - liquid form and then cured.

[0033] In Figure 4In accordance with some embodiments, a planarization process is performed on the underfill 224 to expose the conductive pillars 105. The planarization process may include, for example, a grinding process and / or a chemical mechanical polishing (CMP) process. After performing the planarization process, within process variations, the top surfaces of the conductive pillars 105 and the underfill 224 may be substantially flush (e.g., planar) after the planarization process. In some cases, the planarization process reduces the height of the conductive pillars. In some embodiments, after performing the planarization process, the thickness T1 of the underfill 224 on the interconnect structures 100A - 100B may be in the range of about 10 μm to about 500 μm, but other thicknesses are also possible. The thickness T1 may also correspond to the height by which the conductive pillars 105 protrude from the interconnect structures 100A - 100B after planarization, or may also correspond to the vertical distance between the interconnect structures 100A - 100B and the overlying redistribution structure 208 (see Figure 6 ).

[0034] In Figure 5 , in accordance with some embodiments, conductive vias 207A of the redistribution structure 208 are formed on some or all of the conductive pillars 105. The conductive vias 207A make electrical connections between the conductive pillars 105 and subsequently formed wires 205A of the redistribution structure 208. As an example of forming the conductive vias 207A, a photoresist is formed and patterned over the underfill 224 and the conductive pillars 105. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The patterned photoresist forms openings through the photoresist to expose portions of the underlying conductive pillars 105 such that the openings in the photoresist correspond to the pattern of the conductive vias 207A. Then a conductive material is formed in the openings of the photoresist and on the exposed portions of the conductive pillars 105. The conductive material may be formed by plating (such as electroplating or electroless plating, etc.). The conductive material may include metals such as copper, titanium, tungsten, aluminum, etc. or combinations thereof. The photoresist may be removed by an acceptable ashing or stripping process.

[0035] Turning to Figure 6, according to some embodiments, after forming the conductive via 207A, a dielectric layer 206A and a wire 205A are formed. The dielectric layer 206A is formed over and around the bottom fill 224, the conductive pillar 105, and the conductive via 207A. In some embodiments, the dielectric layer 206A is a sealant, such as a prepreg, resin, resin-coated copper (RCC), molding compound, polyimide, photoimageable dielectric (PID), epoxy resin, etc., and can be applied by suitable techniques such as compression molding, transfer molding, spin coating, etc. The sealant can be applied in a liquid or semi-liquid form and then cured. In some embodiments, the dielectric layer 206A is formed such that the conductive via 207A is buried or covered, and then a planarization process is performed on the dielectric layer 206A to expose the conductive via 207A. Within process variations, the topmost surfaces of the dielectric layer 206A and the conductive via 207A can be substantially flush (e.g., planar) after the planarization process. The planarization process can include, for example, a grinding process and / or a CMP process.

[0036] In some embodiments, the dielectric layer 206A can include other materials, such as silicon oxide, silicon nitride, etc.

[0037] In some embodiments, the dielectric layer 206A is formed to have a thickness in the range of about 5 μm to about 50 μm, but other thicknesses are also possible.

[0038] According to some embodiments, a wire 205A of the redistribution structure 208 is then formed over the dielectric layer 206A and the conductive via 207A. The wire 205A may include, for example, a wire, a redistribution layer or a redistribution line, a contact pad, or other conductive components extending above the main surface of the dielectric layer 206A. As an example of forming the wire 205A, a seed layer is formed over the dielectric layer 206A. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including a plurality of sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located above the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD). Then, a photoresist is formed and patterned over the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning, wherein the pattern of the photoresist corresponds to the wire 205A. An opening is patterned through the photoresist to expose the seed layer, and then a conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating (such as electroplating, electroless plating, etc.). The conductive material may include metals such as copper, titanium, tungsten, aluminum, etc. or a combination thereof. Then, the photoresist and the portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using oxygen plasma, a chemical stripping process, etc. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as wet etching or dry etching. The remaining portions of the seed layer and the conductive material form the wire 205A. Other techniques for forming the wire 205A are also possible. In some cases, the dielectric layer 206A and the metallization pattern including the conductive via 207A and the wire 205A form a redistribution layer of the redistribution structure 208.

[0039] In Figure 7 accordance with some embodiments, the steps and processes discussed above are repeated to form additional redistribution layers of the redistribution structure 208. Figure 7 The additional redistribution layers shown include additional dielectric layers 206B - 206G; additional wires 205B - 205F; and additional conductive vias 207B - 207F. The redistribution layers of the redistribution structure 208 are shown as an example of the redistribution structure 208 including six layers of wires, but more or fewer dielectric layers, wires, or conductive vias may be formed for the redistribution structure 208. If fewer redistribution layers are to be formed, some of the steps and processes discussed below may be omitted. If more redistribution layers are to be formed, some of the steps and processes discussed below may be repeated.

[0040] Additional redistribution layers of the redistribution structure 208 can be formed using techniques similar to those described for the dielectric layer 206A, the wire 205A, and the conductive via 207A. For example, a conductive via 207B can be formed on the wire 205A and can be formed in a similar manner and of similar materials as the conductive via 207A. A dielectric layer 206B can then be formed over the dielectric layer 206A, the wire 205A, and the conductive via 207B. The dielectric layer 206B can be formed in a similar manner and of similar materials as the dielectric layer 206A. A planarization process can be performed on the dielectric layer 206B to expose the conductive via 207B. A wire 205B can then be formed on the dielectric layer 206B and the conductive via 207B. The wire 205B is in physical and electrical contact with the underlying conductive via 207A. The wire 205B can be formed in a similar manner and of similar materials as the wire 205A. In some embodiments, the wires and / or conductive vias can be formed to have different dimensions. For example, one or more of the wires or conductive vias can have a different width, pitch, or thickness than the other wires or conductive vias. In some embodiments, one or more of the dielectric layers can be formed of different materials or have different thicknesses than the other dielectric layers. An example of a redistribution structure 500 having a dielectric layer formed of more than one material is described below for Figure 19 Examples of redistribution structures 500 having dielectric layers formed of more than one material are described.

[0041] Steps or processes similar to these can be implemented to form conductive wires 205C, 205D, 205E, and 205F; conductive vias 207B, 207C, 207D, 207E, and 207F; and dielectric layers 206C, 206D, 206E, 206F, and 206G. The topmost dielectric layer 206G can be formed above the topmost conductive wire 205F and dielectric layer 206E. The topmost dielectric layer 206G can be formed of a material similar to dielectric layers 206A - 206E or a different material. For example, in some embodiments, the topmost dielectric layer 206G is formed of a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. In other embodiments, the dielectric layer 206G is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.; or the like. The dielectric layer 206G can be formed by any acceptable deposition process such as spin coating, CVD, lamination, etc. or a combination thereof. Although one process for forming conductive vias 207A - 207F, dielectric layers 206A - 206G, and conductive wires 205A - 205F has been described, it should be understood that other processes can be used to form the redistribution layers of the redistribution structure 208. For example, the conductive vias and conductive wires of the redistribution layer can be formed simultaneously by forming a single metallization pattern including a via portion corresponding to the conductive via and a line portion corresponding to the conductive wire. In such an embodiment, the line portion of the metallization pattern is located on the main surface of the dielectric layer and extends along the main surface of the dielectric layer, and the via portion of the metallization pattern extends through the dielectric layer to physically and electrically couple the conductive wire to the underlying conductive component. In such an embodiment, no seed layer is formed between the conductive vias and conductive wires of the same redistribution layer.

[0042] In Figure 8 , according to some embodiments, a conductive connector 212 is formed on the redistribution structure 208. The conductive connector 212 allows physical and electrical connection to a die or another package structure such as an integrated circuit package 250 (see Figure 9 ). In some embodiments, an opening can be formed in the topmost dielectric layer of the redistribution structure (e.g., dielectric layer 206G) to expose the topmost conductive wire of the redistribution structure 208 (e.g., conductive wire 205F). The opening exposes the portion of the conductive wire on which the conductive connector 212 is subsequently formed. The opening can be formed, for example, using a laser drilling process. In other embodiments, the opening can be formed by forming a photoresist above the dielectric layer 206G, patterning the photoresist, and etching the dielectric layer 206G through the patterned photoresist using a suitable etching process (e.g., a wet etching process and / or a dry etching process).

[0043] Then, a conductive connection member 212 can be formed on the wire 205F to make an electrical connection to the redistribution structure 208. The conductive connection member 212 can be a ball grid array (BGA) connection member, solder ball, metal post, controlled collapse chip connection (C4) bump, microbump, bump formed by electroless nickel-electroless palladium immersion gold technology (ENEPIG), etc. The conductive connection member 212 can include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, the conductive connection member 212 is formed by first forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow can be performed to shape the material into a desired bump shape. In another embodiment, the conductive connection member 212 includes a metal post (such as a copper post) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal post can be solderless and have substantially vertical sidewalls. In some embodiments, a metal capping layer is formed on top of the metal post. The metal capping layer can include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc. or a combination thereof, and can be formed by a plating process. In some embodiments, a UBM (not shown) is formed on the wire 205F before forming the conductive connection member 212.

[0044] Figure 9Illustrated is the attachment of integrated circuit package 250 to conductive connector 212 to form package structure 200 according to some embodiments. In some embodiments, carrier substrate 202 is peeled away (or “stripped”) from the carrier substrate 202. In some embodiments, the stripping includes projecting light such as laser or UV light onto release layer 203 of carrier substrate 202 such that release layer 203 decomposes under the heat of the light and carrier substrate 202 can be removed. Multiple structures may be formed on carrier substrate 202 and then may be diced to form individual structures that are subsequently processed to form a single package structure 200. The structures may be diced, for example, using one or more saw blades that separate the structures into discrete pieces, thereby forming one or more diced structures. However, any suitable dicing method including laser ablation or one or more wet etches may also be utilized. The dicing process may leave underfill 224 on the sidewalls of interconnect structure 100, or the dicing process may remove underfill 224 from the sidewalls of interconnect structure 100. After the dicing process, redistribution structure 208 may have sidewalls coplanar with the sidewalls of interconnect structure 100, or redistribution structure 208 may have sidewalls coplanar with underfill 224 remaining on the sidewalls of interconnect structure 100. In some embodiments, the thickness of underfill 224 remaining on the sidewalls of interconnect structure 100 may have a thickness D4 in the range of about 40 μm to about 5,000 μm, but other thicknesses are possible. Thickness D4 may also correspond to the lateral offset between the sidewalls of redistribution structure 208 and interconnect structure 100.

[0045] One or more integrated circuit packages 250 are physically and electrically connected to conductive connector 212 to make an electrical connection between integrated circuit package 250 and redistribution structure 208. Integrated circuit package 250 may be placed on conductive connector 212 using a suitable process such as a pick and place process. Figure 9 Illustrated is the attachment of one integrated circuit package 250, but in other embodiments, one, two, or more than three integrated circuit packages 250 may be attached to conductive connector 212. In some embodiments, the integrated circuit packages 250 attached to conductive connector 212 may include more than one of the same type of integrated circuit package, or may include two or more different types of integrated circuit packages. Figure 9 Illustrated is package structure 200 that may be implemented at any suitable prior step during the formation process after dicing. In some embodiments, the lateral distance between opposite sides of package structure 200 is between about 30 mm and about 500 mm, but other distances are possible.

[0046] In some embodiments, integrated circuit package 250 may include one or more integrated circuit dies 252. Figure 9The cross-sectional view shows three integrated circuit dies 252A - 252C, but the integrated circuit package 250 may include more or fewer integrated circuit dies 252 than shown. The integrated circuit dies 252 may include, for example, logic dies (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-chip (SoC), chip-on-wafer (CoW), application processor (AP), microcontroller, etc.), memory dies (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), power management dies (e.g., power management integrated circuit (PMIC) die), radio frequency (RF) die, sensor die, microelectromechanical systems (MEMS) die, signal processing die (e.g., digital signal processing (DSP) die), front-end die (e.g., analog front-end (AFE) die), input / output (I / O) die, etc. or combinations thereof. For example, in some embodiments, the integrated circuit package 250 includes a logic die 252B and a plurality of I / O dies 252A and 252C that interface with the logic die 252B, but other combinations of integrated circuit dies 252 are possible. The integrated circuit dies 252 may be a memory device including multiple memory dies, such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, etc. The integrated circuit dies 252 may be formed in one or more wafers that may include different device regions that may be separated in subsequent steps. The integrated circuit dies 252 may be packaged together with other similar or different integrated circuit dies 252 using known manufacturing techniques.

[0047] The integrated circuit package 250 may include a wiring structure 254 that provides electrical wiring and connections, for example, between the integrated circuit dies 252. The wiring structure 254 may also provide connections from the integrated circuit package 250 to the conductive connectors 212. The wiring structure 254 may include one or more redistribution layers, an integrated fan-out (InFO) structure, through-substrate vias (TSVs), metallization patterns, electrical wiring, wires, conductive vias, etc. or combinations thereof.

[0048] The integrated circuit package 250 may be placed such that the conductive regions of the integrated circuit package 250 (e.g., contact pads, conductive connectors, solder bumps, etc., which may be part of the wiring structure 254) are aligned with the corresponding conductive connectors 212 on the redistribution structure 208. Once in physical contact, the conductive connectors 212 may be bonded to the integrated circuit package 250 using a reflow process to form the package structure 200. As Figure 9As shown, underfill 214 can be deposited between integrated circuit package 250 and redistribution structure 208. Underfill 214 can also at least partially surround conductive connection 212. Underfill 214 can be a material such as molding compound, epoxy resin, underfill, molded underfill (MUF), resin, etc., and can be similar to previously described underfill 224.

[0049] Still referring Figure 9 , external connection 216 can be formed on interconnect structure 100. In some embodiments, UBM is first formed on interconnect structure 100, and external connection 216 is formed above the UBM. External connection 216 can be, for example, a contact bump or a solder ball, but any suitable type of connection can be utilized. In embodiments where external connection 216 is a contact bump, external connection 216 can include a material such as tin or other suitable materials such as silver, lead-free tin, or copper. In embodiments where external connection 216 is a solder bump, external connection 216 can be formed by first forming a solder layer using techniques such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow can be implemented to shape the material into the desired bump shape for external connection 216. In some embodiments, external connection 216 can have a pitch between about 100 μm and about 1,500 μm, but other distances are possible. In this way, package structure 200 can be formed.

[0050] In some embodiments, optional support ring 220 is attached to package structure 200 to provide further mechanical support to reduce warping of package structure 200. Support ring 220 can be attached to package structure 200 by an adhesive, an adhesive film, etc. Support ring 220 can be a material such as metal, but other materials can be used. In some cases, the outer edge of support ring 220 can be flush with the sidewall of package structure 200. Support ring 220 can have a thickness between about 50 μm and about 1,500 μm, but other thicknesses are possible.

[0051] Figure 10 Shows Figure 9 A plan view of the structure shown, where Figure 9 The cross-section of Figure 10 Shown reference section A-A. For clarity, some components such as optional support ring 220 have been omitted from Figure 10 Shown. The dashed outline shows the position of interconnect structure 100 within package structure 200. Figure 9 Shown. The dashed outline shows the position of interconnect structure 100 within package structure 200. Figure 10Four interconnect structures 100 are shown, but in other embodiments, there may be more or fewer interconnect structures 100, the interconnect structures 100 may be of different sizes or shapes than shown, or the interconnect structures 100 may have a different arrangement than shown. In some embodiments, one or both sides of the package structure 200 may have a length L2 between about 30 mm and about 500 mm, but other lengths are possible.

[0052] In some cases, as described herein, by forming a redistribution structure 208 over the plurality of interconnect structures 100, stress or warpage of the package structure 300 can be reduced. Using a plurality of interconnect structures 100 in the package structure 200 can reduce manufacturing costs, reduce assembly time, and reduce warpage of the package structure 200. For example, by planarizing the underfill 224 and the conductive pillars 105, as Figure 4 shown, greater planarity of the above redistribution structure 208 can be achieved. By reducing the warpage of the package structure 200, the risk of problems occurring in the conductive connection members 212 between the integrated circuit package 250 and the redistribution structure 208 can be reduced or eliminated. These problems can include joint failures, joint cracks, bump fatigue, cold joints, high stress, etc. In this way, the techniques described herein can improve device reliability, yield, and performance.

[0053] Figure 11 A cross-sectional view of a package structure 300 of a single interconnect structure 100 according to some embodiments is shown. The package structure 300 is similar to Figure 9 the package structure 200 shown, except that the package structure 300 includes a single interconnect structure 100 instead of a plurality of interconnect structures 100. In embodiments having a single interconnect structure 100, the single interconnect structure 100 may have a length L3 between about 15 mm and about 500 mm, but other lengths are possible. Figure 11 The interconnect structure 100 shown includes conductive pillars 105, which allow a redistribution structure 208 to be formed over the interconnect structure 100, similar to the process Figures 3 to 7 described. The techniques described herein can also reduce the warpage of a package structure including a single interconnect structure 100, which can improve device reliability, yield, and performance, as previously described.

[0054] Figures 12 to 18 An intermediate step in a re-formed package structure 400 (see Figure 18 ) according to some embodiments is shown. The package structure 400 is similar to Figure 9The encapsulated structure 200 shown, in addition to forming the second redistribution structure 408 above the first redistribution structure 402, and the second redistribution structure 408 is formed using a different technology from the first redistribution structure 402. The first redistribution structure 402 may be similar to the redistribution structure 208 described previously and described using a similar technology. The second redistribution structure 408 may be formed using a technology that allows for the formation of smaller wires (e.g., a "fine" process, which may include a silicon foundry manufacturing process), such as wires having a width of about 2 μm or less. In some cases, using a different technology to form the second redistribution structure 408 may result in improved electrical performance, which will be described in more detail below. In some embodiments, the second redistribution structure 408 may have sidewalls coplanar with the sidewalls of the first redistribution structure 402.

[0055] Figure 12 The first redistribution structure 402 formed above the interconnect structures 100A - 100B according to some embodiments is shown. Figure 12 The first redistribution structure 402 shown may be similar to Figure 7 the redistribution structure 208 shown, except that the top dielectric layer 206G is not formed above the topmost wire 205F. The first redistribution structure 402 may be formed using materials and technologies similar to those of the redistribution structure 208. For example, the first redistribution structure 402 includes a plurality of wires 205A - 205F, a plurality of dielectric layers 206A - 206F, and a plurality of conductive vias 207A - 207F. The first redistribution structure 402 is shown as an illustrative example, and more or fewer wires, dielectric layers, and / or conductive vias may be used in other embodiments.

[0056] Figures 13 to 16 An intermediate step in the formation of the second redistribution structure 408 (see Figure 16 ) according to some embodiments is shown. The second redistribution structure 408 includes metallization patterns 405A - 405C and dielectric layers 406A - 406D. The second redistribution structure 408 may have a different number of metallization patterns or dielectric layers than shown. If fewer redistribution layers of the second redistribution structure 408 are to be formed, some of the steps and processes discussed below may be omitted. If more redistribution layers are to be formed, some of the steps and processes discussed below may be repeated.

[0057] In Figure 13In [the structure], a dielectric layer 406A is formed on the first redistribution structure 402. The dielectric layer 406A is formed above the dielectric layer 206F and the wire 205F. In some embodiments, the dielectric layer 406A is formed of a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. In some embodiments, the dielectric layer 406A is formed of a photosensitive material that can be patterned using a lithography process, such as PBO, polyimide, BCB, etc. In other embodiments, the dielectric layer 406A is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.; or a combination thereof. The dielectric layer 406A can be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), lamination, etc. or a combination thereof.

[0058] In Figure 14 [the structure], the dielectric layer 406A is patterned to form an opening that exposes a portion of the wire 205F. The patterning can be implemented using an acceptable process, such as by exposing the dielectric layer 406A to light and developing it when the dielectric layer 406A is a photosensitive material, or by etching using, for example, anisotropic etching when the dielectric layer 406A is not photosensitive.

[0059] In Figure 15In accordance with some embodiments, a metallization pattern 405A is formed over the dielectric layer 406A. The metallization pattern 405A includes conductive elements that extend along a major surface of the dielectric layer 406A and extend through the dielectric layer 406A to physically and electrically couple to an underlying conductive layer (e.g., wire 205F). As an example of forming the metallization pattern 405A, a seed layer is formed over the dielectric layer 406A and in an opening that extends through the dielectric layer 406A to the wire 205F. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located over the titanium layer. The seed layer can be formed using, for example, PVD. Then, a photoresist is formed and patterned over the seed layer. The photoresist can be formed by spin coating, etc., and can be exposed to light and developed for patterning. The patterning forms an opening through the photoresist to expose the seed layer, wherein the pattern of the opening corresponds to the metallization pattern 405A. Then, a conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating (such as electroplating, electroless plating, etc.). The conductive material can include metals such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and the underlying portion of the seed layer forms the metallization pattern 405A. The photoresist and the portions of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as wet etching or dry etching. The combination of the dielectric layer 406A and the metallization pattern 405A forms a redistribution layer of the second redistribution structure 408.

[0060] In Figure 16 accordance with some embodiments, the remaining dielectric layers 406B - 406D and metallization patterns 405B - 405C of the second redistribution structure 408 are formed. The dielectric layers 406B - 406D and the metallization patterns 405B - 405C can be formed using materials and techniques similar to those of the dielectric layer 406A and the metallization pattern 405A. In some embodiments, some or all of the dielectric layers of the second redistribution structure 408 can be thinner than the dielectric layers of the first redistribution structure 402. In some embodiments, one or more of the dielectric layers of the second redistribution structure 408 can have a different thickness from the other dielectric layers of the second redistribution structure 408. In some embodiments, each of the dielectric layers of the second redistribution structure 408 has a thickness in the range of about 2 μm to about 15 μm, but other thicknesses are also possible.

[0061] In some embodiments, the metallization pattern of the second redistribution structure 408 may have different dimensions from the wires and / or conductive vias of the first redistribution structure 402. For example, the wires and / or conductive vias of the first redistribution structure 402 may be wider or thicker than the wires and / or vias of the metallization pattern of the second redistribution structure 408, allowing for longer horizontal routing.

[0062] In some embodiments, the wires of the metallization pattern of the second redistribution structure 408 each have a thickness in the range of about 0.5 μm to about 5 μm, although other thicknesses are possible. In some embodiments, the metallization pattern of the second redistribution structure 408 may be formed to have a line width or line pitch less than about 2 μm. In some cases, a different process than that used to form the first redistribution structure 402 is used to form the second redistribution structure 408, allowing for smaller component sizes to be formed within the second redistribution structure 408. For example, by using silicon foundry processing techniques to form the second redistribution structure 408, the metallization pattern of the second redistribution structure 408 may be formed to have a smaller roughness. Conductive components with smaller roughness may have less insertion loss and less skin effect, and thus may improve signal integrity within the second redistribution structure 408. Additionally, the dielectric layer of the second redistribution structure 408 may be formed to have a smaller thickness, which may reduce the equivalent series resistance (ESR) or equivalent series inductance (ESL) of the dielectric layer, which may improve the power integrity of the package structure 400. By forming the second redistribution structure 408 with finer components in this manner, the high-speed operation of the package structure 400 may be improved.

[0063] In Figure 17 , according to some embodiments, a conductive connector 212 is formed on the second redistribution structure 408. The conductive connector 212 allows for physical and electrical connection to the die or another package structure, such as integrated circuit package 250 (see Figure 18 ). In some embodiments, an opening may be formed in the topmost dielectric layer of the second redistribution structure 408 (e.g., dielectric layer 406D) to expose the topmost wire of the second redistribution structure 408 (e.g., wire 405C). The opening exposes the portion of the wire on which the conductive connector 212 is subsequently formed. The opening may be formed, for example, using a laser drilling process. In other embodiments, the opening may be formed by depositing a photoresist over the dielectric layer 406D, patterning the photoresist, and etching the dielectric layer 406D through the patterned photoresist using a suitable etching process (e.g., a wet etching process and / or a dry etching process).

[0064] Then, the conductive connector 212 may be formed on the wire 405C, thereby making an electrical connection to the second redistribution structure 408. The conductive connector 212 may be similar to that for Figure 8The described conductive connection member 212 can be formed in a similar manner. In some embodiments, a UBM (not shown) is formed on the wire 405C before forming the conductive connection member 212.

[0065] Figure 18 FIG. shows an integrated circuit package 250 attached to a conductive connection member 212 to form a package structure 400 according to some embodiments. The integrated circuit package 250 can be similar to the Figure 9 previously described integrated circuit package 250 and can be attached in a similar manner. The integrated circuit package 250 is physically and electrically connected to the conductive connection member 212 to make an electrical connection between the integrated circuit package 250 and the second redistribution structure 408. In addition, the external connection member 216 and / or the support ring 220 can be formed in a manner similar to that Figure 9 previously described.

[0066] Figure 19 FIG. shows an intermediate step in forming a package structure 500 according to some embodiments. The package structure 500 is similar to the Figure 18 shown package structure 400, except that the first redistribution structure 502 includes a first redistribution layer 502A and a second redistribution layer 502B formed using different dielectric materials. In addition, Figure 19 the shown package structure 500 has two integrated circuit packages 550A and 550B attached to a second redistribution structure 508 formed on the first redistribution structure 502.

[0067] The first redistribution layer 502A and / or the second redistribution layer 502B of the redistribution structure 502 can be formed using techniques similar to those previously described for the redistribution structure 208. The first redistribution structure 502 includes a first redistribution layer 502A having dielectric layers 506A - 506B formed using a first dielectric material and a second redistribution layer 502B having dielectric layers 506C - 506F formed using a second dielectric material different from the first dielectric material. For example, the second dielectric material can be a molding compound having a different composition from the first dielectric material, but other dielectric materials are also possible. The first dielectric material or the second dielectric material can be similar to those previously described for the dielectric layers 206A - 206G (see Figures 6 to 7)The dielectric material described, or it can be another dielectric material. According to some embodiments, the first redistribution structure 502 is an example of a redistribution structure formed as a redistribution layer having more than one material. In other embodiments, one or more of any dielectric layers within the redistribution structure (e.g., redistribution structures 208, 402, or 502) can be formed using a different dielectric material than the other dielectric layers. The first redistribution structure 502 is shown as an illustrative example, and in other embodiments, more or fewer wires, dielectric layers, and / or conductive vias can be used.

[0068] In some embodiments, the wires and / or conductive vias of the first redistribution layer 502A can be formed to have different dimensions than those of the second redistribution layer 502B. For example, one or more of the wires or conductive vias of the first redistribution layer 502A can have a different width, pitch, or thickness than one or more of the wires or conductive vias of the second redistribution layer 502B. In some embodiments, one or more of the dielectric layers 506A - 506B of the first redistribution layer 502A can be formed to have a different thickness than one or more of the dielectric layers 506C - 506F of the second redistribution layer 502B.

[0069] In some cases, forming a redistribution structure 502 with different dielectric layers made of different materials can allow for improved device performance. For example, one or more of the redistribution layers of the first redistribution structure 502 can be formed using a dielectric material that is relatively better suited for the type of electrical signals conducted in those redistribution layers. For example, the redistribution layer through which high - frequency signals are conducted can be formed using a dielectric material that has a relatively lower signal loss at higher frequencies, such as a material with a relatively low dissipation factor. By using different dielectric materials for certain redistribution layers, in this way, by reducing signal loss, resistance, and / or inductance, the signal integrity and efficiency of the package can be improved, and the electronic noise of the package can be reduced, especially at higher - speed operations. As another example, other dielectric materials (such as those that provide relatively better insulation) can be more suitable for redistribution layers that conduct electrical power between components. These are examples, and various dielectric materials can be selected for these or other features or benefits.

[0070] According to some embodiments, a second redistribution structure 508 can be formed on the first redistribution structure 502. Figure 19 The second redistribution structure 508 shown can be similar to Figure 18 the second redistribution structure 408 shown, and can be formed using materials and techniques similar to those of the second redistribution structure 408. In other embodiments, the second redistribution structure 508 may not exist.

[0071] Then, conductive connectors 512A - 512B can be formed on the second redistribution structure 508 to make an electrical connection to the second redistribution structure 508. The conductive connectors 512A - 512B can be similar to the conductive connectors 212 described for Figure 8 , except that the conductive connector 512A has a larger size and a larger pitch than the conductive connector 512B. The conductive connectors 512A - 512B can be formed in a manner similar to that of the conductive connectors 212. In some embodiments, an UBM (not shown) is formed on the second redistribution structure 508 before forming the conductive connectors 512A - 512B.

[0072] Figure 19 Shown is attaching a plurality of integrated circuit packages 550 (e.g., integrated circuit packages 550A and 550B) to the conductive connectors 512A - 512B to form a package structure 500 according to some embodiments. The integrated circuit packages 550 can be similar to the integrated circuit packages 250 described previously for Figure 9 , and can be attached in a similar manner. For example, Figure 19 each of the illustrated integrated circuit packages 550A - 550B includes a logic die 252B and an I / O die 252A docked with the logic die 252B, but other combinations of integrated circuit dies 252 are possible. The integrated circuit packages 550 can be similar or different from each other, and there can be more or fewer integrated circuit packages 550 in other embodiments. Each integrated circuit package 550 can include an interposer 554 that provides electrical wiring and connections between, for example, the integrated circuit dies 252 of the integrated circuit package 550. The interposer 554 can include metallization layers and / or conductive vias ( Figure 19 not shown in). Each interposer 554 can also provide a connection from the integrated circuit package 550 to the conductive connectors 512A - 512B.

[0073] The integrated circuit packages 550 can be placed such that the conductive regions (e.g., contact pads, conductive connectors, solder bumps, etc., which can be part of the interposer 554) of the integrated circuit packages 550 are aligned with the corresponding conductive connectors 512A - 512B on the second redistribution structure 508. Once in physical contact, a reflow process can be utilized to bond the conductive connectors 512A - 512B to the integrated circuit packages 550, thereby forming the package structure 500. An underfill 514 can be deposited between each integrated circuit package 550 and the second redistribution structure 508. An underfill 514 can also be deposited between adjacent integrated circuit packages 550, as Figure 19as shown. The underfill 514 may also at least partially surround the conductive connectors 512A - 512B. The underfill 514 may be a material such as molding compound, epoxy resin, underfill, molded underfill (MUF), resin, etc., and may be similar to the previously described underfill 224. Additionally, the external connectors 216 and / or the support rings 220 may be formed in a manner similar to that previously described for Figure 9 described.

[0074] Other components and processes may also be included in the various embodiments described herein. For example, test structures may be included to assist in the verification testing of 3D packages or 3DIC devices. The test structures may include, for example, test pads formed in the redistribution layer or on the substrate, which allow for testing of the 3D package or 3DIC, using probes and / or probe cards, etc. The verification testing may be implemented on the intermediate structure as well as the final structure. Additionally, the structures and techniques disclosed herein may be used in combination with test methods that incorporate intermediate verification of known good dies to increase yield and reduce costs.

[0075] By utilizing the embodiments described herein, the performance of the device package can be improved, and the reliability of the device package can be improved. Different components of the embodiments described herein can be combined to achieve these and other benefits. By using multiple interconnect structures within the package structure, the cost and assembly time of the package structure can be reduced. The interconnect structures may have conductive pillars, and one or more redistribution structures may be formed on the conductive pillars to make electrical connections to the interconnect structures. The techniques described herein allow for reducing warpage in a package structure having multiple interconnect structures. Reducing the warpage of the package structure can improve joint strength, reliability, and the performance of the devices or packages attached to the redistribution structures of the package structure. Additionally, the disclosed embodiments allow for forming a package structure having a large area (e.g., greater than about 100 nm by 100 nm, etc.) with a reduced risk of joint failure, particularly for joints of bonded integrated device packages. This can allow for using multiple interconnect structures within the package without increasing warpage, which can reduce the cost and processing time of the package. The techniques described herein are also applicable to bonding various structures to form different types of packages. Additionally, using the described process techniques can result in improved yield and improved connection reliability, particularly for packages having a larger area. For example, the process techniques described herein can reduce warpage and thus also reduce problems such as cracks or delamination associated with warpage.

[0076] In some embodiments, a device includes: a first interconnect structure including conductive pillars located on a first side of the first interconnect structure; a second interconnect structure including conductive pillars located on a first side of the second interconnect structure, wherein the second interconnect structure is laterally adjacent to the first interconnect structure; an underfill material extending above the first side of the first interconnect structure, above the first side of the second interconnect structure, and between the first interconnect structure and the second interconnect structure; a first redistribution structure extending above the first side of the first interconnect structure and above the first side of the second interconnect structure, wherein the first redistribution structure is electrically connected to the conductive pillars of the first interconnect structure and the conductive pillars of the second interconnect structure; and an integrated device package attached to the first redistribution structure. In an embodiment, the first interconnect structure includes a first core substrate, and wherein the second interconnect structure includes a second core substrate. In an embodiment, the first redistribution structure physically contacts the conductive pillars of the first interconnect structure and the conductive pillars of the second interconnect structure. In an embodiment, the device includes: a second redistribution structure located between the first redistribution structure and the first interconnect structure and between the first redistribution structure and the second interconnect structure, wherein the conductive components of the second redistribution structure have a larger size than the conductive components of the first redistribution structure. In an embodiment, the first redistribution structure includes a first dielectric layer, the second redistribution structure includes a second dielectric layer, and the first dielectric layer is a different material from the second dielectric layer. In an embodiment, the underfill material surrounds the conductive pillars of the first interconnect structure and the conductive pillars of the second interconnect structure. In an embodiment, the surfaces of the conductive pillars of the first interconnect structure, the surfaces of the conductive pillars of the second interconnect structure, and the surface of the underfill material are flush. In an embodiment, the conductive pillars are copper. In an embodiment, the conductive pillars of the first interconnect structure have a height in the range of 10 μm to 500 μm. In an embodiment, the conductive pillars of the first interconnect structure have a width in the range of 20 μm to 800 μm.

[0077] In some embodiments, a structure includes: a core substrate attached to a first side of a first redistribution structure, wherein the first redistribution structure includes a first conductive component and a first dielectric layer, wherein each core substrate includes conductive pillars, and wherein the conductive pillars of the core substrate physically and electrically contact the first conductive component; a sealant extending over the first side of the first redistribution structure, wherein the sealant extends along sidewalls of each core substrate; and an integrated device package connected to a second side of the first redistribution structure. In an embodiment, sidewalls of the sealant and sidewalls of the first redistribution structure are coplanar. In an embodiment, the first redistribution structure has a size of at least 100 mm by 100 mm. In an embodiment, the structure includes: a second redistribution structure located on a second side of the first redistribution structure, wherein the second redistribution structure includes a second conductive component and a second dielectric layer, wherein the second dielectric layer includes a dielectric material different from the first dielectric layer, and wherein the integrated device package is electrically connected to the second conductive component. In an embodiment, the second conductive component has a line width less than or equal to 2 μm. In an embodiment, sidewalls of the second redistribution structure and sidewalls of the first redistribution structure are coplanar.

[0078] In some embodiments, a method includes: attaching an interconnect structure to a carrier, wherein each of the interconnect structures includes conductive pillars; forming a sealant over the interconnect structures, wherein the sealant extends between adjacent interconnect structures; performing a planarization process on the sealant to expose the conductive pillars, wherein after performing the planarization process, the sealant and the conductive pillars have coplanar surfaces; and forming a first redistribution layer over the sealant and the conductive pillars, wherein a bottom redistribution layer of the first redistribution layer is electrically connected to the conductive pillars. In an embodiment, the method includes: forming a second redistribution layer over the first redistribution layer, wherein the first redistribution layer is formed using a technique different from that of the second redistribution layer. In an embodiment, the second redistribution layer includes a polymer layer. In an embodiment, the method includes: attaching an integrated circuit die to a top redistribution layer of the first redistribution layer.

[0079] The features of several embodiments are outlined above so that those skilled in the art may better understand aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructs do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: a first interconnect structure including conductive pillars on a first side of the first interconnect structure; a second interconnect structure including conductive pillars on a first side of the second interconnect structure, wherein the second interconnect structure is laterally adjacent to the first interconnect structure; an underfill material extending above the first side of the first interconnect structure, above the first side of the second interconnect structure, and between the first interconnect structure and the second interconnect structure, the underfill material having a coplanar surface with each of the conductive pillars; a first redistribution structure located on the coplanar surface, extending above the first side of the first interconnect structure and above the first side of the second interconnect structure, wherein the first redistribution structure is electrically connected to the conductive pillars of the first interconnect structure and the conductive pillars of the second interconnect structure; and an integrated device package including a plurality of integrated circuit dies packaged together, the integrated device package being attached to the first redistribution structure, wherein one of the integrated circuit dies in the integrated device package straddles the underfill material between the first interconnect structure and the second interconnect structure.

2. The semiconductor device according to claim 1, wherein, the first interconnect structure includes a first core substrate, and wherein the second interconnect structure includes a second core substrate.

3. The semiconductor device according to claim 1, wherein, the first redistribution structure physically contacts the conductive pillars of the first interconnect structure and the conductive pillars of the second interconnect structure.

4. The semiconductor device according to claim 1, further comprising: a second redistribution structure located between the first redistribution structure and the first interconnect structure and between the first redistribution structure and the second interconnect structure, wherein conductive components of the second redistribution structure have a larger size than conductive components of the first redistribution structure.

5. The semiconductor device according to claim 4, wherein, the first redistribution structure includes a first dielectric layer, wherein the second redistribution structure includes a second dielectric layer, wherein the first dielectric layer is a material different from the second dielectric layer.

6. The semiconductor device according to claim 1, wherein, the underfill material surrounds the conductive pillars of the first interconnect structure and the conductive pillars of the second interconnect structure.

7. The semiconductor device according to claim 1, wherein, the conductive pillars of the first interconnect structure have a pitch in the range of 50 μm to 1000 μm.

8. The semiconductor device according to claim 1, wherein, the conductive pillars are copper.

9. The semiconductor device according to claim 1, wherein, the conductive pillars of the first interconnect structure have a height in the range of 10 μm to 500 μm.

10. The semiconductor device according to claim 1, wherein, the conductive pillars of the first interconnect structure have a width in the range of 20 μm to 800 μm.

11. A semiconductor structure, Comprising: A plurality of core substrates attached to a first side of a first redistribution structure, wherein the first redistribution structure includes a plurality of first conductive components and a plurality of first dielectric layers, wherein each of the plurality of core substrates includes conductive pillars, and wherein the conductive pillars of the plurality of core substrates physically and electrically contact a first conductive component of the plurality of first conductive components; A sealant extending over the first side of the first redistribution structure, wherein the sealant extends along sidewalls of each of the plurality of core substrates and fills between each adjacent pair of the plurality of core substrates, and wherein the sealant has a coplanar surface with each of the conductive pillars of the plurality of core substrates, and the first side of the first redistribution structure is bonded to the coplanar surface; and An integrated device package including a plurality of integrated circuit dies packaged together, the integrated device package being connected to a second side of the first redistribution structure, and wherein one of the integrated circuit dies in the integrated device package straddles the sealant between corresponding adjacent two core substrates.

12. The semiconductor structure according to claim 11, wherein, Sidewalls of the sealant and sidewalls of the first redistribution structure are coplanar.

13. The semiconductor structure according to claim 11, wherein, The first redistribution structure has a size of at least 100 mm by 100 mm.

14. The semiconductor structure according to claim 11, further comprising: A second redistribution structure located on the second side of the first redistribution structure, wherein the second redistribution structure includes a plurality of second conductive components and a plurality of second dielectric layers, wherein the plurality of second dielectric layers include a dielectric material different from the plurality of first dielectric layers, and wherein the integrated device package is electrically connected to a second conductive component of the plurality of second conductive components.

15. The semiconductor structure according to claim 14, wherein, The second conductive component has a line width less than or equal to 2 μm.

16. The semiconductor structure according to claim 14, wherein, Sidewalls of the second redistribution structure and sidewalls of the first redistribution structure are coplanar.

17. A method of manufacturing a semiconductor device, comprising: Attaching a plurality of interconnect structures to a carrier, wherein each of the plurality of interconnect structures includes a conductive pillar; Forming a sealant over the plurality of interconnect structures, wherein the sealant extends between adjacent ones of the interconnect structures; Performing a planarization process on the sealant to expose the conductive pillars, and wherein after performing the planarization process, the sealant and the conductive pillars have a coplanar surface; Forming a first redistribution layer on the sealant and the conductive pillars, wherein a bottom redistribution layer of the first redistribution layer is formed on the coplanar surface and electrically connected to the conductive pillars; and Attaching an integrated device package including a plurality of integrated circuit dies packaged together to a top redistribution layer of the first redistribution layer, and wherein one of the integrated circuit dies in the integrated device package straddles the sealant between corresponding adjacent two of the interconnect structures.

18. The method according to claim 17, further comprising: forming a second redistribution layer on the first redistribution layer, wherein the first redistribution layer is formed using a technique different from that of the second redistribution layer.

19. The method according to claim 18, wherein, the second redistribution layer includes a polymer layer.

20. The method according to claim 17, wherein, the interconnect structure includes a core substrate.

Images