Semiconductor packaging equipment and its manufacturing method

Abstract

A semiconductor packaging device includes a first conductive wall, a second conductive wall, a first insulating wall, a dielectric layer, a first electrode, and a second electrode. The first insulating wall is disposed between the first conductive wall and the second conductive wall. The dielectric layer has a first portion that covers the bottom surface of the first conductive wall, the bottom surface of the second conductive wall, and the bottom surface of the first insulating wall. The first electrode is electrically connected to the first conductive wall. The second electrode is electrically connected to the second conductive wall.

Description

Technical Field

[0001] This disclosure relates to semiconductor packaging equipment and methods for manufacturing the same. Background Technology

[0002] Deep trench capacitors are formed by etching trenches in a silicon wafer and then filling them with metal and dielectric material. A drawback is the limited ability to fabricate deep trenches. Due to the limitations of the trench etching process, the maximum capacitance of a deep trench capacitor is restricted.

[0003] Stacked capacitors are fabricated by alternating layers of metal and dielectric materials, with each metal layer electrically connected via a redistribution layer (RDL) or via. Fabricating multiple RDLs reduces yield and increases manufacturing costs due to the need for photomasks. Summary of the Invention

[0004] In some embodiments, this disclosure provides a semiconductor packaging apparatus. The semiconductor packaging apparatus includes a first conductive wall, a second conductive wall, a first insulating wall, a dielectric layer, a first electrode, and a second electrode. The first insulating wall is disposed between the first conductive wall and the second conductive wall. The dielectric layer has a first portion covering the bottom surface of the first conductive wall, the bottom surface of the second conductive wall, and the bottom surface of the first insulating wall. The first electrode is electrically connected to the first conductive wall. The second electrode is electrically connected to the second conductive wall.

[0005] In some embodiments, this disclosure provides a semiconductor packaging apparatus. The semiconductor packaging apparatus includes a first conductive wall, a second conductive wall, an insulating wall, a dielectric layer, a first conductive via, a second conductive via, a first electrode, and a second electrode. The insulating wall is disposed between the first conductive wall and the second conductive wall. The dielectric layer covers the upper surface of the first conductive wall, the upper surface of the second conductive wall, and the upper surface of the insulating layer. The first conductive via penetrates the dielectric layer and contacts the first conductive wall. The second conductive via penetrates the dielectric layer and contacts the second conductive wall. The first electrode is electrically connected to the first conductive wall through the first conductive via. The second electrode is electrically connected to the second conductive wall through the second conductive via.

[0006] In some embodiments, this disclosure provides a method for manufacturing a semiconductor packaging device. The method includes: providing a carrier; providing a multilayer structure including a plurality of conductive walls, wherein every two adjacent conductive walls are separated from each other by an insulating wall disposed between the two adjacent conductive walls; bonding the multilayer structure to the carrier; forming a first electrode electrically connected to one of the two adjacent conductive walls; and forming a second electrode electrically connected to the other of the two adjacent conductive walls. Attached Figure Description

[0007] When with attachment Figure 1 When reading the following detailed description, various aspects of the embodiments of this disclosure will be readily understood from it. Note that the various structures may not be drawn to scale, and the dimensions of the various structures may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 A cross-sectional view of a semiconductor packaging apparatus according to some embodiments of the present disclosure is shown.

[0009] Figure 2 Showing Figure 1 A schematic diagram of a semiconductor packaging device.

[0010] Figure 3 Showing Figure 1 The arrangement of multiple semiconductor packaging devices.

[0011] Figures 4A to 4O Various stages of a method for manufacturing a semiconductor packaging device according to some embodiments of the present disclosure are illustrated.

[0012] Figure 5A A cross-sectional view of a stacked structure according to some embodiments of the present disclosure is shown.

[0013] Figure 5B A cross-sectional view of a stacked structure according to some embodiments of the present disclosure is shown.

[0014] Figure 5C A cross-sectional view of a stacked structure according to some other embodiments of the present disclosure is shown.

[0015] Figure 6A and 6B A method for forming an integrated semiconductor packaging device according to some embodiments of the present disclosure is shown.

[0016] Throughout the accompanying drawings and detailed description, the same reference numerals are used to indicate the same or similar parts. Embodiments of this disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. In this disclosure, references to forming or placing a first feature on or over a second feature in the following description may include embodiments in which the first and second features are formed or placed in direct contact, and may also include embodiments in which additional features may be formed and placed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Embodiments of this disclosure are discussed in detail below. However, it should be understood that this disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of this disclosure.

[0019] Figure 1 A cross-sectional view of a semiconductor packaging device 1 according to some embodiments of the present disclosure is shown. In some embodiments, the semiconductor packaging device 1 can be used as a capacitor. The semiconductor packaging device 1 includes conductive walls 10 and 11, an insulating wall 12, a dielectric layer 13, a conductive layer 14, and a conductive layer 15. As used in this disclosure, the term "wall" may refer to a vertical plate or a vertical layer.

[0020] like Figure 1 As shown, conductive walls 10 and 11 are alternately arranged and separated from each other by insulating wall 12. Conductive wall 10 is electrically isolated from conductive wall 11. Conductive wall 11 is disposed between insulating walls 12. Insulating wall 12 is disposed between conductive walls 10 and 11. Conductive walls 10, 11, and 12 together form a sandwich structure. Conductive walls 10 and 11 can be made of the same or different materials and can contain, for example, but not limited to, copper (Cu), aluminum (Al), silver (Ag), graphite, metals, alloys, non-metallic conductive materials, or one or more other suitable conductive materials. Insulating wall 12 can contain, for example, but not limited to, oxides (e.g., silicon oxide or titanium oxide), nitrides (e.g., silicon nitride), polyimide, carbon nanofibers (CNF), or one or more other suitable materials.

[0021] In some embodiments, the insulating wall 19 is arranged to be adjacent to the outermost conductive wall of the conductive walls 10 and 11 (e.g., Figure 1The conductive wall 10 shown is adjacent to the insulating wall 12. The insulating wall 19 may comprise, for example, but not limited to, oxides (e.g., silicon oxide or titanium oxide), nitrides (e.g., silicon nitride), polyimide, carbon nanofibers, or one or more other suitable materials. The insulating wall 19 and the insulating wall 12 may be made of the same material or different materials.

[0022] In some embodiments, the semiconductor wall 17 may be further disposed adjacent to the insulating wall 19. The semiconductor wall 17 may comprise one or more semiconducting materials. The semiconductor wall 17 may comprise, for example, but not limited to, silicon, SiC, Al₂O₃, or one or more other suitable materials. The semiconductor wall 17 may comprise dopants. The semiconductor wall 17 may comprise n-type or p-type dopants. The semiconductor wall 17 may comprise, for example, but not limited to, phosphorus (P), or one or more other suitable materials. The semiconductor wall 17 may comprise, for example, but not limited to, boron (B), or one or more other suitable materials. In some embodiments, the semiconductor wall may be omitted. The semiconductor wall 17 serves as a support structure and may be omitted when more conductive and insulating walls are involved.

[0023] The dielectric layer 13 has three portions 131, 132, and 133. The dielectric layer 13 may comprise, for example, but not limited to, oxides (e.g., silicon oxide or titanium oxide), nitrides (e.g., silicon nitride), polyimide, carbon nanofibers, or one or more other suitable materials. In some embodiments, the dielectric layer 13 comprises silicon oxide, silicon nitride, titanium oxide, or other dielectric materials.

[0024] A portion 131 of the dielectric layer 13 covers the bottom surface 10b of the conductive wall 10, the bottom surface 11b of the conductive wall 11, and the bottom surface 12b of the insulating wall 12. The portion 131 of the dielectric layer 13 is in contact with the bottom surface 10b of the conductive wall 10, the bottom surface 11b of the conductive wall 11, and the bottom surface 12b of the insulating wall 12. In some embodiments, the bottom surfaces 10b of the conductive wall 10, 11b of the conductive wall 11, and 12b of the insulating wall 12 are substantially coplanar.

[0025] A portion 132 of the dielectric layer 13 covers the upper surface 10u of the conductive wall 10, the upper surface 11u of the conductive wall 11, and the upper surface 12u of the insulating wall 12. The portion 132 of the dielectric layer 13 is in contact with the upper surface 10u of the conductive wall 10, the upper surface 11u of the conductive wall 11, and the upper surface 12u of the insulating wall 12. In some embodiments, the upper surfaces 10u of the conductive wall 10, 11u of the conductive wall 11, and 12u of the insulating wall 12 are substantially coplanar.

[0026] A portion 133 of the dielectric layer 13 is disposed adjacent to the conductive wall 11. In some embodiments, a portion 133 of the dielectric layer 13 is disposed adjacent to the outermost conductive wall of the conductive walls 10 and 11 (e.g., Figure 1The conductive wall 11 shown is adjacent to it. In some embodiments, a portion 133 of the dielectric layer 13 covers or contacts the side of the sandwich structure containing the conductive walls 10 and 11 and the insulating wall 12. In some embodiments, a portion 133 of the dielectric layer 13, together with the insulating wall 19 or the semiconductor wall 17, covers or contacts all sides of the sandwich structure containing the conductive walls 10 and 11 and the insulating wall 12.

[0027] In some embodiments, a passivation layer 18 may be further disposed on a portion 132 of the dielectric layer 13. In some embodiments, the passivation layer 18 may cover the sidewalls of the dielectric layer 13 and may extend downward to contact the carrier 16. The passivation layer 18 may comprise, for example, but not limited to, polyimide, CNF, oxides (e.g., titanium oxide, aluminum oxide, hafnium oxide, tantalum oxide), BaTiO3, or one or more other suitable materials.

[0028] exist Figure 1 In the illustrated embodiment, conductive walls 10 and 11 and insulating wall 12 are encapsulated by dielectric layer 13.

[0029] In some embodiments, the semiconductor packaging apparatus 1 further includes a carrier 16. The carrier 16 may comprise a non-conductive or insulating material. The carrier 16 may comprise, for example, but not limited to, glass, ceramic, or other suitable materials. A portion 131 of the dielectric layer 13 is disposed between the carrier 16 and the bottom surface 10b of the conductive wall 10, the bottom surface 11b of the conductive wall 11, and the bottom surface 12b of the insulating wall 12. The carrier 16 does not contact the conductive walls 10 and 11, the insulating wall 12, the semiconductor wall 17, or the insulating wall 19.

[0030] Conductive layers (electrodes) 14 and 15 are patterned conductive layers and may contain conductive traces, one or more conductive pads, one or more conductive solder pads, or other one or more circuit elements. Conductive layers (electrodes) 14 and 15 are electrically isolated from each other. Electrode 14 is electrically connected to a first set of conductive walls (i.e., conductive wall 10), while electrode 15 is electrically connected to a second set of conductive walls (i.e., conductive wall 11). Electrode 14 is electrically connected to conductive wall 10 through conductive via 14a. Conductive via 14a penetrates a portion 132 of dielectric layer 13 and contacts conductive wall 10. Electrode 15 is electrically connected to conductive wall 11 through conductive via 15a. Conductive via 15a penetrates a portion 132 of dielectric layer 13 and contacts conductive wall 11. Electrodes 14, 15, conductive vias 14a and 15a may be made of the same or different materials and may contain, for example, but not limited to, copper or one or more other suitable materials.

[0031] Electrode 14 and electrode 15 are electrically connected to the anode and cathode of an external power source, respectively.

[0032] In some embodiments, electrodes 14 and 15 may be at the same elevation. For example, electrodes 14 and 15 may be disposed on or in contact with a portion 132 of dielectric layer 13.

[0033] In some embodiments, electrodes 14 and 15 may be at different elevations. For example, electrode 14 may be disposed on or in contact with a portion 132 of dielectric layer 13, and electrode 15 may be disposed on or in contact with passivation layer 18, with conductive via 15a penetrating both portion 132 of dielectric layer 13 and passivation layer 18. Passivation layer 18 covers or encapsulates electrode 14.

[0034] The semiconductor packaging device 1 may contain three, four or more conductive walls and insulating walls. In some embodiments, the semiconductor packaging device 1 may contain 10 to 50 conductive walls and insulating walls, or up to 60 conductive walls and insulating walls, or even more conductive walls and insulating walls.

[0035] Figure 2 Showing Figure 1 A schematic diagram of a semiconductor packaging device (passivation layer 18 is not shown). In some embodiments, the semiconductor packaging device 1 may contain 50 conductive and insulating walls, and the width W of the semiconductor packaging device 1 may be approximately 1 mm. The length L of the semiconductor packaging device 1 may be approximately 10 mm to 11 mm. The elevation H of the semiconductor packaging device 1 may be approximately 1 mm. It should be noted that the dimensions (W, L, or H) of the semiconductor packaging device can be designed as needed. The maximum capacitance of the 50-layer semiconductor packaging device 1 can reach approximately 210 nF / mm². 2 Compared with existing technologies such as deep trench capacitors, the semiconductor packaging device 1 according to this disclosure has a smaller size and higher capacitance, and is easier to manufacture.

[0036] In some applications, multiple semiconductor package devices can be used in parallel or in series. Figure 3 Showing Figure 1 The arrangement of multiple semiconductor packaging devices 1. The multiple semiconductor packaging devices 1 are electrically connected via electrodes 20 and 21. Electrode 20 is electrically connected to electrode 14 of each semiconductor packaging device 1. Electrode 21 is electrically connected to electrode 15 of each semiconductor packaging device 1. Electrodes 20 and 21 are respectively connected to the anode and cathode of an external power supply. Figure 3 The plurality of semiconductor packaging devices 1 shown are connected in parallel to achieve higher capacitance.

[0037] In some embodiments, the plurality of semiconductor packaging devices 1 are formed on a wafer with a diameter of 300 mm.

[0038] In some embodiments, electrodes 14, 15, 20, and 21 are located on the same side of the semiconductor packaging apparatus 1. The process of manufacturing the semiconductor packaging apparatus 1 is less complex than the process of manufacturing a semiconductor packaging apparatus having electrodes formed on both sides.

[0039] Figures 4A to 4O Various stages of a method for manufacturing a semiconductor packaging device according to some embodiments of the present disclosure are illustrated.

[0040] refer to Figure 4A A carrier 22 is provided. The carrier 22 may be a glass or semiconductor substrate. The semiconductor substrate may contain, for example, but not limited to, silicon (Si) or other suitable semiconducting materials.

[0041] refer to Figure 4B An insulating layer 19 is formed on the carrier 22.

[0042] refer to Figure 4C ,exist Figure 4B A conductive layer 10 is formed on the insulating layer 19 formed in the stage shown.

[0043] refer to Figure 4D ,exist Figure 4C An insulating layer 12 is formed on the conductive layer 10 formed in the stage shown.

[0044] refer to Figure 4E ,exist Figure 4D A conductive layer 11 is formed on the insulating layer 12 formed in the stage shown.

[0045] refer to Figure 4F ,exist Figure 4E An insulating layer 12 is formed on the conductive layer 11 formed in the stage shown.

[0046] refer to Figure 4G ,exist Figure 4F A conductive layer 10 is formed on the insulating layer 12 formed in the stage shown. A stacked structure including layers 10, 11, 12 and 19 is formed.

[0047] The insulating and conductive layers can be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), or one or more other suitable techniques. Figure 4G The process of sequentially forming insulating layer 12, conductive layer 11, insulating layer 12 and conductive layer 10 is then repeated multiple times.

[0048] refer to Figure 4H It can be used for, for example Figure 4G The structure shown undergoes a sawing operation. The sawing operation can be performed along the scribing lines (as shown by the dashed lines). The sawing operation can be performed on the stacked structure, or it can be performed from the top of the stacked structure to a portion of the underlying carrier 22.

[0049] refer to Figure 4I After the sawing operation, the stacked structure is divided into several units separated from each other by recesses (e.g., R1, R2 and R3).

[0050] refer to Figure 4J Provide dielectric layer 13 to cover Figure 4I Each cell in the unit. A dielectric layer 13 can be disposed on the upper surface of the cell and the side surfaces of the recess. The dielectric layer 13 can be formed, for example, by chemical vapor deposition (CVD), coating, sputtering, etc. Figure 4H and 4I The sawing operation shown creates microcracks on the surface of the stacked structure. Dielectric layer 13 can repair these microcracks. Dielectric layer 13 can also electrically isolate the conductive layers to prevent short circuits. After the dielectric layer 13 is formed, multiple multilayer structures 1' are formed on the carrier 22.

[0051] Subsequently, the plurality of multilayer structures 1' are separated from the carrier 22. Separation may include grinding or debonding. In some embodiments, for example when a semiconductor substrate is used as the carrier, the carrier 22 may be ground to separate the multilayer structures 1' from each other and from the carrier 22. A portion of the semiconductor substrate may remain within the separated multilayer structures 1' and constitute... Figure 4K The semiconductor wall 17 is shown. In some embodiments, such as when a glass substrate is used as a carrier, separation may include debonding the plurality of structures 1' from the carrier 22.

[0052] refer to Figure 4K After separation, the plurality of semiconductor packaging devices 1' are erected, for example, rotated 90 degrees, and bonded to the carrier 16 via the dielectric layer 13. The erected multilayer structure 1' includes a plurality of conductive walls 10 and 11, a plurality of insulating walls 12 and 19, and a semiconductor wall 17. Each pair of adjacent conductive walls 10 and 11 are separated from each other by an insulating wall 12 disposed therebetween. In some embodiments, the carrier 16 may comprise an oxide, such as silicon dioxide. The dielectric layer may comprise oxides (e.g., silicon oxide or titanium dioxide), nitrides (e.g., silicon nitride), polyimide, carbon nanofibers, or one or more other suitable materials as described above. Bonding may comprise hybrid bonding. Hybrid bonding comprises applying heat to form hydrogen covalent bonds between the carrier 16 and the dielectric layer 13. Compared to metallic bonding, hybrid bonding according to the invention can be performed at relatively lower temperatures. Furthermore, hybrid bonding can reduce the use of solder and adhesive.

[0053] refer to Figure 4LA via 14O is formed in a portion 132 of the dielectric layer 13. The via 14O penetrates the portion 132 of the dielectric layer 13 and exposes a corresponding portion of the conductive wall 10.

[0054] refer to Figure 4M A conductive layer (electrode) 14 is formed on the dielectric layer 13, wherein conductive vias are formed in the vias 14O. The electrode 14 is electrically connected to each conductive wall in the conductive wall 10 through corresponding conductive vias in the conductive vias. The electrode 14 may be a redistribution layer.

[0055] refer to Figure 4N ,exist Figure 4M A passivation layer 18 is formed on the structure and the passivation layer covers the structure. The passivation layer 18 is formed on a portion 132 of the dielectric layer 13. Then, a via 15O is formed in the passivation layer 18 and the portion 132 of the dielectric layer 13. The via 15O penetrates the passivation layer 18 and the portion 132 of the dielectric layer 13 and exposes a corresponding portion of the conductive wall 11.

[0056] refer to Figure 4O A conductive layer (electrode) 15 is formed on the passivation layer 18, wherein conductive vias are formed in the vias 15O. Electrode 15 is electrically connected to each conductive wall in the conductive wall 11 through corresponding conductive vias in the conductive vias. Electrode 15 may be a redistribution layer. Electrode 14 and electrode 15 are electrically isolated from each other. Although not in Figure 4N and 4O As shown, however, conductive vias can be formed penetrating the passivation layer 18, and these vias can be connected to the electrode 14, thus allowing the electrode 14 to be connected to an external power source. Following the above process, the following is achieved: Figure 1 Semiconductor packaging equipment 1.

[0057] In some comparative processes for manufacturing semiconductor packaging devices containing capacitor structures, two comb-shaped electrodes with intersecting fingers are formed, and an insulating layer is placed between the electrodes to prevent short circuits. A dielectric layer (such as SiN) can be used as a sacrificial layer to define the location of the second electrode. After the first electrode and insulating layer are formed, the dielectric layer is removed, and then metal is filled to form the second electrode. However, when high capacitance is required, a high aspect ratio can make the process of removing the dielectric layer and filling the metal difficult to implement. If a dielectric layer remains, reliability issues may arise. However, during the manufacturing of the semiconductor packaging device according to this disclosure, it is not necessary to remove the sacrificial layer and it is not necessary to fill the metal material, and the electrodes can be formed, for example, by using only two photomask processes. Therefore, the process for manufacturing the semiconductor packaging device according to the present invention is easier and cheaper than the comparative processes. The semiconductor packaging device according to this disclosure is more stable and can reduce the possibility of electrode breakage due to the removal of the dielectric layer, etc.

[0058] Figure 5A An enlarged cross-sectional view of a stacked structure according to some embodiments of the present disclosure is shown. Prior to forming the conductive walls 10 and 11 and the insulating walls 12 and 19 of the stacked structure, the stacked structure can be patterned according to… Figure 4A to 4G The operations shown are formed. For example... Figure 5A As shown, the resulting stacked structure has a bump-and-dip pattern. Patterning can be performed, for example, by plasma etching. The bump-and-dip pattern can increase the contact surface area, thereby enhancing the bonding of the insulating walls 12 and 19, the conductive walls 10 and 11, and the carrier 22.

[0059] Figure 5B An enlarged cross-sectional view of a stacked structure according to some embodiments of the present disclosure is shown. Figure 5B The stacked structure shown in the lower part and Figure 4I The stacked structure shown is similar. Figure 5B The lower part shows Figure 5B An enlarged cross-sectional view of the dashed rectangle on the upper part. (See example...) Figure 5B As shown in the upper part, in Figure 4I Following the demonstrated operation, the stacked structure is divided into several individual units, the bottom of which is connected to the carrier 22. In some embodiments, the individual units can be... Figures 4A to 4I The illustrated operation is formed. In some embodiments, individual units can be formed by depositing each of insulating layers 12 and 19 and conductive layers 10 and 11 on a predetermined region of carrier 22 using atomic layer deposition (ALD). Individual units can be separated from each other through spaces S1, S2, and S3 without deposited layers. When using ALD, the sides of the stacked structure can be flat; in other words, insulating walls 12 and 19 and conductive walls 10 and 11 can be substantially coplanar along the sides of the stacked structure.

[0060] Figure 5C An enlarged cross-sectional view of a stacked structure according to some other embodiments of the present disclosure is shown. Figure 5C The stacked structure shown in the lower part and Figure 4I The stacked structure shown is similar. The stacked structure can be divided into individual units, for example, by laser grooving. Laser grooving can be performed using plasma. Therefore, after laser grooving, the stacked structure has relatively rough sides, and the recesses formed by the laser grooving gradually taper from the top to the far end of the stacked structure.

[0061] Figures 6A to 6B Various stages of a method for manufacturing a packaging structure according to some embodiments of the present disclosure are shown.

[0062] refer to Figure 6A A substrate 60 with openings O1 and O2 is provided. The substrate 60 may be a wafer, a redistribution layer, etc.

[0063] refer to Figure 6B It can Figure 1 The semiconductor packaging device 1 is respectively placed in openings O1 and O2 to form a packaging structure. Figure 1 The semiconductor packaging device 1 can be embedded in the substrate 60. Since the semiconductor packaging device 1 has an anode and cathode exposed from the upper surface of the carrier 60, it is not necessary to prepare circuitry for connection to the semiconductor packaging device 1 within the substrate. Furthermore, as discussed above, the size of the semiconductor packaging device 1 can be adjusted as needed, making it more flexible for use in various applications.

[0064] Unless otherwise stated, spatial descriptions such as “above,” “below,” “up,” “left,” “right,” “lower,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “above,” and “below” are indications of the orientation shown in the accompanying drawings. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that such arrangement does not deviate from the advantages of the embodiments of this disclosure.

[0065] As used herein, the terms “approximately,” “substantially,” “basically,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to instances where the event or situation occurred precisely or instances where the event or situation was close to occurring. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if a first numerical value is within a range of variation less than or equal to ±10% of a second numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first numerical value may be considered “substantially” the same as or equal to the second numerical value. For example, "basically" vertical can refer to an angle variation range of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0066] If the displacement between two surfaces is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, the two surfaces can be considered coplanar or substantially coplanar. If the displacement between the highest and lowest points of a surface is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, the surface can be considered substantially flat.

[0067] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include plural referents.

[0068] As used herein, the terms “conductive,” “electrically conductive,” and “electrical conductivity” refer to the ability to conduct electric current. Conductive materials generally refer to those materials that offer little or no obstruction to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, conductive materials are those with a conductivity greater than about 10. 4 S / m, such as at least 10 5 S / m or at least 10 6 Conductive materials with conductivity of S / m. The conductivity of the material may sometimes vary with temperature. Unless otherwise stated, the conductivity of the material is measured at room temperature.

[0069] In addition, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that this range format is used for convenience and brevity and should be flexibly interpreted to include not only the numerical values ​​that are explicitly specified as the limits of the range, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0070] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes may be made and equivalents may be substituted without departing from the spirit and scope of this disclosure as defined by the claims. Illustrations may not necessarily be drawn to scale. There may be differences between artistic representations in this disclosure and actual devices due to manufacturing processes and tolerances. Other embodiments of this disclosure may exist that are not specifically shown. The description and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or rearranged to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless expressly indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. A semiconductor packaging apparatus, comprising: First conductive wall; Second conductive wall; A first insulating wall is disposed between the first conductive wall and the second conductive wall; A dielectric layer having a first portion covering the bottom surface of the first conductive wall, the bottom surface of the second conductive wall, and the bottom surface of the first insulating wall; The first electrode is electrically connected to the first conductive wall; as well as The second electrode is electrically connected to the second conductive wall. The first conductive wall, the second conductive wall, and the first insulating wall are encapsulated by the dielectric layer.

2. The semiconductor packaging apparatus of claim 1, wherein the dielectric layer has a second portion covering the upper surface of the first conductive wall, the upper surface of the second conductive wall, and the upper surface of the first insulating wall.

3. The semiconductor packaging apparatus of claim 1, further comprising a carrier, wherein the first portion of the dielectric layer is disposed between the carrier and the bottom surface of the first conductive wall, the bottom surface of the second conductive wall, and the bottom surface of the first insulating wall.

4. The semiconductor packaging apparatus of claim 1, further comprising a second insulating wall disposed adjacent to the first conductive wall.

5. The semiconductor packaging apparatus of claim 4, further comprising a semiconductor wall arranged adjacent to the second insulating wall.

6. The semiconductor packaging apparatus of claim 1, wherein the bottom surface of the first conductive wall, the bottom surface of the second conductive wall, and the bottom surface of the first insulating wall are substantially coplanar.

7. The semiconductor packaging apparatus of claim 2, wherein the upper surface of the first conductive wall, the upper surface of the second conductive wall, and the upper surface of the first insulating wall are substantially coplanar.

8. The semiconductor packaging apparatus of claim 1, wherein the insulating wall, the first conductive wall, and the second conductive wall have an uneven structure.

9. A semiconductor packaging apparatus, comprising: First conductive wall; Second conductive wall; An insulating wall is disposed between the first conductive wall and the second conductive wall; A dielectric layer covering the upper surface of the first conductive wall, the upper surface of the second conductive wall, and the upper surface of the insulating wall; The first conductive via penetrates the dielectric layer and contacts the first conductive wall; The second conductive via penetrates the dielectric layer and contacts the second conductive wall; The first electrode is electrically connected to the first conductive wall through the first conductive through-hole; as well as The second electrode is electrically connected to the second conductive wall through the second conductive via, wherein the first conductive wall, the second conductive wall, and the insulating wall are encapsulated by the dielectric layer.

10. The semiconductor packaging apparatus of claim 9, wherein the first electrode and the second electrode are at the same elevation.

11. The semiconductor packaging apparatus of claim 9, wherein the first electrode and the second electrode are at different elevations.

12. The semiconductor packaging apparatus of claim 9, wherein the first electrode is electrically connected to a set of first conductive walls, and the second electrode is electrically connected to a set of second conductive walls.

13. The semiconductor packaging apparatus of claim 9, wherein the first electrode and the second electrode are electrically connected to the anode and cathode of an external power supply, respectively.

14. The semiconductor packaging apparatus of claim 9, further comprising a passivation layer disposed on the dielectric layer.

15. The semiconductor packaging apparatus of claim 14, wherein the first electrode is encapsulated by the passivation layer.

16. The semiconductor packaging apparatus of claim 9, further comprising a third electrode and a fourth electrode, the third electrode being electrically connected to the first electrode and the fourth electrode being electrically connected to the second electrode, wherein the first electrode and the fourth electrode are respectively connected to the anode and cathode of an external power supply.

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