Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the same include a semiconductor device of a fin field effect transistor including: a first gate structure extending in a first direction; a second gate structure extending in the first direction and aligned with the first gate structure in the first direction; a third gate structure extending in the first direction and arranged in parallel with the first gate structure in a second direction crossing the first direction; a fourth gate structure extending in the first direction and aligned with the third gate structure and arranged in parallel with the second gate structure; an interlayer dielectric layer disposed between the first to fourth gate structures; and a separation wall made of a material different from the interlayer dielectric layer and disposed between the first and second gate structures and the third and fourth gate structures.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device having a fin field-effect transistor and a method for manufacturing the same. Background Technology

[0002] As the semiconductor industry moves towards nanoscale process nodes in pursuit of higher device density, higher performance, and lower costs, challenges in manufacturing and setup have led to the development of three-dimensional designs such as FinFETs. FinFET devices typically feature semiconductor fins with high aspect ratios, forming the channels and source / drain regions of the transistor. Taking advantage of the increased surface area of ​​the channels and source / drain regions, gates are formed above the fin structure and along its sides (e.g., around the fins) to produce faster, more reliable, and better-controlled transistor devices. Metal gate structures, along with high-k gate dielectrics, are frequently used in FinFET devices and are manufactured via gate substitution techniques. Summary of the Invention

[0003] Some embodiments of this disclosure provide a semiconductor device including a fin field-effect transistor, comprising: a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, an interlayer dielectric layer, and a spacer. The first gate structure extends along a first direction. The second gate structure extends in the first direction and is aligned with the first gate structure in the first direction. The third gate structure extends in the first direction and is parallel to the first gate structure in a second direction intersecting the first direction. The fourth gate structure extends in the first direction, is aligned with the third gate structure, and is parallel to the second gate structure. The interlayer dielectric layer is disposed between the first and fourth gate structures. The spacer is made of a different material than the interlayer dielectric layer and is disposed between the first and second gate structures and the third and fourth gate structures.

[0004] Some embodiments of this disclosure provide a semiconductor device comprising: a plurality of fin structures, a plurality of gate structures, and a plurality of partition walls. The plurality of fin structures extend in a first direction and are arranged in a second direction intersecting the first direction. The plurality of gate structures extend in the second direction and are arranged in the first direction. The plurality of partition walls separate one pair of gate structures from another pair of gate structures, wherein the plurality of partition walls are arranged in an alternating manner.

[0005] Some embodiments of this disclosure provide a method for manufacturing a semiconductor device, comprising: forming a pair of sacrificial gate structures over a plurality of channel regions formed over a substrate, each of the pair of sacrificial gate structures including a sacrificial gate electrode layer, a sacrificial gate dielectric layer, and a plurality of sidewall spacers disposed on two sides of the sacrificial gate electrode layer; forming a plurality of interlayer dielectric layers at the two sides of the pair of sacrificial gate structures; patterning the pair of sacrificial gate structures and dielectric layers such that the pair of sacrificial gate structures are divided into a first sacrificial gate structure and a second sacrificial gate structure by at least a partition opening, and further divided into a third sacrificial gate structure and a fourth sacrificial gate structure by the partition opening; forming a partition wall via a first insulating material and a non- A second insulating material, identical to the first insulating material, fills the separating opening; a sacrificial gate electrode layer and a sacrificial gate dielectric layer are removed from the first to fourth sacrificial gate structures, thereby forming a first electrode space and a second electrode space, and a separating wall is exposed between the first electrode space and the second electrode space, and a third electrode space and a fourth electrode space are formed, and a separating wall is exposed between the third electrode space and the fourth electrode space; and a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure are respectively formed in the first electrode space, the second electrode space, the third electrode space, and the fourth electrode space, wherein, during the removal of the sacrificial gate dielectric layer, multiple portions of the first insulating material exposed in the first to fourth electrode spaces are removed. Attached Figure Description

[0006] This disclosure may be described in the following detailed description, and in conjunction with the appendix. Figure 1 Read carefully for the best understanding. It should be emphasized that, according to industry standard practice, the features are not drawn to scale and are for illustrative purposes only. In fact, features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 A cross-sectional view is shown of one of the stages of a sequential process for manufacturing a field-effect transistor device according to an embodiment of the present disclosure.

[0008] Figure 2 A cross-sectional view is shown of one of the stages of a sequential process for manufacturing a field-effect transistor device according to an embodiment of the present disclosure.

[0009] Figure 3 A cross-sectional view is shown of one of the stages of a sequential process for manufacturing a field-effect transistor device according to an embodiment of the present disclosure.

[0010] Figure 4A , Figure 4B , Figure 4C,and Figure 4D Views are shown of various stages of a sequential process for manufacturing a field-effect transistor device according to an embodiment of this disclosure.

[0011] Figure 5A , Figure 5B ,and Figure 5C Views are shown of various stages of a sequential process for manufacturing a field-effect transistor device according to an embodiment of this disclosure.

[0012] Figure 6A , Figure 6B , Figure 6C ,and Figure 6D Views are shown of various stages of a sequential process for manufacturing a field-effect transistor device according to various embodiments of this disclosure.

[0013] Figure 7A and Figure 7B Views are shown of various stages of a sequential process for manufacturing a field-effect transistor device according to an embodiment of this disclosure.

[0014] Figure 8A and Figure 8B Views are shown of various stages of a sequential process for manufacturing a field-effect transistor device according to an embodiment of this disclosure.

[0015] Figure 9A and Figure 9B Views are shown of various stages of a sequential process for manufacturing a field-effect transistor device according to an embodiment of this disclosure.

[0016] Figure 10A , Figure 10B , Figure 10C ,and Figure 10D Views are shown of various stages of a sequential process for manufacturing a field-effect transistor device according to an embodiment of this disclosure.

[0017] Figure 11A and Figure 11B The structure of a semiconductor device according to one embodiment of the present disclosure is shown;

[0018] Figure 11C , Figure 11D ,and Figure 11E The structure of the partition wall according to several embodiments of this disclosure is shown;

[0019] Figure 12A cross-sectional view of a field-effect transistor device according to another embodiment of this disclosure is shown;

[0020] Figure 13 A cross-sectional view of a field-effect transistor device according to another embodiment of this disclosure is shown.

[0021] [Symbol Explanation]

[0022] 10:Substrate

[0023] 100: Mask layer

[0024] 105: Gate insulating layer

[0025] 106: Pad oxide layer

[0026] 107: Silicon nitride masking layer

[0027] 110: Sacrificial gate layer

[0028] 120: Masking Pattern

[0029] 125: Opening

[0030] 130: Separating opening

[0031] 140: Thin filler insulation layer

[0032] 145: Gate opening

[0033] 150: Thick filler insulation layer

[0034] 155: Partition wall

[0035] 160: Gate dielectric layer

[0036] 160': Gate dielectric layer

[0037] 170: Gate electrode layer

[0038] 170': Gate electrode layer

[0039] 20: Fin structure

[0040] 22: Passage Area

[0041] 50: Insulating layer

[0042] 51: Surface portion

[0043] 70: Interlayer dielectric layer

[0044] 80: Sidewall insulation layer

[0045] 90: Contact Etching Stop Layer

[0046] B1: Closed section

[0047] B2: Closed section

[0048] B3: Area

[0049] B4: Area

[0050] B5: Line

[0051] H1: Height

[0052] W1: Width

[0053] W2: Width

[0054] W3: Width

[0055] W4: Width

[0056] W5: Width

[0057] W6: Prominence

[0058] X1-X1: Line

[0059] Y1-Y1: Line Detailed Implementation

[0060] It is understood that the following disclosure provides many different implementations or embodiments for achieving various features of this disclosure. Specific implementations or embodiments of components and configurations are described below to simplify this disclosure. Of course, these are merely embodiments and are not intended to be limiting. For example, the dimensions of elements are not limited to the disclosed range or values, but may depend on the process conditions and / or desired characteristics of the device. Furthermore, in the following description, forming a first feature above or on a second feature may include implementations where the first and second features are formed in direct contact, and may also include implementations where additional features may be formed between the first and second features, thus the first and second features may not be in direct contact. For simplicity and clarity, the various features may be drawn arbitrarily at different scales.

[0061] Furthermore, this document may use spatially relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms to facilitate description of the relationship between one element or feature as illustrated in the accompanying drawings and another (or more) element or feature. In addition to the orientations illustrated in the accompanying drawings, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may have other orientations (rotated 90 degrees or other directions), and the spatially relative terms used herein may be interpreted accordingly. Furthermore, the term “made of” may mean either “comprising” or “consisting of.” In this disclosure, the phrase “one of A, B, and C” refers to “A, B, and / or C” (A; B; C; A and B; A and C; B and C; or A, B, and C), and does not mean that one element is from A, one element is from B, and one element is from C, unless otherwise stated. Throughout this disclosure, the terms "source" and "drain" are used interchangeably, and "source / drain" refers to one or both of the source and drain.

[0062] Figures 1 to 10D Multiple cross-sectional and / or plan views of a sequential fabrication process of a semiconductor device, such as a field-effect transistor, according to one embodiment of this disclosure are shown. It is understood that... Figures 1 to 10D Additional operations are provided before, during, and after the process shown, and for additional implementations of the method, some of the operations described below may be substituted or omitted. The order of operations / processes may be interchangeable.

[0063] Figure 1 A cross-sectional view is shown according to some embodiments of the present disclosure, wherein fin structures 20 are formed above substrate 10.

[0064] Substrate 10 is, for example, a p-type silicon substrate, having an impurity concentration of about 1 × 10⁻⁶. 15 cm -3 Approximately 5×10 15 cm -3 Within the range. In other embodiments, the substrate is an n-type silicon substrate with an impurity concentration ranging from about 1 × 10⁻⁶. 15 cm -3 Approximately 5×10 15 cm -3 Within the range.

[0065] Alternatively, substrate 10 may comprise another elemental semiconductor, such as germanium; a compound semiconductor including group IV-IV compound semiconductors, such as SiC and SiGe; group III-V compound semiconductors, such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In one embodiment, substrate 10 is a silicon layer of an SOI (silicon-on-insulator) substrate. When using a silicon-on-insulator substrate, the fin structure may protrude from the silicon layer of the silicon-on-insulator substrate or may protrude from the insulating layer of the silicon-on-insulator substrate. In the latter case, the silicon layer of the silicon-on-insulator substrate is used to form the fin structure. Amorphous substrates, such as amorphous Si or amorphous SiC, or insulating materials, such as silicon oxide, may also be used as substrate 10. The substrate 10 may include various regions that have been appropriately doped with impurities (e.g., p-type or n-type conductivity).

[0066] The fin structure 20 can be patterned using any suitable method. For example, one or more lithography processes, including dual or multiple patterning processes, may be used to pattern the fin structure. Typically, dual or multiple patterning processes combine lithography and self-alignment processes to allow the creation of patterns with, for example, a spacing smaller than that achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed and patterned over a substrate using a lithography process. Spacers are formed along the sides of the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin structure. In some embodiments, the remaining spacers are used to pattern the hard mask layer 100, and the substrate is patterned via the patterned hard mask layer 100.

[0067] The hard mask layer 100 includes, for example, in some embodiments, a pad oxide (e.g., silicon oxide) layer 106 and a silicon nitride mask layer 107. The pad oxide layer 106 may be formed via a thermal oxidation or chemical vapor deposition process. The silicon nitride mask layer 107 may be formed via physical vapor deposition (PVD) (such as sputtering), chemical vapor deposition (such as plasma-enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), high density plasma chemical vapor deposition (HDPCVD)), atomic layer deposition (ALD), and / or other processes.

[0068] In some embodiments, the thickness of the pad oxide layer 106 is in the range of about 2 nanometers (nm) to about 15 nanometers, and the thickness of the silicon nitride mask layer 107 is in the range of about 2 nanometers to about 50 nanometers. The substrate 10 is patterned into the fin structure 20 by using the hard mask layer 100 (hard mask pattern) as an etching mask, via trench etching using dry etching and / or wet etching methods.

[0069] In one embodiment, the fin structure 20 disposed above the substrate 10 is made of the same material as the substrate 10 and extends continuously from the substrate 10. The fin structure 20 may be intrinsic or appropriately doped with n-type or p-type impurities.

[0070] exist Figure 1 Four fin structures 20 are provided. These fin structures are used for p-type fin field-effect transistors and / or n-type fin field-effect transistors. The number of fin structures 20 is not limited to four. This number may be reduced to one or more. In addition, in some embodiments, one or more dummy fin structures are disposed adjacent to both sides of the fin structure to improve pattern fidelity in the patterning process. The width W1 of the fin structure 20 is in the range of about 5 nanometers to about 40 nanometers in some embodiments, and in the range of about 7 nanometers to about 20 nanometers in some embodiments. The height H1 of the fin structure 20 is in the range of about 100 nanometers to about 300 nanometers in some embodiments, and in the range of about 50 nanometers to 100 nanometers in other embodiments. When the heights of the multiple fin structures 20 are inconsistent, the height from the substrate may be measured from a plane corresponding to the average height of the fin structure.

[0071] Then, as in Figure 2 As shown, an insulating material layer is formed above the substrate 10 to form an insulating layer 50 to completely cover the fin structure 20.

[0072] The insulating material used for the insulating layer 50 is made of, for example, silicon dioxide, formed via LPCVD (low-pressure chemical vapor deposition), plasma chemical vapor deposition, or flow-through chemical vapor deposition. In flow-through chemical vapor deposition, a flowable dielectric material is deposited instead of silicon oxide. As the name suggests, the flowable dielectric material can "flow" during the deposition process to fill gaps or spaces with a high aspect ratio. Typically, various chemicals are added to silicon-containing precursors to make the deposited film flowable. In some embodiments, nitrogen hydride bonds are added. Examples of flowable dielectric precursors, particularly flowable silicon oxide precursors, include silicates, siloxanes, methyl silsesquioxane (MSQ), hydrogen silsesquioxane (HSQ), methyl silsesquioxane / hydrogen silsesquioxane (MSQ / HSQ), perhydrosilazane (TCPS), perhydro-polysilazane (PSZ), tetraethyl orthosilicate (TEOS), or silyl-amine, such as trisilylamine (TSA). These flowable silicon oxide materials are formed in a multi-stage process. After depositing the flowable film, the flowable film is cured and then annealed to remove unwanted elements to form the silicon oxide. When the unwanted elements are removed, the flowable film densifies and shrinks. In some embodiments, multiple annealing processes are performed. The flowable film is cured and annealed once or more. The insulating layer 50 may be SOG, SiO, SiON, SiOCN, or fluorine-doped silicate glass (FSG). The insulating layer 50 may be doped with boron and / or phosphorus.

[0073] After forming the insulating layer 50, a planarization operation is performed to remove the upper portion of the insulating layer 50 and the masking layer 100, which includes a pad oxide layer 106 and a silicon nitride masking layer 107. Then, the insulating layer 50 is further removed, thereby exposing the upper portion of the fin structure 20 (which will become the channel region), as shown in... Figure 3 As shown in the image.

[0074] After the insulating layer 50 is formed, optionally, a heat treatment, such as annealing, is performed to improve the quality of the insulating layer 50. In some embodiments, a thermal process is performed by using rapid thermal annealing (RTA) for about 1.5 seconds to about 10 seconds in an inert gas environment (e.g., N2, Ar, or He environment) at a temperature ranging from about 900°C to about 1050°C.

[0075] After exposing the upper portion of the fin structure 20 from the isolation insulating layer 50, a sacrificial gate insulating layer 105 and a polysilicon layer are formed over the isolation insulating layer 50 and the exposed fin structure 20. Then, operations are performed to obtain a sacrificial gate layer 110 made of polysilicon, as shown in... Figures 4A to 4D As shown in the diagram. The sacrificial gate insulating layer 105 may be silicon oxide, formed via chemical vapor deposition, physical vapor deposition, atomic layer deposition, electron beam evaporation, or other suitable processes. In some embodiments, the thickness of the polysilicon layer ranges from about 5 to about 100 nanometers. Figures 9A to 10D In the described gate replacement technique, both the sacrificial gate insulating layer 105 and the sacrificial gate layer 110 are dummy layers, which are subsequently removed.

[0076] After the polysilicon layer is patterned, sidewall insulating layers 80 (gate sidewall spacers) are also formed on both sides of the sacrificial gate layer 110. The sidewall insulating layers 80 are made of one or more silicon oxide or silicon nitride-based materials, such as SiN, SiCN, SiON, or SiOCN. In one embodiment, silicon nitride is used.

[0077] In some embodiments, after forming the sidewall insulating layer 80, an insulating layer to be used as a contact etch stop layer (CESL) 90 is formed over the sacrificial gate layer 110 (polysilicon layer) and the sidewall insulating layer 80. The contact etch stop layer 90 is made of one or more layers of silicon oxide or silicon nitride-based materials, such as SiN, SiCN, SiON, or SiOCN. In one embodiment, a silicon nitride is used.

[0078] Furthermore, an interlayer dielectric (ILD) 70 is formed in the space between the plurality of sacrificial gate layers 110 (and the sidewall insulating layer 80 and the contact etch stop layer 90), and above the sacrificial gate layers 110. The interlayer dielectric 70 may comprise silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, fluorine-doped silicate glass (FSG), or a low-dielectric-constant dielectric material, and may be fabricated by chemical vapor deposition or other suitable processes. The insulating material used for the isolation insulating layer 50 may be the same as or different from the insulating material used for the interlayer dielectric 70.

[0079] Perform planarization operations, such as etch-back processes and / or chemical mechanical polishing (CMP) processes, to achieve a result similar to that in... Figures 4A to 4D The structure shown. Figure 4A This is a plan view (top view) of a fin field-effect transistor device after the formation of the sacrificial gate layer 110 and the interlayer dielectric layer 70 and the execution of a chemical mechanical polishing operation. Figure 4B It is a perspective view. Figures 1 to 3 and Figure 4C Corresponding to along in Figure 4A The cross-sectional view of line X1-X1 in the middle. Figure 4D Corresponding to along in Figure 4A A cross-sectional view of line Y1-Y1 in the diagram, and Figure 4B Corresponding to in Figure 4A The closed portion B1. Figure 4A Figure 4B In the text, the contact etch stop layer 90 is omitted.

[0080] As in Figure 4A and Figure 4B As shown, multiple sacrificial gate layers 110 are formed in a line-and-space arrangement extending in one direction (X direction) and spaced at a certain spacing. The sacrificial gate layers 110 may include another line-and-space arrangement extending in another direction (Y direction) perpendicular to this one direction, and another line-and-space arrangement with different dimensions.

[0081] A sacrificial gate layer 110 covers the channel region of the fin field-effect transistor, which forms a fin structure 20. In other words, the sacrificial gate layer 110 is formed above the channel region. Through appropriate source / drain fabrication operations, the fin structure not covered by the gate layer will become the source / drain region.

[0082] Next, as in Figures 5A to 5C As shown, in Figures 4A to 4D A masking pattern 120 is formed above the structure shown. Figure 5A It corresponds to in Figure 4A The cross-sectional view of line X1-X1 in the middle. Figure 5B It corresponds to in Figure 4A A cross-sectional view of line Y1-Y1 in the diagram, and Figure 5CIt is a top view. The mask pattern 120 is formed of a material having a high etch selectivity relative to, for example, polysilicon. In one embodiment, the mask pattern 120 is made of silicon nitride. The mask pattern 120 has an opening 125. Depending on the pitch of the gate structures, in some embodiments, the width W3 of the opening 125 in the X direction ranges from about 5 nanometers to about 100 nanometers, while in other embodiments it ranges from about 10 nanometers to 30 nanometers. The width W2 of the opening 125 in the Y direction is adjusted to expose a desired number of gate structures. In Figure 5C it, the width of the opening 125 in the Y direction is such a length that two gate structures are exposed in the opening 125, and multiple edges of the opening in the Y direction are located between multiple adjacent gate structures above the interlayer dielectric layer 70. In some embodiments, the width W2 satisfies 2L + S < W2 < 2L + 3S, where L is the width of the gate structure and S is the space between multiple adjacent gate structures. In other embodiments, the opening 125 is disposed above three or more gate structures, such as three, four, five, or six gate structures. Depending on the pitch of the fin structures, in some embodiments, the width W2 of the opening 125 in the Y direction ranges from about 10 nanometers to about 50 nanometers, and in other embodiments it ranges from about 15 nanometers to 30 nanometers.

[0083] Then, as shown in Figure 6A and Figure 6B it, by using the mask pattern 120 as an etch mask, the sacrificial gate layer 110, the gate insulating layer 105, the sidewall insulating layer (gate sidewall spacer) 80, the contact etch stop layer 90, and a portion of the interlayer dielectric layer 70 are removed to obtain a separation opening 130 that separates the sacrificial gate layer 110. In some embodiments, the etching of the gate layer is performed via plasma etching, and the plasma etching uses a gas including CH4, CF4, CH2F2, CHF3, O2, HBr, Cl2, NF3, N2, and / or He at a pressure of 3 to 20 mTorr. Since each material is etched, in some embodiments, the etching operation includes multiple etching operations using different etchants. The etching operation includes one or more wet etching and / or dry etching operations.

[0084] The etching to form the separation opening 130 is accompanied by etching an oxide layer (etching conditions are different from polysilicon etching and / or silicon nitride etching), and the oxide layer includes the gate insulating layer 105. During the oxide etching, in some embodiments, as shown in Figure 6A [[ID=​​

[0085] It should be noted that the cross-sectional view of the partition opening 130 is in Figure 6A The opening has a rectangular shape, but in some embodiments, the dividing opening 130 has a tapered shape with a larger top dimension and a smaller bottom dimension. Further, as in... Figure 6B As shown, the sidewall insulating layer 80 and the contact etch stop layer 90 are not retained in the separation opening 130.

[0086] In addition, such as in Figure 6C and Figure 6D As shown, the bottom of the separating opening 130 has a protrusion and a recess reflecting the gate structure. In some embodiments, such as in Figure 6C As shown, the bottom of the separating opening 130 includes a protrusion at a location corresponding to the gate structure, and in other embodiments, such as in Figure 6D As shown, the bottom of the separator opening 130 includes a recess at a location corresponding to the gate structure. In some embodiments, the unevenness of the bottom of the separator opening 130 ranges from about 5 nanometers to about 20 nanometers (maximum-minimum).

[0087] Then, as in Figure 7A and Figure 7B As shown, in Figure 6A and Figure 6B A thin filling insulation layer 140 and a thick filling insulation layer 150 are formed on the top of the resulting structure.

[0088] The thin filler insulating layer 140 is made of, for example, the same material as the gate insulating layer 105. In this embodiment, silicon oxide is used. The thin filler insulating layer 140 is formed via chemical vapor deposition or atomic layer deposition. In some embodiments, atomic layer deposition is employed. In some embodiments, atomic layer deposition is performed at a substrate temperature ranging from about 25°C (room temperature) to about 400°C, and in other embodiments, the temperature ranges from about 65°C to 150°C, depending on the desired thickness and / or coverage of the thin insulating layer. In some embodiments, atomic layer deposition is performed at a pressure ranging from about 1500 mTorr to about 4000 mTorr, depending on the desired thickness and / or coverage of the thin insulating layer. In some embodiments, a precursor (e.g., SiH4, Si2H6, O2) is provided as a gas pulse, and one cycle of the atomic layer deposition process includes a pulse supplying the Si precursor and a pulse supplying the O precursor. In some embodiments, two to 30 cycles of the atomic layer deposition process are performed, depending on the desired thickness of the thin insulating layer. In some embodiments, the surface roughness of the thin filler insulating layer 140 formed on the mask pattern 120 is in the range of about 0.1 nanometers to about 2.5 nanometers.

[0089] The thickness of the thin filler insulating layer 140 is in some embodiments ranging from about 0.5 nanometers to about 5 nanometers, and in other embodiments ranging from about 1 nanometer to about 3 nanometers. (As in...) Figure 7A and Figure 7B As shown, a thin filling insulating layer 140 is conformally formed in the separating opening 130 and above the mask pattern 120.

[0090] The thick filler insulating layer 150 is made of a different material than the thin filler insulating layer 140 and includes silicon nitride-based materials such as SiN, SiCN, SiON, or SiOCN. In one embodiment, silicon nitride is used. The thick filler insulating layer 150 is formed via chemical vapor deposition or atomic layer deposition. In some embodiments, atomic layer deposition is used. The thick filler insulating layer 150 is conformally formed in the separation opening 130 and over the thin filler insulating layer 140 above the mask pattern 120. In some embodiments, the bottom of the thin filler insulating layer 140 has an unevenness that reflects the unevenness of the bottom of the separation opening 130.

[0091] After the separating opening 130 is filled with a thin filler insulating layer 140 and a thick filler insulating layer 150, a planarization operation such as chemical mechanical polishing is performed to expose the upper surface of the sacrificial gate layer 110, as shown in Figure 8A and Figure 8BAs shown in the diagram. In other words, the function of the sacrificial gate layer 110 serves as a stop element in the chemical mechanical polishing process. Through this planarization operation, the partition wall 155 is formed.

[0092] After planarization to expose the sacrificial gate layer 110, the sacrificial gate layer 110 and the sacrificial gate insulating layer 105 are removed by dry etching and / or wet etching, thereby forming the gate opening 145, as shown in Figure 9A and Figure 9B As shown in the diagram. During the removal of the sacrificial gate insulating layer 105, since the thin fill insulating layer 140 is made of the same material as the sacrificial gate insulating layer 105 (e.g., silicon oxide), the portion of the thin fill insulating layer 140 exposed to the etching process is also removed. Figure 9A As shown, the thin fill insulating layer 140 that has been disposed between the sacrificial gate layer 110 and the thick fill insulating layer 150 is removed.

[0093] Next, as in Figures 10A to 10D As shown, a metal gate structure is formed, which includes a metal gate dielectric layer 160 and a metal gate electrode layer 170.

[0094] In some embodiments, the gate dielectric layer 160 comprises one or more layers of dielectric material, such as silicon oxide, silicon nitride, or high-dielectric-constant dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-dielectric-constant dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, other suitable high-dielectric-constant dielectric materials, and / or combinations thereof.

[0095] The metal gate electrode layer 170 includes any suitable material, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof.

[0096] In some embodiments, one or more work function adjustment layers (not shown) are also disposed between the gate dielectric layer 160 and the metal gate electrode layer 170. The work function adjustment layer is made of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials. For n-type channel field-effect transistors, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the work function adjustment layer, and for p-type channel field-effect transistors, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used as the work function adjustment layer. The work function adjustment layer may be formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition, electron beam evaporation, or other suitable processes. Furthermore, for n-channel fin field-effect transistors and p-channel fin field-effect transistors that may use different metal layers, the work function adjustment layer may be formed separately.

[0097] When forming a metal gate structure, the gate dielectric layer, the work function adjustment layer, and the gate electrode layer are formed by a suitable film formation method, such as chemical vapor deposition or atomic layer deposition for the gate dielectric layer, and chemical vapor deposition, physical vapor deposition, atomic layer deposition, or electroplating for the metal layer, and then planarization operations such as chemical mechanical polishing are performed.

[0098] In some embodiments, the gate dielectric layer 160 is in contact with a thin filler insulating layer 140, such as in Figure 10A As shown in the image.

[0099] Figure 10C and Figure 10D A top view is shown after the metal gate structure has been formed. Figure 10D Is Figure 10C An enlarged view of the closed portion B2 in the image. (See also...) Figure 10C and Figure 10D As shown, the metal gate structures (160, 170) are separated by a continuous partition wall 155.

[0100] As in Figure 10DAs shown, depending on the spacing of the gate structure, in some embodiments, the width W4 of the spacer 155 (including the thin filler insulating layer 140) along the X direction ranges from about 5 nanometers to about 100 nanometers, and in other embodiments, it ranges from about 10 nanometers to about 30 nanometers. The width W5 of the spacer 155 along the Y direction ranges from about 8 nanometers to about 40 nanometers, and in other embodiments, it ranges from about 12 nanometers to 25 nanometers. In some embodiments, the ratio W4 / W5 ranges from about 2 to about 5. Depending on the spacing of the gate electrodes, in some embodiments, the amount of protrusion W6 between the contact etch stop layer 90 and the end of the spacer 155 ranges from about 2 nanometers to about 10 nanometers.

[0101] What is understood is that, in Figure 10A The structure shown in 10D undergoes further CMOS (Complementary Metal-Oxide-Semiconductor) processes to form various features, such as interconnect vias, interconnect metal layers, passivation layers, etc.

[0102] In the aforementioned embodiment, the sacrificial gate layer 110 is divided into two gate layers. However, in other embodiments, via... Figures 6A to 8B The patterning operation divides the sacrificial gate layer 110 into more than two gate layers. In such a case, as in... Figure 11A As shown, multiple gate structures (each including a gate electrode layer 170) are arranged and separated by partition walls 155.

[0103] In some embodiments, a partition wall 155 separates a pair of gate electrode layers 170 (gate electrodes), as in Figure 11A As shown in the diagram. In some embodiments, the plurality of partition walls 155 are arranged in an alternating manner, as in... Figure 11A As shown in the diagram. In some embodiments, the spacing of the partition walls 155 in the X direction is approximately twice the spacing of the fin structures 20. In other embodiments, the spacing of the partition walls 155 in the X direction is approximately three or four times the spacing of the fin structures 20.

[0104] In some implementations... Figure 11A The circuit is used for static random access memory (SRAM).

[0105] Furthermore, prior to the partition etching operation, the sacrificial gate layer 110 has two ends in its longitudinal direction (X direction). In some embodiments, a partition wall 155 is formed at at least one of these ends, as in... Figure 11A As shown in region B3. In this case, the gate structure, including the gate electrode layer 170, is sandwiched between two partition walls 155. In some embodiments, partition walls 155 are present at both ends.

[0106] In other embodiments, a partition wall 155 is not formed in at least one end, as in Figure 11A As shown in region B4. In this case, one end of the gate structure including the gate electrode layer 170 has a partition wall 155, and the other end of the gate structure has as shown in Figure 11B The structure shown. Figure 11B yes Figure 11A The cross-sectional view of line B5. (As shown in...) Figure 11B As shown, the gate structure, particularly the gate dielectric layer 160, is in contact with the interlayer dielectric layer 70. In some embodiments, there are no partition walls 155 at either end. In some embodiments, the partition walls 155 formed at the ends of the gate structure have a longer width in the Y direction than the partition walls 155 formed in the regions other than the ends. In some embodiments, the partition walls 155 formed at the ends of the gate structure cover more than two gate structures (e.g., 4 to 16 gate structures).

[0107] Figures 11C to 11E A plan view of the partition wall 155 according to various embodiments is shown (only the thick filler insulation layer portion is shown). In some embodiments, such as in Figure 11C As shown, the partition wall 155 has a rectangular shape with rounded corners. In other embodiments, the partition wall 155 has a rectangular main body and two semi-elliptical or semi-circular ends, as shown in... Figure 11D As shown in the diagram. In other embodiments, the partition wall 155 has an elliptical shape, as in... Figure 11E As shown in the diagram, the width of the partition wall is its maximum length in both the X and Y directions.

[0108] In other embodiments, the sacrificial gate insulating layer 105 is not a dummy layer and is made of a dielectric material ultimately used in the field-effect transistor device. In such cases, the high dielectric constant dielectric material described above can be used. When the gate insulating layer 105 is not a dummy layer, it may be made of a different material than the thin fill insulating layer 140. Regarding... Figures 9A to 9B In the operation, the gate insulating layer 105 (e.g., a high dielectric constant dielectric material) is not removed from the gate opening 145. Then, an additional operation is performed to remove the thin fill insulating layer 140 to obtain a result similar to... Figure 9A The structure, except for the presence of the gate insulating layer 105, is as follows: In this case, the metal gate electrode layer 170 contacts the separator wall 155, as in... Figure 12 As shown, because of the gate dielectric layer 160 (see...) Figure 10A The formation of ) is not necessary.

[0109] In the above embodiments, finned field-effect transistors are used. However, the above technology can also be applied to planar field-effect transistors, such as in... Figure 13 As shown. (As in...) Figure 13 As shown, the field-effect transistor includes a channel region 22 of a semiconductor substrate and a gate structure. The gate structure includes a gate dielectric layer 160' formed above the channel region 22 and a gate electrode layer 170' formed above the gate dielectric layer 160'. The channel region is separated by an insulating layer 50, and the two gate structures are separated by a partition wall 155.

[0110] The various embodiments or examples described herein offer several advantages over the prior art. For example, since the thin filling insulating layer 140 is subsequently removed, the width of the gate space to be filled by the metal gate material in the Y direction can become larger. With the enlarged gate opening, the metal gate material, such as the metal gate electrode material, can completely fill the opening without forming voids.

[0111] It should be understood that not all advantages need to be discussed in this article, and no particular advantage is required for all implementations or embodiments, and other implementations or embodiments may provide different advantages.

[0112] According to one embodiment of this disclosure, a semiconductor device including a fin field-effect transistor includes: a first gate structure extending along a first direction; a second gate structure extending along the first direction and aligned with the first gate structure in the first direction; a third gate structure extending in the first direction and arranged parallel to the first gate structure in a second direction intersecting the first direction; a fourth gate structure extending along the first direction, aligned with the third gate structure, and arranged parallel to the second gate structure; an interlayer dielectric layer disposed between the first to fourth gate structures; and a partition wall made of a material different from the interlayer dielectric layer and disposed between the first and second gate structures and the third and fourth gate structures. In one or more of the foregoing and following embodiments, the partition wall contacts the first to fourth gate structures and does not contact any gate structure other than the first to fourth gate structures. In one or more of the foregoing and following embodiments, a side layer is disposed on a side surface of the partition wall in the second direction, and the material forming the core portion of the partition wall is different from the material forming the side layer. In one or more of the foregoing and following embodiments, the core portion of the partition wall is made of a silicon nitride-based material, and the side layer is made of silicon oxide. In one or more of the foregoing and following embodiments, multiple sidewalls in a first direction of the partition wall are in contact with the gate dielectric layer of each of the first to fourth gate structures. In one or more of the foregoing and following embodiments, a bottom layer is provided below the bottom of the partition wall, and the material forming the bottom layer is the same as the material forming the sidewalls. In one or more of the foregoing and following embodiments, each of the first to fourth gate structures includes a gate sidewall spacer, and the gate sidewall spacer is in contact with the partition wall. In one or more of the foregoing and following embodiments, the first to fourth gate structures are disposed on the upper surface of an insulating layer, and the bottom of the partition wall is located below the upper surface of the insulating layer. In one or more of the foregoing and following embodiments, the first gate structure has a first end and a second end in a first direction, the first end of the first gate structure is in contact with the partition wall, and the second end of the first gate structure is in contact with an interlayer dielectric layer different from the partition wall. In one or more of the foregoing and following embodiments, multiple ends of the partition wall penetrate into the interlayer dielectric layer. In one or more of the foregoing and following embodiments, each gate structure in the first to fourth gate structures is disposed above two fin structures extending along a second direction.

[0113] According to another embodiment of this disclosure, a semiconductor device includes: a plurality of fin structures extending along a first direction and arranged in a second direction intersecting the first direction; a plurality of gate structures extending along the second direction and arranged in the first direction; and a plurality of partition walls separating a pair of gate structures from another pair of gate structures. The partition walls are arranged in an alternating manner. In one or more of the foregoing and following embodiments, the spacing between the plurality of partition walls extending along the second direction is twice the spacing between the plurality of fin structures. In one or more of the foregoing and following embodiments, each of the plurality of partition walls contacts both a pair of gate structures and another pair of gate structures, and does not contact any gate structure other than this pair of gate structures and this other pair of gate structures. In one or more of the foregoing and following embodiments, the semiconductor device further includes an end partition wall having a side portion and a side portion, wherein this side portion contacts a pair of gate structures, and this other side portion contacts an interlayer dielectric layer.

[0114] According to another embodiment of this disclosure, in a method for manufacturing a semiconductor device, a pair of sacrificial gate structures are formed over a channel region formed over a substrate. Each of the pair of sacrificial gate structures includes a sacrificial gate electrode layer, a sacrificial gate dielectric layer, and sidewall spacers disposed on both sides of the sacrificial gate electrode layer. An interlayer dielectric layer is located on both sides of the pair of sacrificial gate structures. The pair of sacrificial gate structures and the interlayer dielectric layer are patterned such that the pair of sacrificial gate structures are at least divided by a partition opening into a first sacrificial gate structure and a second sacrificial gate structure, and further divided by this partition opening into a third sacrificial gate structure and a fourth sacrificial gate structure. The partition walls are formed by filling the partition opening with a first insulating material and a second insulating material different from the first insulating material. The sacrificial gate electrode layer and the sacrificial gate dielectric layer are removed from the first to fourth sacrificial gate structures, thereby forming a first electrode space and a second electrode space, and exposing the partition walls between the first electrode space and the second electrode space, and forming a third electrode space and a fourth electrode space, and exposing the partition walls between the third electrode space and the fourth electrode space. A first gate structure, a second gate structure, a third gate structure, and a fourth gate structure are respectively formed in a first electrode space, a second electrode space, a third electrode space, and a fourth electrode space. During the removal of the sacrificial gate dielectric layer, multiple portions of the first insulating material exposed in the first to fourth electrode spaces are removed. In one or more of the foregoing and following embodiments, the sacrificial gate dielectric layer and the first insulating material are made of the same material. In one or more of the foregoing and following embodiments, a third insulating layer is formed over the pair of sacrificial gate structures before patterning them. In one or more of the foregoing and following embodiments, a fin structure is formed over a substrate, and an isolation insulating layer is formed over the substrate such that multiple upper portions of the fin structure are exposed from the isolation insulating layer, and a channel region is included in the exposed multiple upper portions of the fin structure. In one or more of the foregoing and following embodiments, when patterning the pair of sacrificial gate structures, the upper surface of the isolation insulating layer is partially etched such that the bottom of the separating opening is located below the upper surface of the isolation insulating layer.

[0115] Some embodiments of this disclosure provide a semiconductor device including a fin field-effect transistor, comprising: a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, an interlayer dielectric layer, and a spacer. The first gate structure extends along a first direction. The second gate structure extends in the first direction and is aligned with the first gate structure in the first direction. The third gate structure extends in the first direction and is parallel to the first gate structure in a second direction intersecting the first direction. The fourth gate structure extends in the first direction, is aligned with the third gate structure, and is parallel to the second gate structure. The interlayer dielectric layer is disposed between the first and fourth gate structures. The spacer is made of a different material than the interlayer dielectric layer and is disposed between the first and third gate structures and between the second and fourth gate structures.

[0116] In some embodiments, in a semiconductor device, a partition wall is in contact with the first to fourth gate structures and is not in contact with any other gate structures other than the first to fourth gate structures.

[0117] In some embodiments, in a semiconductor device: a plurality of side layers are disposed on a plurality of sides of a partition wall in a second direction, and a material forming the core portion of the partition wall, the material being different from the material forming the side layers.

[0118] In some implementations, in a semiconductor device, the core portion of the separator is made of a silicon nitride-based material, and the side layers are made of silicon oxide.

[0119] In some embodiments, in a semiconductor device, multiple sides of the partition wall in a first direction are in contact with the gate dielectric layer of each of the first to fourth gate structures.

[0120] In some implementations, in a semiconductor device: a bottom layer is provided below the bottom of a separator wall, and the material forming the bottom layer is the same as the material forming the side layer.

[0121] In some embodiments, in a semiconductor device: each of the first to fourth gate structures includes a plurality of gate sidewall spacers, and these gate sidewall spacers are in contact with a partition wall.

[0122] In some embodiments, in a semiconductor device: first to fourth gate structures are disposed on the upper surface of an isolation insulating layer, and the bottom of a partition wall is located below the upper surface of the isolation insulating layer.

[0123] In some embodiments, in a semiconductor device: a first gate structure has a first end and a second end in a first direction, the first end of the first gate structure being in contact with a partition wall, and the second end of the first gate structure being in contact with an interlayer dielectric layer different from the partition wall.

[0124] In some implementations, in a semiconductor device, multiple ends of the spacer extend into the interlayer dielectric layer.

[0125] In some embodiments, in a semiconductor device, each of the first to fourth gate structures is disposed above two fin structures extending along a second direction.

[0126] Some embodiments of this disclosure provide a semiconductor device comprising: a plurality of fin structures, a plurality of gate structures, and a plurality of partition walls. The plurality of fin structures extend in a first direction and are arranged in a second direction intersecting the first direction. The plurality of gate structures extend in the second direction and are arranged in the first direction. The plurality of partition walls separate one pair of gate structures from another pair of gate structures, wherein the plurality of partition walls are arranged in an alternating manner.

[0127] In some embodiments, in a semiconductor device, the spacing between the plurality of partition walls of a line extending along a second direction is twice the spacing between the plurality of fin structures.

[0128] In some implementations, in a semiconductor device, each of a plurality of partition walls is in contact with a pair of gate structures and another pair of gate structures, and is not in contact with any gate structure other than the pair of gate structures and the other pair of gate structures.

[0129] In some embodiments, the semiconductor device further includes an end partition wall having a side portion and a other side portion, wherein the side portion is in contact with a pair of gate structures and the other side portion is in contact with an interlayer dielectric layer.

[0130] Some embodiments of this disclosure provide a method for manufacturing a semiconductor device, comprising: forming a pair of sacrificial gate structures over a plurality of channel regions formed over a substrate, each of the pair of sacrificial gate structures including a sacrificial gate electrode layer, a sacrificial gate dielectric layer, and a plurality of sidewall spacers disposed on two sides of the sacrificial gate electrode layer; forming a plurality of interlayer dielectric layers at the two sides of the pair of sacrificial gate structures; patterning the pair of sacrificial gate structures and dielectric layers such that the pair of sacrificial gate structures are divided into a first sacrificial gate structure and a second sacrificial gate structure by at least a partition opening, and further divided into a third sacrificial gate structure and a fourth sacrificial gate structure by the partition opening; forming a partition wall via a first insulating material and a non- A second insulating material, identical to the first insulating material, fills the separating opening; a sacrificial gate electrode layer and a sacrificial gate dielectric layer are removed from the first to fourth sacrificial gate structures, thereby forming a first electrode space and a second electrode space, and a separating wall is exposed between the first electrode space and the second electrode space, and a third electrode space and a fourth electrode space are formed, and a separating wall is exposed between the third electrode space and the fourth electrode space; and a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure are respectively formed in the first electrode space, the second electrode space, the third electrode space, and the fourth electrode space, wherein, during the removal of the sacrificial gate dielectric layer, multiple portions of the first insulating material exposed in the first to fourth electrode spaces are removed.

[0131] In some embodiments, in the method of manufacturing a semiconductor device, the sacrificial gate dielectric layer and the first insulating material are made of the same material.

[0132] In some embodiments, the method for manufacturing a semiconductor device further includes forming a third insulating layer over the pair of sacrificial gate structures before patterning them.

[0133] In some embodiments, the method for manufacturing a semiconductor device further includes: forming a plurality of fin structures over a substrate; and forming an insulating layer over the substrate such that a plurality of upper portions of the plurality of fin structures are exposed from the insulating layer, wherein a plurality of channel regions are included in the exposed upper portions of the fin structures.

[0134] In some embodiments, in a method for manufacturing a semiconductor device, when patterning a pair of sacrificial gate structures, the upper surface of an isolation insulating layer is partially etched such that the bottom of the separating opening is located below the upper surface of the isolation insulating layer.

[0135] Several embodiments have been outlined above to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they may readily use this disclosure as a basis for the design and modification of other processes and structures to achieve the same purpose or advantages as the embodiments or examples described herein. Those skilled in the art will also understand that equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications may be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device including a fin field-effect transistor, characterized in that, Include: A first gate structure extending along a first direction; A second gate structure extends in the first direction and is aligned with the first gate structure in the first direction; A third gate structure extends in the first direction and is arranged parallel to the first gate structure in a second direction intersecting the first direction; A fourth gate structure extends in the first direction, is aligned with the third gate structure, and is arranged parallel to the second gate structure; An interlayer dielectric layer is disposed between the first and fourth gate structures; as well as A partition wall, made of a different material from the interlayer dielectric layer, is disposed between the first and second gate structures and the third and fourth gate structures; in: Each of the first to fourth gate structures includes a plurality of sidewall spacers. The sidewall spacers of the first gate structure and the sidewall spacers of the second gate structure are separated by the partition wall and are discontinuous. The partition wall comprises a core portion and multiple side layers disposed on multiple first sides extending in the first direction. The material forming a core portion of the partition wall is different from the material forming the side layers; and These side layers are in contact with the interlayer dielectric layer.

2. The semiconductor device according to claim 1, characterized in that, in, The partition wall is in contact with the first to the fourth gate structures, and is not in contact with any other gate structures except the first to the fourth gate structures.

3. The semiconductor device according to claim 1, characterized in that: The side layer is made of SiCN, SiON or SiOCN.

4. The semiconductor device according to claim 1, characterized in that, The core portion of the partition wall is made of a silicon nitride-based material, and the side layers are made of silicon oxide.

5. The semiconductor device according to claim 1, characterized in that, Multiple sides of the partition wall in the first direction are in contact with a gate dielectric layer of each of the first to fourth gate structures.

6. The semiconductor device according to claim 1, characterized in that: A bottom layer is provided below one bottom of the partition wall, and The material forming the bottom layer is the same as the material forming the side layers.

7. The semiconductor device according to claim 1, characterized in that: The multiple second sides of the core portion extend in the second direction and contact the interlayer dielectric layer and a gate dielectric layer of each of the first to fourth gate structures.

8. The semiconductor device according to claim 1, characterized in that, in: The first to fourth gate structures are disposed on an upper surface of an insulating layer, and One bottom of the partition wall is located below the upper surface of the insulating layer.

9. The semiconductor device according to claim 1, characterized in that, in: The first gate structure has a first end and a second end in the first direction. The first end of the first gate structure contacts the partition wall, and The second end of the first gate structure is in contact with the interlayer dielectric layer.

10. The semiconductor device according to claim 1, characterized in that, Multiple ends of the partition wall penetrate into the interlayer dielectric layer.

11. The semiconductor device according to claim 1, characterized in that, Each of the first to fourth gate structures is disposed above two fin structures extending along the second direction.

12. A semiconductor device, characterized in that, Include: Multiple fin structures extend in a first direction and are arranged in a second direction intersecting the first direction; Multiple gate structures extend in the second direction and are arranged in the first direction; Multiple interlayer dielectric layers are located between the gate structures in the first direction; as well as Multiple partition walls, each of the multiple partition walls separating one pair of gate structures and another pair of gate structures and contacting the pair of gate structures and the other pair of gate structures, The plurality of partition walls are arranged in an alternating manner, and each of the plurality of partition walls comprises: A core portion, wherein the core portion is made of a silicon nitride-based material, and the core portion is in contact with the gate structures; Multiple side layers are disposed on multiple first side surfaces extending in the second direction of the core portion, wherein each of the side layers is in contact with the interlayer dielectric layers; and A bottom layer is disposed at the bottom of each of the partition walls, wherein the plurality of side layers and the bottom layer are made of silicon oxide; Each of the gate pair and the other gate pair includes a plurality of sidewall spacers. The sidewall spacers of the gate pair are separated by the core portion of a corresponding partition wall and the bottom layer of the plurality of partition walls and are discontinuous. The sidewall spacers of the other gate pair are separated by the core portion of the corresponding partition wall and the bottom layer and are discontinuous. The second sides of the core portion of the corresponding partition wall extend in the first direction and contact the interlayer dielectric layers and a gate dielectric layer of each of the gate structure pair and the other gate structure pair.

13. The semiconductor device according to claim 12, characterized in that, in, The spacing of the plurality of partition walls along a line extending in the second direction is twice the spacing of the plurality of fin structures.

14. The semiconductor device according to claim 12, characterized in that, Each of the plurality of partition walls is in contact with the pair of gate structures and the other pair of gate structures, and is not in contact with any gate structure other than the pair of gate structures and the other pair of gate structures.

15. The semiconductor device according to claim 12, characterized in that, It also includes an end partition wall having a side portion and a other side portion, wherein, One side of the end partition wall is in contact with a pair of gate structures, while the other side of the end partition wall is in contact with an inter-dielectric layer and is not in contact with any gate structure.

16. A method for manufacturing a semiconductor device, characterized in that, Include: A pair of sacrificial gate structures are formed over a plurality of channel regions formed on a substrate. Each of the sacrificial gate structures includes a sacrificial gate electrode layer, a sacrificial gate dielectric layer, and a plurality of sidewall spacers disposed on two sides of the sacrificial gate electrode layer. Multiple interlayer dielectric layers are formed on both sides of the sacrificial gate structure; The pair of sacrificial gate structures and the interlayer dielectric layers are patterned such that the pair of sacrificial gate structures are at least divided by a partition opening into a first sacrificial gate structure and a second sacrificial gate structure, and are further divided by the partition opening into a third sacrificial gate structure and a fourth sacrificial gate structure, and the portions of the interlayer dielectric layers between the pair of sacrificial gate structures in the partition opening are removed. A partition wall is formed by filling the partition opening with a first insulating material and a second insulating material different from the first insulating material, wherein a portion of the first insulating material of the partition wall is in contact with the interlayer dielectric layers; The sacrificial gate electrode layer and the sacrificial gate dielectric layer are removed from the first to the fourth sacrificial gate structures to form a first electrode space and a second electrode space, and the partition wall is exposed between the first electrode space and the second electrode space to form a third electrode space and a fourth electrode space, and the partition wall is exposed between the third electrode space and the fourth electrode space. as well as A first gate structure, a second gate structure, a third gate structure, and a fourth gate structure are respectively formed in the first electrode space, the second electrode space, the third electrode space, and the fourth electrode space. During the removal of the sacrificial gate dielectric layer, multiple portions of the first insulating material exposed in the first to fourth electrode spaces are removed; Each of the first to fourth gate structures includes a plurality of sidewall spacers. The sidewall spacers of the first gate structure are separated from the sidewall spacers of the second gate structure by the partition wall and are discontinuous. The sidewall spacers of the third gate structure are separated from the sidewall spacers of the fourth gate structure by the partition wall and are discontinuous.

17. The method for manufacturing a semiconductor device according to claim 16, characterized in that, The sacrificial gate dielectric layer and the first insulating material are made of the same material.

18. The method for manufacturing a semiconductor device according to claim 16, characterized in that, It also includes forming a third insulating layer over the pair of sacrificial gate structures before patterning the pair of sacrificial gate structures.

19. The method for manufacturing a semiconductor device according to claim 16, characterized in that, Also includes: Multiple fin structures are formed above the substrate; and An insulating layer is formed above the substrate, exposing multiple upper portions of the fin structures through the insulating layer. These channel regions are included in the exposed upper portions of these fin structures.

20. The method for manufacturing a semiconductor device according to claim 19, characterized in that, When patterning the pair of sacrificial gate structures, a portion of the upper surface of the isolation insulating layer is etched such that a bottom of the separation opening is located below the upper surface of the isolation insulating layer.

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