A high-speed LVDS interface circuit and chip

Abstract

The present invention discloses a high-speed LVDS interface circuit and chip, belonging to the field of analog integrated circuit technology. The interface circuit in the chip includes a first charge pump circuit, a second charge pump circuit, a four-phase switch circuit and a common-mode feedback circuit. In addition, the chip also adopts a compensation structure. The circuit adopts a common-mode feedback circuit to stably output a common-mode voltage, and the charge pump circuit is charged and discharged at the edge of the clock signal jump to reduce the mountain rise / fall time, and the performance of the high-speed interface circuit is improved by a high-frequency compensation circuit.

Description

Technical Field

[0001] The invention belongs to the technical field of analog integrated circuits, and in particular relates to a high-speed LVDS interface circuit and a chip. Background Art

[0002] LVDS (Low-Voltage Differential Signaling) interface circuit is widely used in clock circuits and high-speed digital signal systems. Its specific applications are mainly reflected in the following two aspects:

[0003] First, high-speed analog-to-data converters require high-speed interface chips to output data. As the operating frequency of communication systems continues to increase and bandwidth continues to increase, the speed requirements for interface chips are also getting higher and higher. At the same time, with the continuous breakthroughs in digital signal processing technology, high-speed digital systems have emerged. Therefore, designing high-speed interface circuits is particularly important.

[0004] Second, in large-scale high-speed digital systems, a variety of rich logic voltages are required to implement complex functions. Parasitic capacitance inevitably poses a severe challenge to high-speed and high-signal quality interface circuits. Therefore, it is of great significance to design a high-speed, high-quality LVDS interface circuit. Summary of the invention

[0005] In view of this, the present invention proposes a high-speed LVDS interface circuit and chip, which utilizes charge pump technology and high-frequency compensation technology to improve the working speed of the interface circuit.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0007] A high-speed LVDS interface circuit, comprising a first charge pump circuit, a second charge pump circuit, a four-element switch circuit and a common-mode feedback circuit; the four-element switch circuit comprises first to fourth transistors M1-M4, the first charge pump circuit comprises fifth and sixth transistors M5 and M6 and a first capacitor C1, the second charge pump circuit comprises seventh and eighth transistors M7 and M8 and a second capacitor C2, the common-mode feedback circuit comprises a first resistor R1, a second resistor R2, a third capacitor C3, an operational amplifier OPA, a first current source I1 and a second current source I2;

[0008] One end of the first current source I1 is connected to the voltage source, and the other end is connected to the source of the first, second, fifth and seventh transistors M1, M2, M5 and M7; the drain of the first transistor M1 is connected to the drain of the third transistor M3, the drain of the second transistor M2 is connected to the drain of the fourth transistor M4, the source of the first transistor M1 is connected to the source of the second transistor M2, and the source of the third transistor M3 is connected to the source of the fourth transistor M4; the gate of the third transistor M3 is connected to the clock signal CLK, and the gate of the fourth transistor M4 is connected to the reverse clock signal NCLK; the node between the drains of the first and third transistors M1 and M3 is respectively connected to one end of the first resistor R1 and the first capacitor C1, and the node between the drains of the second and fourth transistors M2 and M4 is respectively connected to one end of the second resistor R2 and the second capacitor C2; the other end of the first resistor R1 and the other end of the second resistor R2 are both connected to the common mode voltage V cm The positive input port of the operational amplifier OPA is connected to the common-mode voltage V cm The negative input port is connected to one end of the third capacitor C3, the other end of the third capacitor C3 is connected to the output end of the operational amplifier OPA, and controls the current size of the second current source I2; the gates of the fifth and sixth transistors M5 and M6 are connected and connected to the clock signal CLK, and the gates of the seventh and eighth transistors M7 and M8 are connected and connected to the reverse clock signal; the drains of the fifth and sixth transistors M5 and M6 are both connected to the other end of the first capacitor C1, the source of the sixth transistor M6 is grounded, and the gate of the fifth transistor M5 is connected to the gate of the first transistor M1; the drains of the seventh and eighth transistors M7 and M8 are both connected to the other end of the second capacitor C2, the source of the eighth transistor M8 is grounded, and the gate of the seventh transistor M7 is connected to the gate of the second transistor M2; the end of the first resistor R1 close to the first capacitor C1 is the forward voltage output port VOUTP, and the end of the second resistor R2 close to the second capacitor C2 is the reverse voltage output port VOUTN.

[0009] A high-speed LVDS interface chip includes the high-speed LVDS interface circuit and packaging structure as described above, wherein the packaging structure is provided with a forward voltage port corresponding to the forward voltage output port VOUTP and a reverse voltage port corresponding to the reverse voltage output port VOUTN, and adjustment inductors Ind_tune are provided between the forward voltage output port and the forward voltage port, and between the reverse voltage output port and the reverse voltage port, and adjustment capacitors Ctune are provided outside the forward voltage port and the reverse voltage port, and the adjustment inductors and the adjustment capacitors are used to perform high-frequency resonance compensation for the parasitic circuit generated by the packaging structure.

[0010] Compared with the prior art, the advantages of the present invention are:

[0011] 1) Traditional pre-emphasis technology requires an additional working current source to inject current to increase the interface rate. The present invention adopts charge pump technology to only charge and discharge the capacitor, saving power consumption.

[0012] 2) The traditional interface circuit uses Miller compensation technology, and there is capacitance in the current source path (actually because the circuit common mode bandwidth is low, the current source is an AC path). The chip of the present invention has a compensation structure, and the compensation structure does not have parasitic capacitance in the signal / current source, which can increase the interface rate.

[0013] 3) The compensation structure of the present invention is a Q value compensation circuit, which can reduce the influence of high-frequency chip parasitics and ensure the high-frequency performance of the interface.

[0014] 4) Under the SMIC 180nm process, the operating speed of the chip of the present invention can be increased to 2.2 GHz. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a circuit schematic diagram of the interface circuit of the present invention.

[0016] Figure 2 This is the circuit schematic diagram of the LVDS interface parasitic circuit.

[0017] Figure 3 It is a circuit schematic diagram of the compensation structure in the chip of the present invention. DETAILED DESCRIPTION

[0018] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0019] like Figure 1 As shown, a high-speed LVDS interface circuit includes a first charge pump circuit, a second charge pump circuit, a four-element switch circuit and a common-mode feedback circuit; the four-element switch circuit includes first to fourth transistors M1-M4, the first charge pump circuit includes fifth and sixth transistors M5 and M6 and a first capacitor C1, the second charge pump circuit includes seventh and eighth transistors M7 and M8 and a second capacitor C2, and the common-mode feedback circuit includes a first resistor R1, a second resistor R2, a third capacitor C3, an operational amplifier OPA, a first current source I1 and a second current source I2;

[0020] One end of the first current source I1 is connected to the voltage source, and the other end is connected to the source of the first, second, fifth and seventh transistors M1, M2, M5 and M7; the drain of the first transistor M1 is connected to the drain of the third transistor M3, the drain of the second transistor M2 is connected to the drain of the fourth transistor M4, the source of the first transistor M1 is connected to the source of the second transistor M2, and the source of the third transistor M3 is connected to the source of the fourth transistor M4; the gate of the third transistor M3 is connected to the clock signal CLK, and the gate of the fourth transistor M4 is connected to the reverse clock signal NCLK; the node between the drains of the first and third transistors M1 and M3 is respectively connected to one end of the first resistor R1 and the first capacitor C1, and the node between the drains of the second and fourth transistors M2 and M4 is respectively connected to one end of the second resistor R2 and the second capacitor C2; the other end of the first resistor R1 and the other end of the second resistor R2 are both connected to the common mode voltage V cm The positive input port of the operational amplifier OPA is connected to the common-mode voltage V cm The negative input port is connected to one end of the third capacitor C3, the other end of the third capacitor C3 is connected to the output end of the operational amplifier OPA, and controls the current size of the second current source I2; the gates of the fifth and sixth transistors M5 and M6 are connected and connected to the clock signal CLK, and the gates of the seventh and eighth transistors M7 and M8 are connected and connected to the reverse clock signal; the drains of the fifth and sixth transistors M5 and M6 are both connected to the other end of the first capacitor C1, the source of the sixth transistor M6 is grounded, and the gate of the fifth transistor M5 is connected to the gate of the first transistor M1; the drains of the seventh and eighth transistors M7 and M8 are both connected to the other end of the second capacitor C2, the source of the eighth transistor M8 is grounded, and the gate of the seventh transistor M7 is connected to the gate of the second transistor M2; the end of the first resistor R1 close to the first capacitor C1 is the forward voltage output port VOUTP, and the end of the second resistor R2 close to the second capacitor C2 is the reverse voltage output port VOUTN.

[0021] This circuit uses charge pump technology. When CLK is low, the current flows through transistor M1 to node VOUTP, and then flows through resistor R1; at this time, M5 is turned on, the upper plate of C1 stores positive charge, and the lower plate stores negative charge. At this time, the positive charge on the lower plate flows to resistor R1, increasing the instantaneous current flowing through R1, which can reduce the rise / fall time of the output clock.

[0022] Specifically, when the circuit starts working, the V CM port to the input port of the amplifier, and from the output port of the amplifier through the current source, transistor M3, and then to the V CM ports, forming a common-mode negative feedback loop, and the operational amplifier is virtually shorted, so V CM The voltage is equal to 1.25V.

[0023] When CLK is low, NCLK is high, M5 is turned on, M6 is turned off, the upper plate of C1 is charged through M5, and the lower plate is charged with an equal amount of negative charge. The positive charge flowing out of the lower plate is:

[0024] Q1(+)=C1×U (1)

[0025] The time for the positive charge to flow through the resistor R1 is from the low level of CLK to the high level of CLK, during which the charge released is αQ1. α is a coefficient related to the process.

[0026] M1 and M4 are turned on, M2 and M3 are turned off, NCLK is at a high level, the positive charge on the upper plate of C2 begins to be discharged through M8, and the lower plate of C2 begins to absorb positive charge (negative charge decreases). Generally, the following relationship is satisfied in the design:

[0027] C1=C2 (2)

[0028] Therefore, the charge absorbed during the period from CLK low level to CLK jumping to high level is αQ1. Assume that there is a parasitic capacitance C at the VOUTP node g , the node voltage jumps from U1 to U2, and the jump time satisfies the following formula:

[0029] ΔT=C g (U1-U2) / I (3)

[0030] I is the current flowing into the node VOUTP. When there is no charge pump circuit, I is generally I1 = 350mA. When there is a charge pump circuit:

[0031] I=0.35+2αQ1 / T (4)

[0032] In the above formula, T is the period of the clock. It can be clearly seen from the formula that the current flowing into the load capacitor increases by using the charge pump technology. Therefore, from formula (3), it can be obtained that the output clock rise / fall ΔT decreases.

[0033] In addition, the common-mode feedback circuit in this circuit adopts single-stage capacitor compensation technology, which only pushes the main pole to the left. This compensation method can reduce the load capacitance on the current source path, thereby increasing the operating rate.

[0034] A high-speed LVDS interface chip comprises the high-speed LVDS interface circuit and a packaging structure as described above, wherein the packaging structure is provided with a forward voltage port corresponding to a forward voltage output port VOUTP and a reverse voltage port corresponding to a reverse voltage output port VOUTN.

[0035] Generally, the chip needs to connect the PAD and the chip pin through a bonding line. The bonding line is equivalent to an inductor, and the chip pin and the pad are equivalent to a capacitor. Figure 2 As shown, the signal flows out from the VOUTP interface, C g is the parasitic capacitance of the PAD and metal wire, Ind1 is the parasitic inductance of the bonding wire, C load is the load capacitance, and R is the load impedance. When the output clock signal jumps, the inductor and capacitor, as energy storage elements, will be charged and discharged to a certain extent, generating reflux, hindering the change of the clock signal, resulting in a decrease in the quality of the output signal. This parasitic circuit deteriorates the signal rise and fall time at high frequencies, causing a series of problems such as signal overshoot.

[0036] To this end, an adjusting inductor Ind_tune can be set between the forward voltage output port and the forward voltage port, and between the reverse voltage output port and the reverse voltage port, and an adjusting capacitor Ctune can be set outside the forward voltage port and the reverse voltage port, and the adjusting inductor and the adjusting capacitor are used to perform high-frequency resonance compensation for the parasitic circuit generated by the packaging structure.

[0037] like Figure 3 As shown, after adopting the above compensation structure, the inductance value of Ind_tune is L=C g , in the circuit:

[0038] C=C load +C g (5)

[0039] From VOUTP, the output equivalent load is:

[0040]

[0041] In the above formula, L1 is the inductance value of Ind1, W represents the signal angular frequency, and j represents an imaginary number.

[0042] When R is relatively small, the above formula is equivalent to:

[0043]

[0044] The resonant frequency and Q value satisfy the following formula:

[0045]

[0046] When the time domain signal passes through the impedance represented by formula (7), we have:

[0047]

[0048] In the above formula, T = 1 / (W0 / 2 / pi).

[0049] Usually the Q value is 0.5, when the signal overshoot and rise / fall time are well compromised. Therefore, Q = 1 / (W0RC) = 0.5, when the inductance value of Ind_tune is L = C g ,

[0050] The capacitance of Ctune satisfies the following formula:

[0051]

[0052] This circuit can achieve very good high frequency performance.

Claims

1. A high-speed LVDS interface circuit, characterized in that: The invention comprises a first charge pump circuit, a second charge pump circuit, a four-element switch circuit and a common-mode feedback circuit; the four-element switch circuit comprises first to fourth transistors (M1-M4), the first charge pump circuit comprises fifth and sixth transistors (M5, M6) and a first capacitor (C1), the second charge pump circuit comprises seventh and eighth transistors (M7, M8) and a second capacitor (C2), and the common-mode feedback circuit comprises a first resistor (R1), a second resistor (R2), a third capacitor (C3), an operational amplifier (OPA), a first current source (I1) and a second current source (I2); One end of the first current source (I1) is connected to the voltage source, and the other end is connected to the source of the first, second, fifth and seventh transistors (M1, M2, M5, M7); the drain of the first transistor (M1) is connected to the drain of the third transistor (M3), the drain of the second transistor (M2) is connected to the drain of the fourth transistor (M4), the source of the first transistor (M1) is connected to the source of the second transistor (M2), the source of the third transistor (M3) is connected to the source of the fourth transistor (M4); the third transistor ( The gate of the fourth transistor (M3) is connected to the clock signal (CLK), and the gate of the fourth transistor (M4) is connected to the reverse clock signal (NCLK); the node between the drains of the first and third transistors (M1, M3) is connected to one end of the first resistor (R1) and the first capacitor (C1), respectively, and the node between the drains of the second and fourth transistors (M2, M4) is connected to one end of the second resistor (R2) and the second capacitor (C2), respectively; the other end of the first resistor (R1) and the other end of the second resistor (R2) are both connected to the common mode voltage (V cm ) is connected to the positive input port of the operational amplifier (OPA) and the common-mode voltage (V cm ), the negative input port is connected to one end of the third capacitor (C3), the other end of the third capacitor (C3) is connected to the output end of the operational amplifier (OPA), and controls the current size of the second current source (I2); The gates of the fifth and sixth transistors (M5, M6) are connected to each other and are connected to a clock signal (CLK), and the gates of the seventh and eighth transistors (M7, M8) are connected to each other and are connected to a reverse clock signal; the drains of the fifth and sixth transistors (M5, M6) are both connected to the other end of the first capacitor (C1), the source of the sixth transistor (M6) is grounded, and the gate of the fifth transistor (M5) is connected to the gate of the first transistor (M1); the drains of the seventh and eighth transistors (M7, M8) are both connected to the other end of the second capacitor (C2), the source of the eighth transistor (M8) is grounded, and the gate of the seventh transistor (M7) is connected to the gate of the second transistor (M2); one end of the first resistor (R1) close to the first capacitor (C1) is a forward voltage output port (VOUTP), and one end of the second resistor (R2) close to the second capacitor (C2) is a reverse voltage output port (VOUTN).

2. A high-speed LVDS interface chip, characterized in that: It comprises the high-speed LVDS interface circuit and packaging structure as described in claim 1, wherein the packaging structure is provided with a forward voltage port corresponding to the forward voltage output port (VOUTP) and a reverse voltage port corresponding to the reverse voltage output port (VOUTN), and adjustment inductors (Ind_tune) are provided between the forward voltage output port and the forward voltage port, and between the reverse voltage output port and the reverse voltage port, and adjustment capacitors (Ctune) are provided outside the forward voltage port and the reverse voltage port, and the adjustment inductors and the adjustment capacitors are used to perform high-frequency resonance compensation for the parasitic circuit generated by the packaging structure.

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