RF power amplifier

Abstract

RF power amplifiers are provided. A radio frequency (RF) power combiner includes a first port having a first inverting input and a first non-inverting input, a second port having a second inverting input and a second non-inverting input, a first stabilization line coupled between the first non-inverting input and the second non-inverting input, and a second stabilization line coupled between the first inverting input and the second inverting input.

Description

[0001] Cross-references to related applications. Technical Field

[0002] The present invention generally relates to circuits and methods for stabilizing radio frequency (RF) power amplifiers. Background Technology

[0003] Ultra-high frequency (SHF) radio frequency (RF) operates within the electromagnetic spectrum between 3 and 30 GHz, while extremely high frequency (EHF) radio frequency (RF) operates within the electromagnetic spectrum from 30 to 300 GHz. The SHF RF band is also known as the centimeter band or centimeter wave because its wavelength ranges from ten to one centimeter, while the EHF RF band is also known as the millimeter band or millimeter wave because its wavelength ranges from ten to one millimeter.

[0004] Automotive radar is a key component of Advanced Driver Assistance Systems (ADAS) and autonomous driving technologies. It provides robust 3D imaging capabilities against adverse weather conditions. A critical parameter for automotive radar is the maximum range at which targets can be observed. To improve the maximum range, sufficient RF power must be transmitted. Therefore, the power capability of the radar transmitter is an important parameter; increasing power capability can provide a competitive advantage. The RF power amplifier is a key component in the radar transmitter. It determines the level of power delivered to the antenna. Major design efforts focus on maximizing the power output of the RF power amplifier while ensuring that the amplifier still maintains a stable operating mode. Summary of the Invention

[0005] A circuit includes a distributor, a combiner, first and second pairs of transistors, and first and second stabilizing lines. The distributor includes a first output port having a first inverting output and a first non-inverting output, and a second output having a second inverting output and a second non-inverting output. The combiner includes a first input port having a first inverting input and a first non-inverting input, and a second input port having a second inverting input and a second non-inverting input. Each of the first pair of transistors has a first input terminal coupled to ground, a first output terminal coupled to the first input port of the combiner, and a first control terminal driven by the first output of the distributor. Each of the second pair of transistors has a second input terminal coupled to ground, a second output terminal coupled to the second input port of the combiner, and a second control terminal driven by the second output of the distributor. The first stabilizing line is coupled between the first non-inverting input and the second non-inverting input of the combiner. The second stabilizing line is coupled between the first inverting input and the second inverting input of the combiner.

[0006] A radio frequency (RF) power combiner includes a first port having a first inverting input and a first non-inverting input, a second port having a second inverting input and a second non-inverting input, a first stability line coupled between the first non-inverting input and the second non-inverting input, and a second stability line coupled between the first inverting input and the second inverting input.

[0007] A method to reduce oscillations in a four-signal system includes receiving a first signal pair including a first inverted signal and a first non-inverted signal, and a second signal pair including a second inverted signal and a second non-inverted signal. The first inverted signal is then amplified with a first inverting transistor having a first inverting inductor coupled to a power supply at a first inverting input, the first non-inverted signal is amplified with a first non-inverting transistor having a first non-inverting inductor coupled to the power supply at a first non-inverting input, the second inverted signal is amplified with a second inverting transistor having a second inverting inductor coupled to the power supply at a second inverting input, and the second non-inverted signal is amplified with a second non-inverting transistor having a second non-inverting inductor coupled to the power supply at a second non-inverting input. Also, the first non-inverting input and the second non-inverting input are coupled, and the first inverting input and the second inverting input are coupled. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a block diagram of a vehicle radar system.

[0009] Figure 2 is a schematic diagram of an inductive load metal oxide semiconductor (MOS) transistor illustrating input impedance.

[0010] Figure 3 is an equivalent LC tank circuit for Figure 2 .

[0011] Figure 4 is a schematic diagram of a single transistor amplifier stage.

[0012] Figure 5 is a schematic diagram of a transistor amplifier stage with common source common gate transistors.

[0013] Figure 6 is a schematic diagram of a differential amplifier illustrating neutralization capacitors.

[0014] Figure 7 is a schematic diagram of a neutralization mechanism for C gd .

[0015] Figure 8 is a schematic diagram of a differential amplifier modified for common mode stability.

[0016] Figure 9 is an equivalent circuit for Figure 8 and an equivalent LC tank circuit.

[0017] Figure 10 is a schematic diagram of a four-transistor power combiner amplifier stage.

[0018] Figure 11A is a schematic diagram of a four-transistor power combiner amplifier stage in differential mode.

[0019] Figure 11B is a schematic diagram of a four-transistor power combiner amplifier stage in common mode.

[0020] Figure 11C is a schematic diagram of a four-transistor power combiner amplifier stage in a first hybrid mode.

[0021] Figure 11D is a schematic diagram of a four-transistor power combiner amplifier stage in a second hybrid mode.

[0022] Figure 12 is a schematic diagram of a four-transistor power combiner amplifier stage in a second hybrid mode, illustrating an oscillation mechanism.

[0023] Figure 13 is a schematic diagram of an equivalent circuit of Figure 12

[0024] Figure 14 is a schematic diagram of a four-transistor power combiner amplifier stage with a stabilization mechanism.

[0025] Figure 15 is a top view of a semiconductor layout of a four-transistor power combiner amplifier stage with a stabilization mechanism.

[0026] Figure 16 is a perspective view of a semiconductor layout of a four-transistor power combiner amplifier stage with a stabilization mechanism. DETAILED DESCRIPTION

[0027] Detailed embodiments of the application are disclosed herein; however, it is to be understood that the disclosed embodiments are merely exemplary of the application and can be embodied in various and alternative forms. The Figures are not necessarily to scale; some features can be exaggerated or minimised for the sake of clarity. The specific structural and functional details disclosed herein are not to be interpreted as limiting, but are merely representative bases for teaching one skilled in the art to employ the application in a variety of arrangements and scenarios.

[0028] The term "substantially" can be used herein to describe an embodiment disclosed or claimed that is "close" to or "approximately" a stated value or property. In such instances, the term "substantially" can be used to indicate that the value or property being modified is "essentially" the stated value or property. It is to be understood that such a term is not to be interpreted as requiring or implying that the value or property is the exact stated value or property being modified. ​within 0%, 0.1%, 0.5%, 1%, 2%, 3%, 4%, 5%, or 10%.

[0029] As used herein, the term "non-inverting input" refers to an input intended to be substantially in phase with a reference, typically the non-inverting input is substantially in phase 0 degrees with the reference. As used herein, the term "non-inverting output" refers to an output intended to be substantially in phase with an input, typically the non-inverting output is substantially in phase 0 degrees with the input.

[0030] As used herein, the term "non-inverting output" refers to an output intended to be substantially in phase with an input, typically the non-inverting output is substantially in phase 0 degrees with the input.

[0031] One of the challenges in RF and millimeter wave power amplifier design is to maximize gain and output power while ensuring that the circuit remains stable. Instability in high frequency amplifiers stems from inherent internal feedback paths within individual transistors that are created by parasitic capacitances from the output (drain / collector) to the input (gate / base). This feedback can create a negative real impedance at the transistor input, which in turn will lead to an oscillation condition when the remaining passive components at the input form a resonant LC circuit. When power from multiple transistors is combined at the amplifier output, there can be multiple oscillation modes, each of which needs to be stabilized. Techniques are disclosed herein to stabilize unwanted oscillation modes in power combining amplifiers without adversely affecting the desired signal.

[0032] Figure 1 is a block diagram of a vehicle-mounted radar system 100. A transmitter 102 transmits a signal that reflects off of an object 110, such as a vehicle. A receiver 104 then detects the reflected signal. The transmitter 102 and receiver 104 are coupled with a signal processor 106 and a frequency generator 108 that control the signals transmitted and received by the transmitter 102 and receiver 104, respectively. The transmitter incorporates an RF power amplifier that is used to deliver the required transmit power to an RF antenna. The amplifier can be implemented using a variety of electronic components. For the purposes of this discussion, we will use a metal-oxide-semiconductor field-effect transistor (MOSFET) transistor, recognizing that the principles apply to other switching components (e.g., bipolar junction transistor (BJT), high electron mobility transistor (HEMT), etc.) and that these switching components can be made using known semiconductor processing materials (e.g., Si-based, SiC, GaN, GaAs, AlGaAs, etc.). These materials are typically from Group III, IV, or V elements, although other elements can be used.

[0033] Figure 2This is a schematic diagram of a single MOS transistor amplifier stage 200, which includes a single MOS transistor 202, a gate-to-drain capacitance 206, a gate inductor 204, and is coupled to an inductive load 208. The schematic also illustrates the input impedance Z. in Under the specified assumptions expressed in Equation 1,

[0034] (1)

[0035] Looking at the transistor gate, the impedance can have a negative real part and an imaginary part of capacitance, as expressed in Equation 2.

[0036] (2)

[0037] If this device is combined with an inductor at the input, the overall circuit will form a resonant LC energy storage section with negative real impedance, which is the condition for oscillation. Figure 3 yes Figure 2 The equivalent LC energy storage circuit is 300. In Figure 3 In the equivalent LC energy storage circuit 300, R x 302 represents Z in Looking at the negative real part of the transistor, L g It is a gate inductor 304, and C x 306 is the equivalent capacitance. To prevent oscillation, a capacitance greater than R can be added to the gate. x A positive resistor.

[0038] Figure 4 This is a schematic diagram of a single transistor amplifier stage 400. Amplifier stage 400 includes transistor 402, gate inductor 404, gate-to-drain capacitance 406, load inductor 408, and gate resistor 410. Unfortunately, the resistor consumes power and adversely affects the power gain of the circuit. Alternatively, a cascode transistor M2 can be added. Figure 5 This is a schematic diagram of a transistor amplifier stage 500 with a cascode transistor. The amplifier stage 500 includes a transistor 502, a gate inductor 504, a gate-to-drain capacitance 506, a load inductor 508, and a cascaded transistor 410. The cascode device generates a low-impedance node at the drain of M1 and connects to C... gd The feedback signal is highly attenuated. However, the cascode configuration limits the voltage headroom at the circuit output, and thus limits the maximum achievable output power.

[0039] RF power amplifiers are typically implemented as differential circuits, which allow for higher output power through power combining. Differential signal paths also improve the circuit's power supply rejection. Figure 6This is a schematic diagram of the differential amplifier 600 with capacitors 606 and 608. The differential amplifier 600 includes a first pair of transistors 602 and 604, a distributor 610, and a combiner 612. The differential amplifier stage 600 uses transformers 610 and 612 to couple the signals at its input and output. Such a circuit operates using two types of signals: differential and common-mode. Differential signals (V...) d ) is the excitation of two transistors with opposite phases, while the common-mode signal (V) cm The difference is equivalent for both transistors. Generally, the differential signal is desired and needs to be amplified, while the common-mode signal is parasitic and must be attenuated. The transformer facilitates this, providing a low-impedance path for the differential signal and a high impedance path for the common-mode signal. However, for both types of signals, the stability of the amplifier stage should be carefully examined to ensure proper operation.

[0040] First, consider the differential signal and the corresponding line of symmetry along the circuit. For the differential signal, all circuit nodes on the line of symmetry are equivalent to ground connections. Based on this, it can be observed that the differential half-circuit (on one side of the line of symmetry) corresponds to the signal from... Figure 2 The similarity between inductively loaded transistors. (Source: Figure 2 The analysis results indicate a potential stability problem with the differential signal. This problem stems from the capacitance C. gd The feedback path. Gate capacitance C gd Inside the transistor, and possibly not shown in subsequent diagrams, this feedback path, if removed, will prevent instability under any conditions. The differential circuit allows for the addition of a neutralizing capacitor (C...). neut This is accomplished easily by the neutralizing capacitor (C). neut Charges of opposite polarity taken from the opposite phase signal path are injected into the gate. Figure 7 It is C gd A schematic diagram of the neutralization mechanism 700, wherein the transistor 702 with gate capacitance 704 can be neutralized by capacitor C. neut 706 neutralization. As a result, if C neut = C gd The net charge feedback from the drain to the gate is zero, and the feedback path is eliminated. For Figure 6 Each of the two transistors 602 and 604 in the circuit performs this operation.

[0041] So far, we have solved the amplifier stability problem for differential signals. If we now consider common-mode signals, we will observe that all components on both sides of the axis of symmetry are identical and handle identical signals. The circuit will again reduce to... Figure 2 The circuit shown has the following important difference: from the neutralizing capacitor Cneut charge is now added to the charge through C gd charge, rather than canceling it. As a result, the neutralization technique that solves the differential instability problem exacerbates the common mode instability problem.

[0042] Figure 8 is a schematic diagram of a differential amplifier modified for common mode stability. Differential amplifier 800 includes a first pair of transistors 802, 804, a divider 810, a combiner 812, and bias resistors 814, 816. Figure 8 shows a circuit modification that can ensure both differential and common mode stability simultaneously. The large bias resistors 814, 816 are essentially open circuits at the frequencies of interest. The floating center tap of the input transformer results in an open circuit for the common mode signal. As a result, the input of the circuit can only see the parasitic capacitance C p . Figure 9 is a schematic diagram of the equivalent circuit 900 and equivalent LC tank circuit 950 of Figure 8 . Equivalent circuit 900 includes transistor 902 with parasitic capacitance C p 904, gate and neutral capacitances 906, and load inductance 908. Although the transistor still provides a negative real impedance, the absence of a resonant LC tank eliminates the conditions for oscillation.

[0043] Figure 8 The circuit architecture in Figure 10 is sufficient to ensure stability of a differential amplifier that combines the power of two transistors, commonly referred to as a "push-pull" architecture. There is often a need to supply higher output power, which requires combining more than two signal paths, in which case the stability measures above can not be sufficient.

[0044] Figure 10 is a schematic diagram of a four-transistor power combiner amplifier stage 1000, which illustrates a power combiner 1002 and a power divider 1004. Figure 10 illustrates a power combiner amplifier with four output transistors. The input is supplied by a differential driver stage (not shown), similar to Figure 8The input power is divided by the power divider and supplied to the four transistors of the output stage, whose amplified output power is subsequently combined by the power combiner to provide the differential output. This architecture is capable of providing higher power compared to the differential push-pull amplifier. The four-transistor amplifier combines the signals of two differential amplifiers. Therefore, ideally, it will provide twice the output power, but due to the losses of the passive components, the actual power increase is slightly less. For factors higher than two, power combiners with more transistors are typically used (e.g., 8 transistors for a power factor increase of 4). The general case of N stages is called a Distributed Active Transformer (DAT) amplifier. Although the present disclosure is shown for a four-transistor amplifier, the techniques can be applied to amplifiers with more stages.

[0045] In the previous sections, it was shown that the differential amplifier stage can handle two types of signals, depending on their polarity: i) differential and ii) common mode. Also, measures were disclosed for stabilizing the amplifier with respect to both types of signals. In an amplifier with four output transistors, there are two additional degrees of freedom, resulting in a total of four possible signal configurations or modes. Figure 11A - D shows the four possibilities. Figure 11A is a schematic diagram of a four-transistor power-combining amplifier stage in the differential mode. Figure 11B is a schematic diagram of a four-transistor power-combining amplifier stage in the common mode. Figure 11C is a schematic diagram of a four-transistor power-combining amplifier stage in the first hybrid mode. Figure 11D is a schematic diagram of a four-transistor power-combining amplifier stage in the second hybrid mode.

[0046] Along with identifying the differential and common mode signals, there are two hybrid modes in addition. Using the methods from the previous sections, differential and common mode stability can be ensured. Adding neutralizing capacitors to the transistor pairs M1-M2 and M3-M4 will ensure stability in the differential mode ( Figure 11A ) and hybrid mode 1 ( Figure 11C ). Letting the power divider float and using large resistors to bias all four transistors will ensure stability in the common mode ( Figure 11B ), similar to the conventional solution for the differential push-pull amplifier in Figure 8 However, hybrid mode 2 ( Figure 11D ) does not benefit from any of the above measures and can be prone to oscillation. Figure 12 shows the equivalence between the output stage in hybrid mode 2 and the circuit in Figure 2 . Figure 12 is a schematic diagram of a four-transistor power-combining amplifier stage 1200 in the second hybrid mode, illustrating the oscillation mechanism through the power combiner 1202. Figure 13 is a schematic diagram of a four-transistor power-combining amplifier stage 1300 in the second hybrid mode, illustrating the oscillation mechanism through the power combiner 1302. Figure 12Figure 13 shows a schematic diagram of an equivalent circuit 1300 of the amplifier stage 1000. The amplifier stage 1300 has a single MOS transistor 1302, a gate-to-drain capacitance 1306, a gate inductance 1304, and is coupled with an inductive load 1308. The gate inductance 1304 includes the inductance of the power divider (e.g., 1004, 1404), and the inductive load 1308 includes the inductance of the power combiner (e.g., 1002, 1402).

[0047] One possible solution to this stability problem is to introduce separate transformers in front of the transistor pairs M1-M2 and M3-M4, which would isolate the inductance of the power divider from the transistor gates, similar to the solution in Figure 6 The drawback of this approach is a large increase in the required circuit area due to the additional transformers.

[0048] The present disclosure presents an area-efficient circuit solution that prevents mixed-mode oscillation without adversely affecting the desired differential-mode signal. First, consider the signal of the desired differential-mode Figure 11A It is observed that the signals handled by transistors M1 and M4 are nominally identical, having the same amplitude and phase. The same is true for the signals of M2 and M3. Therefore, by shorting the drains of M1 and M4, and the drains of M2 and M3, the operation of the circuit in its differential mode will not be altered, as no current will flow through the shorted segments (i.e., the voltage across each shorted segment is identical). Figure 14 Figure 14 shows a modification of the given circuit, where the shorted segments are implemented with transmission lines. This circuit handles the differential signal mode unaltered.

[0049] Figure 14 Figure 14 shows a modification of the given circuit, where the shorted segments are implemented with transmission lines. This circuit handles the differential signal mode unaltered.

[0050] Now consider the two unwanted hybrid modes ( Figure 11C and Figure 11D ). It can be observed that in both modes the signal phase through transistors M1 and M4 and M2 and M3 are opposite. Therefore, for both hybrid modes, Figure 14 the shorted section in will introduce a significant power loss. This actually means that these hybrid modes cannot be excited and oscillation is not possible.

[0051] Therefore, Figure 14 the solution presented in Figure 11D allows us to stabilize the hybrid modes by eliminating the conditions for oscillation of the hybrid modes while at the same time leaving the desired differential mode unchanged. Here transistor M1 is coupled to the first inverting input to the combiner, M2 is coupled to the first non-inverting input to the combiner, M3 is coupled to the second non-inverting input to the combiner, and M4 is coupled to the second inverting input to the combiner. Therefore, when the circuit is operated in hybrid mode 2 ( ), coupling the first inverting input to the combiner with the second inverting input to the combiner and coupling the first non-inverting input to the combiner with the second non-inverting input to the combiner will reduce the common mode oscillation.

[0052] In the above discussion we considered both hybrid modes in order to show that the solution is equally applicable to both, although already hybrid mode 1 is stabilized with the addition of the neutralizing capacitor and only hybrid mode 2 is at risk of oscillation and therefore of interest.

[0053] Figure 15 and Figure 16 shows a practical geometric implementation of the presented solution. Figure 15 is a top view of a semiconductor layout of a four-transistor power combiner amplifier stage with a stabilization mechanism. Figure 16 is a perspective view of a semiconductor layout of a four-transistor power combiner amplifier stage with a stabilization mechanism.

[0054] While the application has been illustrated and described in considerable detail with various embodiments, it is not intended that the application be limited to only such details. Additional advantages and modifications will readily occur to those skilled in the art. The application in its broader aspects is therefore not limited to the specific details, representative apparatus and method, and illustrative examples shown and described. Accordingly, departures can be made from such details without departing from the spirit or scope of the general inventive concept. Thus, the application is not to be limited by the foregoing description, but is instead to be defined by the scope of the appended claims.

Claims

1. A circuit comprising: a divider having a first output port with a first inverting output and a first non-inverting output and a second output with a second inverting output and a second non-inverting output; a combiner having a first input port with a first inverting input and a first non-inverting input and a second input port with a second inverting input and a second non-inverting input; a first pair of transistors, wherein each transistor has a first input terminal coupled to ground, a first output terminal coupled to the first input port of the combiner, and a first control terminal driven by the first output port of the divider; a second pair of transistors, wherein each transistor has a second input terminal coupled to ground, a second output terminal coupled to the second input port of the combiner, and a second control terminal driven by the second output of the divider; a first stabilization line coupled between the first non-inverting input and the second non-inverting input of the combiner; and a second stabilization line coupled between the first inverting input and the second inverting input of the combiner.

2. The circuit of claim 1, wherein the transistors are metal oxide semiconductor field effect transistors (MOSFETs) and the input terminals are source terminals, the output terminals are drain terminals, and the control terminals are gate terminals.

3. The circuit of claim 1, wherein the transistors are bipolar junction transistors (BJTs) and the input terminals are emitter terminals, the output terminals are collector terminals, and the control terminals are base terminals.

4. The circuit of claim 1, wherein the first stabilization line and the second stabilization line are Al or Cu.

5. The circuit of claim 1, wherein the first stabilization line includes a first inductor and the second stabilization line includes a second inductor.

6. The circuit of claim 1, wherein the first stabilization line includes a first capacitor and the second stabilization line includes a second capacitor.

7. The circuit of claim 1, wherein the first stabilization line includes a first resistor and the second stabilization line includes a second resistor.

8. The circuit of claim 1, wherein the divider includes four inductive output segments and the combiner includes four inductive input segments.

9. The circuit of claim 1, wherein the combiner and the divider are configured to operate at frequencies at or above 20 GHz.

10. A radio frequency (RF) power combiner comprising: a first port having a first inverting input and a first non-inverting input; a second port having a second inverting input and a second non-inverting input; a first stabilization line coupled between the first non-inverting input and the second non-inverting input; a second stabilization line coupled between the first inverting input and the second inverting input.

11. The radio frequency (RF) power combiner of claim 10, wherein the radio frequency (RF) power combiner is configured to operate at frequencies at or above 20 GHz. ​ ​ 12. The radio frequency (RF) power combiner of claim 10, further comprising a first inductor coupled between the first non-inverting input and the power terminal, a second inductor coupled between the first inverting input and the power terminal, a third inductor coupled between the second non-inverting input and the power terminal, and a fourth inductor coupled between the second inverting input and the power terminal.

13. The radio frequency (RF) power combiner of claim 12, wherein the first inverting input is substantially in phase with the second inverting input, and the first non-inverting input is substantially in phase with the second non-inverting input, while the inverting and non-inverting inputs are out of phase.

14. The radio frequency (RF) power combiner of claim 10, wherein the first stabilization line comprises the first inductor, and the second stabilization line comprises the second inductor.

15. The radio frequency (RF) power combiner of claim 10, wherein the first stabilization line comprises the first capacitor, and the second stabilization line comprises the second capacitor.

16. A method to reduce oscillations in a four-signal system, comprising: receiving a first signal pair comprising a first inverting signal and a first non-inverting signal, and a second signal pair comprising a second inverting signal and a second non-inverting signal; amplifying the first inverting signal with a first inverting transistor coupling a first inverting inductor with a power supply at a first inverting input; amplifying the first non-inverting signal with a first non-inverting transistor coupling a first non-inverting inductor with the power supply at a first non-inverting input; amplifying the second inverting signal with a second inverting transistor coupling a second inverting inductor with the power supply at a second inverting input; amplifying the second non-inverting signal with a second non-inverting transistor coupling a second non-inverting inductor with the power supply at a second non-inverting input; coupling the first non-inverting input and the second non-inverting input; and coupling the first inverting input and the second inverting input.

17. The method of claim 16, wherein coupling the first non-inverting input and the second non-inverting input is in response to the first non-inverting transistor and the first inverting transistor operating in common mode, and coupling the first inverting transistor and the second inverting transistor is in response to the second non-inverting transistor and the second inverting transistor operating in common mode.

18. The method of claim 17, wherein coupling the first non-inverting input and the second non-inverting input is via a first inductor, and coupling the first inverting input and the second inverting input is via a second inductor.

19. The method of claim 17, wherein coupling the first non-inverting input and the second non-inverting input is via a first capacitor, and coupling the first inverting input and the second inverting input is via a second capacitor.

20. The method of claim 17, wherein coupling the first non-inverting input and the second non-inverting input is via a first stabilization transistor, and coupling the first inverting input and the second inverting input is via a second stabilization transistor. ​

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