Systems, methods, and apparatus for enabling partial data transmission with indicators

Abstract

The present invention discloses a system, apparatus and method for an interface-based system that can be composed of different sets of blocks with different data bus sizes. These different data bus sizes can be optimized by allowing partial data transmission on buses of different sizes.

Description

Background Art

[0001] Some protocols do not provide for transferring partial data from one data bus to a second data bus of increased capacity. This deficiency can result in systems with mismatched data bus sizes requiring additional merging buffers at all points in the interconnect and wherever the data bus size mismatch occurs. These additional merging buffers result in an undesirable increase in area and / or power requirements for the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The accompanying drawings provide a visual representation that will be used to more fully describe the various representative embodiments and can be used by those skilled in the art to better understand the disclosed representative embodiments and their inherent advantages. In the accompanying drawings, like reference numerals represent corresponding elements.

[0003] Figure 1 An interface system is shown.

[0004] Figure 2 A merge buffer implementation is shown.

[0005] Figure 3 illustrative embodiments described herein.

[0006] Figure 4 Another embodiment described herein is shown.

[0007] Figure 5 A table according to a representative embodiment is shown.

[0008] Figure 6 Another table according to another representative embodiment is shown. DETAILED DESCRIPTION

[0009] Although the present disclosure is capable of embodiment in many different forms, specific embodiments are shown in the drawings and will be described in detail herein, it should be understood that the disclosure should be considered as an example of the principles described and is not intended to limit the disclosure to the specific embodiments shown and described. In the following description, like reference numerals are used to describe the same, similar or corresponding parts in the several views of the drawings.

[0010] In this document, relational terms such as first and second, top and bottom, etc. may be used solely to distinguish one entity or action from another and do not necessarily require or imply any actual such relationship or order between such entities or actions. The terms "comprises," "comprising," "including," "containing," or any other variations thereof are intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitations, an element beginning with "comprises" does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0011] Reference throughout this document to "one embodiment," "certain embodiments," "an embodiment," or similar terms means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of such phrases in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments without limitation.

[0012] As used herein, the term "or" is to be interpreted as inclusive or meaning any one or any combination. Thus, "A, B, or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B, and C." An exception to this definition occurs only when a combination of elements, functions, steps, or actions are inherently mutually exclusive in some way.

[0013] For simplicity and clarity of description, reference numerals may be repeated in the accompanying drawings to indicate corresponding or similar elements. Many details are set forth to provide an understanding of the embodiments described herein. The embodiments may be practiced without these details. In other cases, well-known methods, procedures, and components are not described in detail to avoid obscuring the embodiments. This specification should not be considered to be limited to the scope of the embodiments described herein.

[0014] The following terminology may be used in the description of the various embodiments of the present disclosure.

[0015] Auxiliary: additional, supplementary.

[0016] AXI: Advanced eXtensible Interface (AXI). AXI is Developed interface.

[0017] AXID: Advanced eXtensible Interface (AXI) identifier. AXI is Developed for AMBA microcontroller bus interface, and is currently used by many companies such as For use by limited liability companies.

[0018] Beat: A single data transfer within an AXI burst.

[0019] Block Offset: Specifies the desired data within a block of data stored within a cache line. Sometimes referred to simply as "offset."

[0020] Buffer: A temporary storage area, typically located in RAM. The purpose of most buffers is to act as a holding area that allows the CPU to manipulate data before transferring it to the device.

[0021] Bus: A communication mechanism that transfers data between components within a computer, between modules of a computer, or between computers. As used herein, the term "bus" encompasses all related hardware components (wires, optical fibers, etc.) and software, including communication protocols.

[0022] Cache: Cache memory, also known as CPU memory, is random access memory (RAM) that a computer microprocessor can access faster than it can access regular RAM. This memory is typically integrated directly with the CPU chip or placed on a separate chip with a separate bus interconnect to the CPU.

[0023] Cache block: The basic unit of cache storage. It can contain multiple bytes / words of data. A cache line is the same as a cache block. Note that this is different from a cache line.

[0024] CPU: Central Processing Unit; an electronic circuit within a computer that carries out the instructions of a computer program by performing the basic arithmetic, logic, control, and input / output (I / O) operations specified by the instructions.

[0025] Execution: The basic operating process of a computer. This is the process by which a computer retrieves program instructions from its memory, determines the actions indicated by the instructions, and performs those actions. This cycle is repeated continuously by the central processing unit (CPU) from the time the computer is turned on until it is shut down.

[0026] Flowchart: A type of diagram that represents an algorithm, workflow, or process. The flowchart shows the steps as various types of boxes and indicates their order.

[0027] Generate: Produce, create, or result from one or more steps or actions.

[0028] Index: Describes which cache set the data has been placed into.

[0029] Interface: A hardware connection or user interface. Interface can also be used as a verb to describe how two devices connect to each other. Hardware interfaces are used to connect two or more electronic devices together.

[0030] Microarchitecture: Computer organization, the way a given instruction set architecture (ISA) is implemented in a processor.

[0031] Interface bridge: Joins two or more interfaces to a tier. The tiers are joined by an interface bridge as if they were all joined to the same switch.

[0032] I / O: Input / Output, the transfer of data between the processor and peripheral devices in a data processing system. I / O devices may include keyboards, displays, pointing devices, etc., which may be coupled directly or through an intervening I / O controller.

[0033] Merge: Combine parts of data.

[0034] Merge buffer: A type of buffer that stores data that is to be merged or has been merged.

[0035] Module: A component or part of a program or device that may include hardware, software, or a combination of hardware and software. In modules that include software, the software may include one or more routines or subroutines. One or more modules may constitute a program and / or device.

[0036] Offset: Block offset is sometimes referred to simply as "offset" or "displacement".

[0037] Operation: A single step performed by a computer during the execution of a program.

[0038] Sort tags: Categories of metadata that help describe an item and allow it to be found again through browsing or searching.

[0039] Peripheral: A computer device, such as a keyboard or printer, that is not part of the basic computer (i.e., memory and microprocessor). These auxiliary devices are generally intended to be connected to a computer.

[0040] Protocol Bridge: A device that connects two networks, such as a local area network (LAN) or two segments of the same LAN that use the same protocol, such as Ethernet or Token Ring.

[0041] Register: A temporary storage area.

[0042] Source code: Any collection of code written in a human-readable programming language, possibly with comments, typically in plain text. A program's source code is specifically designed to facilitate the work of a computer programmer, who specifies actions to be performed by the computer by writing the source code. This source code is typically converted by an assembler or compiler into binary machine code that the computer understands. This machine code can then be stored for later execution. Alternatively, the source code can be interpreted and thus executed immediately.

[0043] Tag: A unique identifier for a set of data. Because different areas of memory can be mapped into blocks, tags are used to distinguish between these areas.

[0044] In interface protocols, such as the AXI protocol, there is typically no provision for transferring partial data from a first bus to a second bus, which is a wider data bus, also described as an increased capacity bus. This results in systems based on interfaces, such as AXI-based systems, having mismatched data bus sizes, which means that the system uses additional merging buffers at all points on the interconnect where such a data bus size mismatch is encountered. This results in undesirable additional area / power overhead for the system. The embodiments described herein enable partial data transfers over a wider data bus, thereby optimizing the area / power metrics of the system.

[0045] A sufficiently complex AXI-based system can consist of a diverse collection of blocks with different data bus sizes. These varying data bus sizes require merging buffers at each point where a data bus width mismatch is encountered. Merging buffers are required when data is moved from a narrow data bus to a wider data bus, and data is generally not guaranteed to arrive back-to-back on the narrow data bus because the AXI protocol does not support partial data transfers on the wider data bus.

[0046] Figure 1 A system 100 is shown that includes a first interface shown as an AXI master 102 , an interface-to-interface bridge shown as an AXI-to-AXI bridge 104 , and a second interface shown as an AXI slave 106 .

[0047] The first interface, shown as an AXI host 102, has a memory module 110. The memory module 110 includes one or more registers 112 and one or more data buffers 114. The registers 112 serve as temporary storage areas or memory areas built into the memory module 110. The registers 112 can be used to fetch instructions and store them as each instruction is executed. The registers 112 can be used to pass data from the memory to the processor.

[0048] The data buffer 114 is used to buffer data at the AXI master 102. The data in the data buffer 114 is received via the bus 116.

[0049] The interface-to-interface bridge, shown as AXI-to-AXI bridge 104, includes a memory or storage module 120. The storage module 120 includes one or more registers 122 and one or more merge buffers 124.

[0050] The second interface, shown as AXI slave 106 , includes a storage module or memory module 126 .

[0051] The second interface (AXI slave 106) has a 2 GHz clock, and the first interface (AXI master 102) has a 1 GHz clock. The difference between these two clocks is indicated by dashed line 103. Register 112 communicates with register 122 via bus 118. Register 122 communicates with memory module 126 via 128.

[0052] The first interface (AXI master 102) has a 64B data bus 116, and the second interface (AXI slave 106) has a 32B data bus 130. The AXI to AXI bridge 104 manages data bus width mismatches and has a tracker to handle transactions. Figure 1 As shown, bus width and clock speed are proportional. Thus, the AXI master 102 has a 64B data bus 116 and a 1 GHz clock, while the AXI slave 106 has a 32B data bus 130 and a 2 GHz clock.

[0053] Figure 1 The AXI to AXI bridge 104 is shown using full read buffering to merge two 32B beats (130) into one 64B beat (116) because there is no guarantee that the two 32B beats will arrive back to back. This can result in significant overhead in terms of area if the AXI host 102 has many outstanding read transactions.

[0054] Figure 2 A system 200 is shown, which includes a first interface (AXI master 202), an interface-to-interface bridge 240 (AXI-to-AXI bridge 204), and a second interface (AXI slave 206). ReadA (ARLEN=0x0, ARSIZE=64B) 232 and ReadB (ARLEN=0x0, ARSIZE=64B) 234 are shown. AXI-to-AXI bridge 204 sends ReadA (ARLEN=0x1, ARSIZE=32B) 236 and ReadB (ARLEN=0x1, ARSIZE=32B) 238.

[0055] Shown are Data_A0, 32B, 240; Data_B0, 32B, 242; Data_A1, RLAST, 32B, 244; Data_B1, RLAST, 32B, 246; RData_A0A1, RLAST, 64B, 250; and RData_B0B1, RLAST, 64B, 252. The merge buffer covers the window from the time the first data 240 arrives until the last data 252 is delivered.

[0056] Figure 2 The figure shows that there are two pending read requests on the narrow data bus side (e.g., a 32B data bus). It is possible that the first chunk (half) for both reads arrives before the second chunk is available. The AXI to AXI bridge 204 needs to save the first read chunk because the wider data bus side (64B) can only accept data when both chunks are available. This requires the use of a merge buffer.

[0057] For example: if the AXI host 232 supports 256 outstanding read requests, where each outstanding read request is one cache line size, then the size of the merge buffer required in this case is 64B×256=128K floating point operations per second, which is a significant overhead in terms of PPA.

[0058] The embodiment described herein includes an AXI slave 206 that tags each read data beat with a chunk valid identifier called "CV."

[0059] There are parameters for CV (block-efficient) generation:

[0060] Each bit of CV indicates the portion of the data bus that carries valid data.

[0061] The portion of the wider data bus represented by each bit of CV is the same size as the narrowest data bus in the system.

[0062] The width of a CV on a particular bus is determined by the ratio of the narrowest data bus size in the system to its own bus size.

[0063] a. For example: In a system with 64B and 32B data bus widths, CV will be a 2-bit value for the 64B bus.

[0064] b. For example: In a system with 64B, 32B, and 16B data bus widths, CV will be a 4-bit value for a 64B bus and a 2-bit value for a 32B bus.

[0065] The CV value of 0 is not allowed.

[0066] Allows CV to have staggered values.

[0067] For example, in a system with 64B and 16B data bus widths, the allowed CV value is 0101.

[0068] It is shown that the RLAST semantics do not change with the specific implementation, which means that RLAST always arrives on the last data beat, even if the last data beat may not contain valid data on the entire bus. This ensures that all existing IPs that are monitoring RLAST to detect the protocol completion window still comply with the process.

[0069] like Figure 3 As shown, system 300 has 64B and 32B bus widths, where CV on a 64B bus is 2 bits wide and each bit indicates half validity.

[0070] Specifically, if Figure 3 As shown, CV[1:0]=2'b11, 302 has a valid lower chunk (CV[0]) 306 and a valid upper chunk (CV[1]) 304. Next, CV[1:0]=2'b01, 308 has a valid lower chunk (CV[0]) 312 and an invalid upper chunk (CV[1]) 310. Third, CV[1:0]=2'b10, 314 has an invalid lower chunk (CV[0]) 318 and a valid upper chunk (CV[1]) 316.

[0071] exist Figure 3 In the case shown, the legal value of CV[1:0](302,308,314) = {2'b11,2'b10,2'b01}

[0072] Figure 4 A block validation example 400 is shown according to embodiments described herein. Figure 4 A system 400 is shown, which includes a first interface (AXI master 402), an interface-to-interface bridge (AXI-to-AXI bridge 404), and a second interface (AXI slave 406). ReadA (ARLEN=0x0, ARSIZE=64B) 432 and ReadB (ARLEN=0x0, ARSIZE=64B) 434 are sent from the AXI master 402. The AXI-to-AXI bridge 404 sends ReadA (ARLEN=0x1, ARSIZE=32B) 436 and ReadB (ARLEN=0x1, ARSIZE=32B) 438.

[0073] Data_A0,32B,440; Data_B0,32B,442; Data_B1,RLAST,32B,446; and Data_A1,RLAST,32B,444 are sent from the AXI slave 406. Bits RData_A0,64B,CV=01,450; RData_B0B1,RLAST,64B,CV=11,452; and RData_A1,RLAST,64B,CV=10,454 are shown.

[0074] Figure 4 and Figure 2is different because data bits 440, 442, 444, and 446 are in different sequences, i.e., A0 (440) and A1 (444) are not in direct sequence; instead, B0 (442) and B1 (446) are between A0 (440) and A1 (444). In addition, there is no merge buffer, as Figure 2 In addition, bits 450, 452, and 454 have associated CV identifiers. The order of data 440, 442, 444, and 446 is random.

[0075] like Figure 4 As shown, the AXI to AXI bridge 404 sends partial data RDATA_A0 (440) on the wider data bus using a block valid indication of CV=01 (450). When Data_B0 (442) and Data_B1 (446) arrive back-to-back from the narrow side, they can be compressed into a single wider data bus response and sent as RData_B0B1 with CV=11 (452). Finally, when the second beat (444) of ReadA arrives, it is sent with CV=10 and an RLAST indication (454).

[0076] The AXI master 402 needs to understand the meaning of the associated CV value so that the AXI master 402 can receive the correct portion of the data.

[0077] The embodiment also includes one or more flags from the AXI master 402 that can inform the AXI slave 406 whether the AXI master 402 can tolerate a partial data transfer. This flag can be identified or referred to as "ChunkValidEnable." A traditional AXI master can choose to drive ChunkValidEnable = 0.

[0078] If the AXI slave 406 is not capable of driving different chunk valid values, then this is an implementation where the flag may be set to all ones.

[0079] If the AXI master 402 sets ChunkValidEnable=0, the AXI slave 406 sets CV=all 1s.

[0080] Figure 5 A representation 500 is shown, which includes "new field" 502, "channel" 504, "driver" 506, "width" 508, and "meaning" 510. In field 502 are "chunk valid enable" 512 and CV[N-1:0] 522. Channel 504 includes AR 514 and R 524. Driver 506 includes AXI master 516 and AXI slave 526. Width 508 includes "1" 518 and "N" 528. Meaning 510 includes descriptions of what the driver indicates (520, 530).

[0081] If the AXI system does not have the flexibility to add new fields, the ARUSER / RUSER fields can be used to populate the new fields.

[0082] Figure 5 The illustrated embodiment can be enhanced by driving two or more (up to N, where "N" is any suitable number) different 32B data beats on a single 64B read data bus, as shown. Figure 6 shown.

[0083] Figure 6 The implementation shows that the AXI slave is marked with a special message "Multiple Data Transfer Enabled". In this mode, each different chunk being transferred is associated with its own set of R channel fields, such as:

[0084] RID[N-1:0](642);

[0085] RRESP[N-1:0](652);

[0086] RUSER[N-1:0](662); and

[0087] RLAST[N-1:0](672).

[0088] The AXI host can use the field "MDTEnable" (Multiple Data Transfer Enable) (622) to control whether it can accept multiple narrow data beats with different RIDs on the wider data bus. Note that there can be "N" unique RIDs and RLASTs that can reach a single RDATA bus, and the host should be able to uniquely identify and handle it.

[0089] This will enable the chunk merge buffer to be eliminated while meeting high bandwidth demands without wasting any data bus efficiency.

[0090] Figure 6 A representation 600 is shown, including "new field" 602, "channel" 604, "driver" 606, "width" 608, and "meaning" 610.

[0091] In field 602 are "chunk valid enable" 612; MDTEnable 621; CV[N-1:0] 622; RID[N-1:0] 642; RRESP[N-1:0] 652; RUSER[N-1:0] 662; and RLAST[N-1:0] 672;

[0092] Channel 604 includes AR 614; AR 623; R 624; R 644; R 654; R 664; and R 674.

[0093] Driver 606 includes AXI master 616, AXI master 625, AXI slave 626, AXI slave 646, AXI slave 656, AXI slave 666, and AXI slave 676. Thus, there are intermediate AXI interface slaves that can optionally send portions of data over a wider bus.

[0094] Width 608 includes “1” 618 ; “1” 627 ; “N” 628 ; “N×M (M=RID width)” 648 ; “N×M (M=RRESP width)” 658 ; “N×M (M=RUSER width)” 668 ; and “N” 678 .

[0095] Meaning 610 includes a description of the instructions, as shown by 620, 629, 630, 650, 660, 670, and 680, respectively.

[0096] If the AXI master sets MDTEnable=0, the AXI slave sets the same value on RID 642, RRESP 652, RUSER 662, and RLAST 672 for all narrow beats within a wider beat.

[0097] If the AXI system does not have the flexibility to add new fields, the ARUSER / RUSER fields can be used to populate the new fields.

[0098] By eliminating the need to merge all data beats from the narrow bus side, the need for merging buffers at all intermediate points on the interconnect is eliminated, thus optimizing the system from an area / power perspective.

[0099] If the system wants to optimize the latency of a critical portion of data, the intermediate agent / AXI slave can choose to send part of the data on a wider data bus. This improves the performance of the entire system.

[0100] Interconnects without a coalescing buffer need to fully serialize requests so that all narrow beats can arrive back-to-back and be coalesced to form wider data beats. According to the embodiments shown in the present disclosure, such interconnects without a coalescing buffer do not need to serialize requests, and all requests can be sent in parallel, thereby improving system performance.

[0101] One or more of these embodiments may be executed on a computing device. A computing device may be understood as any device having a processor, a memory unit, inputs, and outputs. This may include, but is not intended to be limited to, cellular phones, smartphones, tablet computers, laptop computers, desktop computers, personal digital assistants, graphics processing units, field programmable gate arrays, and the like. Components of a computer may include, but are not limited to, a processing unit, a system memory, and a system bus that couples various system components, including the system memory, to the processing unit.

[0102] Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and that can be accessed by a computer.

[0103] Communication media typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal (such as a carrier wave) or other transport mechanism, and includes any information delivery media. The term "modulated data signal" refers to a signal that has one or more of its characteristics set or changed so as to encode information in the signal. By way of example, and not limitation, communication media include wired media such as a wired network or a direct wired connection, and wireless media such as acoustic, radio frequency, infrared, and other wireless media. Combinations of any of the above should also be included within the scope of computer-readable media.

[0104] System memory includes computer storage media in the form of volatile and / or nonvolatile memory such as read-only memory (ROM) and random-access memory (RAM). A basic input / output system (BIOS), containing the basic routines that help to transfer information between elements within the computer, such as during startup, is typically stored in ROM.

[0105] Any combination of one or more computer-usable or computer-readable media may be utilized. A computer-usable or computer-readable medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. More specific examples of computer-readable media (a non-exhaustive list) would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), optical fiber, a portable compact disc read-only memory (CDROM), an optical storage device, a transmission medium (such as those supporting the Internet or an intranet), or a magnetic storage device.

[0106] A computer-usable or computer-readable medium may even be paper or another suitable medium on which the program is printed, as the program may be captured electronically, for example, via optical scanning of the paper or other medium, and then compiled, interpreted, or otherwise processed in a suitable manner as needed, and then stored in a computer memory. In the context of this document, a computer-usable or computer-readable medium may be any medium that can contain, store, convey, propagate, or transmit the program for use by or in connection with an instruction execution system, apparatus, or device. A computer-usable medium may include a propagated data signal having the computer-usable program code embodied therewith, either in baseband or as part of a carrier wave. The computer-usable program code may be transmitted using any suitable medium, including but not limited to wireless, wireline, fiber optic cable, RF, etc.

[0107] The computer program code for performing the operation can be written in any combination of one or more programming languages, including object-oriented programming languages such as Java, Smalltalk, C++, C#, and conventional procedural programming languages such as "C" programming language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer or entirely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer through any type of network (including a local area network (LAN) or a wide area network (WAN)), or can be connected to an external computer (e.g., by using the Internet of an Internet Service Provider).

[0108] The present embodiment is described below with reference to the flowchart and / or block diagram of the method, apparatus, system and computer program product according to the embodiment.It should be understood that each box of the flowchart and / or block diagram and the combination of boxes in the flowchart and / or block diagram can be implemented by computer program instructions.

[0109] These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device create a device for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer program instructions can also be stored in a computer-readable medium, which can instruct the computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable medium produce an article of manufacture including an instruction device, which implements the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0110] The computer program instructions may also be loaded onto a computer or other programmable data processing apparatus so that a series of operational steps are performed on the computer or other programmable apparatus to produce a computer-implemented process, so that the instructions executed on the computer or other programmable apparatus provide a process for implementing the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0111] Unless otherwise stated, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.

[0112] As will be appreciated by those skilled in the art, the present disclosure may be embodied as a system, method, or computer program product. Thus, embodiments may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, which may be collectively referred to herein as a "circuit," "module," or "system." Furthermore, embodiments may take the form of a computer program product embodied in any tangible medium of expression having computer-usable program code embodied in the medium.

[0113] The devices, systems, and methods presented herein provide an advancement in the art.

[0114] The various representative embodiments described in detail herein are given by way of example and not limitation. Those skilled in the art will appreciate that various changes in the form and details of the embodiments described may be made to produce equivalent embodiments that are within the scope of the appended claims.

[0115] It can be seen that the systems and methods presented herein provide an advancement over the prior art.

[0116] Accordingly, some of the disclosed embodiments are listed in the following items.

[0117] 1. A method comprising: generating one or more identifiers, wherein each identifier has a plurality of bit and width components; and marking one or more data beats with an associated identifier selected from the one or more identifiers; wherein each bit of the identifier indicates a portion of a data bus that carries valid data; wherein the width of the identifier on a particular data bus is determined by a ratio of a narrowest data bus size to a bus size of the identifier; and enabling partial data transmission of the data beat based on the identifier.

[0118] 2. The method according to item 1, wherein some parameters of the second data bus are the same as the size of the narrowest data bus.

[0119] 3. The method of claim 1 , wherein the identifier has an interleaved value.

[0120] 4. The method according to item 1 further comprises: assigning a completion code associated with the identifier representing the last data beat.

[0121] 5. The method according to item 1 further includes: using a mark to determine whether partial data transmission is allowed.

[0122] 6. The method of item 1, further comprising: driving multiple data beats on a single read data bus, wherein the single read data bus is wider than the data beats.

[0123] 7. The method of item 6, wherein the single read data bus is 64B.

[0124] 8. The method of item 1, further comprising: interleaving one or more unrelated data beats in a non-sequential order on a single read data bus.

[0125] 9. The method according to item 1, wherein the part of the identifier represents valid data and / or invalid data.

[0126] 10. An apparatus comprising: a first bus having a first width; a second bus having a second width, the second width being greater than the first width; and an interface configured to send partial data on the second bus using an identifier indicating that the partial data is valid, wherein the identifier has a plurality of bits and a width component, wherein each bit of the identifier indicates a portion of a first data bus that carries valid data, and wherein the width of the identifier on the first data bus is determined by a ratio of a narrowest data bus size to a width of the first data bus.

[0127] 11. The apparatus according to item 10, further comprising: an interface slave associated with the first data bus; and an interface master associated with the second data bus.

[0128] 12. The apparatus according to item 11, wherein the interface master indicates to the interface slave whether the interface master can accept partial data transmission.

[0129] 13. The apparatus according to item 11, further comprising: one or more intermediate interface slaves, wherein the one or more intermediate interface slaves are configured to send partial data.

[0130] 14. The apparatus of item 11, wherein the interface slave drives a plurality of data beats on the second data bus.

[0131] 15. The apparatus according to item 10, further comprising: an interleaving buffer configured to store interleaved single data beats.

[0132] 16. The apparatus of item 10, wherein the identifier has an interleaved value.

[0133] 17. The device according to item 10, wherein some parameters of the second data bus are the same as the size of the narrowest data bus.

[0134] The various representative embodiments described in detail herein are given by way of example and not limitation. Those skilled in the art will appreciate that various changes in the form and details of the embodiments described may be made to produce equivalent embodiments that are within the scope of the appended claims.

Claims

1. A method for transmitting partial data, the method comprising: At a bridge between a first data bus having a first data bus size and a second data bus having a second data bus size larger than the first data bus size: generating one or more second data beats based on one or more first data beats received via the first data bus, each second data beat comprising data from the one or more first data beats; generating one or more identifiers, each identifier having a plurality of bit and width components; as well as marking one or more second data beats with an associated identifier selected from the one or more identifiers, wherein each bit of the identifier indicates a portion of the second data bus carrying valid data, and wherein the width of the identifier on the second data bus is determined by a ratio of a narrowest data bus size to a second data bus size; and Partial data transmission in the second data beat is enabled based on the identifier. 2 . The method according to claim 1 , wherein some parameters of the second data bus are the same as the size of the narrowest data bus. The method of claim 1 , wherein the identifier has an interleaved value.

4. The method according to claim 1, further comprising: A completion code associated with the identifier representing the last data beat of the read transaction is specified.

5. The method according to claim 1, further comprising: A flag is utilized to determine whether a host component coupled to the second data bus is capable of accepting a partial data transfer.

6. The method according to claim 1, further comprising: A plurality of data beats from the first read data bus are driven onto a second read data bus, wherein the second read data bus is wider than the first read data bus. The method according to claim 6 , wherein a width of the second read data bus is 64B.

8. The method according to claim 1, further comprising: One or more unrelated data beats from a first read data bus are interleaved in a non-sequential order on a second read data bus, wherein the second read data bus is wider than the first read data bus.

9. The method of claim 1, wherein the portion of the identifier represents valid data and / or invalid data.

10. The method according to claim 1, further comprising: receiving, at the network bridge, a read request from a host component of a computer system, the read request indicating whether the host component is able to accept a partial data transfer; Transmitting the read request from the network bridge to a slave component of the computer system: In response to the read request, receiving the first data beat from the slave component via the first data bus at the bridge; enabling partial data transfer in the second data beat based on the identifier when the host component indicates that the host component can accept partial data transfer on the second data bus; and When the host component indicates that the host component cannot accept partial data transmission on the second data bus, partial data transmission in the second data beat is disabled.

11. A device for transmitting partial data, the device comprising: a first data bus having a first data width; a second data bus having a second data width, the second data width being greater than the first data width; and A bridge interface, located between the first data bus and the second data, and configured to: generating a second data beat based on a first data beat received via the first data bus, wherein the second data beat is sent via the second data bus, the second data beat including data from the one or more first data beats; Generate identifiers with multiple bit and width components; marking the second data beat with the identifier; as well as The second data beat is sent on the second data bus, the second data beat comprising partial data and the identifier, wherein each bit of the identifier indicates a portion of the second data bus carrying valid data, and wherein the width of the identifier on the second data bus is determined by a ratio of a narrowest data bus size to the width of the second data bus.

12. The apparatus according to claim 11, further comprising: an interface slave associated with the first data bus; and An interface host is associated with the second data bus.

13. The apparatus of claim 12, wherein the interface master indicates to the interface slave whether the interface master can accept a partial data transfer.

14. The apparatus according to claim 12, further comprising: One or more intermediate interface slaves are configured to send partial data.

15. The apparatus of claim 12, wherein the interface slave drives the first data beat on the first data bus.

16. The apparatus according to claim 11, further comprising: An interleaving buffer is configured to store the interleaved first data beats. The apparatus of claim 11 , wherein the identifier has an interleaved value.

18. The apparatus according to claim 11, wherein some parameters of the second data bus are the same as the narrowest data bus size.

19. The apparatus of claim 11, wherein the bridge interface is further configured to: receiving a read request from an interface host of a computer system, the read request indicating that the interface host is able to accept a partial data transfer; transmitting the read request from the bridge interface to an interface slave; receiving the first data beat from the interface slave on the first data bus in response to the read request; When the interface slave indicates that the interface master can accept partial data transmission: sending the second data beat including partial data and the identifier on the second data bus; and When the interface slave indicates that the interface master cannot accept partial data transmission, partial data transmission in the second data beat is disabled.

Images