Three-dimensional NOR array including active area pillars and method of manufacturing the same

Abstract

A semiconductor structure includes a vertical alternating stack of insulating strips and conductive strips located above a substrate and laterally spaced from each other by line grooves. A semiconductor region assembly and a laterally alternating sequence of dielectric pillar structures are located in a corresponding one of the line grooves. A memory film is located between each pair of adjacent vertical alternating stacks and laterally alternating sequences. Each of the semiconductor region assemblies includes a source pillar structure, a drain pillar structure, and a channel structure, the channel structure including a pair of lateral semiconductor channels laterally connecting the source pillar structure and the drain pillar structure. The memory film may include a charge storage layer or a ferroelectric material layer.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. non-provisional patent application serial number 16 / 707,036, filed on December 9, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to the field of semiconductor devices, and in particular, to a three-dimensional memory device including a two-dimensional array of active area pillars and a vertical channel plate and a method of manufacturing the same. Background Art

[0004] NOR memory devices include memory cells connected in parallel. The memory cells are directly connected to the source and drain without passing through adjacent memory cells for source and / or drain connection. Therefore, NOR memory cells can be directly accessed without passing through adjacent memory cells. Therefore, NOR memory devices can provide faster access speeds compared to NAND memory devices and can be used in storage class memory (SCM) devices. Summary of the invention

[0005] According to one aspect of the present disclosure, a semiconductor structure is provided, which includes: a vertical alternating stack of insulating strips and conductive strips located above a substrate and laterally spaced apart from each other by line grooves; a laterally alternating sequence of semiconductor region components and dielectric pillar structures located within a corresponding one of the line grooves; and a memory film located between each pair of adjacent vertical alternating stacks and laterally alternating sequences, wherein each of the semiconductor region components includes: a corresponding first active area pillar structure extending through each level of the conductive strips; a corresponding second active area pillar structure extending through each level of the conductive strips and laterally spaced apart from the corresponding first active area pillar structure, one of the corresponding first active area pillar structure and the corresponding second active area pillar structure is a source pillar structure, and the other of the corresponding first active area pillar structure and the corresponding second active area pillar structure is a drain pillar structure; and a corresponding channel structure, the corresponding channel structure including a pair of lateral semiconductor channels laterally connecting the corresponding first active area pillar structure and the corresponding second active area pillar structure.

[0006] According to another aspect of the present disclosure, a method for forming a semiconductor structure is provided, the method comprising: forming a vertical alternating stack of insulating strips and spacer material strips laterally separated from each other by line grooves above a substrate, wherein each of the spacer material strips is formed into or subsequently replaced by a corresponding conductive strip; forming a memory film on the sidewalls of the vertical alternating stack in the line grooves; forming an alternating sequence of a first active area column structure and a second active area column structure in each of the line grooves on a corresponding subset of the memory film, wherein the first active area column structure includes a source column structure and the second active area column structure includes a drain column structure, or the first active area column structure includes a drain column structure and the second active area column structure includes a source column structure; and forming a channel structure, the channel structure laterally connecting a corresponding pair of first active area column structures and second active area column structures in the line grooves. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The drawings with the same reference numerals refer to the same structure. Each drawing with the letter suffix A is a top view, i.e., a plan view. For example, Figure 1A , Figure 2A , Figure 3A etc. are top views. Each figure with a letter suffix B is a vertical cross-sectional view along the vertical plane B-B' in the figure with the same figure number and letter suffix A. Each figure with a letter suffix C is a vertical cross-sectional view along the vertical plane C-C' in the figure with the same figure number and letter suffix A. Each figure with a letter suffix D is a vertical cross-sectional view along the vertical plane D-D' in the figure with the same figure number and letter suffix A. For example, Figure 1B is along Figure 1A A vertical cross-section of the plane B-B', Figure 1C is along Figure 1A Some structures are shown in a top view and three vertical cross-sectional views, and some other structures are shown in a top view and two vertical cross-sectional views.

[0008] Figure 1A , Figure 1B and Figure 1C are various views of a first exemplary structure after forming a first access line according to the first embodiment of the present disclosure.

[0009] Figure 2A , Figure 2B and Figure 2C 2 are various views of a first exemplary structure after forming a first connection via structure according to the first embodiment of the present disclosure.

[0010] Figure 3A , Figure 3B and Figure 3C2 are various views of a first exemplary structure after forming a vertically alternating sequence of insulating layers and sacrificial material layers according to the first embodiment of the present disclosure.

[0011] Figure 4A , Figure 4B and Figure 4C 2 are various views of a first exemplary structure after forming line trenches and vertical alternating stacks of insulating strips and sacrificial material strips according to a first embodiment of the present disclosure.

[0012] Figure 5A , Figure 5B and Figure 5C are various views of a first exemplary structure after forming a memory film according to the first embodiment of the present disclosure.

[0013] Fig. 6A , Figure 6B and Figure 6C are various views of a first exemplary structure after forming a sacrificial trench fill structure according to the first embodiment of the present disclosure.

[0014] Fig. 7A , Figure 7B and Figure 7C 2 are various views of a first exemplary structure after forming a pillar cavity according to the first embodiment of the present disclosure.

[0015] Fig. 8A , Figure 8B and Figure 8C 1 are various views of a first exemplary structure after forming a first active area pillar structure and a second active area pillar structure according to the first embodiment of the present disclosure.

[0016] Fig. 9A , Fig. 9B and Fig. 9C are various views of a first exemplary structure after forming a trench cavity according to the first embodiment of the present disclosure.

[0017] Fig. 10A , Fig. 10B and Fig. 10C are various views of a first exemplary structure after forming a channel structure and a dielectric core according to the first embodiment of the present disclosure.

[0018] Fig.11A , Fig. 11B , Fig. 11C and Fig.11D are various views of a first exemplary structure after forming backside trenches according to the first embodiment of the present disclosure.

[0019] Fig. 12A , Fig. 12B , Fig. 12C and Fig.12D 1 are various views of a first exemplary structure after forming a back-side recess according to the first embodiment of the present disclosure.

[0020] Fig.13A , Fig. 13B , Fig. 13C and Fig.13D 2 are various views of a first exemplary structure after forming a conductive strip according to the first embodiment of the present disclosure.

[0021] Fig.14A , Fig. 14B , Fig. 14C and Fig.14D 2 are various views of a first exemplary structure after forming a dielectric wall structure in a backside trench according to the first embodiment of the present disclosure.

[0022] Fig.15A , Fig. 15B , Fig. 15C and Fig.15D 2 are various views of the first exemplary structure after forming a second connection via structure according to the first embodiment of the present disclosure.

[0023] Fig.16A , Fig. 16B , Fig. 16C and Fig.16D are various views of a first exemplary structure after forming a second access line according to the first embodiment of the present disclosure. Fig.16E For along Fig. 16B A horizontal cross-sectional view taken on the horizontal plane EE'. Fig.16F For along Fig.16E A vertical cross-sectional view taken along the horizontal plane F-F'. Figure 16G for Fig.16E and 16F A circuit diagram of a first exemplary structure is shown.

[0024] Fig.17A , Fig. 17B and Fig. 17C 2 are various views of a second exemplary structure after forming an access cavity according to the second embodiment of the present disclosure.

[0025] Fig.18A , Fig.18B and Fig.18C 2 are various views of a second exemplary structure after the access cavity is expanded by removing a physically exposed portion of a memory film according to the second embodiment of the present disclosure.

[0026] Fig.19A , Fig.19B and Fig.19C2 are various views of a second exemplary structure after forming a back-side recess according to the second embodiment of the present disclosure.

[0027] Fig. 20A , Fig. 20B and Fig. 20C 2 are various views of a second exemplary structure after forming a conductive strip according to a second embodiment of the present disclosure.

[0028] Fig.21A , Fig. 21B and Fig. 21C are various views of a second exemplary structure after forming a dielectric post structure by filling the access cavity with a dielectric material according to the second embodiment of the present disclosure.

[0029] Fig.22A , Fig. 22B and Fig. 22C 2 are various views of a second exemplary structure after forming a second connection via structure according to the second embodiment of the present disclosure.

[0030] Fig.23A , Fig. 23B and Fig.23C 2 are various views of a second exemplary structure after forming a second access line according to the second embodiment of the present disclosure.

[0031] Fig.24A , Fig. 24B , Fig.24C and Fig.24D Various views of alternative embodiments of the first exemplary structure according to the first embodiment of the present disclosure.

[0032] Fig.25A , Fig.25B ,and Fig.25C Various views of alternative embodiments of the second exemplary structure according to the second embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] As described above, embodiments of the present disclosure relate to NOR-type three-dimensional memory devices including a two-dimensional array of active area pillars and a vertical channel plate and methods of manufacturing the same, various aspects of which are described below. Embodiments of the present disclosure can be used to form a three-dimensional NOR memory device including a ferroelectric or charge storage type memory cell, which includes ferroelectric or charge storage transistors that are electrically connected in parallel, vertically spaced apart, and overlap or lie below each other.

[0034] The drawings are not drawn to scale. Multiple instances of an element may be repeated where a single instance of an element is shown, unless explicitly described or otherwise clearly indicated that there is no repetition of an element. Serial numbers such as "first," "second," and "third" are used only to identify similar elements, and different serial numbers may be used throughout the specification and claims of this disclosure. The term "at least one" element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.

[0035] The same reference numerals represent the same elements or similar elements. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements that provide an edge or surface shared by the elements. If two or more elements are not in direct contact with each other, the two elements are "separated" from each other.

[0036] As used herein, a first element positioned "on" a second element may be positioned on the outside of a surface of the second element or on the inside of the second element. As used herein, a first element is "directly" positioned on a second element if there is physical contact between a surface of the first element and a surface of the second element. As used herein, a first element is "electrically connected to" a second element if there is a conductive path composed of at least one conductive material between the first element and the second element. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component thereof.

[0037] As used herein, "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0038] A monolithic three-dimensional memory array is a memory array in which multiple memory levels are formed above a single substrate (such as a semiconductor wafer) without an intervening substrate. The term "monolith" refers to the layers of each level of the array being deposited directly on the layers of each lower level of the array. In contrast, a two-dimensional array can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent 5,915,167, entitled "Three-dimensional Structure Memory", a non-monolithic stacked memory is constructed by forming memory levels on separate substrates and vertically stacking the memory levels. The substrate may be thinned or removed from the memory level before bonding, but since the memory level is initially formed above a separate substrate, such memory is not a true monolithic three-dimensional memory array. Various three-dimensional memory devices disclosed herein include monolithic three-dimensional NOR string memory devices and may be manufactured using various embodiments described herein.

[0039] refer to Figure 1A , Figure 1B and Figure 1C , showing a first exemplary structure according to a first embodiment of the present disclosure. The first exemplary structure includes a substrate 8, which may be a semiconductor substrate such as a commercially available silicon wafer. Optionally, semiconductor devices (not shown) such as complementary metal oxide semiconductor (CMOS) transistors may be formed on the top surface of the substrate 8. The CMOS transistors may include control (i.e., driver) circuitry for controlling a NOR memory array subsequently formed thereon.

[0040] An insulating spacer 12 may be formed over the substrate 8. In the case where a semiconductor device is formed on the top surface of the substrate 8, the insulating spacer 12 may be formed over such a semiconductor device (such as a field effect transistor). A first line-level dielectric layer 14 may be formed over the insulating spacer 12. The first line-level dielectric layer 14 includes a dielectric material such as silicon oxide and may have a thickness in the range of 50 nm to 500 nm. A line cavity extending laterally along a first horizontal direction hd1 may be formed through the first line-level dielectric layer 14. At least one conductive material may be deposited in the line cavity, and excess portions of the at least one conductive material may be removed from above a horizontal plane including the top surface of the first line-level dielectric layer 14. The remaining portion of the at least one conductive material includes a first access line 24. The first access line 24 may be used as a source line or a bit line of a subsequently formed three-dimensional NOR memory array. In one embodiment, the first access line 24 is used as a source line.

[0041] The first access lines 24 are parallel to each other and extend laterally along a first longitudinal direction, which may be a first horizontal direction hd1. The first access lines 24 may have the same line width along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. The first access lines 24 may be formed as a one-dimensional periodic array having a periodicity along the second horizontal direction hd2. Memory cells may then be formed over the first access lines 24.

[0042] See also Figure 2A , Figure 2B and Figure 2C , a first via-level dielectric layer 16 may be formed over the first line-level dielectric layer 14. The first via-level dielectric layer 16 includes a dielectric material such as silicon oxide, and may have a thickness in a range of 50 nm to 500 nm. A via cavity may be formed through the first via-level dielectric layer 16. At least one conductive material may be deposited in the via cavity, and excess portions of the at least one conductive material may be removed from above a horizontal plane including a top surface of the first via-level dielectric layer 16. The remaining portions of the at least one conductive material include first connection via structures 26. Each first connection via structure 26 may be formed on a top surface of a corresponding one of the first access lines 24. If the first access line 24 is used as a source line, the first connection via structure 26 may be used as a source connection via structure, or if the first access line 24 is used as a drain line, the first connection via structure 26 may be used as a drain connection via structure. The layer stack of the insulating spacer 12 , the first line-level dielectric layer 14 , and the first via-level dielectric layer 16 is referred to herein as an underlying insulating layer 10 .

[0043] refer to Figure 3A , Figure 3B and Figure 3C, a vertically alternating sequence of a first material layer (such as an insulating layer 32L) and a second material layer (such as a spacer material layer) is formed above the underlying insulating layer 10. As used herein, a "vertically alternating sequence" refers to an alternating sequence of multiple instances of a first element and multiple instances of a second element that are vertically alternating, such that an instance of the second element overlies each instance of the first element and / or potentially underlies each instance of the first element, and an instance of the first element overlies each instance of the second element and / or potentially underlies each instance of the first element. The vertically alternating sequence may include a stack of alternating multiple first material layers (which may be insulating layers 32L) and second material layers (which may be sacrificial material layers 42L). As used herein, a "material layer" refers to a layer that includes a material throughout its entirety. As used herein, an alternating plurality of first elements and second elements refers to a structure in which instances of the first element and instances of the second element are alternating. Each instance of a first element that is not an end element of an alternating plurality of elements is adjacent to two instances of the second element on both sides, and each instance of a second element that is not an end element of an alternating plurality of elements is adjacent to two instances of the first element on both ends. Therefore, the vertical alternating sequence of the first element and the second element is an alternating plurality of first elements and second elements, wherein the alternation of the first element and the second element occurs in the vertical direction. The first element may have the same thickness therebetween, or may have different thicknesses. The second element may have the same thickness therebetween, or may have different thicknesses. The alternating plurality of first material layers and second material layers may start with an instance of the first material layer or an instance of the second material layer, and may end with an instance of the first material layer or an instance of the second material layer. In one embodiment, the instance of the first element and the instance of the second element may form a unit that is periodically repeated in the alternating plurality of elements.

[0044] Each first material layer includes a first material, and each second material layer includes a second material different from the first material. In one embodiment, each first material layer may be an insulating layer 32L, and each second material layer may be a sacrificial material layer. In this case, the stack may include alternating multiple insulating layers 32L and sacrificial material layers 42L, and constitute a prototype stack including alternating layers of insulating layers 32L and sacrificial material layers 42L. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component thereof.

[0045] In one embodiment, the vertically alternating sequence (32L, 42L) may include an insulating layer 32L composed of a first material and a sacrificial material layer 42L composed of a second material, wherein the second material is different from the material of the insulating layer 32L. Insulating materials that can be used for the insulating layer 32L include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, etc.) and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the insulating layer 32L may be silicon oxide.

[0046] The second material of the sacrificial material layer 42L is a sacrificial material that is selectively removable with respect to the first material of the insulating layer 32. As used herein, removal of a first material is "selective with respect to" a second material if the removal process removes the first material at a rate at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0047] The sacrificial material layer 42L may include an insulating material, a semiconductor material, or a conductive material. The second material of the sacrificial material layer 42L may then be replaced with a conductive electrode, which may be used as a word line. Non-limiting examples of the second material include silicon nitride, an amorphous semiconductor material (such as amorphous silicon), and a polycrystalline semiconductor material (such as polycrystalline silicon). In one embodiment, the sacrificial material layer 42L may be a spacer material layer including silicon nitride or a semiconductor material including at least one of silicon and germanium.

[0048] In one embodiment, the insulating layer 32L may include silicon oxide, and the sacrificial material layer may include silicon nitride. The first material of the insulating layer 32L may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for the insulating layer 32L, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of the sacrificial material layer 42L may be formed, for example, by CVD or atomic layer deposition (ALD).

[0049] The thickness of the insulating layer 32L and the sacrificial material layer 42L may be in the range of 20 nm to 50 nm, but smaller and larger thicknesses may be used for each insulating layer 32L and each sacrificial material layer 42L. The number of repetitions of the pair of insulating layers 32L and sacrificial material layers (e.g., control gate electrodes or sacrificial material layers) 42L may be in the range of 2 to 1,024, and typically in the range of 8 to 256, but more repetitions may also be used. In one embodiment, each sacrificial material layer 42L in the vertically alternating sequence (32L, 42L) may have a uniform thickness that is substantially constant within each respective sacrificial material layer 42L. In one embodiment, the vertically alternating sequence (32L, 42L) may start at the bottommost one of the insulating layers 32L and end at the topmost one of the insulating layers 32L.

[0050] The vertical alternating sequence (32L, 42L) may be patterned in a peripheral region (not shown) relative to the Figure 3A , Figure 3B , Figure 3C The memory array region is shown laterally offset along a first horizontal direction hd1 to form a stepped surface. The stepped surface may then be used to form a connecting via structure contacting a corresponding conductive strip. An anti-stepped dielectric material portion may be formed above the stepped surface in a vertical alternating sequence (32L, 42L).

[0051] Although the present disclosure is described using an embodiment in which the spacer material layer is a sacrificial material layer 42L that is subsequently replaced with a conductive strip, embodiments in which the sacrificial material layer is formed as a conductive strip, such as a heavily doped polysilicon strip, are expressly contemplated herein. In this case, the step of replacing the spacer material layer with the conductive strip may be omitted.

[0052] refer to Figure 4A , Figure 4B and Figure 4C A photoresist material stack (not shown) including at least a photoresist layer may be formed above the vertical alternating sequence (32L, 42L) and may be photolithographically patterned to form a linear opening therein. The linear opening extends laterally along a first horizontal direction hd1 and has a uniform width along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. The pattern in the photoresist material stack may be transferred through the vertical alternating sequence (32L, 42L) by at least one anisotropic etching using the patterned photoresist material stack as an etching mask. The portion of the vertical alternating sequence (32L, 42L) below the linear opening in the patterned photoresist material stack is etched to form a linear groove 49. As used herein, a "linear groove" refers to a groove having a straight extension laterally along a horizontal direction.

[0053] The line grooves 49 extend laterally along the first horizontal direction hd1 through the vertically alternating sequence (32L, 42L). In one embodiment, the line grooves 49 have a corresponding uniform width that does not change when translated along the first horizontal direction hd1. In one embodiment, the line grooves 49 may always have the same width, and the spacing between adjacent pairs of line grooves 49 may be the same. In this case, the line grooves 49 may constitute a one-dimensional periodic array of line grooves 49, which has a spacing along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. The width of the line grooves 49 along the second horizontal direction hd2 may be in the range of 30nm to 300nm, such as 40nm to 100nm, but smaller and larger widths may also be used.

[0054] Line trench 49 extends through each layer of the vertical alternating sequence (32L, 42L). The chemical properties of the anisotropic etching process used to etch the material through the vertical alternating sequence (32L, 42L) can be alternating to optimize the etching of the first material and the second material in the vertical alternating sequence (32L, 42L). The anisotropic etching can be, for example, a series of reactive ion etching. The sidewalls of line trench 49 can be substantially vertical, or can be tapered. The patterned photolithographic material stack can then be removed, for example, by ashing.

[0055] Each of the line grooves 49 may include a sidewall (or multiple sidewalls) extending substantially perpendicular to the topmost surface of the substrate 8. Each of the line grooves 49 extends vertically through each layer of the vertical alternating sequence (32L, 42L). A row of first connecting via structures 26 may be physically exposed at the bottom of each line groove 49. The patterned portion of the insulating layer 32L includes an insulating strip 32 having a uniform width and extending laterally along the first horizontal direction hd1. The patterned portion of the sacrificial material layer 42L includes a sacrificial material strip 42 having a uniform width and extending laterally along the first horizontal direction hd1. Each vertical stack group of insulating strips 32 and sacrificial material strips 42 includes a vertical alternating stack of insulating strips 32 and sacrificial material strips 42. A plurality of vertical alternating stacks (32, 42) are formed above the insulating layer 10 below.

[0056] The line grooves 49 extend laterally along the first horizontal direction hd1, and each vertical alternating stack (32, 42) of insulating strips 32 and sacrificial material strips 42 may be located between a corresponding pair of adjacent line grooves 49 that are laterally spaced apart along the second horizontal direction hd2. The vertical alternating stacks (32, 42) of insulating strips 32 and spacer material strips (such as sacrificial material strips 42) are laterally spaced apart from each other by the line grooves 49. In general, the vertical alternating stacks of insulating strips 32 and spacer material strips may be formed above the substrate 8. Although the present disclosure is described using an embodiment in which the spacer material strips are formed as sacrificial material strips 42, embodiments in which the spacer material strips are formed as conductive strips are explicitly contemplated herein. In the case in which the spacer material strips are formed as sacrificial material strips 42, each of the sacrificial material strips may be subsequently replaced with a corresponding conductive strip.

[0057] See also Figure 5A , Figure 5B and Figure 5C , a continuous memory film may be formed on the physically exposed surface of the line groove 49 and over the vertical alternating stack (32, 42). The continuous memory film extends into each of the line grooves 49 and over the vertical alternating stack (32, 42). In one embodiment, the continuous memory film is formed by sequentially depositing a continuous blocking dielectric layer, a continuous charge storage layer, and a continuous tunneling dielectric layer into the line groove 49. The continuous blocking dielectric layer includes at least one dielectric material such as silicon oxide and / or aluminum oxide, and may have a thickness in the range of 3nm to 15nm. The continuous charge storage layer includes a charge storage material such as silicon nitride, and may have a thickness in the range of 3nm to 10nm. The continuous tunneling dielectric layer includes a tunneling dielectric layer such as a silicon oxide layer or an ONO stack, that is, a layer stack of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, and may have a thickness in the range of 1.5nm to 4nm.

[0058] The continuous memory film may be patterned by removing the horizontal portion of the continuous memory film. For example, an anisotropic etching process may be performed to sequentially etch through the horizontal portion of the continuous tunneling dielectric layer, the horizontal portion of the continuous charge storage layer, and the horizontal portion of the continuous blocking dielectric layer. The remaining vertical portion of the continuous memory film includes a memory film 50. Each memory film 50 may include a layer stack that includes a blocking dielectric layer 52, a charge storage layer 54, and a tunneling dielectric layer 56 from one side to the other. Each blocking dielectric layer 52 is a patterned portion of a continuous blocking dielectric layer. Each charge storage layer 54 is a patterned portion of a continuous charge storage layer. Each tunneling dielectric layer 56 is a patterned portion of a continuous tunneling dielectric layer. The memory film 50 is formed on the sidewalls of the vertical alternating stacks (32, 42) in the line groove 49. Specifically, each memory film 50 may be formed on the sidewalls of the corresponding vertical alternating stacks (32, 42) and in a corresponding one of the line grooves 49. In one embodiment, a pair of memory films 50 may be formed in each line groove 49.

[0059] See also Fig. 6A , Figure 6B ,and Figure 6C , the sacrificial trench filling material may be deposited in the remaining volume of the line trench 49. The sacrificial trench filling material includes a material that can selectively remove the material of the outermost layer of the tunnel dielectric layer 56, which may be thermal silicon oxide. For example, the sacrificial trench filling material may include silicon nitride, porous or non-porous organic silicate glass, borosilicate glass, a silicon-germanium alloy containing germanium with an atomic concentration in the range of 15% to 50%, amorphous carbon, diamond-like carbon (DLC), or an organic polymer material. Excess portions of the sacrificial trench filling material may be removed from above a horizontal plane including the top surface of the topmost insulating strip 32 by a planarization process such as a chemical mechanical planarization process and / or a recess etching process. Each remaining portion of the sacrificial trench filling material located in a corresponding one of the line trenches 49 includes a sacrificial trench filling structure 71R. The sacrificial trench filling structure 71R is formed in each line trench 49 on a corresponding pair of memory films 50. Each memory film 50 is located on a corresponding longitudinal sidewall of the vertical alternating stacks (32, 42) extending laterally along the first horizontal direction hd1. Each sacrificial trench filling structure 71R may have a shape of a track.

[0060] See also Fig. 7A , Figure 7B and Figure 7C, a photoresist layer (not shown) may be applied over the first exemplary structure and may be photolithographically patterned to form an array of openings. The array of openings may include a first group of openings and a second group of openings, the first group of openings overlying a corresponding one of the first connecting via structures 26, and the second group of openings being laterally offset relative to a corresponding one of the first group of openings along a first horizontal direction hd1. Each opening in the photoresist layer may have a corresponding rectangular shape having a pair of edges extending laterally along the first horizontal direction hd1 and a pair of edges extending laterally along the second horizontal direction hd2. A row of openings having uniform spacing may be formed in the photoresist layer over each sacrificial trench filling structure 71R. Each opening in the photoresist layer may have two edges extending from one sidewall of the underlying sacrificial trench filling structure 71R to the other sidewall of the underlying sacrificial trench filling structure 71R along the second horizontal direction hd2.

[0061] An anisotropic etching process is performed to etch a first portion of the sacrificial trench filling structure 71R, which is an unmasked portion of the sacrificial trench filling structure 71R. The unetched portion of each sacrificial trench filling structure 71R includes a second portion referred to herein as the first sacrificial trench filling material portion 71, a third portion referred to herein as the second sacrificial trench filling material portion 73, and a fourth portion referred to herein as the third sacrificial trench filling material portion 75. In one embodiment, the chemistry of the anisotropic etching process may be selected so that the unmasked portion of the sacrificial trench filling structure 71R is selective to the material of the memory film 50, that is, the material of the memory film 50 is not etched. A vertically extending cavity is formed in the volume from which the first portion of the sacrificial trench filling structure 71R is removed. The vertically extending cavity is columnar and may have a horizontal cross-sectional shape that is substantially unchanged when translated in the vertical direction, and is referred to herein as a columnar cavity (31, 33).

[0062] The pillar cavities (31, 33) include a first type pillar cavity (e.g., source cavity) 31 and a second type pillar cavity (e.g., drain cavity) 33, below which the top surface of the first connecting via structure 26 is physically exposed, and the second type pillar cavity is formed between a pair of adjacent first type via cavities 31 spaced apart along the first horizontal direction hd1. The top surface of the first via-level dielectric layer 16 may be physically exposed in each second type pillar cavity 33. Each sacrificial trench filling structure 71R is divided into a plurality of discrete material portions, the plurality of discrete material portions including a laterally alternating sequence of first sacrificial trench filling material portions 71 and second sacrificial trench filling material portions 73 alternating along the first horizontal direction hd1 with an intervening pillar cavity (31, 33). In addition, the plurality of discrete material portions formed by each sacrificial trench filling structure 71R may include a third sacrificial trench filling material portion 75 located in a peripheral region where a backside trench will be subsequently formed. Each of the third sacrificial trench filling material portions 75 may have a length in the first horizontal direction hd1 that is greater than a length of each of the first and second sacrificial trench filling material portions 71 and 73 .

[0063] See also Fig. 8A , Figure 8B and Figure 8C , doped semiconductor material may be deposited in the column cavity (31, 33). The conductivity type of the semiconductor channel subsequently formed is referred to herein as the first conductivity type, and the conductivity type of the doped semiconductor material deposited in the column cavity (31, 33) is referred to herein as the second conductivity type. In other words, the doped semiconductor material deposited in the column cavity (31, 33) has a doping of the second conductivity type, such as n-type conductivity. In one embodiment, the doped semiconductor material deposited in the column cavity (31, 33) may include heavily doped polysilicon or heavily doped amorphous silicon (which is subsequently converted to doped polysilicon). The doped semiconductor material may include an atomic concentration of 5.0×10 19 / cm 3 Up to 2.0×10 21 / cm 3 The second conductivity type dopant may be present in a range of about 100 to about 100 nm, although smaller and larger atomic concentrations may also be used.

[0064] Excess portions of the doped semiconductor material may be removed from above the top surface of the topmost insulating strip 32 of the vertical alternating stack (32, 42). Each remaining portion of the doped semiconductor material filling the corresponding first type column cavity 31 includes a first active area column structure 61, and each remaining portion of the doped semiconductor material filling the corresponding second type column cavity 33 includes a second active area column structure 63. The active area column structures (61, 63) serve as source and drain regions of subsequently formed field effect transistors. Each first connecting via structure 26 may contact a corresponding one of the first access lines 24 and a corresponding one of the first active area column structures 61.

[0065] In one embodiment, the first active area pillar structure 61 may be a source pillar structure used as a source region, and the second active area pillar structure 63 may be a drain pillar structure used as a drain region. In this case, the first access line 24 may be a source line, and the first connection via structure 26 may be a source connection via structure.

[0066] In another embodiment, the first active region pillar structure 61 may be a drain pillar structure used as a drain region, and the second active region pillar structure 63 may be a source pillar structure used as a source region. In this case, the first access line 24 may be a drain line (i.e., a bit line), and the first connection via structure 26 may be a drain connection via structure.

[0067] See also Fig. 9A , Fig. 9B and Fig. 9C , a trench cavity 65 may be formed by removing a first sacrificial trench filling material portion 71 (which is a second portion of a sacrificial trench filling structure 71R) between adjacent pairs of corresponding first active area pillar structures 61 and corresponding second active area pillar structures 63. For example, a photoresist layer (not shown) may be applied over the first exemplary structure and may be photolithographically patterned to form an opening in an area overlying the first sacrificial trench filling material portion 71. The first sacrificial trench filling material portion 71 may be removed selectively to the material of the first active area pillar structure 61, the second active area pillar structure 63, the memory film 50, and the first through-hole level dielectric layer 16. For example, a wet etching process may be used to selectively etch the material of the first sacrificial trench filling material portion 71 to the material of the first active area pillar structure 61, the second active area pillar structure 63, the memory film 50, and the first through-hole level dielectric layer 16. A pair of inner sidewalls of the memory film 50 , the sidewall of the first active area pillar structure 61 and the sidewall of the second active area pillar structure 63 may be physically exposed around each channel cavity 65 .

[0068] See also Fig. 10A , Fig. 10B and Fig. 10C, a semiconductor channel material layer may be conformally deposited in the channel cavity 65 and above the top surface of the topmost insulating strip 32. The semiconductor channel material layer includes a doped semiconductor material having a first conductivity type doping opposite to the second conductivity type of the dopant in the first active area pillar structure 61 and the second active area pillar structure 63. The first conductivity type may be p-type and the second conductivity type may be n-type, or vice versa. The atomic concentration of the first conductivity type dopant in the semiconductor channel material layer may be in the range of from 1.0×10 15 / cm 3 to 1.0×10 18 / cm 3 Such as from 3.0×10 15 / cm 3 Up to 3.0×10 17 / cm 3 The semiconductor channel material layer may be in the range of 3 nm to 30 nm, such as 5 nm to 15 nm, but lower and higher atomic concentrations may also be used. The semiconductor channel material layer may be polycrystalline silicon or amorphous silicon deposited by a conformal deposition process such as a low pressure chemical vapor deposition (LPCVD) process. The thickness of the semiconductor channel material layer may be in the range of 3 nm to 30 nm, such as 5 nm to 15 nm, but smaller and larger thicknesses may also be used.

[0069] A planarizable dielectric material such as silicon oxide may be deposited in the unfilled volume of the channel cavity 65. Excess portions of the planarizing dielectric material and the semiconductor channel material layer may be removed from above a horizontal plane including the top surface of the topmost insulating strip 32 of the vertical alternating stack (32, 42) by a planarization process. The planarization process may use a chemical mechanical planarization (CMP) process and / or at least one recess etching process. Each remaining portion of the semiconductor channel material layer in the channel cavity 65 includes a channel structure 60 substantially composed of a doped semiconductor material. Each remaining portion of the planarizable dielectric material in the channel cavity 65 includes a dielectric core 66.

[0070] Generally speaking, a laterally alternating sequence of first active region pillar structures 61 and second active region pillar structures 63 may be formed in each line trench 49 on a corresponding subset of the memory film 50. The first active region pillar structure 61 may include a source pillar structure and the second active region pillar structure 63 may include a drain pillar structure, or the first active region pillar structure 61 may include a drain pillar structure and the second active region pillar structure 63 may include a source pillar structure. Each channel structure 60 contacts and laterally connects a corresponding pair of first active region pillar structures 61 and second active region pillar structures 63 in a corresponding line trench 49.

[0071] Each channel structure 60 includes a pair of lateral semiconductor channels 60L that laterally connect the corresponding first active area pillar structure 61 and the corresponding second active area pillar structure 63. Each lateral semiconductor channel 60L extends laterally along the first horizontal direction hd1 and vertically extends through each level of the sacrificial material strips 42 within the vertical alternating stack (32, 42). In one embodiment, each of the line trenches 49 and the lateral semiconductor channels 60L can extend laterally along the first horizontal direction hd1.

[0072] Each of the channel structures 60 further includes a pair of lateral vertical channel plates 60W extending laterally along the second horizontal direction hd2 and contacting a corresponding one of the first active area column structure 61 and the second active area column structure 63. Each of the channel structures 60 further includes a corresponding horizontal channel plate 60H located below a horizontal plane including the bottom surface of the bottommost sacrificial material strip 42 of the vertical alternating stack (32, 42). Each of the channel structures 60 laterally surrounds and encapsulates a corresponding dielectric core 66. Each dielectric core 66 may have a pair of vertical sidewalls parallel to the longitudinal direction of the line groove 49 (i.e., the first horizontal direction hd1), and a pair of vertical sidewalls perpendicular to the longitudinal direction of the line groove 49.

[0073] In one embodiment, the second sacrificial trench filling material portion 73 may include a dielectric material such as silicon nitride, porous or non-porous organosilicate glass, borosilicate glass, amorphous carbon, diamond-like carbon (DLC), or an organic polymer material, and the second sacrificial trench filling material portion 73 may be a dielectric pillar structure that remains in the final device structure. In one embodiment, a subset of the first active area pillar structures 61 may contact a first side of a corresponding one of the dielectric pillar structures including the second sacrificial trench filling material portion 73, and a subset of the second active area pillar structures 63 may contact an opposite side of a corresponding one of the dielectric pillar structures. In one embodiment, the dielectric pillar structure including the second sacrificial trench filling material portion 73 may contact a vertical sidewall of the first active area pillar structure 61 and a vertical sidewall of the second active area pillar structure 63.

[0074] See also Fig.11A , Fig. 11B , Fig. 11C and Fig.11D, a photoresist layer (not shown) may be applied over the first exemplary structure and may be photolithographically patterned to form an opening. In one embodiment, the opening may be a linear opening extending laterally in the second horizontal direction hd2 in the peripheral region. An anisotropic etching process may be performed to etch through the vertical alternating stack (32, 42) and the unmasked portion of the third sacrificial trench filling material portion 75. A backside opening such as a backside trench 79 may be formed below the opening in the photoresist layer. The backside trench 79 may include a pair of longitudinal sidewalls extending laterally in the second horizontal direction hd2 and laterally spaced apart in the first horizontal direction hd1. Each of the vertical alternating stacks (32, 42) may be cut from the level of the topmost sacrificial material strip in the sacrificial material strips 42 to the level of the bottommost sacrificial material strip in the sacrificial material strips 42. Therefore, each of the sacrificial material strips 42 may have a corresponding sidewall physically exposed to the backside trench 79. In one embodiment, the backside trenches 79 may extend vertically through each level of the vertical alternating stack ( 32 , 42 ).

[0075] See also Fig. 12A , Fig. 12B , Fig. 12C and Fig.12D , the backside recess 43 may be formed by performing an isotropic etching process that selectively etches the material of the sacrificial material strip 42 to the material of the insulating strip 32 and the outermost material of the memory film 50 (i.e., the material of the blocking dielectric layer 52). An isotropic etchant may be supplied into the backside trench 79 during the isotropic etching process. In an illustrative example, if the sacrificial material strip 42 includes silicon nitride, a wet etching process using hot phosphoric acid may be performed to remove the sacrificial material strip 42. The backside recess 43 may extend laterally along the first horizontal direction hd1. A pair of memory films 50 may be physically exposed to each backside recess 43.

[0076] See also Fig.13A , Fig. 13B , Fig. 13C and Fig.13D If the etching for forming the backside recess 43 over-etches through the memory film 50 to expose the sidewalls of the first active area pillar structure or the second active area pillar structure in the backside recess 43, the exposed sidewalls of the first active area pillar structure 61 or the second active area pillar structure 63 may be oxidized by wet oxidation or dry oxidation to form isolation silicon oxide on the exposed sidewalls. At least one conductive material may be deposited in the remaining volume of the backside recess 43. The conductive strip 46 may be formed in the backside recess 43 by at least one conductive material deposition process that employs a precursor gas supplied into the backside recess 43 through the backside trench 79.

[0077] For example, the metal barrier layer can be deposited directly on the physically exposed surface of the backside blocking dielectric layer in the backside recess 43, or, in the case where the backside blocking dielectric layer is not used, on the physically exposed surface of the blocking dielectric layer 52 and the insulating strip 32. The metal barrier layer includes a conductive metal material, which can be used as a diffusion barrier and / or adhesion promoting layer for a subsequently deposited metal filler material. The metal barrier layer may include a conductive metal nitride material such as TiN, TaN, WN, or a stack thereof, or may include a conductive metal carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metal barrier layer may be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metal barrier layer may be in the range of 2nm to 8nm, such as 3nm to 6nm, but smaller and larger thicknesses may also be used. In one embodiment, the metal barrier layer may be substantially composed of a conductive metal nitride such as TiN.

[0078] The metal fill material is deposited in the remaining volume of the backside recess 43, on the sidewalls of the backside trench 79, and above the topmost insulating strip 32 to form a metal fill material portion. The metal fill material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metal fill material portion can be essentially composed of at least one elemental metal. The at least one elemental metal of the metal fill material portion can be selected from, for example, tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metal fill material portion can be essentially composed of a single elemental metal. In one embodiment, the metal fill material portion can be deposited using a fluorine-containing precursor gas such as WF 6 In one embodiment, the metal filling material portion may be a tungsten layer including a residual level of fluorine atoms as impurities.

[0079] A plurality of conductive strips 46 (i.e., conductive strips having a strip shape) may be formed in a plurality of backside recesses 43, and a continuous metal material layer may be formed on the sidewalls of the backside trenches 79 and above the topmost insulating strip 32. Each conductive strip 46 includes a portion of a metal barrier layer and a metal filling material portion located between a pair of vertically adjacent dielectric material strips, such as a pair of insulating strips 32, and between a pair of laterally adjacent line trenches 49. Each line trench 49 is filled with a corresponding set of first active area pillar structures 61, second active area pillar structures 63, channel structures 60, dielectric cores 66, and dielectric pillar structures including second sacrificial trench filling material portions 73.

[0080] The deposited metal material of the continuous conductive material layer is etched back from the sidewalls of the backside trench 79 and from above the topmost insulating strip 32, for example, by isotropic wet etching, anisotropic dry etching, or a combination thereof. Each remaining portion of the deposited metal material in the backside recess 43 constitutes a conductive strip 46. Each conductive strip 46 can be a word line. Therefore, after forming the channel structure 60, the sacrificial material strip 42 is replaced with a conductive strip 46. A vertical alternating stack of insulating strips 32 and conductive strips 46 is formed above the substrate 8. The vertical alternating stacks (32, 42) can be laterally spaced apart from each other by line trenches 49.

[0081] Each conductive strip 46 can be used as a combination of a plurality of transistor gate electrodes (e.g., control gate electrodes) at the same level and a word line that electrically interconnects (i.e., electrically shorts) the plurality of gate electrodes at the same level. The plurality of gate electrodes within each conductive strip 46 are gate electrodes of charge storage or ferroelectric field effect transistors in a NOR configuration. In other words, each conductive strip 46 can be a word line that is used as a common gate electrode for a plurality of transistors.

[0082] Although the present disclosure is described using an embodiment in which the spacer material layer is formed as a sacrificial material layer 42L, embodiments in which the spacer material layer is formed as a conductive layer and is divided into conductive strips 46 are explicitly contemplated herein. In one embodiment, when forming the line trenches 49, a plurality of alternating stacks that divide the vertical alternating sequence into insulating strips 32 and conductive strips 46 may be performed.

[0083] Each adjacent combination of the first active region pillar structure 61, the second active region structure 63, the channel structure 60, the portion of the memory film 50 adjacent to the channel structure 60, and the portion of the conductive strip 46 that passes through the memory film 50 and is laterally spaced from the channel structure 60 constitutes a NOR string. Each lateral semiconductor channel 60L is configured to allow current to flow along a first horizontal direction hd1 and may include a vertical semiconductor plate. The semiconductor region components (61, 60, 63) and the lateral alternating sequence of dielectric pillar structures including the second sacrificial trench filling material portion 73 are located in a corresponding one of the line trenches 49. Each semiconductor region component (61, 60, 63) includes a first active region pillar structure (e.g., source region) 61, a channel structure 60, and a second active region pillar structure (e.g., drain region) 63.

[0084] See also Fig.14A , Fig. 14B , Fig. 14C and Fig.14D, a dielectric fill material such as silicon oxide may be deposited in the backside trench 79 to form a dielectric wall structure 76. In one embodiment, the dielectric wall structure 76 may fill the entire volume of the backside trench 79. The horizontal portion of the dielectric fill material deposited above the horizontal plane including the top surface of the topmost insulating strip 32 forms a dielectric material layer, which is referred to herein as a second via level dielectric layer 84, through which the second connecting via structure is subsequently formed.

[0085] See also Fig.15A , Fig. 15B , Fig. 15C , Fig.15D , a second connection via structure (eg, drain connection via structure) 94 may be formed through the second via-level dielectric layer 84 on a corresponding one of the second active region pillar structures 63. Each second active region pillar structure 63 may be contacted by a corresponding one of the second connection via structures 94.

[0086] See also Fig.16A , Fig. 16B , Fig. 16C and Fig.16D , a second line-level dielectric layer 86 may be formed over the second via-level dielectric layer 84. The second line-level dielectric layer 86 includes a dielectric material such as silicon oxide, and may have a thickness in a range of 50 nm to 500 nm. A line cavity extending laterally along a second horizontal direction hd2 may be formed through the second line-level dielectric layer 86. At least one conductive material may be deposited in the line cavity, and excess portions of the at least one conductive material may be removed from above a horizontal plane including a top surface of the second line-level dielectric layer 86. The remaining portions of the at least one conductive material include second access lines (e.g., bit lines) 96. Alternatively, the second access lines 96 may be formed first, and then the second line-level dielectric layer 86 may be formed between the second access lines 96.

[0087] In the case where the first access line 24 is used as a source line of the three-dimensional NOR memory array, the second access line 96 is used as a drain line (i.e., a bit line) of the three-dimensional NOR memory array. In the case where the first access line 24 is used as a drain line of the three-dimensional NOR array, the second access line 96 is used as a source line of the three-dimensional NOR memory array. The second via-level dielectric layer 84 and the second line-level dielectric layer 86 are collectively referred to as a capping insulating layer 80.

[0088] like Fig.16E , Fig.16F and Figure 16G As shown, each memory cell 100 includes a charge storage or ferroelectric field effect transistor. Fig.16EAs shown, adjacent memory cells 100A and 100B in the same device level (i.e., at the level of the same word line 46) share the same channel structure 60, the same source region (e.g., the first active region pillar structure) 61, and the same drain region (e.g., the second active region pillar structure) 63, but have different lateral semiconductor channels 60L of the same channel structure 60, different memory films 50 located in the same vertical device level, and different gate electrodes (i.e., different word lines) 46.

[0089] A plurality of memory cells (ie, transistors) 100 are also vertically stacked above the substrate 8, as shown in FIG. Fig.16F The vertically separated memory cells (ie, transistors) 100 share the same channel structure 60 (including the same lateral semiconductor channel 60L), the same source region 61 and the same drain region 63, but have different gate electrodes (ie, portions of the vertically separated word lines) 46 located in different vertical device levels.

[0090] Optionally, the back body contact 27 may be connected to the horizontal channel plate 60H of the semiconductor structure 60, such as Fig.16F The back side body contact 27 is not electrically connected to the first access line 24 (eg, source line). Alternatively, the back side body contact 27 is omitted.

[0091] See also Fig.17A , Fig. 17B and Fig. 17C The second exemplary structure according to the second embodiment of the present disclosure can be derived from Fig. 10A , Fig. 10B and Fig. 10C Specifically, the second sacrificial trench filling material portion 73 may be selectively removed from the materials of the first active area pillar structure 61 and the second active area pillar structure 63. For example, a photoresist material layer may be applied to Fig. 10A , Fig. 10B and Fig. 10C The first exemplary structure of the active area pillar structure 61 and the second exemplary structure of the active area pillar structure 63 may be formed by photolithographic patterning to form an opening in an area overlying the second sacrificial trench filling material portion 73. An isotropic etching process or an anisotropic etching process that selectively etches the material of the first active area pillar structure 61 and the second active area pillar structure 63 and the material of the second sacrificial trench filling material portion 73 may be performed to form the access cavity 179.

[0092] See also Fig.18A , Fig.18B and Fig.18C , the portion of the memory film 50 located around the second sacrificial trench filling material portion 73 is Fig.17A , Fig. 17B and Fig. 17CWithout being incidentally removed during the processing steps of Fig.17A , Fig. 17B and Fig. 17C Each memory film 50 may be divided into a plurality of memory films 50 that are laterally spaced apart along the first horizontal direction hd1. Fig.17A , Fig. 17B and Fig. 17C The processing steps and / or Fig.18A , Fig.18B and Fig.18C Each memory film 50 divided by at least one etching process performed at the processing step of may contact the sidewalls of the first active area pillar structure 61, the second active area pillar structure 63 and the channel structure 60. Each access cavity 179 may extend laterally between a pair of adjacent vertical alternating stacks (32, 42). Generally speaking, the access cavity 179 may be formed between adjacent pairs of corresponding first active area pillar structures 61 and corresponding active area pillar structures 63 that are not connected by any of the channel structures 60. Each of the access cavities 179 may extend vertically through each level of the sacrificial material strip 42.

[0093] See also Fig.19A , Fig.19B ,and Fig.19C , the backside recess 43 may be formed by performing an isotropic etching process that selectively etches the material of the sacrificial material strip 42 to the material of the insulating strip 32 and the outermost material of the memory film 50 (i.e., the material of the blocking dielectric layer 52). During the isotropic etching process, an isotropic etchant may be supplied into the access cavity 179. In an illustrative example, if the sacrificial material strip 42 includes silicon nitride (e.g., for a ferroelectric memory device), a wet etching process using hot phosphoric acid may be performed to remove the sacrificial material strip 42. Alternatively, if the sacrificial material strip 42 includes undoped polysilicon, a wet etching process using a polysilicon selective etching medium may be performed to remove the sacrificial material strip 42. The backside recess 43 may extend laterally along the first horizontal direction hd1. A pair of memory films 50 may be physically exposed to each backside recess 43.

[0094] See also Fig. 20A , Fig. 20B ,and Fig. 20CIf the etching for forming the backside recess 43 over-etches through the memory film 50 to expose the sidewalls of the first active area pillar structure or the second active area pillar structure in the backside recess 43, the exposed sidewalls of the first active area pillar structure 61 or the second active area pillar structure 63 may be oxidized by wet oxidation or dry oxidation to form isolation silicon oxide on the exposed sidewalls. The conductive strip 46 may be formed in the backside recess 43 by at least one conductive material deposition process using a precursor gas supplied into the backside recess 43 through the access chamber 179.

[0095] For example, the metal barrier layer can be deposited directly on the physically exposed surface of the backside blocking dielectric layer in the backside recess 43, or, in the case where the backside blocking dielectric layer is not used, on the physically exposed surface of the blocking dielectric layer 52 and the insulating strip 32. The metal barrier layer includes a conductive metal material, which can be used as a diffusion barrier and / or adhesion promoting layer for a subsequently deposited metal filler material. The metal barrier layer may include a conductive metal nitride material such as TiN, TaN, WN, or a stack thereof, or may include a conductive metal carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metal barrier layer may be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metal barrier layer may be in the range of 2nm to 8nm, such as 3nm to 6nm, but smaller and larger thicknesses may also be used. In one embodiment, the metal barrier layer may be substantially composed of a conductive metal nitride such as TiN.

[0096] The metal fill material is deposited in the remaining volume of the backside recess 43, on the sidewalls of the access cavity 179, and above the topmost insulating strip 32 to form a metal fill material portion. The metal fill material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metal fill material portion can be essentially composed of at least one elemental metal. The at least one elemental metal of the metal fill material portion can be selected from, for example, tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metal fill material portion can be essentially composed of a single elemental metal. In one embodiment, the metal fill material portion can be deposited using a fluorine-containing precursor gas such as WF 6 In one embodiment, the metal filling material portion may be a tungsten layer including a residual level of fluorine atoms as impurities.

[0097] A plurality of conductive strips 46 (i.e., conductive strips having a strip shape) may be formed in the plurality of backside recesses 43, and a continuous metal material layer may be formed on the sidewalls of the access cavity 179 and over the topmost insulating strip 32. Each conductive strip 46 includes a portion of a metal barrier layer and a metal filling material portion located between a pair of vertically adjacent dielectric material strips, such as a pair of insulating strips 32, and between a pair of laterally adjacent line trenches 49.

[0098] The deposited metal material of the continuous conductive material layer is etched back from the sidewalls of the access cavity 179 and from above the topmost insulating strip 32, for example, by isotropic wet etching, anisotropic dry etching, or a combination thereof. Each remaining portion of the deposited metal material in the backside recess 43 constitutes a conductive strip 46. Each conductive strip 46 can be a conductive line structure. Therefore, after forming the channel structure 60, the sacrificial material strip 42 is replaced with a conductive strip 46. A vertical alternating stack of insulating strips 32 and conductive strips 46 is formed above the substrate 8. The vertical alternating stacks (32, 42) can be laterally spaced apart from each other by line trenches 49.

[0099] Each conductive strip 46 can be used as a combination of multiple transistor gate electrodes (e.g., control gate electrodes) located at the same level and a word line that electrically interconnects (i.e., electrically shorts) the multiple gate electrodes located at the same level. The multiple gate electrodes within each conductive strip 46 are control gate electrodes of field effect transistors in a NOR configuration. In other words, each conductive strip 46 can be a word line used as a common control gate electrode for multiple vertical memory devices.

[0100] See also Fig.21A , Fig. 21B ,and Fig. 21C , a dielectric filling material such as silicon oxide may be deposited in the access cavity 179 to form a dielectric pillar structure 176. In one embodiment, the dielectric pillar structure 176 may fill the entire volume of the corresponding access cavity 179. The horizontal portion of the dielectric filling material deposited above the horizontal plane including the top surface of the topmost insulating strip 32 forms a dielectric material layer, which is referred to herein as a second via level dielectric layer 84, through which the second connecting via structure is subsequently formed. Each line trench 49 is filled with a corresponding set of first active area pillar structures 61, second active area pillar structures 61, channel structures 60, dielectric cores 66, and dielectric pillar structures 176.

[0101] Each adjacent combination of the first active region pillar structure 61, the second active region pillar structure 63, the channel structure 60, the pair of memory films 50, and the portion of the conductive strip 46 that is laterally spaced apart from the channel structure 60 by the pair of memory films 50 constitutes a NOR string. Each lateral semiconductor channel 60L is configured to allow current to flow along a first horizontal direction hd1 and can be configured as a vertical semiconductor plate. The laterally alternating sequence of semiconductor region components (61, 60, 63) and dielectric pillar structures 176 can be located in a corresponding one of the line grooves 49. Each semiconductor region component (61, 60, 63) includes a first active region pillar structure 61, a channel structure 60, and a second active region pillar structure 63.

[0102] The memory film 50 may be located between each pair of adjacent vertical alternating stacks (32, 42) and lateral alternating sequences ((61, 60, 63), 176). Each of the memory films 50 contacts no more than a single channel structure 60 within the lateral alternating sequence of lateral semiconductor channels 60L and dielectric pillar structures 176 located within a corresponding one of the line trenches 49.

[0103] See also Fig.22A , Fig. 22B ,and Fig. 22C , the second connection via structures 94 may be formed through the second via-level dielectric layer 84 on a corresponding one of the second active area pillar structures 63. Each of the second active area pillar structures 63 may be contacted by a corresponding one of the second connection via structures 94.

[0104] See also Fig.23A , Fig. 23B ,and Fig.23C , a second line-level dielectric layer 86 may be formed over the second via-level dielectric layer 84. The second line-level dielectric layer 86 includes a dielectric material such as silicon oxide, and may have a thickness in a range of 50 nm to 500 nm. A line cavity extending laterally along a second horizontal direction hd2 may be formed through the second line-level dielectric layer 86. At least one conductive material may be deposited in the line cavity, and excess portions of the at least one conductive material may be removed from above a horizontal plane including a top surface of the second line-level dielectric layer 86. The remaining portion of the at least one conductive material includes a second access line (e.g., a bit line) 96.

[0105] In the case where the first access line 24 is used as a source line of the three-dimensional NOR memory array, the second access line 96 is used as a drain line (e.g., a bit line) of the three-dimensional NOR memory array. In the case where the first access line 24 is used as a drain line of the three-dimensional NOR array, the second access line 96 is used as a source line of the three-dimensional NOR memory array. The second via-level dielectric layer 84 and the second line-level dielectric layer 86 are collectively referred to as a capping insulating layer 80.

[0106] See also Fig.24A , Fig. 24B , Fig.24C and Fig.24D , illustrating an alternative embodiment of the first exemplary structure. The alternative embodiment of the first exemplary structure can be derived from the first exemplary structure by using a memory film 150 including a combination of a ferroelectric material layer 152 and an optional gate dielectric layer 156 (rather than a memory film 50 including a layer stack of a blocking dielectric layer 52, a charge storage layer 54, and a tunneling dielectric layer 56). In this alternative embodiment, each memory cell 100 includes a ferroelectric memory transistor instead of a charge storage transistor.

[0107] In one embodiment, the memory film 150 consists essentially only of a ferroelectric material layer 152. In another embodiment, the memory film includes a multi-film stack of a ferroelectric material layer 152 and a non-ferroelectric gate dielectric layer 156 (e.g., a silicon oxide layer). As used herein, "ferroelectric material" refers to a crystalline material that exhibits spontaneous electric polarization in the absence of an external electric field. The ferroelectric material layer 152 can be an insulating ferroelectric material layer. In one embodiment, the ferroelectric material layer 152 includes a hafnium oxide layer that contains at least one dopant selected from Al, Zr, and Si and has a ferroelectric non-centrosymmetric orthorhombic phase. Alternatively, other ferroelectric materials such as barium titanate, bismuth ferrite, lead titanate, lead zirconate titanate, etc. can be used. The ferroelectric material layer 152 can have a thickness in the range of 1.5 nm to 15 nm, such as 3 nm to 10 nm, but smaller and larger thicknesses can also be used.

[0108] See also Fig.25A , Fig.25B ,and Fig.25C , illustrating an alternative embodiment of the second exemplary structure. The alternative embodiment of the second exemplary structure can be derived from the second exemplary structure by adopting a memory film 150 including a combination of a ferroelectric material layer 152 and a gate dielectric layer 156 (rather than a memory film 50 including a layer stack of a blocking dielectric layer 52, a charge storage layer 54, and a tunneling dielectric layer 56). In this alternative embodiment, each memory cell 100 includes a ferroelectric memory transistor instead of a charge storage transistor.

[0109] Although the present disclosure is described using an embodiment in which the first access line 24 extends laterally along the first horizontal direction hd1 and the second access line 96 extends laterally along the second horizontal direction hd2, an embodiment in which the first access line 24 extends laterally along the second horizontal direction hd2 and the second access line 96 extends laterally along the first horizontal direction hd1 is explicitly contemplated.

[0110] Referring to all the drawings and in accordance with various embodiments of the present disclosure, there is provided a semiconductor structure comprising vertically alternating stacks (32, 46) of insulating strips 32 and conductive strips 46 located above a substrate 8 and laterally spaced apart from each other by line trenches 49; a laterally alternating sequence (61, 60, 63, 73 or 176) of semiconductor region components (61, 60, 63) and dielectric pillar structures 73 or 176 located within a respective one of the line trenches 49; and a memory film 50 located between each adjacent pair of the vertically alternating stacks (32, 46) and laterally alternating sequences (61, 60, 63, 73 or 176), wherein the semiconductor region components ( Each of the semiconductor layers 61, 60, and 63) includes: a corresponding first active region column structure 61 extending through each level of the conductive strip 46; a corresponding second active region column structure 63 extending through each level of the conductive strip 46 and laterally spaced apart from the corresponding first active region column structure 61, one of the corresponding first active region column structure 61 and the corresponding second active region column structure 63 being a source column structure, and the other of the corresponding first active region column structure 61 and the corresponding second active region column structure 63 being a drain column structure; and a corresponding channel structure 60 including a pair of lateral semiconductor channels 60L laterally connecting the corresponding first active region column structure 61 and the corresponding second active region column structure 63.

[0111] In one embodiment, each of the lateral semiconductor channels 60L extends vertically and continuously through each level of the conductive strips 46 within the vertical alternating stack (32, 46). In one embodiment, each of the line trenches 49 and the lateral semiconductor channels 60L extends laterally along a first horizontal direction hd1; and each of the channel structures 60 further includes a pair of lateral vertical channel plates 60W extending laterally along a second horizontal direction hd2 and contacting a respective one of the first active region pillar structure 61 and the second active region pillar structure 63.

[0112] In one embodiment, each of the channel structures 60 further includes a corresponding horizontal channel plate 60H located below a horizontal plane including the bottom surface of the bottommost conductive strip 46 of the vertical alternating stack (32, 46). In one embodiment, each of the channel structures 60 laterally surrounds and encapsulates a corresponding dielectric core 66 having a pair of vertical sidewalls parallel to the longitudinal direction of the line trenches 49.

[0113] A first access line 24 may be provided, which is parallel to each other and is located below the vertical alternating stack (32, 46) and the horizontal alternating sequence. A first connecting via structure 26 may be provided, which contacts a corresponding one of the first access lines 24 and a corresponding one of the first active area pillar structures 61. A second access line 96 may be provided, which is parallel to each other and covers the vertical alternating stack (32, 46) and the horizontal alternating sequence. A second connecting via structure 94 is provided, which contacts a corresponding one of the second access lines 96 and a corresponding one of the second active area pillar structures 63. In one embodiment, the line groove 49 extends laterally along the first horizontal direction hd1. The first access line 24 extends along a first longitudinal direction that is horizontal and parallel to the first horizontal direction hd1; and the second access line 96 extends along a second longitudinal direction hd2 that is horizontal and perpendicular to the first longitudinal direction hd1.

[0114] In one embodiment, at least one dielectric pillar structure (73 or 176) within each line trench laterally contacts the corresponding first active area pillar structure 61 and the corresponding second active area pillar structure 63. In one embodiment, each of the memory films 50 includes a corresponding layer stack, which includes, from one side to the other, a blocking dielectric layer 52, a charge storage layer 54, and a tunneling dielectric layer 56. In one embodiment, each of the memory films includes a ferroelectric material layer 152.

[0115] In one embodiment, each of the memory films 50 contacts a plurality of channel structures 60 in a laterally alternating sequence of semiconductor region components ( 61 , 60 , 63 ) and dielectric pillar structures ( 73 or 176 ) located within a respective one of the line trenches 49 .

[0116] In one embodiment, each of the memory films 50 contacts only a single channel structure 60 in the laterally alternating sequence ( 61 , 60 , 63 , 73 or 176 ) of semiconductor region components ( 61 , 60 , 63 ) and dielectric pillar structures ( 73 or 176 ) located within a corresponding one of the line trenches 49 .

[0117] Various structures of the present disclosure may be used to provide a compact three-dimensional array of NOR memory devices. The memory cells of the three-dimensional array of NOR memory devices may include charge storage transistors or ferroelectric transistors. NOR memory devices include a source and a drain in each memory cell and may provide faster access speeds than NAND memory devices and may be used in storage class memory (SCM) devices.

[0118] Although specific preferred embodiments are mentioned above, it will be understood that the present disclosure is not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of..." or the words "consisting of..." replace the words "comprising" or "including". Embodiments using specific structures and / or configurations are shown in the present disclosure, and it should be understood that the present disclosure can be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A semiconductor structure, comprising: a vertical alternating stack of insulating and conductive strips located above the substrate and laterally spaced apart from one another by line trenches; a laterally alternating sequence of semiconductor region components and dielectric pillar structures located within a respective one of said line trenches; as well as a memory film located between each adjacent pair of the vertical alternating stacks and the lateral alternating sequences, Each of the semiconductor region components comprises: a respective first active area pillar structure extending through each level of said conductive strips; a respective second active area pillar structure extending through each level of the conductive strips and laterally spaced apart from the respective first active area pillar structure, one of the respective first active area pillar structure and the respective second active area pillar structure being a source pillar structure and the other of the respective first active area pillar structure and the respective second active area pillar structure being a drain pillar structure; a corresponding channel structure, the corresponding channel structure comprising a pair of lateral semiconductor channels laterally connecting the corresponding first active area pillar structure and the corresponding second active area pillar structure; and a corresponding dielectric core, the corresponding dielectric core having a pair of first vertical side walls parallel to the longitudinal direction of the line groove and a pair of second vertical side walls perpendicular to the longitudinal direction of the line groove, wherein the corresponding channel structure laterally surrounds the corresponding dielectric core and contacts the pair of first vertical side walls of the corresponding dielectric core and contacts the pair of second vertical side walls of the corresponding dielectric core, wherein each of the memory films contacts only a single channel structure within a laterally alternating sequence of semiconductor region components and dielectric pillar structures within a respective one of the line trenches, The method for manufacturing the semiconductor structure includes: forming access cavities between respective first active area pillar structures and adjacent pairs of respective active area pillar structures that are not connected by any of the channel structures, wherein each of the access cavities extends vertically through each level of the sacrificial material strips; forming a backside recess by isotropically etching the strip of sacrificial material using an isotropic etchant supplied into the access cavity; and The conductive strip is deposited in the backside recess using a precursor gas supplied into the backside recess through the access chamber.

2. The semiconductor structure of claim 1 wherein each of the lateral semiconductor channels extends vertically continuously through each level of the conductive strips within the vertical alternating stack.

3. The semiconductor structure according to claim 1, wherein: Each of the line trench and the lateral semiconductor channel extends laterally along a first horizontal direction; and Each of the channel structures further includes a pair of lateral vertical channel plates extending laterally along a second horizontal direction and contacting a corresponding one of the first active area pillar structure and the second active area pillar structure.

4. The semiconductor structure of claim 1 wherein each of the channel structures further comprises a respective horizontal channel plate located below a horizontal plane including a bottom surface of a bottommost conductive strip of the vertical alternating stack.

5. The semiconductor structure according to claim 1, further comprising: first access lines, the first access lines being parallel to each other and underlying the laterally alternating sequence; and A first connection via structure contacts a corresponding one of the first access lines and a corresponding one of the first active area pillar structures.

6. The semiconductor structure according to claim 5, further comprising: second access lines, the second access lines being parallel to each other and overlying the vertical alternating stack and the horizontal alternating sequence; and A second connection via structure contacts a corresponding one of the second access lines and a corresponding one of the second active area pillar structures.

7. The semiconductor structure of claim 6, wherein: The linear grooves extend laterally along a first horizontal direction; The first access line extends along a first longitudinal direction that is horizontal and parallel to the first horizontal direction; and The second access line extends along a second longitudinal direction that is horizontal and perpendicular to the first longitudinal direction. 8 . The semiconductor structure of claim 1 , wherein at least one dielectric pillar structure within each linear trench laterally contacts a corresponding first active region pillar structure and a corresponding second active region pillar structure. 9 . The semiconductor structure of claim 1 , wherein each of the memory films comprises a respective layer stack including, from one side to the other side, a blocking dielectric layer, a charge storage layer, and a tunneling dielectric layer.

10. The semiconductor structure of claim 1, wherein each of the memory films comprises a layer of ferroelectric material.

11. The semiconductor structure of claim 1, wherein the respective channel structures further comprise a pair of lateral vertical channel plates extending laterally along a horizontal direction perpendicular to a longitudinal direction of the line trenches.

12. The semiconductor structure of claim 11, wherein: One of the pair of lateral vertical channel plates contacts a sidewall of one of the first active area pillar structures; and The other of the pair of lateral vertical channel plates contacts a sidewall of one of the second active area pillar structures.

13. The semiconductor structure of claim 11, wherein the pair of lateral vertical channel plates extend vertically from at least a horizontal plane containing a bottom surface of a bottommost conductive strip within the vertical alternating stack to a horizontal plane containing a topmost surface of a topmost conductive strip within the vertical alternating stack.

14. The semiconductor structure of claim 11, wherein each of the pair of lateral vertical channel plates of the respective channel structure abuts to a respective pair of vertically extending edges of the pair of lateral semiconductor channels of the respective channel structure.

15. The semiconductor structure of claim 11, wherein the pair of lateral vertical channel plates of the respective channel structures and the pair of lateral semiconductor channels of the respective channel structures have a same material composition and a same lateral thickness.

16. The semiconductor structure of claim 1, wherein all sidewall surfaces of the respective dielectric core contact a respective one of the inner sidewalls of the respective channel structure.

17. The semiconductor structure of claim 1, wherein: The respective channel structures include horizontally extending semiconductor material portions that are adjacent to bottom edges of the pair of lateral semiconductor channels and have the same material composition as the pair of lateral semiconductor channels; and The respective dielectric core contacts the entirety of the top surface of the horizontally extending semiconductor material portion.

18. A method of forming a semiconductor structure, comprising: forming a vertical alternating stack of insulating strips and spacer material strips laterally spaced from one another by line trenches over the substrate, wherein each of the spacer material strips is formed into or subsequently replaced by a respective conductive strip; forming a memory film on the sidewalls of the vertically alternating stacks in the line trenches; forming an alternating sequence of first and second active area pillar structures within each of the line trenches on a corresponding subset of the memory film, wherein the first active area pillar structures include source pillar structures and the second active area pillar structures include drain pillar structures, or the first active area pillar structures include drain pillar structures and the second active area pillar structures include source pillar structures; and forming a channel structure, the channel structure laterally connecting a corresponding pair of first active area column structures and second active area column structures in the line trench, wherein each of the memory films contacts only a single channel structure within a laterally alternating sequence of semiconductor region components and dielectric pillar structures within a respective one of the line trenches, Wherein, the method further comprises: forming access cavities between respective first active area pillar structures and adjacent pairs of respective active area pillar structures that are not connected by any of the channel structures, wherein each of the access cavities extends vertically through each level of the sacrificial material strips; forming a backside recess by isotropically etching the strip of sacrificial material using an isotropic etchant supplied into the access cavity; and The conductive strip is deposited in the backside recess using a precursor gas supplied into the backside recess through the access chamber.

19. The method according to claim 18, further comprising: forming a sacrificial trench fill structure within each of the line trenches; forming a pillar cavity in the sacrificial trench fill structure by removing a first portion of the sacrificial trench fill structure; as well as A doped semiconductor material is deposited in the pillar cavity, wherein the first active area pillar structure and the second active area pillar structure include portions of the doped semiconductor material filling the pillar cavity.

20. The method according to claim 19, further comprising: forming a trench cavity by removing a second portion of the sacrificial trench fill structure between adjacent pairs of respective first active area pillar structures and respective second active area pillar structures; conformally depositing a semiconductor channel material layer in the channel cavity; as well as A portion of the semiconductor channel material layer is removed from outside the channel cavity, wherein a remaining portion of the semiconductor channel material layer includes the channel structure.

21. The method of claim 19, further comprising: forming a continuous memory film extending into each of the line trenches and over the vertical alternating stacks; patterning the continuous memory film by removing horizontal portions of the continuous memory film, wherein remaining vertical portions of the continuous memory film include the memory film; as well as The sacrificial trench filling structure is formed on the memory film.

22. The method of claim 18, wherein: The strips of spacer material are formed as strips of sacrificial material; and The method also includes replacing the strip of sacrificial material with the conductive strip after forming the channel structure.

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