Equipment Manufacturing

Abstract

A method for manufacturing a device, wherein the device includes a plurality of material segments and at least one junction connecting two or more material segments. In a masking stage, a mask is formed on a bottom layer of the device. The mask includes a plurality of grooves exposing the bottom layer, each groove corresponding to one of the material segments. Corresponding portions of two or more grooves are (a) narrowed or (b) separated by discontinuities at locations corresponding to at least one junction. In a selective area growth stage, material is concentratedly grown in the grooves to form material segments on the bottom layer. The two or more material segments are connected at at least one junction.

Description

Technical Field

[0001] The present disclosure relates to a method of manufacturing a device and the resulting device. Background Art

[0002] Quantum computing is a class of computing in which intrinsic quantum mechanical phenomena such as superposition and entanglement of quantum states are exploited to perform certain calculations at speeds much faster than any classical computer has ever been able to achieve. In "topological" quantum computers, calculations are performed by manipulating quasiparticles (called "non-Abelian anyons") that appear in certain physical systems. Anyons have unique physical properties that distinguish them from both fermions and bosons. Non-Abelian anyons also have unique properties relative to Abelian anyons. It is these unique properties that serve as the basis for topological quantum computing, in which information is encoded as the topological properties of non-Abelian anyons; in particular, braiding their space-time world lines. This has certain benefits compared to other quantum computing models. A key benefit is stability, because quantum braiding is not affected by perturbations of the scale that may cause error-induced quantum decoherence in other types of quantum computers.

[0003] Broadly speaking, two types of physical systems have so far been considered as potential hosts of non-Abelian anyons, namely "5 / 2 fractional quantum Hall" systems in condensed matter physics, and (more recently) semiconductor-superconductor (SE / SC) nanowires. Regarding the latter, a key advance in the field has been the realization that non-Abelian anyons in the form of "Majorana zero modes" (MZMs) can be formed in regions of a semiconductor (SE) coupled to a superconductor (SU). Based on this phenomenon, small networks of SE / SU nanowires, each comprising a section of semiconductor coated with a superconductor, can be used to create qubits.

[0004] A quantum bit, or qubit, is an element on which a measurement with two possible outcomes can be performed, but which at any given time (when not being measured) can actually be in a quantum superposition of two states corresponding to different outcomes.

[0005] A "topological" qubit is a qubit implemented in the form of an MZM based on the non-Abelian anyon technology described above. A non-Abelian anyon is a quasiparticle, which means that it is not a particle itself, but an excitation in an electron liquid that behaves at least partially like a particle. In particular, anyons are quasiparticles that appear in two-dimensional systems (two degrees of freedom in space). Majorana zero modes are special bound states of such quasiparticles. Under certain conditions, these states can be formed close to the semiconductor / superconductor interface in a SE / SU nanowire network in a way that enables them to be manipulated as qubits for the purpose of quantum computing. Regions or "segments" of the nanowire network between MZMs are said to be in a "topological" state. Summary of the invention

[0006] Although recent developments in fabrication techniques have led to significant improvements in the quality of nanowire networks, the discussed approaches all face quality challenges.

[0007] Various micro / nanofabrication methods can be used to produce high-quality semiconductor (as well as superconductors and insulators) structures required for quantum devices for potential use in the field of quantum computing. Particular challenges exist in the case of epitaxial structures (in-plane line networks), where masks are used to guide the growth process, which can be controlled kinetically and / or thermodynamically.

[0008] Selective area growth (SAG) is a popular method used for the growth of structures. For example, SAG of semiconductor systems allows scientists to realize structures required for quantum computing with many semiconductor nanowire junctions. The realization of complex topological quantum networks requires highly uniform material properties, not only along the nanowires but also across the junctions of intersecting nanowires. Due to fundamental epitaxial growth limitations, nanowire junctions tend to overgrow due to preferential nucleation at pattern intersections. This leads to the formation of additional atomic planes and can result in non-uniform material properties, which may be detrimental to computing using SAG systems.

[0009] Embodiments of the present invention provide methods of fabricating high quality structures, such as nanowires grown via selective area growth.

[0010] According to one aspect disclosed herein, a method for manufacturing a device can be provided, wherein the device includes a plurality of material segments and at least one junction, the at least one junction connecting (joining) two or more of the material segments, and wherein the method includes: in a masking stage, forming a mask on a bottom layer of the device, wherein the mask includes a plurality of grooves exposing the bottom layer, each groove corresponding to one of the material segments, and wherein a corresponding portion of each of two or more of the grooves is (a) narrowed, or (b) interrupted and separated at a position corresponding to at least one junction; in a selective area growth stage, growing material concentrated in the grooves by selective area growth to form material segments on the bottom layer; and connecting the two or more material segments at at least one junction.

[0011] By reducing the width of the mask (i.e., the trench of the mask) in the junction region compared to the rest of the mask (i.e., the main body of the trench), the preferential nucleation at the junction can be limited by the natural faceting and termination of the crystals grown in the narrower trenches. Alternatively, by placing an empty spot in the mask at the junction, undesirable nucleation can be limited. In this case, there is little or no nucleation at the junction, and the junction is formed by merging the grown material segments, for example, via a conductive bridge across the discontinuity. The corresponding portion of one or more trenches can be, for example, the two ends of the trench. Or, as another example, the corresponding portion of one or more trenches can be the main body of the trench, for example, between the two ends of the trench.

[0012] Typically, more material grows at the intersection or junction of features (i.e., material segments) than at features without intersections. Embodiments of the present invention use modified mask patterns for selective area grown junctions through shape biasing to promote improved material and transport properties across the junction. In other words, the mask allows for uniform growth throughout the material segments and at the junction (intersection, junction, etc.).

[0013] Herein, a material segment refers to any structure grown in a corresponding groove (i.e., channel) of a mask. A material segment does not necessarily mean a straight line, but does not exclude a straight line. For example, multiple curved material lines can be grown in corresponding curved grooves, which can be connected at junctions.

[0014] In an embodiment, the connecting may include merging by lateral growth of material during a selective area growth phase.

[0015] Alternatively, the connecting may comprise connecting two or more material segments via an electrical conductor in a subsequent stage to the selective area growth stage.

[0016] In embodiments, at least one junction may connect only two or three of the material segments; thereby forming a T-junction.

[0017] In an embodiment, at least four of the material segments may be connected at at least one junction, wherein corresponding portions of at least four grooves (a) narrow or (b) are interrupted and separated at positions corresponding to at least one junction; and wherein the connection comprises connecting at least four material segments at at least one junction; thereby forming a cross junction.

[0018] In an embodiment, the device may include a plurality of junctions, each junction connecting at least some of the material segments, wherein two or more corresponding material segments are connected at each corresponding junction, wherein for each corresponding junction, the mask includes two or more corresponding sets of grooves corresponding to the two or more corresponding material segments, wherein a corresponding portion of each of the two or more corresponding grooves (a) narrows or (b) is interrupted and separated at a position corresponding to at least one junction, wherein the growth includes: growing material in the corresponding groove sets by selective area growth to form two or more corresponding material segments on the underlying layer, and wherein the connecting includes connecting the two or more corresponding material segments at each corresponding junction.

[0019] In an embodiment, the bottom layer may be a bottom layer of a wafer. In an embodiment, the bottom layer may be a substrate of a wafer.

[0020] In an embodiment, the plurality of grooves may be formed by etching a mask from the bottom layer. In an embodiment, the pattern of the plurality of grooves may be defined by photolithography. In an embodiment, the mask may be an insulating mask. In an embodiment, the mask may be a dielectric. In an embodiment, the bottom layer may be an insulating material. In an embodiment, the material may be a semiconductor. In an embodiment, the material may be grown by epitaxy.

[0021] In an embodiment, the method may comprise: in a superconductor growth phase, growing a layer of superconductor material on at least some of the material segments. In an embodiment, the layer of superconductor material is applied using a particle beam. In an embodiment, the superconductor material may be grown by epitaxy.

[0022] In an embodiment, the device may be a quantum device and wherein the segments of material may be nanowires.

[0023] According to another aspect disclosed herein, a device may be provided, comprising: a plurality of material segments and at least one junction connecting two or more of the material segments; a mask formed on a bottom layer of the device, wherein the mask comprises a plurality of grooves exposing the bottom layer, each groove corresponding to a material segment, and wherein a corresponding portion of each of at least two grooves is (a) narrowed, or (b) separated by interruptions, at a position corresponding to at least one junction; wherein two or more material segments are connected across a portion of the mask, and wherein the material segments comprise material grown in selective regions in the two or more grooves.

[0024] According to another aspect disclosed herein, a method of operating the device may be provided, wherein the material segment is a nanowire, and wherein the method includes inducing at least one Majorana zero-mode MZM in one or more of the nanowires, wherein the at least one MZM is induced by cooling the superconductor to a superconducting temperature and applying a magnetic field to the device. The induction of the at least one MZM may also include controlling at least one of the one or more nanowires with a gate using an electrostatic potential.

[0025] This summary is provided to introduce some concepts in a simplified form, which will be further described in the following detailed description. This summary is neither intended to identify the key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. The claimed subject matter is also not limited to implementations that solve any or all of the disadvantages pointed out herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] For a better understanding of the present technology, and to show how embodiments may be implemented, reference is made, by way of example only, to the following drawings, in which:

[0027] Figure 1 schematically illustrates an example method for fabricating a nanowire network;

[0028] Figure 2 A top-down scanning electron microscope image of an InAs nanowire network selectively grown on a GaAs substrate is shown;

[0029] Figure 3 Example images showing overgrowth at junctions of a selective area grown semiconductor;

[0030] Figure 4 schematically illustrates an example mask for growing material segments by selective area growth, and an example image of a nanowire that has been grown in the example mask;

[0031] Figure 5 schematically illustrates an example mask for growing material segments by selective area growth;

[0032] Figure 6 illustrates an example image of a nanowire that has been merged across an empty spot in a mask;

[0033] Figure 7 schematically illustrates two example masks for growing a T-junction; and

[0034] Figure 8 An example mask for growing an L-shaped junction is schematically illustrated. DETAILED DESCRIPTION

[0035] Epitaxial semiconductor-superconductor materials are promising platforms for superconducting electronics and superconducting quantum computing. In the context of topological quantum computing, superconducting nanowires with strong spin-orbit coupling can support topological excitations, which can serve as the basis for fault-tolerant quantum information processing.

[0036] Current methods for synthesizing semiconductor-superconducting materials for superconducting nanowire electronics are based on two-dimensional planar materials (see, e.g., Shabani et al., PRB 93, 155402 (2016)), or on bottom-up grown nanowire materials (see, e.g., Krogstrup et al., Nature Materials 14, 400-406 (2015)).

[0037] One problem with current technology is overgrowth of material at junctions of the material being grown. When structures such as nanowires are grown using SAG techniques, they tend to overgrow at the points where they meet (i.e., the junctions of the material segments). The junction can be a cross, intersection, or intersection of multiple material segments, and its width is typically thicker than the rest of the material segments. In other words, the junction of the material segments is wider than the rest of the material segments. This non-uniform shape / geometry (e.g., thickness and / or width) of the material can adversely affect the resulting devices that contain these structures. A scanning electron microscope image of an overgrown junction is shown in FIG. Figure 3 Two knots 302a, 302b are shown (in this case crossed knots), each of which connects four material segments 304a-304g. One of these segments 304a forms part of each of the two knots 302a, 302b.

[0038] To address this and other issues, embodiments of the present invention use a modified mask approach to fabricate devices whereby the trenches of the mask in which the material being grown are modified at points where the material being grown will be connected. The mask is modified so that the trenches are narrowed (i.e., their width is reduced) at points corresponding to junctions, or the trenches are discontinuous (i.e., they are separated by a portion of the mask) at points corresponding to junctions. Once growth occurs in the trenches, the material segments can be connected (e.g., merged). For example, the material being grown can be connected by lateral extension of the material crystals.

[0039] refer to Figure 1 and Figure 5 Now an example three-stage manufacturing method will be described. The manufacturing method can be used to create a device having multiple material segments and one or more junctions. Each junction connects two or more material segments, such as Figure 3 As shown. The fabrication method can be used to create semiconductor (SE) and / or semiconductor / superconductor (SE / SU) nanowire networks, which in turn can form the basis of quantum devices or circuits (e.g., for quantum computers) or other hybrid semiconductor-superconductor platforms. In particular, the method is particularly suitable for fabricating SE / SU nanowire networks capable of hosting stable MZMs, which can form the basis of trouble-free topological quantum computing. In this article, SE / SU nanowires refer to semiconductor wires coated with superconductors.

[0040] However, the method is not limited to the fabrication of nanowires. Embodiments of the invention can be used to fabricate any structure where material is grown via selective area growth. For example, the described techniques can be used for waveguides, for example, in short-distance optical networks. An optical waveguide is a physical structure that guides electromagnetic waves in the spectrum, for example, an optical fiber. Alternatively, these techniques can be used to couple capacitive islands.

[0041] SAG is a growth method using a crystal growth vacuum chamber, such as chemical beam epitaxy (CBE), molecular beam epitaxy, and MOCVD. See, for example, GJ Davies Proc. SPIE 2140, Epitaxial Growth Processes, 58 (May 11, 1994); doi: 10.1117 / 12.175795; M Fahed, PhD thesis: Selectivearea growth of in-plane III-V nanostructures using molecular beam epitaxy, 2016. http: / / www.theses.fr / 2016LIL10114 ; Fukui et al., Appl. Phys. Lett. 58, 2018 (1991); doi: http: / / dx.doi.org / 10.1063 / 1.105026.

[0042] Because the material segments are grown using SAG, a network of entire segments (e.g., SE / SU nanowires) or multiple such networks can be fabricated as a whole on a substrate. The substrate (e.g., insulating substrate) and the network can be directly incorporated into the final product without transferring the segments to a different surface.

[0043] The manufacture of quantum devices involves building a wafer by depositing multiple layers or materials across a substrate, usually in different patterns. The entire process involves multiple steps as the different layers are built up. For the following description, "substrate" will be considered in this article to refer to the base layer, and "wafer" will refer to the substrate plus any other layers that have been deposited across the substrate at the current stage of the manufacturing process.

[0044] In the first phase I (masking phase), a mask 102 is formed on the bottom layer of the device (e.g., the bottom layer of the wafer 104). The mask can be an amorphous mask or an insulating mask (i.e., the insulating mask 102 can be made of an insulating material). The insulating material can be a dielectric material. The bottom layer of the wafer can be the substrate 104 itself, or it can be an intermediate material layer that has been deposited on the substrate. The mask includes a set of grooves that expose the bottom layer of the device, for example, the substrate. The entire mask can be formed at the same time, or the mask can be formed in stages.

[0045] Each groove of the mask corresponds to a material segment. In other words, material is grown in each groove to form a corresponding material segment, or in other words, each groove maps to a corresponding material segment. For example, each groove may correspond to a nanowire in the sense that a nanowire is formed in each groove. Herein, a material segment does not imply any particular shape or size. Each groove may have the same shape and / or size, some grooves may have the same shape and / or size, or each groove may have a different shape and / or size.

[0046] In some embodiments, the groove is formed so that two or more grooves are separated by discontinuities at positions corresponding to the junctions. That is, the corresponding parts of the two or more grooves are separated by a part of the mask. In other words, at least one groove can have at least one open end that is not connected (or separated) to any other groove, and these open ends are located at the junction of the groove. The discontinuity (i.e., separation) can be the order of several nanometers. Two or more grooves can be placed so that the material segments grown in those grooves will form a T-junction once connected. Figure 4 An example of a T-junction 402a formed from three material segments 404a, 404b, 404c is shown in FIG. The T-junction 402a is formed by growing material in three corresponding trenches 406a, 406b, 406c in the mask 400. As shown, the three corresponding trenches are separated by a discontinuity 408a.

[0047] In some embodiments, the grooves are formed so that at least four grooves are separated by discontinuities at locations corresponding to the junctions. That is, corresponding portions of the at least four grooves are separated by a portion of the mask. A portion of the mask serves as an initial barrier between the open ends of the grooves. The at least four grooves can be placed so that the material segments grown in these grooves will form a cross junction once connected, that is, once the four lengths of material are grown and connected, it will appear as if two longer material segments cross each other at the junction. Figure 4 Also shown is an example of a cross junction 402b formed from four material segments 404a, 404d, 404e, 404f. The cross junction 402b is formed by growing material in four corresponding trenches 406a, 406d, 406e, 406f in the mask 400. As shown, the four corresponding trenches are separated by discontinuities 408b.

[0048] The mask may include a single group of two or more grooves separated by a discontinuity (i.e., a portion of the mask). Alternatively, the mask may include multiple groups of two or more grooves, each separated by a corresponding discontinuity (i.e., a portion of the mask). The grooves may be formed so that they do not overlap, i.e., they do not spatially overlap or cover the same area of ​​the underlying layer.

[0049] In an alternative embodiment, the grooves of the mask are formed so that corresponding portions of two or more grooves narrow at positions corresponding to the junctions. That is, as the grooves approach the positions corresponding to the junctions, the width of the grooves decreases. In other words, the corresponding portions of the three grooves at the positions of the junctions are thinner (i.e., narrower) than the corresponding main portions of the three grooves. Preferably, the grooves have the same thickness as each other at both their widest and narrowest points (i.e., in a direction perpendicular to the plane of the substrate). However, this is not required. Examples of such shape offsets are as follows: Figure 5 As shown. Here, four grooves meet at a junction 502. Each groove is narrower at the junction 502 than at the groove portion not at the junction. For example, each groove can have a first end 504a-d, a different second end, and a main body portion 506a-d between the first end and the second end. The first ends 504 of two or more grooves meet at the junction 502. The corresponding first ends 504 of at least two or more grooves are narrower than the main body portion 506 of the corresponding groove. One or more grooves can form a corresponding second different junction at their second ends in the same manner.

[0050] Figure 7An example mask that can be used to manufacture a device is illustrated. A first example mask 700a includes two grooves 702a, 702b, in which two corresponding material segments can be grown. The two grooves are separated by a discontinuity 704a. The discontinuity separates a portion of one groove (i.e., the end) from a portion of another groove (i.e., the main body). The two material segments grown in the two grooves can be connected to form a junction 706. In this case, a T-shaped junction (i.e., T-shaped) will be formed. A second example mask 700b includes three grooves 702c, 702d, 702e, in which three corresponding material segments can be grown. The three grooves are separated by a discontinuity 704b. The discontinuity separates a portion of each groove (i.e., the end) from a portion of the other grooves (i.e., the end). The three material segments grown in the three grooves can be connected to form a junction 706.

[0051] Figure 8 An example mask that can be used to manufacture a device is illustrated. Mask 800 includes two grooves 802a, 802b, in which two corresponding material segments can be grown. The two grooves are separated by a discontinuity 804. The discontinuity separates a portion (i.e., an end) of one groove from a portion (i.e., an end) of the other groove. The two material segments grown in the two grooves can be connected to form a junction 806. In this case, an L-shaped junction (i.e., an L-shape) will be formed.

[0052] exist Figure 1 In the example of FIG. 1 , a patterned layer of insulating material 102 (insulating mask) is formed on top of an insulating substrate 104. In this example, the substrate is the bottom layer of a wafer, which may be the bottom layer of a device. A side view and a top view of the substrate 104 with the insulating mask 102 are shown in FIG. Figure 1 . The substrate 104 may be formed of any suitable substrate material, such as InP (indium phosphide), and in the described example is an insulating substrate. In the described example, the insulating material 102 is an oxide, but it may be any insulating (e.g., dielectric) material that supports SAG in the second stage II of the manufacturing method (see below).

[0053] The insulating mask or oxide layer 102 is patterned, as the oxide layer 102 is formed so as to leave the trenches (or narrow strips) of the substrate - in the intended area 106 - exposed (i.e. not covered by the mask 102). The pattern in this context refers to the structure of the intended area 106, which will eventually become the structure of the nanowire network, because it is in this exposed area 106 that the semiconductor (SE) nanowires are grown. Therefore, the size and structure of the nanowires match the size and structure of the exposed area 106. Although Figure 1Only one exposed region 106 is shown, but material (e.g., nanowires) may be grown in multiple regions simultaneously and all descriptions regarding the intended region 106 apply equally to multiple such regions. Thus, the structure of the entire nanowire network may be defined by the structure of the (multiple) exposed regions, which themselves are defined by the trench structure of the mask. In this example, the strips, and thus the resulting nanowires, have a width on the order of tens or hundreds of nanometers.

[0054] The insulating mask 102 may be formed so as to expose the intended area 106 in any suitable manner. For example, a uniform, continuous dielectric layer, such as an oxide, may be deposited on the substrate 104 or other underlying layer, and then the exposed area 106 may be formed by selectively etching away the insulating mask 102 from the intended area 106 (in which case the etching defines the final nanowire network structure). As another example, the insulating material 102 may be selectively deposited on the substrate 104 using a mask that prevents the material (e.g., oxide) 102 from being deposited in the intended area 106 (in which case the mask defines the final nanowire network structure). The oxide 102 may be, for example, silicon oxide (SiOx). More generally, any suitable dielectric or other insulator may be used.

[0055] In the second phase II (semiconductor growth phase, or SAG phase), material 108 is grown in the grooves that expose the bottom layer of the wafer. In the case where the bottom layer is the substrate itself, material 108 is grown on the exposed portion of the substrate. The growth of the material is initiated in each group of grooves. The growth can be initiated at the same time or at different times. For example, growth can be initiated in a first group of grooves, and then growth is initiated in a second group, a different groove. The material can be a semiconductor. In this case, the semiconductor material grown in the selective area forms a nanowire network.

[0056] Return to reference Figure 1 In the example of , material 108 (eg, semiconductor material) is selectively grown within the desired region 106, on top of the exposed portion of substrate 104. Figure 1 An example is shown in the upper right corner of FIG. 1 , where a side view of the substrate 104 is shown. Due to the patterning of the mask 102, the selectively grown semiconductor 108 forms an in-plane nanowire (i.e., the nanowire is located at the position of the substrate 104). The semiconductor material 108 can be, for example, indium arsenide (InAs), indium antimonide (InSb), or any other semiconductor with a relatively large spin-orbit and G factor. The SAG semiconductor 108 can be, for example, a confined 2DEG (two-dimensional electron gas) semiconductor heterostructure or a single material semiconductor.

[0057] SAG is a growth method using a crystal growth vacuum chamber. SAG refers to the local growth of material in the exposed area of ​​the substrate, and the growth conditions are selected to prevent such growth on the mask itself. For example, this can be based on chemical beam epitaxy (CBE), molecular beam epitaxy (MBE), or metal organic chemical vapor deposition (MOCVD). In the context of semiconductors, SAG can refer to a type of epitaxial semiconductor growth (also known as selective area epitaxy) in which a patterned insulating mask is used to define the desired structure (photolithographic form) that defines the semiconductor material to be grown. Epitaxy refers to a technique in which a second crystal is grown on the first crystal using a first crystal as a seed. In SAG, the process is adjusted so that semiconductor growth occurs only on areas of the substrate that are not covered by the insulating mask 102, rather than on the insulating mask itself, for example, not on a dielectric mask. This is different from other deposition / growth processes, such as bottom-up growth (without the use of a mask) and uniform deposition (epitaxial or otherwise), in which the material is deposited uniformly across the surface regardless of its material composition (such as stage III - see below). SAG may be performed in high vacuum or ultra-high vacuum and may require careful tuning to achieve the desired selective semiconductor growth.

[0058] In the second stage II, any suitable SAG process can be used to create the desired material segments, for example, SE nanowires in the exposed region 106. The SAG nanowires are defined along a high symmetry in-plane crystal orientation on the substrate, which also gives the nanowires well-defined facets. This makes the SU / SE interface flat, possibly atomically flat, and well defined.

[0059] SAG is known per se and will not be discussed in further detail here. For a further description of SAG, see, for example, GJ Davies, M Fahed, and Fukui et al. cited above.

[0060] Suffice it to say that the selective area growth phase is such that at the end of this phase, material 108 fills the desired region 106 (i.e., the region 106 where the underlying layer or substrate 104 is not covered by mask 102). In some cases, it may extend outward in a direction normal to (perpendicular to) the plane of the underlying layer or substrate 104 (hereinafter the z-direction) so as to protrude outward from mask 102. That is, semiconductor material 108 extends a greater distance in the z-direction from underlying layer or substrate 104 than from mask 102. In this way, semiconductor material 108 forms nanowires that are substantially in the plane of underlying layer or substrate 102 (in-situ nanowires).

[0061] Once two or more material segments are formed by SAG, they are connected to form a junction. Similarly, four material segments can be connected to form a junction. In some embodiments, the connection is part of the SAG stage. The material segments merge by lateral growth of material crystals. That is, the connection of material segments (e.g., nanowires) can occur naturally during (or at the end of) the SAG stage. In the case where the grooves are separated by discontinuities, the open ends of the previously separated grooves extend laterally to merge with each other. That is, they grow across the mask portions that separate the material segments. An example of this phenomenon is Figure 6 Herein, as a proof of concept, two material segments 602a, 602b are shown during their merging at a junction 604.

[0062] Alternatively, the material segments may be connected after the SAG stage (but before any superconductor growth stage, if any). The material segments may be connected using an electrical conductor, such as a metal lead or material. That is, the open ends of the separated trenches are connected with a conductive material. The electrical conductor may act as a semiconductor bridge, bridging the separated segments of semiconductor material.

[0063] Regardless of how the material segments are connected, they are connected across the mask. That is, lateral extension of the (semiconductor) material causes material to grow over portions of the mask that act as barriers between isolated trenches, e.g., open-ended trenches. Alternatively, an electrical conductor is placed over the portion to connect the isolated trenches.

[0064] In an optional third stage III (superconductor growth stage), a layer of superconducting (SU) material 112 may be grown on at least a portion of the network of material segments, for example, a nanowire network. Figure 1 In the example of, a superconducting material layer is grown using a particle beam 110. Herein, a superconducting material means a material that exhibits superconducting properties at least under certain conditions. An example of such a material is aluminum (Al). Alternatively, superconductor material 112 can be niobium (Nb), titanium nitride (TiN) or any other superconductor. In the following example, a superconductor is epitaxially grown in stage III, and superconductor growth stage III may be referred to as an epitaxial growth stage in this context. However, the technology is not limited in this respect, and the desired result can be achieved via the growth of a non-epitaxial superconductor in the third stage.

[0065] For example, superconducting material 112 may be grown in stage III using molecular beam epitaxy (MBE) electron gun epitaxy.

[0066] At least a portion of the superconductor layer 112 is deposited on top of the material segment such that the portion of the superconductor layer 112 ( Figure 1The semiconductor material 108 of the nanowire is directly in contact with the SE 108 of the nanowire (denoted as 116 in FIG. 1 ). That is, the semiconductor 108 of the nanowire is at least partially covered by the superconducting material.

[0067] This is also a form of epitaxy, but not SAG. In particular, in the epitaxial growth stage III, epitaxial growth does occur on the mask (or dielectric layer) 102, as well as on the SE 108 of the nanowire.

[0068] In one possible technique, the beam can be angled substantially in the z-direction (the direction perpendicular to the plane of the substrate) such that substantially all exposed surfaces of the mask 102 and the SE material 108 are covered by the SU layer 112. However, in another illustrated example, the particle beam 110 is incident on the substrate 104 at a non-zero angle of incidence relative to the z-direction (deposition angle). Due to this non-zero deposition angle and the protruding structure of the SE core 108 of the nanowire, the SE of the nanowire is only partially coated by the superconductor layer 112; that is, a portion of the SE nanowire core (labeled as 118) is not coated by the superconductor material. Most of the insulating mask 102 is also coated by the superconductor layer 112, but due to the angle of the incident beam 110 and the protruding structure of the SE nanowire core 108, a small area (shaded area) of the insulating mask 102 adjacent to the protruding SE nanowire 108 is exposed, i.e., is not coated by the SU material. One such shaded area is at Figure 1 The shaded region 120 is marked as 120 in FIG. 1. The shaded region 120 separates the SE material 108 from a portion of the SU layer 112 in the "side gate" region 122. The portion of the SU layer 112 in the side gate region 122 can be used to form a gate for controlling the nanowires, or (more likely) the SU material can be etched away from this region and replaced with a more suitable gate material. Either way, the shaded gap 120 ensures that the gate operates as intended. Forming the gap 120 using this "in situ" patterning (described above) in the SU epitaxy stage III ensures that material does not need to be too close to the delicate nanowires 108 to be etched away.

[0069] The SAG stage II and superconductor growth stage III can be performed in a vacuum chamber, preferably without moving the substrate 104 between stages. These stages can be performed under high vacuum or ultra-high vacuum conditions (~10-8-10-12 Torr or less), and these vacuum conditions can be maintained between stages. Among other things, this can ensure that the SE / SU interface is clean and free of unwanted impurities.

[0070] Both the SAG phase and the superconductor growth phase may require carefully calibrated conditions to enter the respective "growth windows" of the two phases to achieve the desired (semiconductor) material growth and superconductor material growth, respectively. The growth conditions, temperature and flux are selected according to the material type. For example, for MBE (which can be used for both the SAG phase II and the superconductor growth phase III), the substrate is usually heated to a temperature of about 500°C or higher to clean the native oxide on the surface. However, in the SAG growth phase II and the SU growth phase III, the corresponding temperature windows for the expected growth to occur depend on the composition of the SE material 108 and the SU material 112, respectively. The superconductor can be grown / deposited in situ without breaking the vacuum. In this way, the surface of the SAG will not be oxidized in the air and remains clean until the SU is added, which ensures the cleanliness of the SE-SU interface.

[0071] The substrate (or bottom layer of a wafer) 104 and mask 102 on which the SE / SU nanowire network is grown can be incorporated into a final product, such as a quantum circuit or quantum computer, as well as the SE / SU nanowire network, without transferring the nanowires from the substrate on which they were originally fabricated.

[0072] Embodiments of the disclosed technology include topologically protected quantum computing circuits that include nanowire networks formed using such hybrid semiconductor and superconductor regions. Figure 2 In FIG. 1 , a line pattern consisting of InAs nanowires grown on an insulating GaAs substrate is shown. In particular, Figure 2 The fabrication of complex networks based on one-dimensional nanowire networks is shown.

[0073] As described above, selective area growth (SAG) of nanowire networks can be used to produce Majorana-based topological qubits, which exploit the formation of superconducting islands, some of which are topological (T) and some of which are non-topological (e.g., conventional s-wave (S)). The SAG technique can provide a high degree of control over the shape of the device being produced and can therefore be used to produce components used in scalable topological quantum computing. In an example embodiment, one or more Majorana zero modes, MZMs, can be induced in at least one nanowire (i.e., material segment) of a nanowire network by cooling the superconductor to a superconducting temperature and applying a magnetic field to the device.

[0074] The examples described herein are to be understood as illustrative examples of embodiments of the present invention. Further embodiments and examples are contemplated. Any feature described with respect to any one example or embodiment may be used alone or in combination with other features. In addition, any feature described with respect to any one example or embodiment may also be combined with one or more features of any other example or embodiment, or any combination of any other example or embodiment may be used. In addition, equivalents and modifications not described herein may also be adopted within the scope of the present invention, the scope of which is defined by the claims.

Claims

1. A method of manufacturing a device, wherein the device comprises a plurality of material segments and at least one knot, the at least one knot connecting two or more of the plurality of material segments, and wherein the method comprises: In a masking stage, a mask is formed on a bottom layer of the device, wherein the mask includes a plurality of trenches exposing the bottom layer, each trench corresponding to one of the material segments, and wherein a corresponding portion of each of at least two of the trenches (a) is narrowed or (b) is separated by a discontinuity at a location corresponding to the at least one junction; In the selective area growth stage, the material concentrated in the groove is grown by selective area growth to form the material segment on the bottom layer; as well as The two or more material segments are connected at the at least one junction.

2. The method according to claim 1, wherein the connecting comprises: The merging occurs by lateral growth of the material during the selective area growth phase.

3. The method of claim 1, wherein the connecting comprises: In a stage subsequent to the selective area growth stage, the two or more material segments are connected via an electrical conductor.

4. The method of claim 1, wherein the at least one junction connects only two or three of the material segments; thereby forming a T-junction.

5. The method of claim 1 , wherein at least four of the material segments are connected at the at least one junction, wherein a corresponding portion of each of the at least four grooves (a) is narrowed, or (b) is interrupted and separated at a position corresponding to the at least one junction, and wherein the connecting comprises connecting the at least four material segments at the at least one junction; thereby forming a cross junction.

6. A method according to claim 1, wherein the device includes a plurality of junctions, each junction connecting at least some of the material segments, wherein two or more corresponding material segments are connected at each corresponding junction, wherein for each corresponding junction, the mask includes two or more corresponding sets of grooves corresponding to the two or more corresponding material segments, wherein a corresponding portion of each of the two or more corresponding grooves is (a) narrowed or (b) interrupted and separated at a position corresponding to the at least one junction, wherein the growing includes growing material in the corresponding groove sets by selective area growth to form the two or more corresponding material segments on the bottom layer, and wherein the connecting includes connecting the two or more corresponding material segments at each corresponding junction. The method according to claim 1 , wherein the bottom layer is a bottom layer of a wafer. The method of claim 1 , wherein the bottom layer is a substrate of a wafer.

9. The method of claim 1, wherein the plurality of trenches are formed by etching the mask from the bottom layer.

10. The method of claim 1, wherein the pattern of the plurality of trenches is defined by photolithography. The method according to claim 1 , wherein the mask is an insulating mask.

12. The method of claim 1, wherein the mask is a dielectric.

13. The method of claim 1, wherein the bottom layer is an insulating material.

14. The method of claim 1, wherein the material is a semiconductor.

15. The method of claim 1, wherein the material is grown by epitaxy.

16. The method according to claim 1, comprising: In the superconductor growth phase, a superconductor material layer is grown on at least some of the material segments.

17. A method according to claim 16, wherein the layer of superconductor material is applied using a particle beam.

18. The method of claim 16, wherein the superconductor material is grown by epitaxy.

19. The method of claim 1, wherein the device is a quantum device, and wherein the segments of material are nanowires.

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