A dual-pulse test circuit and method for a three-level integrated inverter IGBT module

Abstract

The present invention discloses a dual-pulse test circuit and method for a three-level integrated inverter IGBT module, comprising a DC power supply, a first switch module, a second switch module, a third switch module, a fourth switch module, a fifth switch module, a sixth switch module, a seventh switch module, an eighth switch module, a ninth switch module, a tenth switch module, an eleventh switch module, and an inductor. The first to eleventh switch modules and the inductor module constitute a test circuit conversion unit, and different test circuits are used for different IGBTs in the IGBT module to be tested. At the same time, compared with the traditional dual-pulse test method for a single IGBT, due to the multiple circuit combinations composed of the first to eleventh switch modules, a dual-pulse test can be more conveniently performed on each IGBT in the IGBT module to be tested, thereby improving test efficiency and test consistency.

Description

Technical Field

[0001] The present invention belongs to the field of double pulse technology when semiconductor switching devices are used in bridge arms, and in particular to the field of large-scale double pulse testing of integrated IGBT modules. Background Art

[0002] The semiconductor switching device IGBT is used in the bridge arm. The current overshoot and voltage overshoot that occur during the switching process have a great impact on the switching process of the IGBT. The double pulse test is a common test method for the current overshoot and voltage overshoot of the IGBT in the bridge arm during the switching process.

[0003] For IGBT modules with multiple commutation circuits, dual-pulse testing of the IGBTs involved in each commutation process requires setting up test circuits one by one. This is cumbersome and has low test efficiency, making it unsuitable for large-scale IGBT dual-pulse testing. Summary of the Invention

[0004] In order to solve the above-mentioned disadvantages in performing double-pulse testing on IGBT modules with multiple commutation circuits, the purpose of the present invention is to propose a double-pulse integrated testing method for IGBT modules with ANPC three-level topology, which can solve the current problem of being unfavorable for double-pulse testing of IGBT modules with ANPC three-level topology.

[0005] To achieve the above objectives, the present invention provides a dual-pulse test circuit for a three-level integrated inverter IGBT module, comprising a DC power supply, wherein the positive electrode of the DC power supply is connected to the a-terminal of the third switch module K3 and the a-terminal of the fifth switch module K5, and the b-terminal of the third switch module K3 is connected to the b-terminal of the tenth switch module K10 and the b-terminal of the eighth switch module K8;

[0006] The b-end of the fifth switch module K5 is connected to the b-end of the fourth switch module K4, the a-end of the tenth switch module K10, the a-end of the seventh switch module K7, and the b-end of the eleventh switch module K11;

[0007] The b-end of the seventh switch module K7 is connected to the a-end of the inductor L, the a-end of the eighth switch module K8, and the b-end of the ninth switch module K9. The b-end of the inductor L is connected to the AC output end of the IGBT module to be tested.

[0008] End a of the ninth switch module K9, end a of the eleventh switch module K11, and end a of the sixth switch module are connected; end b of the sixth switch module, end a of the fourth switch module K4, end a of the second switch module K2, and end a of the first switch module K1 are connected; end b of the first switch module K1 is connected to end a of the first resistor R1; and end b of the first resistor R1 is connected to the negative electrode of the DC power supply.

[0009] Furthermore, the a-terminal of the third switch module K3 is connected to the positive bus capacitor C bus+ The positive terminal of the positive bus capacitor C bus+ The negative end of the fifth switch module K5 is connected to the b end and the negative bus capacitor C bus- The positive terminal of the negative bus capacitor C bus- The negative end of is connected to the a end of the sixth switch module.

[0010] Furthermore, a second resistor R2 is connected between the b-end of the third switch module K3 and the b-end of the tenth switch module K10 , and a third resistor R3 is connected between the a-end of the eleventh switch module K11 and the a-end of the sixth switch module.

[0011] Furthermore, the switch module is a switch or a relay.

[0012] Furthermore, the inductor L is an air-core inductor.

[0013] Based on the dual-pulse test method of the three-level integrated inverter IGBT module of the above circuit, a dual-pulse test loop for different IGBTs in the IGBT module to be tested is formed by selectively closing the first switch module K1, the second switch module K2, the third switch module K3, the fourth switch module K4, the fifth switch module K5, the sixth switch module K6, the seventh switch module K7, the eighth switch module K8, the ninth switch module K9, the tenth switch module K10, and the eleventh switch module K11.

[0014] Further, the first switch module, the second switch module, the third switch module, the fourth switch module and the seventh switch module are closed to form a double-pulse test loop for T1 of the IGBT module to be tested; the first switch module, the second switch module, the third switch module, the fourth switch module and the eighth switch module are closed to form a double-pulse test loop for T3 and T5 of the IGBT module to be tested; the first switch module, the second switch module, the fifth switch module, the sixth switch module and the seventh switch module are closed to form a double-pulse test loop for T4 of the IGBT module to be tested; the first switch module, the second switch module, the fifth switch module, the sixth switch module and the ninth switch module are closed to form a double-pulse test loop for T2 and T6 of the IGBT module to be tested.

[0015] Furthermore, the tenth switch module and the eleventh switch module are closed to form a discharge loop, and the residual charge is released after each IGBT of the IGBT module to be tested is tested.

[0016] Compared with the prior art, the present invention has at least the following beneficial technical effects:

[0017] To address the fact that different IGBT dual-pulse tests within an integrated ANPC three-level IGBT module require different circuits, an integrated circuit switching device is designed. The first to eleventh switch modules and an inductor form a test circuit conversion unit. By switching these switch modules in different combinations, the test circuits required for different IGBT dual-pulse tests can be easily switched. This allows for large-scale standardized dual-pulse testing of integrated ANPC three-level IGBT modules, improving both test efficiency and test consistency.

[0018] Furthermore, the second resistor and the third resistor form a discharge unit of the test circuit, which is used to release residual charge in the circuit after the IGBT test is completed.

[0019] Furthermore, the positive bus capacitor and the negative bus capacitor in the test circuit are used to filter the power supply and provide high current. The test method of the present invention can form a dual-pulse test loop for different IGBTs in the IGBT module to be tested by selectively closing the eleven switch modules, which is easy to operate.

[0020] Furthermore, after the double-pulse test of each IGBT is completed, the residual charge of the positive and negative bus capacitors is reliably released, thereby realizing a fast and standardized double-pulse test process for all IGBTs within the IGBT module to be tested.

[0021] Furthermore, the switch module is a relay, which is simple to control and easy to operate. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1a The pulse test circuit provided by the present invention;

[0023] Figure 1b In order to form a corresponding test loop when performing a double pulse test on different IGBTs inside the IGBT module to be tested, it is necessary to fill in the switch selection list of the eleven switch modules;

[0024] Figure 2a This is the test circuit corresponding to the double pulse test of T1 inside the IGBT module to be tested;

[0025] Figure 2b The switching information of the six IGBTs corresponding to the double pulse test of T1 inside the IGBT module to be tested;

[0026] Figure 2c A schematic diagram of the current path of the inductor's stored charge when performing a double-pulse test on T1 inside the IGBT module to be tested;

[0027] Figure 2dA schematic diagram of the current path of the inductor releasing electricity when performing a double pulse test on T1 inside the IGBT module to be tested;

[0028] Figure 3a This is the test circuit corresponding to the double pulse test of T2 inside the IGBT module to be tested;

[0029] Figure 3b This is the switching information of the six IGBTs corresponding to the double pulse test of T2 inside the IGBT module to be tested;

[0030] Figure 3c A schematic diagram of the current path of the inductor's stored charge when performing a double-pulse test on T2 inside the IGBT module to be tested;

[0031] Figure 3d A schematic diagram of the current path of the inductor releasing electricity when performing a double pulse test on T2 inside the IGBT module to be tested;

[0032] Figure 4a This is the test circuit corresponding to the double pulse test of T3 inside the IGBT module to be tested;

[0033] Figure 4b This is the switching information of the six IGBTs corresponding to the double pulse test of T3 inside the IGBT module to be tested;

[0034] Figure 4c A schematic diagram of the current path of the inductor's stored charge when performing a double-pulse test on T3 inside the IGBT module to be tested;

[0035] Figure 4d A schematic diagram of the current path of the inductor releasing electricity when performing a double pulse test on T3 inside the IGBT module to be tested;

[0036] Figure 5a This is the test circuit corresponding to the double pulse test of T4 inside the IGBT module to be tested;

[0037] Figure 5b This is the switching information of the six IGBTs corresponding to the double pulse test of T4 inside the IGBT module to be tested;

[0038] Figure 5c A schematic diagram of the current path of the inductor's stored charge when performing a double-pulse test on T4 inside the IGBT module to be tested;

[0039] Figure 5d A schematic diagram of the current path of the inductor releasing electricity when performing a double pulse test on T4 inside the IGBT module to be tested;

[0040] Figure 6aThis is the test circuit corresponding to the double pulse test of T5 inside the IGBT module to be tested;

[0041] Figure 6b This is the switching information of the six IGBTs corresponding to the double pulse test of T5 inside the IGBT module to be tested;

[0042] Figure 6c Schematic diagram of the current path of the inductor stored charge when performing a double pulse test on T5 inside the IGBT module to be tested;

[0043] Figure 6d A schematic diagram of the current path of the inductor releasing electricity when performing a double pulse test on T5 inside the IGBT module to be tested;

[0044] Figure 7a This is the test circuit corresponding to the double pulse test of T6 inside the IGBT module to be tested;

[0045] Figure 7b The switching information of the six IGBTs corresponding to the double pulse test of T6 inside the IGBT module to be tested;

[0046] Figure 7c A schematic diagram of the current path of the inductor's stored charge when performing a double-pulse test on T6 inside the IGBT module to be tested;

[0047] Figure 7d A schematic diagram of the current path of the inductor releasing electricity when performing a double pulse test on T6 inside the IGBT module to be tested;

[0048] Figure 8 It is a circuit for releasing the electricity of busbar supporting capacitor;

[0049] Figure 9 This is the circuit diagram of a Type I-NPC three-level integrated inverter IGBT module. DETAILED DESCRIPTION

[0050] In order to make the purpose and technical solution of the present invention clearer and easier to understand, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. The specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0051] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more. In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0052] like Figure 1a As shown, a double pulse test circuit for a three-level integrated inverter IGBT module includes a DC power supply DC_supply, a first switch module K1, a second switch module K2, a third switch module K3, a fourth switch module K4, a fifth switch module K5, a sixth switch module K6, a seventh switch module K7, an eighth switch module K8, a ninth switch module K9, a tenth switch module K10, an eleventh switch module K11, and a positive bus capacitor C bus+ , negative bus capacitor C bus- , a first resistor R1, a second resistor R2, a third resistor R3 and an inductor L;

[0053] The b-end of the first switch module is connected to the a-end of the first resistor, and the a-end of the first switch module is connected to the b-end of the sixth switch module;

[0054] The b-end of the second switch module is connected to the b-end of the first resistor, and the a-end of the second switch module is connected to the b-end of the sixth switch module;

[0055] The a terminal of the third switch module is connected to the + terminal of the DC power supply, and the b terminal of the third switch module is connected to the node BUS+;

[0056] The a terminal of the fourth switch module is connected to the b terminal of the sixth switch module, and the b terminal of the fourth switch module is connected to BUS_N;

[0057] The a terminal of the fifth switch module is connected to the + terminal of the DC power supply, and the b terminal of the fifth switch module is connected to BUS_N;

[0058] The a terminal of the sixth switch module is connected to BUS-, and the b terminal of the sixth switch module is connected to the a terminal of the second switch module;

[0059] The terminal a of the seventh switch module is connected to BUS_N, and the terminal b of the seventh switch module is connected to the terminal a of the inductor;

[0060] The a terminal of the eighth switch module is connected to the a terminal of the inductor L, and the b terminal of the eighth switch module is connected to BUS+;

[0061] The a terminal of the ninth switch module is connected to BUS-, and the b terminal of the ninth switch module is connected to the a terminal of the inductor L;

[0062] The a terminal of the tenth switch module is connected to BUS_N, and the b terminal of the tenth switch module is connected to the a terminal of the second resistor;

[0063] The a terminal of the eleventh switch module is connected to the b terminal of the third resistor, and the b terminal of the eleventh switch module is connected to BUS_N;

[0064] Positive bus capacitor C bus The + end of the positive bus capacitor is connected to BUS+, and the - end of the positive bus capacitor is connected to BUS_N;

[0065] Negative bus capacitor C bus The + end of the - is connected to BUS_N, and the - end of the negative bus capacitor is connected to BUS-;

[0066] The a terminal of the first resistor is connected to the b terminal of the first switch module, and the b terminal of the first resistor is connected to the - terminal of the power module;

[0067] The a terminal of the second resistor is connected to the b terminal of the tenth switch module, and the b terminal of the second resistor is connected to BUS+;

[0068] The end a of the third resistor is connected to BUS-, and the end b of the third resistor is connected to the end a of the eleventh switch module;

[0069] The end a of the inductor L is connected to the end b of the seventh switch module, and the end b of the inductor is connected to the AC output end of the IGBT module to be tested.

[0070] The first to eleventh switch modules are switches or relays. Preferably, the switch modules are relays.

[0071] By selectively closing the above eleven switch modules, a double-pulse test loop for different IGBTs in the IGBT module to be tested can be formed; and after the double-pulse test of each IGBT is completed, the positive bus capacitor C bus + and negative bus capacitors C bus -Residual charge is released, thus realizing a fast and standardized double pulse test process for all IGBTs in the IGBT module to be tested.

[0072] like Figure 1b As shown, according to the content of the present invention, a dual-pulse test is performed on different IGBTs inside the IGBT module of the ANPC to be tested, and by switching the switching states of the first to eleventh switch modules, different dual-pulse test circuits and discharge circuits for the residual power of the positive bus capacitor and the negative bus capacitor are formed.

[0073] Close the first switch module, the second switch module, the third switch module, the fourth switch module, and the seventh switch module to form a double-pulse test loop for T1 of the IGBT module to be tested;

[0074] Close the first switch module, the second switch module, the third switch module, the fourth switch module, and the eighth switch module to form a double-pulse test loop for T3 and T5 of the IGBT module to be tested;

[0075] Close the first switch module, the second switch module, the fifth switch module, the sixth switch module, and the seventh switch module to form a double-pulse test loop for T4 of the IGBT module to be tested;

[0076] Close the first switch module, the second switch module, the fifth switch module, the sixth switch module, and the ninth switch module to form a double-pulse test loop for T2 and T6 of the IGBT module to be tested;

[0077] The tenth and eleventh switch modules are closed to form a discharge loop for the positive bus capacitor and the negative bus capacitor, ensuring that the residual charge of the positive bus capacitor and the negative bus capacitor is released after each IGBT of the IGBT module to be tested is tested.

[0078] like Figure 2a As shown, the first switch module, the third switch module, the fourth switch module, the seventh switch module and the second switch module are closed in sequence to form a double pulse test loop for the T1 device inside the IGBT module to be tested; Figure 2b The following table shows the IGBT control signal list for the double pulse test process of the T1 device, where "1" represents a high level and "0" represents a low level. Figure 2cThe figure shows the storage circuit of the inductor when performing a double pulse test on the T1 device. The circuit is composed of DC_supply, T1 device, T2 device and the inductor, and the current overshoot when the T1 device is turned on is tested; Figure 2d The figure shows the inductor releasing the electric charge loop when the double pulse test is performed on the T1 device. The loop is composed of the D5 device, the T2 device and the inductor, and the voltage overshoot during the shutdown process of the T1 device is tested.

[0079] like Figure 3a As shown, according to the content of the present invention, the first switch module, the fifth switch module, the sixth switch module, the ninth switch module and the second switch module are closed in sequence to form a double pulse test loop for the T2 device inside the IGBT module to be tested; Figure 3b The following table shows the IGBT control signal list for the double pulse test process of the T2 device, where "1" represents a high level and "0" represents a low level. Figure 3c The figure shows the storage circuit of the inductor when the double pulse test is performed on the T2 device. The circuit is composed of DC_supply, D5 device, T2 device and the inductor, and the current overshoot when the T2 device is turned on is tested; Figure 3d The figure shows the inductor releasing the electric charge loop when performing double pulse test on the T2 device. The loop is composed of the D3 device, the D4 device and the inductor, and the voltage overshoot during the shutdown process of the T2 device is tested.

[0080] like Figure 4a As shown, according to the content of the present invention, the first switch module, the third switch module, the fourth switch module, the eighth switch module and the second switch module are closed in sequence to form a double pulse test loop for the T3 device inside the IGBT module to be tested; Figure 4b The following table shows the IGBT control signal list for the double pulse test process of the T3 device, where "1" represents a high level and "0" represents a low level. Figure 4c The figure shows the storage circuit of the inductor when the double pulse test is performed on the T3 device. The circuit is composed of DC_supply, D6 device, T3 device and the inductor, and the current overshoot when the T3 device is turned on is tested; Figure 4d The figure shows the inductor releasing the charge loop when performing a double pulse test on the T3 device. The loop is composed of the D1 device, the D2 device and the inductor, and the voltage overshoot during the shutdown process of the T3 device is tested.

[0081] like Figure 5a As shown, according to the content of the present invention, the first switch module, the fifth switch module, the sixth switch module, the seventh switch module and the second switch module are closed in sequence to form a double pulse test loop for the T4 device inside the IGBT module to be tested; Figure 5bThe following table shows the IGBT control signal list for the double pulse test process of the T4 device, where "1" represents a high level and "0" represents a low level. Figure 5c The figure shows the storage circuit of the inductor when the double pulse test is performed on the T4 device. The circuit is composed of DC_supply, T3 device, T4 device and the inductor, and the current overshoot when the T4 device is turned on is tested; Figure 5d The figure shows the inductor releasing the charge loop when performing a double pulse test on the T4 device. The loop is composed of the D6 device, the T3 device and the inductor, and the voltage overshoot during the shutdown process of the T4 device is tested.

[0082] like Figure 6a As shown, according to the content of the present invention, the first switch module, the third switch module, the fourth switch module, the eighth switch module and the second switch module are closed in sequence to form a double pulse test loop for the T5 device inside the IGBT module to be tested; Figure 6b The following table shows the IGBT control signal list for the double pulse test process of the T5 device, where "1" represents a high level and "0" represents a low level. Figure 6c The figure shows the storage circuit of the inductor when the double pulse test is performed on the T5 device. The circuit is composed of DC_supply, D2 device, T5 device and the inductor, and the current overshoot when the T5 device is turned on is tested; Figure 6d The figure shows the inductor releasing the charge loop when performing a double pulse test on the T5 device. The loop is composed of the D1 device, the D2 device and the inductor, and the voltage overshoot during the shutdown process of the T5 device is tested.

[0083] like Figure 7a As shown, according to the present invention, the first switch module, the fifth switch module, the sixth switch module, the ninth switch module and the second switch module are closed in sequence to form a double pulse test loop for the T6 device inside the IGBT module to be tested; Figure 7b The following table shows the IGBT control signal list for the double pulse test process of the T6 device, where "1" represents a high level and "0" represents a low level. Figure 7c The figure shows the storage circuit of the inductor when the double pulse test is performed on the T6 device. The circuit is composed of DC_supply, D3 device, T6 device and the inductor, and the current overshoot when the T6 device is turned on is tested; Figure 7d The figure shows the inductor releasing the electric charge loop when performing double pulse test on the T6 device. The loop is composed of the D3 device, the D4 device and the inductor, and the voltage overshoot during the shutdown process of the T6 device is tested.

[0084] like Figure 8As shown, according to the present invention, after the IGBT double pulse test inside the IGBT module to be tested is completed, only the tenth switch module and the eleventh switch module are closed, forming a circuit to connect the positive bus capacitor C using the second resistor and the third resistor. bus+ and negative bus capacitor C bus- The residual power discharge circuit.

[0085] The test circuit and test method provided by the present invention can also be used to test a Type I-NPC three-level integrated inverter IGBT module. The circuit diagram of the Type I-NPC three-level integrated inverter IGBT module is shown in FIG. Figure 9 shown.

[0086] The above content is only for explaining the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. A double pulse test circuit for a three-level integrated inverter IGBT module, characterized in that: A DC power supply is included, wherein the positive electrode of the DC power supply is connected to the a-end of the third switch module K3 and the a-end of the fifth switch module K5, and the b-end of the third switch module K3 is connected to the b-end of the tenth switch module K10 and the b-end of the eighth switch module K8; The b-end of the fifth switch module K5 is connected to the b-end of the fourth switch module K4, the a-end of the tenth switch module K10, the a-end of the seventh switch module K7, and the b-end of the eleventh switch module K11; The b-end of the seventh switch module K7 is connected to the a-end of the inductor L, the a-end of the eighth switch module K8, and the b-end of the ninth switch module K9. The b-end of the inductor L is connected to the AC output end of the IGBT module to be tested. End a of the ninth switch module K9, end a of the eleventh switch module K11, and end a of the sixth switch module are connected; end b of the sixth switch module, end a of the fourth switch module K4, end a of the second switch module K2, and end a of the first switch module K1 are connected; end b of the first switch module K1 is connected to end a of the first resistor R1; and end b of the first resistor R1 is connected to the negative electrode of the DC power supply; The a-end of the third switch module K3 is connected to the positive bus capacitor C bus+ The positive terminal of the positive bus capacitor C bus+ The negative end of the fifth switch module K5 is connected to the b end and the negative bus capacitor C bus- The positive terminal of the negative bus capacitor C bus- The negative end of is connected to the a end of the sixth switch module; A second resistor R2 is connected between the b-end of the third switch module K3 and the b-end of the tenth switch module K10, and a third resistor R3 is connected between the a-end of the eleventh switch module K11 and the a-end of the sixth switch module; The inductor L is an air-core inductor.

2. A double pulse test circuit for a three-level integrated inverter IGBT module according to claim 1, characterized in that: The first switch module K1, the second switch module K2, the third switch module K3, the fourth switch module K4, the fifth switch module K5, the sixth switch module K6, the seventh switch module K7, the eighth switch module K8, the ninth switch module K9, the tenth switch module K10 and the eleventh switch module K11 are relays.

3. A double pulse test method for a three-level integrated inverter IGBT module based on the circuit of claim 1, characterized in that: By selectively closing the first switch module K1, the second switch module K2, the third switch module K3, the fourth switch module K4, the fifth switch module K5, the sixth switch module K6, the seventh switch module K7, the eighth switch module K8, the ninth switch module K9, the tenth switch module K10, and the eleventh switch module K11, a double-pulse test loop for different IGBTs in the IGBT module to be tested is formed.

4. The double pulse test method for a three-level integrated inverter IGBT module according to claim 3, characterized in that: Close the first switch module, the second switch module, the third switch module, the fourth switch module and the seventh switch module to form a double-pulse test loop for T1 of the IGBT module to be tested; Close the first switch module, the second switch module, the third switch module, the fourth switch module and the eighth switch module to form a double-pulse test loop for T3 and T5 of the IGBT module to be tested; Close the first switch module, the second switch module, the fifth switch module, the sixth switch module, and the seventh switch module to form a double-pulse test loop for T4 of the IGBT module to be tested; The first switch module, the second switch module, the fifth switch module, the sixth switch module and the ninth switch module are closed to form a double-pulse test loop for T2 and T6 of the IGBT module to be tested.

5. The double pulse test method for a three-level integrated inverter IGBT module according to claim 4, characterized in that: The tenth switch module and the eleventh switch module are closed to form a discharge circuit, and the residual charge is released after each IGBT of the IGBT module to be tested is tested.

Images