Pixel and associated transfer gate fabrication method

Abstract

A method for forming a transfer gate includes: (i) forming a dielectric pillar on a surface of a semiconductor substrate; and (ii) growing an epitaxial layer around the dielectric pillar on the semiconductor substrate. The dielectric pillar has a pillar height exceeding the epitaxial layer height relative to the surface. The method further includes removing the dielectric pillar to create a trench in the epitaxial layer. A pixel includes a doped semiconductor substrate having a positive surface opposite a back surface. The positive surface is formed extending a depth z relative to the positive surface within the doped semiconductor substrate along a direction z perpendicular to both the positive and back surfaces. T The trenches. Pixels have a doping concentration distribution, and the derivative of the doping concentration distribution with respect to the direction z is at depth z. T The points are discontinuous.

Description

Technical Field

[0001] This application relates to the field of image sensor technology, and more particularly to a method for manufacturing pixels and associated transfer gates. Background Technology

[0002] Camera modules in commercial products (such as standalone digital cameras, mobile devices, automotive parts, and medical devices) include an image sensor and its pixel array. The pixel array comprises multiple pixels. The pixel density of the pixel array is the number of pixels per unit area on the image sensor. In operation, the lens of the camera module forms an image of an object on the image sensor within its field of view. The object can be viewed as multiple infinitesimally small point light sources (“pulses”) incident on the camera. The lens images each of these pulses onto the plane of the pixel array as a corresponding one of multiple point spread functions (“impulse responses”). The resolution of the image captured by the image sensor depends in part on the pixel size, compared to the magnitude of the impulse response. Therefore, one way to increase the maximum achievable resolution of a camera is to increase the pixel density by reducing the pixel size. The motivation to reduce the pixel size led to the development of pixels with vertically shifting gates.

[0003] Each pixel in a plurality of pixels includes a photodiode region, a floating diffusion region, and a transfer gate. The transfer gate controls the current from the photodiode region to the floating diffusion region and can be part of a field-effect transistor. The potential of the photodiode region exceeds the potential of the floating diffusion region. Light reaching the photodiode region generates photoelectrons. Turning on the transfer gate forms a conductive channel that allows accumulated photoelectrons to transfer from the photodiode region or flow to the floating diffusion region. When the transfer gate is pulsed to the off state, the potential barrier is higher than that of the photodiode region, thus preventing photoelectrons from flowing to the floating diffusion region.

[0004] In a common pixel architecture, the photodiode and floating diffusion region are laterally shifted within the pixel in a lateral direction parallel to a plane of the pixel array, with the transfer gate located between the photodiode and the floating diffusion region. This plane is horizontally oriented relative to a vertical direction that defines the direction in which vertically incident light (illumination) reaches the pixel array. This horizontal orientation limits how much pixel density can be increased. Therefore, one way to increase pixel density is to orient the photodiode, transfer gate, and floating diffusion in a direction with a vertical component. Such a transfer gate is an example of a vertical transfer gate. Summary of the Invention

[0005] While vertical transfer gates can increase pixel density, fabricating pixels with vertical transfer gates involves complex processing. The gate electrode material of the vertical transfer gate is located in a trench that must extend from the top surface of the pixel's semiconductor substrate to a depth of approximately 0.4 micrometers. This distance makes it challenging to form a sufficiently deep photodiode region via ion implantation from the top surface. When the trench is formed via reactive ion etching (RIE) or reactive ion sputtering (RIS), the surface features of its sidewalls and bottom surface cause electron transport hysteresis and dark current, resulting in image artifacts such as black spots and white pixels. The embodiments disclosed herein improve upon these problems.

[0006] In a first aspect, a method for forming a transfer gate includes (i) forming a dielectric pillar on a surface of a semiconductor substrate and (ii) growing an epitaxial layer around the dielectric pillar on the semiconductor substrate. The dielectric pillar has a pillar height exceeding the epitaxial layer height relative to the surface. The method further includes removing the dielectric pillar to create a trench in the epitaxial layer.

[0007] The trenches formed according to this method, rather than via RIE or RIS, do not have the aforementioned surface features that cause image artifacts. An additional advantage of this method is that the thickness of the epitaxial layer determines the trench depth. Since epitaxial growth can produce layers that meet strict thickness tolerances, the trench depth can also meet those tolerances.

[0008] In a second aspect, the pixel includes a doped semiconductor substrate. The doped semiconductor substrate has a front surface opposite to the back surface. The front surface is formed extending at a depth z relative to the front surface within the doped semiconductor substrate along a direction z perpendicular to both the front and back surfaces. T The trenches. Pixels have a doping concentration distribution, and the derivative of the doping concentration distribution with respect to the direction z is at depth z. T The points are discontinuous. Attached Figure Description

[0009] Figure 1 Describe the camera that images the scene.

[0010] Figure 2 This is a schematic cross-sectional view of a semiconductor substrate, which is... Figure 1 An example of a semiconductor substrate for a camera.

[0011] Figure 3 This is a circuit diagram for a four-transistor (“4T”) pixel. Figure 2 The candidate pixel circuit architecture for the pixel.

[0012] Figure 4 This is a cross-sectional view of a pixel in the embodiment, which is formed on... Figure 2 An example of a pixel in a semiconductor substrate.

[0013] Figure 5 This is a schematic cross-sectional view of a semiconductor substrate in the embodiment, which includes a photodiode portion embedded therein.

[0014] Figure 6 In the embodiments Figure 5 A schematic cross-section of a semiconductor substrate after an etch stop layer has been deposited on it.

[0015] Figure 7 This is a cross-sectional schematic diagram of the substrate assembly in the embodiment, which is formed after pillars are formed on the semiconductor substrate. Figure 6 The coated substrate.

[0016] Figure 8 In the embodiments Figure 7 A cross-sectional schematic diagram of the substrate assembly after the epitaxial growth of the epitaxial layer on the semiconductor substrate.

[0017] Figure 9 In the embodiments Figure 8 A cross-sectional schematic diagram of the substrate assembly after the doped regions have been implanted into the epitaxial layer and the semiconductor substrate.

[0018] Figure 10 In the embodiments Figure 9 Substrate components in removal Figure 7 A cross-sectional schematic diagram of a substrate assembly with trenches formed after the pillars are erected.

[0019] Figure 11 In the embodiments Figure 10 A cross-sectional schematic diagram of a trenched substrate assembly having a dielectric layer serving as a trench liner. Figure 10 The coated substrate.

[0020] Figure 12 This is a cross-sectional view of a pixel in the embodiment, showing the pixel after the trench is filled with the gate electrode. Figure 11 Trenched substrate assembly.

[0021] Figure 13 This is a schematic graph illustrating the dopant concentration as a function of depth in the illustrated embodiment.

[0022] Figure 14 This is a flowchart of a method for forming a vertical transfer gate in the illustrated embodiment. Detailed Implementation

[0023] Throughout this specification, references to "an example" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the invention. Therefore, the phrases "in an example" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same example. Furthermore, in one or more examples, particular features, structures, or characteristics may be combined in any suitable manner.

[0024] For ease of description, spatial relative terms such as “below,” “under,” “bottom,” “below,” “above,” “top,” etc., are used herein to describe the relationship of one element or feature to another element or feature(s), as shown in the figures. It will be understood that, in addition to the orientation depicted in the figures, spatial relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as “below,” “under,” or “below” other elements or features will be oriented as “above” other elements or features. Thus, the terms “below” and “below” can cover both orientations of above and below. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein will be interpreted accordingly. Furthermore, it will be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more intermediate layers.

[0025] The term "semiconductor substrate" can refer to a substrate formed using semiconductors such as silicon, silicon-germanium, germanium, gallium arsenide, and combinations thereof. The term "semiconductor substrate" can also refer to a substrate formed from one or more semiconductors that has undergone prior process steps to form regions and / or junctions within the substrate. Semiconductor substrates can also include various features such as doped and undoped semiconductors, epitaxial layers of silicon, and other semiconductor structures formed on the substrate.

[0026] Several terms within the field are used throughout this specification. These terms should have their general meaning within the field, unless explicitly defined herein or their context of use will otherwise clearly imply otherwise. It should be noted that element names and symbols are used interchangeably throughout this document (e.g., Si vs. silicon). However, they have the same meaning.

[0027] Figure 1 A camera 190 is depicted for imaging a scene. The camera 190 includes an image sensor 100, which includes a semiconductor substrate 110. The semiconductor substrate 110 may include at least one of silicon and germanium. The semiconductor substrate 110 includes a pixel array 112A. The image sensor 100 may be part of a chip-scale package or an on-board chip package.

[0028] Figure 2 This is a schematic cross-sectional view of semiconductor substrate 210, which is an example of semiconductor substrate 110 of image sensor 100. Figure 2 The cross-section shown is parallel to the plane formed by orthogonal directions 298X and 298Z (hereinafter referred to as the xz plane), which are orthogonal to direction 298Y. In this document, the xy plane is formed by orthogonal directions 298X and 298Y, and the plane parallel to the xy plane is referred to as the transverse plane. Unless otherwise stated, the height of an object in this document refers to the extent of the object in direction 298Z or 180° in the opposite direction. References to axes x, y, or z, or associated directions ±x, ±y, or ±z, refer to directions 298X, 298Y, and 298Z, respectively. Furthermore, in this document, the horizontal plane is parallel to the xy plane, the width refers to the object's extension in the y-direction, and the vertical refers to the z-direction.

[0029] Semiconductor substrate 210 has a bottom substrate surface 211 and a top substrate surface 219, each of which may be perpendicular to direction 298Z. Hereinafter, the top substrate surface 219 may be referred to as the front surface of semiconductor substrate 210, and the bottom substrate surface 211 may be referred to as the back surface of semiconductor substrate 210. Hereinafter, the top substrate surface 219 may be referred to as the unilluminated surface of semiconductor substrate 210, and the bottom substrate surface 211 opposite to the top substrate surface 219 may be referred to as the illuminated surface of semiconductor substrate 210. Semiconductor substrate 210 includes a plurality of pixels 212 forming a pixel array 212A, which is an example of pixel array 112A. The pixels 212 are arranged in multiple rows and multiple columns in directions 298X and 298Y, respectively. Pixel array 212A has a pixel pitch 213 in direction 298X. Pixel array 212A has a pitch P in direction 298Y, which in this embodiment is equal to the pixel pitch 213. y In this embodiment, the pixel pitch 213 is less than 1.1 μm; for example, the pixel pitch 213 can be equal to 0.9 μm.

[0030] Figure 3 This is a circuit diagram of a four-transistor (“4T”) pixel 290, which is a candidate pixel circuit architecture for pixel 212. Pixel 290 includes a photodiode PD, a transfer transistor TX, a reset transistor RST, a source follower transistor SF, and a row select transistor RS. Pixel 290 is electrically connected to bit line 202 of image sensor 100. It is best to refer to the following description simultaneously. Figure 2 and Figure 3 .

[0031] Each pixel 212 includes a corresponding photodiode region 240 of a corresponding photodiode PD, a vertical transfer gate 280 of a corresponding transfer transistor (e.g., transfer transistor TX), and a corresponding floating diffusion region 260. The photodiode region 240 of each pixel 212 is at least partially buried in the semiconductor substrate 210 and is configured to generate and accumulate charge in response to incident light (illumination) thereon, which enters, for example, from the bottom substrate surface 211 of the semiconductor substrate 210 (e.g., the back surface of the semiconductor substrate 210) during the integration period of the image sensor 100. The electrical connection from the photodiode region 240 to the floating diffusion region 260 depends on the voltage applied to the vertical transfer gate 280. For example, charge (e.g., photoelectrons) accumulated in photodiode region 240 (e.g., the source of transfer transistor TX) during the integration period of image sensor 100 can be selectively transferred to floating diffusion region 260 (e.g., the drain of transfer transistor TX), depending on, for example, the voltage applied to the vertical transfer gate 280 of the transfer transistor (e.g., transfer transistor TX) associated with pixel 212 during a subsequent charge transfer period. Photodiode region 240 can have various configurations, including pinned photodiode configurations and partially pinned photodiode configurations.

[0032] Each vertical transfer gate 280 of the transfer transistor (e.g., the vertical gate portion of the transfer transistor TX) is formed in a corresponding trench 220 formed by the top substrate surface 219. The trench 220 includes a side surface 219S and a bottom surface 219B.

[0033] In this embodiment, each pixel 212 is a four-transistor pixel or a 4T pixel, and also includes a reset transistor RST, a source follower transistor SF, and a row select transistor RS. The reset transistor RST is coupled between the power supply line and the floating diffusion region 260 to reset under the control of a reset signal during a reset period (e.g., discharging or charging the floating diffusion region 260 to a preset voltage, such as the power supply voltage V). DD The reset transistor RST is also coupled to the photodiode region 240 of the photodiode PD via the transfer transistor TX to selectively reset the reset photodiode region 240 to a preset voltage during the reset period. The floating diffusion region 260 is coupled to the gate of the source follower transistor SF. The source follower transistor SF is coupled between the power supply line and the row select transistor RS. The source follower transistor SF operates to output an image signal modulated based on the received voltage of the floating diffusion region 260, where the image signal corresponds to the amount of photoelectrons accumulated in the photodiode region 240 during the integration period at its gate. The row select transistor RS, under the control of the row select signal, selectively couples the output of the source follower transistor RS (e.g., the image signal) to the readout column line (e.g., bit line 202).

[0034] In operation, during the integration period (also known as the exposure or accumulation period) of the image sensor 100, the photodiode region 240 of the photodiode PD detects or absorbs light incident on the pixel 212, and the light generates charge. During the integration period, the transfer transistor TX is turned off, i.e., the vertical transfer gate 280 of the transfer transistor TX receives a cutoff signal (e.g., a negative bias voltage). The photogenerated charge accumulated in the photodiode region 240 indicates the amount of light incident on the photodiode region 240 of the photodiode PD. After the integration period, the transfer transistor TX forms a conductive channel along the vertical transfer gate structure formed near the photodiode region 240, and when a transfer signal (e.g., a positive bias voltage) is received at the vertical transfer gate 280, the photogenerated charge is transferred through the conductive channel to the floating diffusion region 260. The source follower transistor SF generates an image signal. The row selection transistor RS, coupled to the source follower transistor, then selectively reads the signal onto the column bit lines for subsequent image processing.

[0035] The disclosed vertical transfer gate structure can be applied to any of a variety of additional or alternative types of pixel cells, such as five-transistor pixel cells or six-transistor pixel cells and / or so on.

[0036] Figure 4 This is a cross-sectional view of pixel 400, used as an example of pixel 212. (The last sentence appears to be incomplete and possibly refers to a different topic.) Figure 2 A pixel 400 is formed in an example of a semiconductor substrate 410. The pixel 400 includes a trench 420 and a photodiode region 440 formed in the semiconductor substrate 410. In an embodiment, the pixel 400 includes at least one of a floating diffusion region 460, a gate electrode 425, and a dielectric layer 450 (e.g., a gate oxide layer). The dielectric layer 450 has a thickness 454 and may include at least one of a nitride material and an oxide material. In an embodiment, the thickness 454 is between 2 nanometers and 10 nanometers. The material constituting the gate electrode 425 may include at least one of polysilicon, a metal, and other conductive materials. The trench 420, the dielectric layer 450, and the gate electrode 425 together form a vertical transfer gate 480 of the transfer transistor of the pixel 400. The vertical transfer gate 480 is electrically connected to the photodiode region 440 and is Figure 2 Example of vertical transfer gate 280.

[0037] Semiconductor substrate 410 has a surface 419 forming a trench 420. Surface 419 includes a planar region 418 surrounding the trench 420. The trench 420 extends into the semiconductor substrate 410 to a trench depth 426 relative to the planar region 418. Surface 419 is an example of top substrate surface 219. Figure 4This represents the transverse plane 406 at a trench depth of 426 relative to the planar region 418.

[0038] In an embodiment, the trench depth 426 is between 0.1 micrometers and 0.9 micrometers. In at least one of directions 298X and 298Y, the trench 420 has a width 421 that can be between 50 nanometers and 0.3 micrometers. In an embodiment, the trench 420 has a non-uniform width between the planar region 418 and its bottom at the trench depth 426. Therefore, the width 421 can be the width of the trench 420 at a depth equal to approximately half the trench depth 426. In an embodiment, the trench 420 has a uniform width between the planar region 418 and its bottom at the trench depth 426. The semiconductor substrate 410 has as... Figure 2 An example of bottom substrate surface 211 is bottom substrate surface 411.

[0039] Photodiode region 440 is Figure 2 An example of a photodiode region 240 includes a bottom photodiode portion 441 below trench 420 and a top photodiode portion 445 adjacent to trench 420. The bottom photodiode portion 441 is formed at a photodiode depth 442 relative to planar region 418. The bottom photodiode portion 441 is adjacent to the top photodiode portion 445 at a horizontal plane 407 and extends away from planar region 418 toward bottom substrate surface 411. Horizontal plane 407 is perpendicular to direction 298Z. The top photodiode portion 445 is formed at a photodiode depth 443 relative to planar region 418, photodiode depth 443 being less than trench depth 426 and extending toward horizontal plane 407 toward bottom substrate surface 411. Depth 442 exceeds trench depth 426 by depth 432, and in this embodiment, depth 432 is between 30 nm and 300 nm.

[0040] In this embodiment, the semiconductor substrate 410 is p-type doped, the photodiode region 440 is n-type doped, and the floating diffusion region 460 is n-type doped. + Type doping. In an embodiment, the floating diffusion region 460 has 10 per cubic centimeter. 19 One charge carrier and 5 × 10⁵ per cubic centimeter 20 The doping concentration between charge carriers. A floating diffusion region 460 is formed at a junction depth 463 relative to the planar region 418, the junction depth 463 being smaller than the trench depth 426 and the photodiode depth 443. A dielectric layer 450 is disposed on the planar region 418 and in the trench 420, lining the sidewalls of the trench. The dielectric layer 450 has a top surface 459. In an embodiment, a portion of the gate electrode 425 is disposed on the top surface 459, such that photocurrent from the photodiode region 440 can reach the floating diffusion region 460.

[0041] Semiconductor substrate 410 has a bottom substrate surface (or bottom surface 411) opposite to a top substrate surface (or top surface) 419. Lateral plane 406 and bottom substrate surface 411 are separated by a distance 416, which in this embodiment is between 2.0 micrometers and 3.5 micrometers. In this embodiment, pixel 400 operates in image sensor 100 as a facing... Figure 1 The imaging lens of the camera 190 is one of a plurality of back-illuminated pixels in the pixel array 112A. Light transmitted through the imaging lens is incident on the bottom surface 411. Effective detection of this light depends on the proximity of the photodiode portion 441 to the bottom surface 411, and therefore also on the depth at which ions are implanted into the semiconductor substrate relative to the top surface 419.

[0042] Figure 5 This is a schematic cross-sectional view of a semiconductor substrate 510, which includes a photodiode portion 541 embedded therein. The semiconductor substrate 510 and the photodiode portion 541 are corresponding examples of the semiconductor substrate 410 and the photodiode portion 441, respectively. The semiconductor substrate 510 has a bottom substrate surface 511 and a top substrate surface 519, which are corresponding examples of the top substrate surface 411 and the bottom substrate surface 419 of the semiconductor substrate 410.

[0043] In this embodiment, at least a portion of the semiconductor substrate 510 is an epitaxial substrate, i.e., a layer or substrate formed via an epitaxial process. For example, the top surface 519 may be the top surface of the epitaxial layer; the bottom surface 511 may be the bottom surface of the epitaxial layer. The advantage of the top surface 519 being the top surface of the epitaxial layer is that it facilitates the formation of the epitaxial layer thereon, as discussed regarding... Figure 8 As described.

[0044] Figure 6 This is a schematic cross-sectional view of a coated substrate 600, which is a semiconductor substrate 510 on which an etch stop layer 630 has been deposited. In an embodiment, the etch stop layer 630 is formed of a high-k dielectric material and / or an oxide.

[0045] Figure 7 This is a schematic cross-sectional view of substrate assembly 700, which is a coated substrate 600 formed on semiconductor substrate 510 after pillars 740 are formed. Pillars 740 have a top surface 742 at a height 746 above the top surface 519 of semiconductor substrate 510. Pillars 740 may be formed of a dielectric.

[0046] In an embodiment, the pillar 740 is formed by: depositing a dielectric layer on the etch stop layer 630 using a process such as chemical vapor deposition, patterning the dielectric layer using photoresist, for example, by photolithography, and etching the patterned dielectric layer so that the pillar 740 is the remainder of the dielectric layer. The dielectric layer may have a thickness between 0.3 micrometers and 0.6 micrometers. In an embodiment, the substrate assembly 700 includes an etch stop layer 730, which is the remainder of the etch stop layer 630 after the dielectric layer and the etch stop layer 630 have been etched.

[0047] In this embodiment, a first patterning and etching process (e.g., dry etching or wet etching) is applied to etch the patterned dielectric layer. A second patterning and wet etching process using hydrofluoric acid (HF) etches the patterned etch stop layer 630 and cleans the silicon surface of the semiconductor substrate 510 without damaging the silicon surface. The first and second processes create pillars 740 on the etch stop layer 730. The location of the pillars 740 corresponds to the location of the vertical transfer gate of the transfer transistor (e.g., vertical transfer gate 480). The thickness or height of the pillars 740 corresponds to the depth of the vertical transfer gate into the semiconductor substrate 510.

[0048] In this embodiment, the etch selectivity of the dielectric forming pillar 740 exceeds the etch selectivity of the etch stop layer 630. The etch selectivity can be relative to the semiconductor substrate 510. That is, for a given etchant, the dielectric forming pillar 740 has an etch rate exceeding the etch rate of the etch stop layer 630, such that, in this embodiment, the semiconductor substrate 510 is not damaged while the dielectric layer is etched to form the pillar 740. This process may include reactive ion etching.

[0049] Figure 8This is a schematic cross-sectional view of substrate assembly 800, which is substrate assembly 700 formed after epitaxial growth of epitaxial layer 830 on semiconductor substrate 510. Epitaxial layer 830 may surround pillar 740 in a lateral plane. In an embodiment, epitaxial layer 830 and semiconductor substrate 510 are formed of the same material and have the same conductivity type, such that layer 830 is a homogeneous epitaxial layer relative to semiconductor substrate 510. Epitaxial layer 830 has a top surface 839 and sidewall surfaces 832 and 834 adjacent to pillar 740. Sidewall surfaces 832 and 834 may represent regions of continuous surfaces on opposite sides of pillar 740. Epitaxial layer 830 has a thickness 836 between top surfaces 519 and 839. In an embodiment, thickness 836 is between 0.1 micrometers and 0.9 micrometers. For example, thickness 836 may be between 0.3 micrometers and 0.6 micrometers. Height 746 extends beyond thickness 836 by a certain distance 837, for example, at least 10 nanometers. In this embodiment, the distance 837 is between 10 nanometers and 50 nanometers, which makes it possible to properly etch the pillars 740 to create trenches in the epitaxial layer 830, as described below.

[0050] Figure 9 This is a cross-sectional schematic diagram of substrate assembly 900, which is substrate assembly 800 after the doped region 945 is implanted into semiconductor substrate 510 and epitaxial layer 830. Doped region 945 is an example of top photodiode portion 445. Doped region 945 and photodiode portion 541 form photodiode region 940 (which is an example of photodiode region 440).

[0051] Figure 10 This is a cross-sectional schematic diagram of a trenched substrate assembly 1000, which is the substrate assembly 900 after removing the pillar 740 and the etch stop layer 730. Surfaces 832, 834 and the top surface 519 form a trench 1034. When the substrate assembly 800 does not include the etch stop layer 730, the trench 1034 has a trench depth equal to the thickness 836 of the epitaxial layer 830. Thus, the thickness 836 is... Figure 4 Example of a trench depth of 426.

[0052] Figure 11 This is a cross-sectional schematic diagram of a trenched substrate assembly 1100. The trenched substrate assembly 1100 is a trenched substrate assembly 1000 in which a dielectric layer 1150 is deposited on surfaces 839, 832, 834, and 519, making the dielectric layer 1150 a liner for trench 1034. The dielectric layer 1150 is an example of dielectric layer 450.

[0053] Figure 12This is a cross-sectional view of pixel 1200, which is a trenched substrate assembly 1100 after trench 1034 is filled with gate electrode 1225 (which is an example of gate electrode 425). Pixel 1200 is an example of pixel 400. Trench 1034, dielectric layer 1150, and gate electrode 1225 together form the vertical transfer gate 1280 of the transfer transistor of pixel 1200. The vertical transfer gate 1280 is electrically connected to photodiode region 440 and is Figure 4 Example of a vertical transfer gate 480. Dielectric layer 1150 has a top surface 1159.

[0054] Epitaxial layer 830 may include floating diffusion region 860 (which is Figure 4 (Example of floating diffusion region 460). In this embodiment, a portion of the gate electrode 1225 is disposed on the top surface 1159, such that photocurrent from the photodiode region 940 can reach the floating diffusion region 860.

[0055] Figure 12 This indicates the depth z below the top surface 839. T The plane at point 1206 has a depth of z. T It equals a thickness of 836. Figure 12 This represents the distance z3 between plane 1206 and the bottom substrate surface 511. Plane 1206 is... Figure 4 Example of plane 406.

[0056] Through the following about Figure 14 The distinguishing feature of the pixel 1200 manufactured by the discussed method 1400 is the doping concentration distribution ρ(z) along the z-direction. Since the implantation of the photodiode portion 541 occurs before the epitaxial growth of the epitaxial layer 830, the doping concentration distribution ρ(z) abruptly decreases at plane 1206, which is located at depth z relative to the top surface 839. T And it is located at a depth z3 relative to the bottom substrate surface 511. Plane 1206 corresponds to the surface plane of the epitaxial layer 830 or the interface between the epitaxial layer 830 and the semiconductor substrate 510. Depth z T The thickness 836 is equal to that of the epitaxial layer 830. The doping concentration distribution ρ(z) has a derivative with respect to z ρ′(z) = dρ(z) / dz. In the embodiment, ρ′(z) is at a depth z corresponding to depth z3. T The points are discontinuous.

[0057] Figure 13This is a schematic graph 1300 illustrating the doping concentration 1310 as a function of depth relative to the bottom substrate surface 511. The doping concentration 1310 is an illustrative example of the doping concentration distribution ρ(z). Graph 1300 represents depths z1, z2, and z3 relative to the bottom substrate surface 511, where z3 > z2 > z1 > z0 and z0 corresponds to the bottom substrate surface 511. The semiconductor substrate 510 is located between z0 and z3, with its top surface 519 at depth z3. The doping concentration 1300 increases between depths z1 and z2 and decreases between depths z2 and z3. Due to the reasons described above in the explanation of the doping concentration distribution ρ(z), the doping concentration 1300 drops abruptly at z3. Graph 1300 illustrates the doping concentration 1320 of a conventional pixel at depths exceeding z3, for example, in a conventional pixel where a photodiode portion is embedded between surfaces 418 and 411 of the semiconductor substrate 410. Figure 4 ), instead of from the top surface 519 ( Figure 5 At depth z3, due to the nature of the implantation distribution in the same material layer, the doping concentration 1320 and its derivative with respect to z are continuous with the doping concentration 1320 and its derivative, respectively.

[0058] Figure 14 This is a flowchart illustrating a method 1400 for forming a vertical transfer gate, such as a vertical transfer gate 1280. Method 1400 includes steps 1440, 1450, and 1480. In an embodiment, method 1400 further includes at least one of steps 1420, 1430, and 1460.

[0059] Step 1420 includes implanting a first doped region into the semiconductor substrate. The doped region may be formed of a dopant having a conductivity opposite to that of the semiconductor substrate. In an example of step 1420, when the top surface 519 has no layers such as an etch stop layer 630, a dielectric layer forming pillars 740, or an epitaxial layer 830 thereon, a photodiode portion 541 is implanted at the top substrate surface 519 of the semiconductor substrate 510 via an ion implantation process. The advantage of performing step 1420 is that the absence of additional layers allows the photodiode portion 541 to extend deeper into the semiconductor substrate, away from the top surface 519, i.e., away from the silicon oxide interface containing defect / trap sites that induce dark currents. Furthermore, the total well capacity of the corresponding photodiode can be increased by increasing the volume of the photodiode portion 541. An additional advantage of step 1420 is that the photodiode portion 541 can be formed closer to the bottom substrate surface 511, which allows for more efficient detection of light (illumination) incident on the bottom substrate surface 511.

[0060] Step 1430 includes depositing an etch stop layer on the semiconductor substrate, wherein the first etch selectivity of the etch stop layer exceeds the second etch selectivity of the dielectric pillar. In the example of step 1430, the etch stop layer 630 is deposited on the top surface 519. Figure 6 ).

[0061] Step 1440 includes forming dielectric pillars on the surface of the semiconductor substrate. For example, step 1440 may include depositing a dielectric material on an etch stop layer to form a dielectric layer, patterning the dielectric layer with a photoresist, and subsequently performing an etching process to remove portions of the dielectric layer and the etch stop layer to form a stack of dielectric pillars and the remaining (unetched) portions of the dielectric layer and the etch stop layer. In the example of step 1440, pillars 740 are formed on the top surface 519 of the semiconductor substrate 510. Figure 7 When method 1400 includes step 1430, pillars 740 are formed on etch stop layer 730.

[0062] Step 1450 includes growing an epitaxial layer around a dielectric pillar on a semiconductor substrate. The dielectric pillar has a pillar height exceeding the height of the epitaxial layer relative to the surface of the semiconductor substrate. In an example of step 1450, an epitaxial layer 830 is epitaxially grown on a semiconductor substrate 510. Figure 8 The epitaxial layer 830 can be grown on the semiconductor substrate 510 until its thickness 836 is 20 to 50 nanometers smaller than its height 746.

[0063] In an embodiment, step 1450 is performed after step 1420, such that the pixel produced by method 1400 has a doping concentration of 1310. Step 1440 may also be performed after 1420, because the presence of the pillar 740 produced by step 1440 may complicate the implantation process of step 1420.

[0064] Step 1460 includes embedding a second doped region into the epitaxial layer and the semiconductor substrate. In an example of step 1460, the doped region 945 ( Figure 9 It is implanted into the epitaxial layer 830 and the semiconductor substrate 510 via an ion implantation process.

[0065] Step 1480 includes removing the dielectric pillars. In an embodiment, the dielectric pillars are removed via a wet etching process. In an example of step 1480, the pillars 740 are removed from the substrate assembly 900. Figure 9 Remove to produce a trenched substrate assembly 1000. Figure 10 The trench 1034 is formed in the epitaxial layer. In an embodiment, step 1480 creates a trench in the epitaxial layer. For example, removing pillar 740 results in the formation of trench 1034 in the epitaxial layer 830.

[0066] In this embodiment, the top surface 519 is the bottom surface of the trench 1034. The photodiode portion 541 is located at a depth 1032 below the top substrate surface 519. Depth 1032 is Figure 4 An example of depth 432. Forming trench 1034 via removal of pillar 740 means that control of depth 1032 does not depend on the etch depth tolerance associated with the removal of semiconductor material (e.g., the semiconductor material of epitaxial layer 830). Instead, control of depth 1032 depends in part on the etch depth tolerance associated with the removal of pillar 740 and etch stop layer 730. Since etch stop layer 730 can be selected to have a slow etch rate, the depth of trench 1034, and therefore depth 1032, can be controlled more precisely compared to forming a similar trench by etching silicon.

[0067] Step 1480 may include at least one of steps 1482 and 1484. Step 1482 includes using a dielectric layer as a trench liner. In an example of step 1482, dielectric layer 1150 ( Figure 11 ) to be used as the inner lining of groove 1034.

[0068] Step 1484 includes filling the trench with gate electrode material. In an example of step 1484, the trench 1034 is filled with material constituting the gate electrode 1225, such that step 1484 produces pixel 1200.

[0069] Combination of features

[0070] The features described above and the features claimed below can be combined in various ways without departing from their scope. The following examples illustrate some possible non-limiting combinations:

[0071] (A1) A method for forming a transfer gate, comprising: (i) forming a dielectric pillar on a surface of a semiconductor substrate; and (ii) growing an epitaxial layer around the dielectric pillar on the semiconductor substrate. The dielectric pillar has a pillar height exceeding the epitaxial layer height relative to the surface. The method further comprises removing the dielectric pillar to create a trench in the epitaxial layer. The trench is formed according to this method, rather than via RIE or RIS, resulting in a trench free from the aforementioned surface features that cause image artifacts.

[0072] (A2) Method (A1) may also include filling the trench with a conductive material after removing the dielectric column.

[0073] (A3) Any method according to method (A1) or (A2) may also include lining the trench with a dielectric layer after removing the dielectric column.

[0074] (A4) Any of the methods in (A1)-(A3) may further include: implanting a first doped region into a semiconductor substrate prior to growing an epitaxial layer.

[0075] (A5) Method (A4) may also include implanting a second doped region into (i) a semiconductor substrate and (ii) an epitaxial layer adjacent to the trench.

[0076] (A6) In any method (A4) or (A5), removing the dielectric pillar to form a trench may include forming a direction z perpendicular to the positive surface of the semiconductor substrate and extending to a depth z relative to the positive surface of the semiconductor substrate. T The trench. The implanted first and second doped regions have doping concentration distributions. The derivative of the doping concentration distribution with respect to the z-direction at depth z. T The points are discontinuous.

[0077] (A7) In any of the methods (A1)-(A6), forming a dielectric pillar may include forming a dielectric layer on a semiconductor substrate, patterning the dielectric layer, and etching the patterned dielectric layer to form a dielectric pillar.

[0078] (A8) In method (A7), forming a dielectric layer may include depositing a dielectric material on a semiconductor substrate until the thickness of the dielectric material is between 0.3 micrometers and 0.6 micrometers.

[0079] (A9) In any of the methods (A7)-(A8), forming the dielectric pillar may further include depositing an etch stop layer on the semiconductor substrate prior to forming the dielectric layer.

[0080] (A10) In method (A9), forming a trench may include removing the area of ​​the etch stop layer between the dielectric pillar and the semiconductor substrate.

[0081] (A11) In any of the methods (A9)-(A10), the etch stop layer has an etch rate that is less than the etch rate of the dielectric layer.

[0082] (A12) In any of the methods (A1)-(A11), the dielectric pillar has a pillar height, and growing the epitaxial layer may include epitaxially growing the epitaxial layer until the pillar height exceeds the epitaxial layer height by 20 nanometers and 50 nanometers.

[0083] (A13) In any of the methods (A1)–(A12), forming a trench may include wet etching of the dielectric pillar.

[0084] (B1) The pixel includes a doped semiconductor substrate. The doped semiconductor substrate has a front surface opposite to the back surface. The front surface is formed extending at a depth z relative to the front surface within the doped semiconductor substrate along a direction z perpendicular to both the front and back surfaces. T The trenches. Pixels have a doping concentration distribution, and the derivative of the doping concentration distribution with respect to the direction z is at depth z.T The points are discontinuous.

[0085] (B2) Pixel (B1) may also include a gate dielectric layer serving as a trench liner, and a conductive material filling the trench to form a gate electrode for a transistor.

[0086] (B3) In any pixel (B1) or (B2), the doping concentration distribution can be associated with the photodiode region adjacent to the photodiode formed by the trench. The photodiode region is located at a certain distance from the positive surface.

[0087] (B4) In any of pixels (B1)-(B3), the photodiode region may include a top photodiode portion and a bottom photodiode portion adjacent to the top photodiode portion. The bottom photodiode portion is formed to extend away from the positive surface and is configured to accumulate photogenerated charge in response to incident illumination. The bottom photodiode portion may be located at a depth greater than z. T At that depth.

[0088] (B5) In any of the pixels (B1)-(B4), at least a portion of the gate electrode of the transistor may be formed on the positive surface above the photodiode region.

[0089] Any pixel in (B6) of pixels (B1)-(B5) may also include a floating diffusion region adjacent to the trench. The transistor is a transfer transistor coupled to the photodiode and the floating diffusion region, and selectively transfers photogenerated charge from the photodiode in response to incident illumination to the floating diffusion region.

[0090] Modifications to the methods and systems described above can be made without departing from the scope of these embodiments. Therefore, it should be noted that the content contained in the above description or shown in the accompanying drawings should be interpreted as illustrative rather than restrictive. In this document, unless otherwise stated, the phrase "in some embodiments" is equivalent to the phrase "in some embodiments" and does not refer to all embodiments. The appended claims are intended to cover all general and specific features described herein, as well as all statements regarding the scope of the methods and systems, and for linguistic purposes, they may be considered to be somewhere in between.

Claims

1. A method for forming a transfer gate, comprising: Dielectric pillars are formed on the surface of a semiconductor substrate; An epitaxial layer is grown around a dielectric pillar on a semiconductor substrate, the dielectric pillar having a pillar height exceeding the height of the epitaxial layer relative to the surface; as well as Remove dielectric pillars to create trenches in the epitaxial layer; The method further includes: Before growing the epitaxial layer, a first doped region is implanted into the semiconductor substrate; and The second doped region is implanted into (i) the semiconductor substrate and (ii) the epitaxial layer adjacent to the trench; The removal of dielectric pillars to form trenches includes: Formed along a direction perpendicular to the positive surface of the semiconductor substrate. Depth of extension relative to the positive surface of the semiconductor substrate The trench; wherein the implanted first and second doped regions have doping concentration distributions, the doping concentration distributions being relative to the orientation The derivative of the depth The points are discontinuous.

2. The method according to claim 1, further comprising: After removing the dielectric pillars, the trenches are filled with a conductive material.

3. The method according to claim 2, further comprising: After removing the dielectric pillars, a gate dielectric layer is used as the trench liner.

4. The method according to claim 1, wherein forming the dielectric pillar comprises: A dielectric layer is formed on a semiconductor substrate; Patterned dielectric layer; as well as Etch a patterned dielectric layer to form dielectric pillars.

5. The method of claim 4, wherein forming the dielectric layer comprises depositing a dielectric material on a semiconductor substrate until the thickness of the dielectric material is between 0.3 micrometers and 0.6 micrometers.

6. The method according to claim 4, further comprising forming the dielectric pillar: An etch stop layer is deposited on the semiconductor substrate before the dielectric layer is formed.

7. The method of claim 6, wherein forming the trench includes removing the etch stop layer in the region between the dielectric pillar and the semiconductor substrate.

8. The method of claim 6, wherein the etch stop layer has an etch rate less than that of the dielectric layer.

9. The method of claim 1, wherein the dielectric pillar has a pillar height and the epitaxial layer is grown comprising: Epitaxial layers are grown epitaxially until the column height exceeds the epitaxial layer height by 20 to 50 nanometers.

10. The method of claim 1, wherein forming the trench comprises wet etching the dielectric pillar.

11. A pixel, comprising: A doped semiconductor substrate has a front surface opposite a back surface and a doping concentration distribution. The front surface is formed along a direction z perpendicular to both the front and back surfaces, extending to a depth relative to the front surface within the doped semiconductor substrate. The trench, the derivative of the doping concentration distribution with respect to the direction z at depth Discontinuous at the point; The doping concentration distribution is associated with the photodiode region adjacent to the photodiode formed in the trench, and the photodiode region is located at a certain distance from the positive surface; The photodiode region further includes a top photodiode portion and a bottom photodiode portion adjacent to the top photodiode portion. The bottom photodiode portion extends away from the positive surface and is configured to accumulate photogenerated charge in response to incident illumination. The bottom photodiode portion is positioned at a depth greater than [the specified depth]. At that depth.

12. The pixel of claim 11, wherein the trench has a gate dielectric layer serving as a trench liner, and a conductive material filling the trench to form a gate electrode for a transistor.

13. The pixel of claim 11, wherein at least a portion of the gate electrode of the transistor is formed on the positive surface above the photodiode region.

14. The pixel of claim 11, further comprising: A floating diffusion zone is set adjacent to the trench; The transistor is a transfer transistor coupled to a photodiode and a floating diffusion region, and selectively transfers photogenerated charges from the photodiode to the floating diffusion region in response to incident illumination.

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