Display device

Abstract

A display device is provided. The display device includes: a circuit element layer disposed on a substrate; a first insulating layer disposed on the circuit element layer; a first conductor pattern disposed on the first insulating layer; a second insulating layer disposed on the first conductor pattern; a second conductor pattern disposed on the second insulating layer; a third insulating layer disposed on the second conductor pattern; an electrode for a light-emitting diode disposed on the third insulating layer; and a pixel-defining layer disposed on the third insulating layer and including an opening overlapping the electrode for the light-emitting diode. The opening overlaps the first conductor pattern, and in plan view, an area of ​​the opening matches an area of ​​the first conductor pattern or is disposed within the area of ​​the first conductor pattern.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0025353 filed on February 28, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a display device, and more particularly, to a light-emitting display device. Background Art

[0003] A display device, such as a light-emitting diode display, includes a display panel on which pixels for displaying an image are arranged. Each pixel may include a light-emitting diode (LED), a transistor and a capacitor for causing the LED to emit light at a predetermined brightness and in a predetermined sequence. Signal lines for applying or transmitting signals and / or voltages to the pixels are arranged in the display panel.

[0004] The higher the resolution of a display device, the more vivid and lively the image can be. To increase the display resolution, more pixels must be arranged in a limited area, so a design that can increase the integration of pixels and signal lines without interfering with other characteristics of the display device is required. Summary of the Invention

[0005] It may be advantageous to reduce the gaps between the wirings of a display device to increase the display resolution. The electrodes of the light-emitting diodes disposed within the light-emitting region of the pixel may overlap with conductor patterns such as wiring disposed thereunder. Due to the overlapping conductor patterns, it may be difficult to make the surface of the insulating layer between the electrodes and the conductor patterns flat. In the case where the insulating layer is uneven, the electrodes formed thereon may be uneven, so that in the case of incident external light, due to the curved (or uneven) electrodes, reflective color bands or stripes may be generated and visually identified. In the case where the polarizing layer is not used as an anti-reflection layer, color bands are more likely to be generated.

[0006] Embodiments of the present invention provide a display device that can prevent the generation of color bands or reduce the intensity of color bands if they are generated, without using a polarizing layer as an anti-reflection layer.

[0007] A display device according to an embodiment may include: a circuit element layer disposed on a substrate; a first insulating layer disposed on the circuit element layer; a first conductor pattern disposed on the first insulating layer; a second insulating layer disposed on the first conductor pattern; a second conductor pattern disposed on the second insulating layer; a third insulating layer disposed on the second conductor pattern; an electrode of a light-emitting diode disposed on the third insulating layer; and a pixel defining layer disposed on the third insulating layer and including an opening overlapping the electrode of the light-emitting diode. The opening overlaps the first conductor pattern, and in a plan view, an area of ​​the opening matches an area of ​​the first conductor pattern or is disposed within the area of ​​the first conductor pattern.

[0008] In a cross-sectional view, a width of the first conductor pattern may be equal to or greater than a width of the opening.

[0009] Each of the second insulating layer and the third insulating layer may include an organic insulating material.

[0010] The first insulating layer may include an inorganic insulating material.

[0011] The electrodes of the light emitting diode may be electrically connected to the second conductor pattern through the contact holes of the third insulating layer.

[0012] The display device may further include a data line disposed between the first insulating layer and the second insulating layer.

[0013] The display device may further include a driving voltage line disposed between the second insulating layer and the third insulating layer.

[0014] The display device may further include a light blocking member that does not overlap the opening of the pixel defining layer over the light emitting diode; and a color filter that overlaps the opening of the pixel defining layer over the light emitting diode.

[0015] The display device may further include an encapsulation layer disposed between the light emitting diode and the light blocking member.

[0016] The circuit element layer may include a plurality of transistors, and the plurality of transistors may include: a transistor including a polycrystalline semiconductor; and a transistor including an oxide semiconductor.

[0017] A display device according to an embodiment may include: a first insulating layer including an inorganic insulating material; a conductor pattern provided on the first insulating layer; a second insulating layer provided on the conductor pattern and including an organic insulating material; a connection electrode provided on the second insulating layer; a third insulating layer provided on the connection electrode and including an organic insulating material; a pixel electrode provided on the third insulating layer and electrically connected to the connection electrode through a contact hole of the third insulating layer; and a pixel defining layer provided on the third insulating layer and overlapping the pixel electrode. The entire opening overlaps the conductor pattern.

[0018] In a cross-sectional view, a width of the conductor pattern may be greater than a width of the opening.

[0019] At least two edges of the opening and at least two edges of the conductor pattern may be aligned with each other.

[0020] The display device may further include: a data line disposed between the first insulating layer and the second insulating layer; and a driving voltage line disposed between the second insulating layer and the third insulating layer.

[0021] The display device may further include: a common electrode disposed on the pixel defining layer; an encapsulation layer disposed on the common electrode; and a light blocking member and a color filter disposed on the encapsulation layer.

[0022] The display device may further include a touch sensor layer disposed between the encapsulation layer and the light blocking member.

[0023] A display device according to an embodiment may include: a circuit element layer disposed on a substrate; a first insulating layer disposed on the circuit element layer; a connecting member disposed on the first insulating layer; a second insulating layer disposed on the connecting member; a third insulating layer disposed on the second insulating layer; an electrode of a light-emitting diode disposed on the third insulating layer; and a pixel defining layer disposed on the third insulating layer and including an opening overlapping the electrode of the light-emitting diode. The electrode of the light-emitting diode may be electrically connected to the connecting member via a first contact hole in the third insulating layer and a second contact hole in the second insulating layer. The width of the first contact hole may be greater than the width of the second contact hole in a direction intersecting the second contact hole and the opening.

[0024] The first contact hole and the second contact hole may be asymmetric with respect to the connection member in a direction crossing the second contact hole and the opening.

[0025] The electrode of the light emitting diode may include a first portion overlapping the opening and a second portion extending from the first portion toward the connection member, and the second portion of the electrode may include a portion contacting a top surface of the second insulating layer.

[0026] Each of the second insulating layer and the third insulating layer may include an organic insulating material.

[0027] According to the embodiment, the generation of the reflective color band can be prevented or the intensity of the color band can be reduced, thereby preventing the color band from being visually recognized. In addition, the embodiment can provide a recognizable effect throughout the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Additional understandings according to embodiments of the present invention will become more apparent by describing in detail embodiments of the present invention with reference to the accompanying drawings, in which:

[0029] Figure 1is a schematic plan view showing a display device according to an embodiment;

[0030] Figure 2 is a schematic plan view of approximately one pixel region in a display region according to an embodiment;

[0031] Figure 3 It is along Figure 2 A schematic cross-sectional view taken along line AA';

[0032] Figure 4 is a schematic plan view of approximately one pixel region in the display device according to the embodiment;

[0033] Figure 5 It is along Figure 4 A schematic cross-sectional view taken along line BB';

[0034] Figure 6 is a schematic plan view of approximately one pixel region in the display device according to the embodiment;

[0035] Figure 7 It is along Figure 6 A schematic cross-sectional view taken along line CC';

[0036] Figure 8 It is along Figure 6 A schematic cross-sectional view taken along line D-D';

[0037] Figure 9 is an equivalent circuit diagram of a pixel of a display device according to an embodiment; and

[0038] Figure 10 is a schematic cross-sectional view of a display device according to an embodiment. DETAILED DESCRIPTION

[0039] Hereinafter, embodiments of the invention will be described with reference to the accompanying drawings. Although the invention can be modified in various ways and have additional embodiments, the embodiments are shown in the drawings and will be described in the specification. However, the scope of the invention is not limited to the embodiments shown in the drawings and the specification, and should be interpreted as including all changes, equivalents, and alternatives included in the spirit and scope of the invention.

[0040] In the drawings, the sizes and thicknesses of elements may be exaggerated for clarity and ease of description. However, the invention is not limited to the sizes and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, and other elements may be exaggerated for clarity. In the drawings, the thicknesses of some layers and regions may be exaggerated for better understanding and ease of description.

[0041] Furthermore, in the specification, the phrase “in a plan view” means when a target portion is viewed from above, and the phrase “in a cross-sectional view” means when a cross section taken by vertically cutting the target portion is viewed from the side.

[0042] When a layer, film, zone, substrate or region is referred to as being "on" another layer, film, zone, substrate or region, the layer, film, zone, substrate or region may be directly on the other layer, film, zone, substrate or region, or an intermediate layer, film, zone, substrate or region may be present therebetween. In addition, when a layer, film, zone, substrate or region is referred to as being "below" another layer, film, zone, substrate or region, the layer, film, zone, substrate or region may be directly below the other layer, film, zone, substrate or region, or an intermediate layer, film, zone, substrate or region may be present therebetween. In addition, "on ..." or "on ..." may include positioning on or below a target and does not necessarily mean a direction based on gravity.

[0043] The term "overlying" as used herein may include layer, stacked, facing or variations thereof, extending over, covering or partially covering, or any other suitable term as would be appreciated and understood by one of ordinary skill in the art. The term "non-overlying" as used herein may include "spaced apart from" or "separated from" or "offset from" and any other suitable equivalents as would be appreciated and understood by one of ordinary skill in the art.

[0044] Throughout this specification, when an element is referred to as being “connected” to another element, the element may be “directly connected” to the other element, or “electrically connected” to the other element with one or more intermediate elements interposed therebetween. It will also be understood that when the terms “comprise” and variations thereof, “include” and / or variations thereof are used in this specification, they or it may specify the presence of stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components and / or any combination thereof.

[0045] In the drawings, labels x, y, and z are used to indicate directions, with x being a first direction, y being a second direction perpendicular to the first direction, and z being a third direction perpendicular to the first and second directions.

[0046] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another or to facilitate description and explanation thereof. For example, when a "first hole" is discussed in the specification, it may also be referred to as a "second hole" or a "third hole" in the claims without departing from the teachings herein, and the "second hole" and "third hole" may be named in a similar manner.

[0047] Figure 1 is a schematic plan view showing a display device according to an embodiment.

[0048] Reference Figure 1 The display device includes a display panel 10. The display panel 10 includes a display area DA for displaying an image and a non-display area NA. The non-display area NA is disposed at the periphery of the display area DA, and elements and / or signal lines for generating and / or transmitting various signals applied to the display area DA are arranged in the non-display area NA. The display area DA may be within a boundary line BL indicated by a dotted line, while the non-display area NA may be outside the boundary line BL. The display area DA may correspond to a screen.

[0049] A plurality of pixels PX may be arranged in a matrix form in the display area DA of the display panel 10. Signal lines such as data lines DL, gate lines GL, etc. may also be provided within the display area DA. The gate lines GL may extend approximately along a first direction x (e.g., a row direction), and the data lines DL may extend approximately along a second direction y (e.g., a column direction). Each pixel PX is electrically connected to the gate lines GL and the data lines DL, and may therefore receive a gate signal (also referred to as a scan signal) and a data voltage (also referred to as a data signal) from the gate lines GL and the data lines DL. A driving voltage line VL1 that transmits a driving voltage to the pixel PX and an initialization voltage line VL2 that transmits an initialization voltage to the pixel PX may be arranged in the display area DA. The driving voltage line VL1 may extend approximately along the second direction y. The initialization voltage line VL2 may extend approximately along the first direction x.

[0050] The display panel 10 may include a touch sensor layer in which touch electrodes are arranged for sensing a contact touch or a non-contact touch of a user. The touch electrodes may be mainly provided inside the display area DA.

[0051] A pad portion (also referred to as a "pad" or "solder pad") may be provided inside the non-display area NA of the display panel 10. The pad portion may include a pad for receiving a signal from outside the display panel 10. The display device may include a flexible printed circuit film 20, one end of which is connected (e.g., bonded) to the pad portion of the display panel 10. The other end of the flexible printed circuit film 20 may be connected to a printed circuit board or the like and thus may receive a signal (such as image data) and a power voltage (such as a driving voltage, a common voltage, etc.).

[0052] A driving device that generates and / or processes various signals for driving the display panel 10 may be provided inside the non-display area NA or may be provided in / on the flexible printed circuit film 20 connected to the pad portion. The driving device may include a data driver that applies a data voltage to the data line DL, a gate driver that applies a gate signal to the gate line GL, and a signal controller that controls the data driver, the scan driver, or the gate driver.

[0053] The gate driver may be integrated into the non-display area NA of the display panel 10 as drive circuits 40a and 40b. The drive circuits 40a and 40b may include a drive circuit 40a disposed on one side of the display area DA and a drive circuit 40b disposed on the other side of the display area DA, and may extend along the second direction y. The drive circuits 40a and 40b may be electrically connected to the gate lines GL. The drive circuits 40a and 40b may include a shift register including sequentially subordinately connected stages, and each stage may include a transistor and a capacitor. Each stage may generate and output a gate signal.

[0054] The data driver and the signal controller may be provided as an IC chip 30. The IC chip 30 may be disposed inside the non-display area NA of the display panel 10. The IC chip 30 may be positioned in the flexible printed circuit film 20. The data driver and the signal controller may be formed as a single chip or separate chips.

[0055] Figure 2 is a schematic plan view of approximately one pixel region in a display region according to an embodiment, and Figure 3 It is along Figure 2 In order to provide an easily understood drawing, some elements that may be provided inside one pixel region are omitted.

[0056] Reference Figure 2 and Figure 3 , the pixels PX provided in the display panel 10 can display one of the primary colors. The primary colors may be red, green, and blue. A combination of red pixels, green pixels, and blue pixels may be arranged in the display panel 10. The display panel 10 may have a structure in which a plurality of layers, wirings, and elements for forming and driving the pixels PX are stacked.

[0057] The substrate SB may be formed of an insulating material such as plastic, glass, etc. The substrate SB may include one or more barrier layers for preventing moisture from penetrating from the outside. The barrier layer may include a silicon oxide (SiO x ), silicon nitride (SiN x ) and other inorganic insulating materials.

[0058] A circuit element layer CEL including circuit elements such as transistors and capacitors for driving the pixels PX may be provided on the substrate SB. Although a single circuit element layer CEL is shown, the circuit element layer CEL may include conductive layers, semiconductor layers, and insulating layers for forming transistors and capacitors.

[0059] The first insulating layer ILa may be provided on the circuit element layer CEL. The first insulating layer ILa may include silicon nitride (SiN x ), silicon oxide (SiO x ) etc. The first insulating layer ILa may be referred to as an interlayer insulating layer.

[0060] A first data conductive layer including a connection member CM and a conductor pattern CP (also referred to as a first conductor pattern) may be disposed on the first insulating layer ILa. The conductor pattern CP may be a wiring electrically connecting circuit elements disposed in the circuit element layer CEL. The conductor pattern CP may be a signal line such as a data line.

[0061] The second insulating layer ILb may be disposed on the first data conductive layer. The second insulating layer ILb may be referred to as a first planarization layer.

[0062] A second data conductive layer including a conductor pattern (also referred to as a second conductor pattern) such as a connection electrode LE may be disposed on the second insulating layer ILb. The connection electrode LE may be electrically connected to the connection member CM through a contact hole of the second insulating layer ILb.

[0063] A third insulating layer ILc may be disposed on the second data conductive layer. The third insulating layer ILc may be referred to as a second planarization layer.

[0064] The first and second data conductive layers may include metals such as aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), and tantalum (Ta). The first and second data conductive layers may include one or more metal layers.

[0065] The second insulating layer ILb and the third insulating layer ILc may include an organic insulating material such as polyimide, acrylic polymer, siloxane polymer, or the like.

[0066] The first electrode E1 of the light-emitting diode LED may be disposed on the third insulating layer ILc. The first electrode E1 may be electrically connected to the connection electrode LE through a contact hole H1 of the third insulating layer ILc. The first electrode E1 may include a metal or metal alloy such as silver (Ag), nickel (Ni), gold (Au), platinum (Pt), aluminum (Al), copper (Cu), aluminum neodymium (AlNd), and aluminum nickel lanthanum (AlNiLa). The first electrode E1 may include a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The first electrode E1 may be referred to as a pixel electrode.

[0067] A pixel defining layer (PDL) including an opening OP overlapping the first electrode E1 may be disposed on the third insulating layer ILc. The pixel defining layer (PDL) may include an organic insulating material such as polyimide, polyacrylate, or polyamide. The pixel defining layer (PDL) may be a black pixel defining layer formed by patterning a black photoresist. The pixel defining layer (PDL) may include a black dye or pigment to improve contrast.

[0068] The opening OP of the pixel defining layer PDL may define an area corresponding to the light emitting area of ​​the pixel PX. For example, the opening OP and the light emitting area may be substantially identical to each other. Although the opening OP is formed in a rhombus shape, the opening OP may have various shapes such as a quadrilateral, a polygon, a circle, an ellipse, etc.

[0069] The entire area of ​​the opening OP may overlap with the conductor pattern CP. In a plan view, the area of ​​the opening OP may be substantially equal to the area of ​​the conductor pattern CP or may be provided inside the area of ​​the conductor pattern CP. At least two edges of the opening OP and at least two edges of the conductor pattern CP may be substantially aligned with each other (or, substantially parallel to each other or substantially matching each other). Except for the extension direction of the conductor pattern CP, the width of the conductor pattern CP corresponding to the width of the opening OP may be substantially the same. For such a structure, the conductor pattern CP overlapping with the opening OP may be formed into a shape and area corresponding to the shape and area of ​​the opening OP, respectively. Although in Figure 2 A portion of the middle conductor pattern CP not overlapping the opening OP extends in the second direction y, but in an embodiment, the portion may extend in a direction different from the second direction y or in at least two directions.

[0070] If only a portion of the opening OP overlaps the conductor pattern CP, the second insulating layer ILb and the third insulating layer ILc may be uneven in the area of ​​the opening OP, which serves as the light-emitting area. Consequently, the first electrode E1 disposed on the third insulating layer ILc may be uneven. If the first electrode E1 is uneven, when external light enters the display panel 10, color bands such as green and magenta may appear at the edge of the incident area. In a structure that prevents external light reflection by using a light blocking member BM and a color filter CF rather than a polarizing layer as an anti-reflection layer, reflective color bands may be problematic. In the area where the opening OP and the conductor pattern CP overlap, the flatness of the first electrode E1 in the light-emitting area can be improved by forming and disposing the conductor pattern CP corresponding to the opening OP, thereby preventing the generation of reflective color bands or reducing the intensity of the reflective color bands. Furthermore, the flat area of ​​the second insulating layer ILb and the third insulating layer ILc, which improves the flatness of the light-emitting area, can be reduced, and the second insulating layer ILb and / or the third insulating layer ILc can be formed thinner.

[0071] Such a relationship between the opening OP and the conductor pattern CP can be applied regardless of the color of the pixel PX. However, in the case of a green pixel in which a light-emitting area smaller than that of a red pixel or a blue pixel is formed, the opening OP and the conductor pattern CP may be designed not to overlap.

[0072] The emission layer EL of the light emitting diode LED may be disposed on the first electrode E1, and the second electrode E2 of the light emitting diode LED may be disposed on the emission layer EL. The second electrode E2 may also be referred to as a common electrode.

[0073] The first electrode E1 may be an anode serving as a hole injection electrode, and the second electrode E2 may be a cathode serving as an electron injection electrode. Holes and electrons are injected into the emission layer EL from the first electrode E1 and the second electrode E2, respectively. When excitons, which are bound to the injected hole-electron pairs, drop from an excited state to a ground state, they may emit light.

[0074] An encapsulation layer EN protecting the light emitting diode LED may be disposed on the second electrode E2. The encapsulation layer EN may be a thin film encapsulation layer having a structure in which an organic insulating layer is disposed between inorganic insulating layers.

[0075] The touch sensor layer TSL may be disposed on the encapsulation layer EN. The touch electrodes of the touch sensor layer TSL may be formed in a mesh structure having openings overlapping the openings OP of the pixel defining layer PDL.

[0076] A light blocking member BM may be provided on the touch sensor layer TSL. The light blocking member BM may include a black dye or pigment and may reduce or prevent light reflection caused by a metal layer of the display panel 10, etc. The light blocking member BM may be provided on a portion that does not overlap the opening OP, which serves as the light emitting area. The light blocking member BM may also be referred to as a black matrix.

[0077] A color filter CF may be provided on the touch sensor layer TSL. The color filter CF may transmit one of red, green, and blue. The color filter CF displaying different colors may overlap with the light blocking member BM and the opening OP of the pixel defining layer PDL. The combination of the color filter CF and the light blocking member BM may function as an anti-reflection layer. In such a structure, a polarizing layer may not be required as an anti-reflection layer, and thus the thickness of the display panel 10 may be reduced. The color filter CF may include quantum dots or phosphors and may convert the color of light emitted from the light emitting diode LED into red or green.

[0078] An overcoat OC may be disposed on the color filter CF.

[0079] Figure 4 is a schematic plan view of approximately one pixel region in the display device according to the embodiment, and Figure 5 It is along Figure 4 A schematic cross-sectional view taken along line BB'.

[0080] Reference Figure 4 and Figure 5 , the entire opening OP can be overlapped with the conductor pattern CP, and in a plan view, the opening OP can be arranged inside the area of ​​the conductor pattern CP. In all directions, the width of the conductor pattern CP can be greater than the width of the corresponding opening OP. For such a structure, the conductor pattern CP overlapping with the opening OP can be formed into a shape corresponding to the opening OP and can have an area wider than the area of ​​the opening OP. In the case where the conductor pattern CP does not interfere with other wiring between the first insulating layer ILa and the second insulating layer ILb, it can be advantageous to form the conductor pattern CP to be wider. For example, by using a wider conductor pattern CP, the flatness of the first electrode E1 can be improved not only in the light-emitting area but also in the vicinity of the light-emitting area. Therefore, it can more effectively prevent the generation of reflective color bands. It is also possible to increase the process margin for overlapping with the opening OP.

[0081] Figure 6 is a schematic plan view of approximately one pixel region in a display device according to an embodiment, Figure 7 It is along Figure 6 A schematic cross-sectional view taken along line CC' of FIG. Figure 8 It is along Figure 6 A schematic cross-sectional view taken along line DD'.

[0082] Reference Figure 6 、 Figure 7 and Figure 8 The first electrode E1 of the light emitting diode LED may be electrically connected to the connection member CM through the contact hole H2 of the second insulating layer ILb and the contact hole H3 of the third insulating layer ILc. The connection member CM may be a first data conductive layer disposed between the first insulating layer ILa and the second insulating layer ILb.

[0083] In the area overlapping with the connecting member CM, the contact hole H2 of the second insulating layer ILb and the contact hole H3 of the third insulating layer ILc may have substantially the same width. The contact hole H3 of the third insulating layer ILc may be formed wide toward the opening OP of the pixel defining layer PDL. In the direction crossing the contact hole H2 of the second insulating layer ILb and the opening OP of the pixel defining layer PDL, the width of the contact hole H3 may be greater than the width of the contact hole H2. In the direction crossing the contact hole H2 of the second insulating layer ILb and the opening OP of the pixel defining layer PDL, the contact hole H2 of the second insulating layer ILb and the contact hole H3 of the third insulating layer ILc may be asymmetric relative to the connecting member CM. As Figure 6 As shown in FIG, one edge of the contact hole H3 of the third insulating layer ILc may be adjacent to the opening OP of the pixel defining layer PDL, or may contact or nearly contact the opening OP of the pixel defining layer PDL.

[0084] The first electrode E1, including a portion disposed in the opening OP serving as the light-emitting region, includes an extension portion extending from the light-emitting region toward the connecting member CM to connect to the connecting member CM. However, in the case where the extension portion is disposed on the third insulating layer ILc, the extension portion may be formed to be inclined toward the connecting member CM rather than parallel to the plane of the substrate SB. This is because the third insulating layer ILc may be inclined toward the contact hole H2 (not shown). Depending on the color of the pixel, the distance between the light-emitting region and the connecting member CM and / or the inclination of the extension portion of the first electrode E1 of the pixel may vary. For example, in the case where the distance between the light-emitting region of the pixel and the connecting member CM is large, the inclination of the extension portion of the first electrode of the pixel may be large, and such an inclination may result in the generation of color bands having colors such as green and magenta at the edges of the region where external light is incident.

[0085] In the illustrated embodiment, a portion of the third insulating layer ILc that may be disposed between the contact hole H2 of the second insulating layer ILb and the opening OP of the pixel defining layer PDL is removed (i.e., the contact hole H3 of the third insulating layer ILc is formed wide toward the opening OP of the pixel defining layer PDL), so that the extended portion of the first electrode E1 may be formed to be primarily positioned directly on the second insulating layer ILb rather than on the third insulating layer ILc. Consequently, the length of the extended portion may be reduced, or the inclination of the inclined portion in the extended portion may be reduced, or the generation of color banding may be prevented or reduced.

[0086] Although not shown, the encapsulation layer EN, the touch sensor layer TSL, the light blocking member BM, the color filter CF, and the overcoat OC stated above may be further entirely or selectively disposed on the light emitting diode LED.

[0087] Figure 9 is an equivalent circuit diagram of a pixel of a display device according to an embodiment.

[0088] The pixel PX may include transistors T1 to T7 electrically connected to the signal lines GL1 to GL5 , DL, and VL1 to VL3 , a storage capacitor Cst, a boost capacitor Cbs, and a light emitting diode LED.

[0089] The signal lines GL1 to GL5, DL, and VL1 to VL3 may include gate lines GL1 to GL5, data lines DL, and voltage lines VL1 to VL3. The gate lines GL1 to GL5 may be electrically connected to a gate driver, and the data lines DL may be electrically connected to a data driver. The gate lines GL1 to GL5 may include a scan line GL1, an inverted scan line GL2, an initialization control line GL3, a bypass control line GL4, and a light emitting control line GL5. The voltage lines VL1 to VL3 may include a driving voltage line VL1, an initialization voltage line VL2, and a common voltage line VL3. The driving voltage line VL1, the initialization voltage line VL2, and the common voltage line VL3 may each be connected to a voltage generator.

[0090] The second to seventh transistors T2 to T7 may receive gate signals from the gate lines GL1 to GL5 , respectively.

[0091] The scan line GL1 can transmit a scan signal GW to the second transistor T2. The inverted scan line GL2 can transmit an inverted scan signal GC to the third transistor T3. The scan signal GW and the inverted scan signal GC can have opposite polarities. For example, when a high voltage is applied to the scan line GL1, a low voltage can be applied to the inverted scan line GL2.

[0092] The initialization control line GL3 can transmit an initialization control signal GI to the fourth transistor T4. The bypass control line GL4 can transmit a bypass signal GB to the seventh transistor T7. The bypass control line GL4 can be a scan line GL1 electrically connected to adjacent pixels PX along the second direction y. The emission control line GL5 can transmit an emission control signal EM to the fifth transistor T5 and the sixth transistor T6.

[0093] The data line DL can transmit a data voltage Vdat. The driving voltage line VL1 can transmit a driving voltage ELVDD, the initialization voltage line VL2 can transmit an initialization voltage Vint, and the common voltage line VL3 can transmit a common voltage ELVSS. The brightness of the light-emitting diode LED can be adjusted based on the magnitude of the data voltage Vdat applied to the pixel PX. The driving voltage ELVDD, the initialization voltage Vint, and the common voltage ELVSS can each be a DC voltage having a predetermined level.

[0094] Regarding transistors T1 to T7, the first transistor T1, serving as a driving transistor, may be a P-type transistor and may include a polycrystalline semiconductor. The first transistor T1 controls the magnitude of the driving current output to the anode of the light-emitting diode LED based on a data voltage Vdat applied to the gate electrode of the first transistor T1. The gate electrode of the first transistor T1 is electrically connected to the first electrode of the storage capacitor Cst. The source electrode of the first transistor T1 is electrically connected to the drain electrode of the second transistor T2 and to the driving voltage line VL1 via the fifth transistor T5. The drain electrode of the first transistor T1 is electrically connected to the anode of the light-emitting diode LED via the sixth transistor T6.

[0095] The second transistor T2, serving as a switching transistor, may be a P-type transistor and may include a polycrystalline semiconductor. The gate electrode of the second transistor T2 is electrically connected to the scan line GL1 and to the first electrode of the boost capacitor Cbs. The source electrode of the second transistor T2 is electrically connected to the data line DL, and the drain electrode of the second transistor T2 is electrically connected to the source electrode of the first transistor T1. When the second transistor T2 is turned on by the gate-on voltage (low voltage) of the scan signal GW transmitted via the scan line GL1, the data voltage Vdat transmitted via the data line DL can be transmitted to the source electrode of the first transistor T1.

[0096] The third transistor T3, serving as a compensation transistor, can be an N-type transistor and may include an oxide semiconductor. The third transistor T3 can electrically connect the drain and gate electrodes of the first transistor T1. Therefore, the data voltage Vdat is converted to a compensation voltage by the first transistor T1, which can be transmitted to the first electrode of the storage capacitor Cst. The gate electrode of the third transistor T3 is electrically connected to the inverting scan line GL2, and the source electrode of the third transistor T3 is electrically connected to the drain electrode of the first transistor T1. The drain electrode of the third transistor T3 is electrically connected to the first electrode of the storage capacitor Cst, the gate electrode of the first transistor T1, and the second electrode of the boost capacitor Cbs. When the third transistor T3 is turned on by the gate-on voltage of the inverting scan signal GC transmitted via the inverting scan line GL2, the third transistor T3 electrically connects the gate and drain electrodes of the first transistor T1. The voltage applied to the gate electrode of the first transistor T1 is stored in the storage capacitor Cst, which can maintain a constant voltage at the gate electrode of the first transistor T1 for a period of time.

[0097] The fourth transistor T4 as an initialization transistor can be an N-type transistor and can include an oxide semiconductor. The gate electrode of the fourth transistor T4 is electrically connected to the initialization control line GL3. The fourth transistor T4 can initialize the gate electrode of the first transistor T1 and the first electrode of the storage capacitor Cst using the initialization voltage Vint. The gate electrode of the fourth transistor T4 is electrically connected to the initialization control line GL3, and the source electrode of the fourth transistor T4 is electrically connected to the initialization voltage line VL2. The drain electrode of the fourth transistor T4 is electrically connected to the first electrode of the storage capacitor Cst, the gate electrode of the first transistor T1, and the second electrode of the boost capacitor Cbs. The fourth transistor T4 is turned on due to the gate-on voltage (high voltage) of the initialization control signal GI transmitted through the initialization control line GL3, and thus the initialization voltage Vint can be transmitted to the gate electrode of the first transistor T1 and the first electrode of the storage capacitor Cst.

[0098] The fifth transistor T5, serving as an operation control transistor, may be a P-type transistor and may include a polycrystalline semiconductor. The fifth transistor T5 may transmit the driving voltage ELVDD to the first transistor T1. The gate electrode of the fifth transistor T5 is electrically connected to the light emission control line GL5, the source electrode of the fifth transistor T5 is electrically connected to the driving voltage line VL1, and the drain electrode of the fifth transistor T5 is electrically connected to the source electrode of the first transistor T1. The sixth transistor T6, serving as a light emission control transistor, may be a P-type transistor and may include a polycrystalline semiconductor. The sixth transistor T6 may transmit the driving current output from the first transistor T1 to the light emitting diode LED. The gate electrode of the sixth transistor T6 is electrically connected to the light emission control line GL5, the source electrode of the sixth transistor T6 is electrically connected to the drain electrode of the first transistor T1, and the drain electrode of the sixth transistor T6 is electrically connected to the anode of the light emitting diode LED.

[0099] The seventh transistor T7, serving as a bypass transistor, may be a P-type transistor and may include a polycrystalline semiconductor. The seventh transistor T7 may initialize the anode of the light-emitting diode LED. The gate electrode of the seventh transistor T7 is electrically connected to the bypass control line GL4, the source electrode of the seventh transistor T7 is electrically connected to the anode of the light-emitting diode LED, and the drain electrode of the seventh transistor T7 is electrically connected to the initialization voltage line VL2. When the seventh transistor T7 is turned on by the gate-on voltage (low voltage) of the bypass signal GB, the initialization voltage Vint may be applied to the anode of the light-emitting diode LED.

[0100] A second electrode of the storage capacitor Cst is electrically connected to the driving voltage line VL1, and a cathode of the light emitting diode LED is electrically connected to a common voltage line VL3 transmitting a common voltage ELVSS.

[0101] As described above, the first transistor T1 may include a polycrystalline semiconductor, and the third transistor T3 and the fourth transistor T4 may include an oxide semiconductor. The second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include a polycrystalline semiconductor. Therefore, the first transistor T1 can have a high electron mobility and reduce the leakage current of the third transistor T3 and the fourth transistor T4. As described above, the third transistor T3 and the fourth transistor T4 include a semiconductor material different from the semiconductor material of the first transistor T1, so that more stable performance can be provided and reliability can be improved. At least one of the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include an oxide semiconductor.

[0102] When a high voltage is applied to the scan line GL1, a low voltage can be applied to the inverted scan line GL2. When a low voltage is applied to the scan line GL1, a high voltage can be applied to the inverted scan line GL2. Since the inverted scan signal GC applied to the inverted scan line GL2 is a signal with a phase opposite to the scan signal GW, the gate voltage of the first transistor T1 can decrease after the data voltage Vdat is input. Conversely, the scan signal GW can increase the gate voltage of the first transistor T1. Therefore, when the data voltage Vdat representing black is input, the gate voltage of the first transistor T1 can decrease. Since the boost capacitor Cbs is provided between the scan line GL1 and the gate electrode of the first transistor T1, the gate voltage of the first transistor T1 can increase, thereby stably outputting the data voltage representing black.

[0103] In an embodiment, the third transistor T3 and the fourth transistor T4 may also include polycrystalline semiconductors and may be P-type transistors. In this case, the second transistor T2 and the third transistor T3 may receive the same gate signal, and the pixel PX may not include the boosting capacitor Cbs.

[0104] In an embodiment, the pixel PX includes seven transistors T1 to T7 , one storage capacitor Cst, and one boosting capacitor Cbs, but the number of transistors, the number of capacitors, and connection relationships therebetween may vary.

[0105] Figure 10 is a schematic cross-sectional view of a display device according to an embodiment. Figure 10 The stacked structure of the display panel 10 and the configuration of the circuit element layer CEL are shown in more detail.

[0106] Reference Figure 10 A buffer layer BF, which may include an inorganic insulating material, may be disposed on the substrate SB. A semiconductor layer A6 of the sixth transistor T6 may be disposed on the buffer layer BF. The semiconductor layer A6 may include a channel C6, a source electrode S6, and a drain electrode D6. The source electrode S6 and the drain electrode D6 are disposed on opposite sides of the channel C6. The semiconductor layer A6 may include a polycrystalline semiconductor.

[0107] An insulating layer IN1 may be disposed on the semiconductor layer A6, and a first gate conductive layer including a gate electrode G6 of the sixth transistor T6 and a scan line GL1 may be disposed on the insulating layer IN1. The sixth transistor T6 and the first, second, fifth, and seventh transistors T1, T2, T5, and T7 (not shown in the drawings) may have substantially the same stacked structure.

[0108] An insulating layer IN2 may be disposed on the first gate conductive layer, and a second gate conductive layer including a lower gate electrode G3 a of the third transistor T3 may be disposed on the insulating layer IN2 .

[0109] An insulating layer IN3 may be disposed on the second gate conductive layer, and a semiconductor layer A3 of the third transistor T3 may be disposed on the insulating layer IN3. The semiconductor layer A3 may include a channel C3, a source electrode S3, and a drain electrode D3. The source electrode S3 and the drain electrode D3 are disposed on opposite sides of the channel C3. The semiconductor layer A3 may include an oxide semiconductor.

[0110] The insulating layer IN4 may be provided on the semiconductor layer A3, and a third gate conductive layer including an upper gate electrode G3b of the third transistor T3 and an initialization voltage line VL2 may be provided on the insulating layer IN4. The upper gate electrode G3b may be electrically connected to the lower gate electrode G3a through contact holes of the insulating layers IN3 and IN4. The third transistor T3 may have a dual-gate structure including a lower gate electrode G3a that may be a portion of an extension of the inverted scan line GL2 and an upper gate electrode G3b electrically connected to the lower gate electrode G3a. Except that the fourth transistor T4 may not include a configuration corresponding to the lower gate electrode G3a, the third transistor T3 and Figure 10 The fourth transistor T4 not shown in FIG. 1 may have substantially the same structure.

[0111] An insulating layer IN5 may be provided on the third gate conductive layer. The insulating layer IN5 may be the first insulating layer ILa stated above.

[0112] A first data conductive layer including a data line DL, a conductor pattern CP, and a connection member CM may be disposed on the insulating layer IN5. The connection member CM may be electrically connected to the drain electrode D6 through a contact hole in the insulating layers IN1 to IN5. The conductor pattern CP may electrically connect the gate electrode of the first transistor T1 to the drain electrodes of the third transistor T3 and the fourth transistor T4.

[0113] An insulating layer IN6 may be disposed on the first data conductive layer. A second data conductive layer including a connection electrode LE and a driving voltage line VL1 may be disposed on the insulating layer IN6. The insulating layer IN6 may be the second insulating layer ILb described above. The connection electrode LE may be electrically connected to the connection member CM through a contact hole in the insulating layer IN6. The connection electrode LE is formed to overlap the light-emitting region and, therefore, may function as a shielding electrode to reduce coupling between the first electrode E1 and other signal lines.

[0114] An insulating layer IN7 may be disposed on the second data conductive layer, and a first electrode E1 of the light-emitting diode LED may be disposed on the insulating layer IN7. The insulating layer IN7 may be the third insulating layer ILc described above. The first electrode E1 may be electrically connected to the connection electrode LE through a contact hole in the insulating layer IN7. The elements and layers disposed between the buffer layer BF and the third insulating layer ILc may correspond to the circuit element layer CEL described above.

[0115] An insulating layer IN8 including an opening OP overlapping the first electrode E1 may be disposed on the insulating layer IN7. The insulating layer IN8 may be the pixel defining layer PDL stated above.

[0116] The opening OP may completely overlap the conductor pattern CP. In a plan view, the area of ​​the opening OP may substantially match the area of ​​the conductor pattern CP or may be disposed within the area of ​​the conductor pattern CP. The conductor pattern CP may substantially correspond to the opening OP or be formed as a larger area. Thus, the flatness of the insulating layer IN7 and the first electrode E1 thereon in the light-emitting region is improved, thereby preventing or reducing the generation of reflective color bands.

[0117] The emission layer EL of the light emitting diode LED may be disposed on the first electrode E1, and the second electrode E2 of the light emitting diode LED may be disposed on the emission layer EL. The second electrode E2 may be disposed throughout the pixel PX.

[0118] On the light emitting diode LED, all or some of the encapsulation layer EN, the touch sensor layer TSL, the light blocking member BM, the color filter CF, and the overcoat OC stated above may be further disposed.

[0119] The positions and arrangements of the above elements may be varied in various ways according to design. For example, the third transistor T3 may have a stack structure substantially identical to that of the sixth transistor T6, in which case the insulating layers IN3 and IN4 may be omitted.

[0120] The foregoing is illustrative of example embodiments and should not be construed as limiting thereof. Although several example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the present inventive concept. Therefore, all such modifications are intended to be included within the scope of the present inventive concept as defined in the claims. Therefore, it will be understood that the foregoing is illustrative of various example embodiments and should not be construed as limited to the specific example embodiments disclosed, and modifications of the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the appended claims.

Claims

1. A display device, comprising: a circuit element layer disposed on the substrate; a first insulating layer, disposed on the circuit element layer; a first conductor pattern, disposed on the first insulating layer; a second insulating layer, disposed on the first conductor pattern; a second conductor pattern, disposed on the second insulating layer; a third insulating layer, disposed on the second conductor pattern; an electrode of the light-emitting diode, disposed on the third insulating layer; as well as a pixel defining layer disposed on the third insulating layer and comprising an opening overlapping the electrode of the light emitting diode, wherein The opening overlaps the first conductor pattern, In a plan view, an area of ​​the opening matches an area of ​​the first conductor pattern or is provided inside the area of ​​the first conductor pattern, and The first conductor pattern is electrically connected to the drain electrode of a third transistor serving as a compensation transistor and the drain electrode of a fourth transistor serving as an initialization transistor, the gate electrode of the third transistor receives an inverted scan signal, and the gate electrode of the fourth transistor receives an initialization control signal.

2. The display device according to claim 1, wherein In a cross-sectional view, a width of the first conductor pattern is equal to or greater than a width of the opening.

3. The display device according to claim 1, wherein Each of the second insulating layer and the third insulating layer includes an organic insulating material.

4. The display device according to claim 3, wherein The first insulating layer includes an inorganic insulating material.

5. The display device according to claim 1, wherein The electrode of the light emitting diode is electrically connected to the second conductor pattern through the contact hole of the third insulating layer.

6. The display device according to claim 1, further comprising: The data line is arranged between the first insulating layer and the second insulating layer.

7. The display device according to claim 1, further comprising: The driving voltage line is arranged between the second insulating layer and the third insulating layer.

8. The display device according to claim 1, further comprising: a light blocking member, the light blocking member being above the light emitting diode and not overlapping the opening of the pixel defining layer; as well as A color filter is provided above the light emitting diode and overlaps the opening of the pixel defining layer.

9. The display device according to claim 8, further comprising: An encapsulation layer is disposed between the light emitting diode and the light blocking member.

10. The display device according to claim 1, wherein The circuit element layer includes a plurality of transistors, and the plurality of transistors include: A transistor comprising a polycrystalline semiconductor; and A transistor including an oxide semiconductor.

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