Iterative error correction with adjustable parameters after a threshold number of iterations

Abstract

The present application relates to iterative error correction with adjustable parameters after a threshold number of iterations. A processing device in a memory system reads sense words from a memory device and performs a plurality of parity check equations on corresponding subsets of the sense words to determine a plurality of parity check equation results. The processing device uses the plurality of parity check equation results to determine a syndrome of the sense word, determines whether the syndrome of the sense word satisfies a codeword criterion, and in response to the syndrome of the sense word not satisfying the codeword criterion, performs an iterative low density parity check LDPC correction process, wherein at least one criterion of the iterative LDPC correction process is adjusted after performing a threshold number of iterations.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly to iterative error correction utilizing adjustable parameters after a threshold number of iterations in a memory subsystem. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] One embodiment of the present disclosure provides a system, the system comprising: a memory device; and a processing device operatively coupled to the memory device to perform operations comprising: reading a sense word from the memory device; performing a plurality of parity check equations on corresponding subsets of the sense words to determine a plurality of parity check equation results; determining a syndrome of the sense word using the plurality of parity check equation results; determining whether the syndrome of the sense word satisfies a codeword criterion; and in response to the syndrome of the sense word not satisfying the codeword criterion, performing an iterative low density parity check (LDPC) correction process, wherein at least one criterion of the iterative LDPC correction process is adjusted after performing a threshold number of iterations.

[0004] Another embodiment of the present disclosure provides a method, the method comprising: reading a sense word; performing a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results; determining a syndrome of the sense word using the plurality of parity check equation results; determining whether the syndrome of the sense word satisfies a codeword criterion; and in response to the syndrome of the sense word not satisfying the codeword criterion, performing an iterative low density parity check (LDPC) correction process, wherein at least one criterion of the iterative LDPC correction process is adjusted after performing a threshold number of iterations.

[0005] Yet another embodiment of the present disclosure provides a non-transitory computer-readable storage medium comprising instructions, which, when executed by a processing device, causes the processing device to perform operations comprising: reading a sense word from a memory device; executing a plurality of parity check equations on corresponding subsets of the sense words to determine a plurality of parity check equation results; determining whether the plurality of parity check equation results indicate an error in the sense word; and in response to the parity check equation results indicating an error in the sense word: performing a first iteration of an error correction process; performing a threshold number of iterations of the error correction process, wherein the threshold number of iterations including flipping any bits in the sense word where the number of parity check equation results in an unsatisfied state is greater than or equal to a maximum number of parity check equation results in an unsatisfied state for any bit of the sense word from a previous iteration minus one; and performing one or more subsequent iterations of the error correction process after the threshold number of iterations, wherein the one or more subsequent iterations include flipping any bits in the sense word where the number of parity check equation results in an unsatisfied state is equal to the maximum number of parity check equation results in an unsatisfied state for any bit of the sense word from the previous iteration. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description provided below and the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is shown.

[0008] Figure 2 is a flow chart of an example method for configuring iterative error correction parameters using criteria from previous iterations according to some embodiments of the present disclosure.

[0009] Figure 3 is a diagram illustrating a sense word syndrome matrix for configuring iterative error correction parameters according to some embodiments of the present disclosure.

[0010] Figure 4 is a flow chart of an example method of an iterative error correction process in which one or more parameters are configured using criteria from a previous iteration, according to some embodiments of the present disclosure.

[0011] Figure 5 is a diagram illustrating an updated sense word syndrome matrix used to configure iterative error correction parameters after one or more iterations according to some embodiments of the present disclosure.

[0012] Figure 6is a flow chart of an example method of iterative error correction utilizing adjustable parameters after a threshold number of iterations according to some embodiments of the present disclosure.

[0013] Figure 7 is a flow chart of an example method of an iterative error correction process in which one or more parameters are adjusted after a threshold number of iterations, according to some embodiments of the present disclosure.

[0014] Figure 8 is a diagram illustrating an updated sense word syndrome matrix used to configure iterative error correction parameters after one or more iterations according to some embodiments of the present disclosure.

[0015] Fig. 9 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0016] Aspects of the present disclosure are directed to iterative error correction using adjustable parameters after a threshold number of iterations in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a mixture of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as memory devices that store data. The host system may provide data for storage at the memory subsystem and may request retrieval of data from the memory subsystem.

[0017] An example of a memory subsystem is a solid state drive (SSD) that includes one or more non-volatile memory devices and a memory subsystem controller that manages the non-volatile memory devices. The memory subsystem controller may encode data into a format that can be stored at the memory device. For example, a class of error detection and correction codes (ECC) such as low-density parity check (LDPC) codes may be used to encode data. LDPC codes are capacity-approximation codes, which means that there are practical constructions that allow the error threshold to be set very close to the theoretical maximum. This error threshold defines an upper limit on data errors, whereby the probability of losing information can be minimized. LDPC codes are reliable and efficient, which makes them useful in bandwidth-constrained applications. For example, the encoded data written to the physical memory cells of a memory device may be referred to as a codeword. Data that may contain errors and is different from a codeword read from a cell may be referred to as a sense word. A sense word may include one or more of user data, error correction codes, metadata, or other information.

[0018] When performing error correction code operations, as part of a read operation, the encoded data stored on the storage device may be transmitted from the memory device to the memory subsystem controller. The memory subsystem controller may perform a decoding operation to decode the encoded data into the original bit sequence that was encoded for storage on the memory device. The number of bits of the decoded data received by the memory subsystem controller may be flipped due to noise, interference, distortion, bit synchronization errors, or errors from the medium itself (both intrinsic and extrinsic). For example, a bit that was originally stored as a 0 may be flipped to a 1, or vice versa, a bit that was originally stored as a 1 may be flipped to a 0.

[0019] Conventional memory subsystems perform error correction code operations that attempt to correct bit flip errors in sense words read from memory devices. For example, conventional memory subsystems may perform error correction code operations on stored data to detect and correct errors in the encoded data. In many cases, an iterative process is used to decode the data. Segments of a data array may be decoded to produce corresponding bit (e.g., sense word) strings.

[0020] In general, the error correction code capability of conventional memory subsystems is a time and resource intensive process. The error correction process utilizes several parity check equations, each parity check equation is applicable to a subset of bits of a sense word, and the parity check equations are used together to identify bit flip errors in the sense word. In each iteration of the conventional error correction process, each bit of the sense word may be processed at least twice (e.g., two or more passes are used for the entire sense word). For example, during the first pass, the memory subsystem controller may identify the energy associated with each bit of the sense word and identify the maximum energy associated with any bit of the sense word. In one embodiment, the energy associated with a given bit (also referred to herein as the energy level) may be represented by several unsatisfied parity check equations associated with the bit. In another embodiment, the energy may be the number of unsatisfied parity check equations plus the XOR of the current bit value and its original value. A second pass is then required for each bit of the sense word to compare the energy of each bit with the identified maximum energy. The conventional error correction process may then include flipping those bits with energies that match the maximum energy and moving to the next iteration of the process. The need to process each bit of the sense word twice in order to identify those bits that should be flipped in a given iteration adds additional time and complexity to the conventional error correction process.

[0021] Aspects of the present disclosure address the above and other deficiencies by configuring iterative error correction parameters using criteria from a previous iteration or partial iteration in a memory subsystem. In one embodiment, a parity check component of a memory subsystem controller reads a sense word from a memory device of the memory subsystem and performs several parity check equations on a corresponding subset of the sense word. In one embodiment, each of the parity check equations corresponds to a different bit subset of the sense word, but different subsets may share one or more bits. Each parity check equation generates a parity check equation result indicating whether the number of bits set to a value of '1' in a corresponding subset of the sense word is an even number or an odd number. In one embodiment, if the number of bits set to a value of '1' in a corresponding subset is an even number, the parity check equation result is referred to as being in a satisfied state (i.e., a state indicating that there is no error in the corresponding subset of the sense word), and if the number of bits set to a value of '1' in a corresponding subset is an odd number, the parity check equation result is referred to as being in an unsatisfied state (i.e., a state indicating that there is an error in the corresponding subset of the sense word). Since any bit of the sense word can be part of a plurality of different subsets, the bit can contribute to or be associated with a plurality of parity check equation results. In one embodiment, the parity check component logically combines all parity check equation results to determine the syndrome of the sense word. If the syndrome of the sense word does not meet the codeword criteria (e.g., does not indicate that all parity check equation results are in a satisfied state), the parity check component determines that there are one or more errors in the sense word and starts the iterative LDPC correction process. Once the parity check component starts to flip the bits in the sense word, the bit sequence can be referred to as a corrected word. In one embodiment, each iteration after the first iteration or at least one iteration after the first iteration uses a criterion based at least in part on the previous iteration of the LDPC correction process. The criterion is used to determine which bits of the corrected word are flipped (i.e., changed from '1' to '0' or from '0' to '1') and can include, for example, the maximum energy of any bit of the corrected word from the previous iteration (i.e., the iteration performed immediately before the current iteration). The parity check component may perform multiple iterations of the LDPC correction process until the syndrome of the corrected word satisfies the codeword criteria, or until a threshold number of iterations is reached.

[0022] Other aspects of the present disclosure solve the above and other defects by implementing iterative error correction using adjustable parameters after a threshold number of iterations. In one embodiment, a parity check component of a memory subsystem controller reads a sense word from a memory device of a memory subsystem and executes several parity check equations on a corresponding subset of the sense word. Each parity check equation generates a parity check equation result indicating whether the number of bits set to a value of '1' in a corresponding subset of the sense word is an even number or an odd number. If the syndrome of the sense word does not satisfy the codeword criteria (e.g., does not indicate that all parity check equation results are in a satisfied state), the parity check component determines that there are one or more errors in the sense word and uses adjustable parameters to start an iterative LDPC correction process after a threshold number of iterations. In one embodiment, a first threshold number of iterations are initially performed using a first criterion based at least in part on a previous iteration of the LDPC correction process (e.g., the maximum number of parity check equation results that are in an unsatisfied state for any bit of the sense word or the corrected word from the previous iteration minus one). For any iteration performed after reaching a first threshold number of iterations, the LDPC correction process can use a second criterion, which is also based at least in part on a previous iteration of the LDPC correction process, but may be different from the first criterion. For example, the second criterion may include a maximum number of parity check equation results that are not satisfied for any one of the correction words from a previous iteration. The parity check component may perform multiple iterations of the LDPC correction process until the syndrome of the correction word satisfies the codeword criterion, or until a second threshold number of iterations is reached. The additional details of the parity check component and the iterative LDPC correction process are described below.

[0023] By using criteria from a previous iteration or configuring iterative error correction parameters using adjustable parameters after a threshold number of iterations, the number of times each bit of the sense word is processed (i.e., the number of passes for each bit of the sense word) can be reduced from two or more times to only one time during the error correction process. For example, during a single pass, the memory subsystem controller can identify the number of unsatisfied parity check equation results associated with each bit of the sense word and identify any bit of the sense word for which the number of unsatisfied parity check equations is equal to the maximum number of parity check equation results that are in an unsatisfied state for any bit of the sense word from the previous iteration. In one embodiment, the memory subsystem controller flips those bits and moves to the next iteration of the process without having to perform a second pass on the sense word. This reduces the time and complexity of the parity check and error correction process, thereby freeing up the resources of the memory subsystem controller to perform other operations. In addition, the techniques described herein can enable error correction to be completed in fewer iterations and reduce uncorrectable errors. In addition, although iterative error correction techniques are described herein in the context of reading data stored in a memory subsystem, it should be understood that these same techniques are also applicable to other implementations. For example, in an optical communication system, it may be necessary to verify whether received data matches transmitted data. If errors are identified in the received data, the iterative error correction techniques described herein may be applied to correct those errors. Advantages similar to those described above may be achieved in any number of different implementations of these techniques.

[0024] Figure 1 An example computing system 100 is shown that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., storage device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such memory devices.

[0025] The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0026] The computing system 100 can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked commercial device), or such computing device that includes a memory and a processing device.

[0027] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is shown. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0028] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0029] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), etc. The physical host interface may be used to transmit data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access memory components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1Memory subsystem 110 is shown as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0030] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0031] Some examples of non-volatile memory devices (e.g., memory device 130) include "NAND" (NAND) type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. A cross-point array of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grid data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0032] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, for example, a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of such memory cell arrays. In some embodiments, a particular memory device may include an SLC portion of a memory cell, and an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0033] Although nonvolatile memory components such as a 3D cross-point nonvolatile memory cell array and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-selected memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), non-OR (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM).

[0034] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data and other such operations at the memory device 130. The memory subsystem controller 115 can include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0035] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0036] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been shown as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0037] Typically, the memory subsystem controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), name spaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0038] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0039] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) can externally manage the memory device 130 (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., the local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0040] In one embodiment, the memory subsystem 110 includes a parity check component 113 that can configure iterative error correction parameters using criteria from a previous iteration or partial iteration in the memory subsystem 110. In one embodiment, in response to the syndrome of the sense word read from one of the memory devices 130 or 140 not satisfying the codeword criteria (e.g., one or more of the parity check equation results are in an unsatisfied state), the parity check component can perform an iterative LDPC correction process. In one embodiment, the parity check component 113 determines the number of parity check equation results that are in an unsatisfied state for each bit of the sense word, and determines the maximum number of parity check equation results that are in an unsatisfied state for any bit of the sense word. If the current iteration is the first iteration of the iterative LDPC correction process, the parity check component 113 can flip any bit in the sense word where the energy level (e.g., the threshold number of parity check equation results that are in an unsatisfied state) meets the energy threshold condition (e.g., greater than or equal to the threshold energy level), and flip each of the parity check equation results associated with those bits. In one embodiment, the threshold energy level is equal to the maximum energy of any bit of the sense word (e.g., the maximum number of parity check equation results in an unsatisfied state). If the current iteration is not the first iteration, the parity check component 113 may flip any bit in the sense word that has an energy equal to the maximum energy of any bit of the corrected word from the previous iteration, and flip each of the parity check equation results associated with those bits. The parity check component 113 further determines whether the number of iterations performed in the iterative LDPC correction process meets the iteration criteria (e.g., less than a threshold number of iterations), and if so, continues the LDPC correction process by moving to the next iteration. In response to the number of iterations performed not meeting the iteration criteria (e.g., meeting or exceeding a threshold number of iterations), the parity check component 113 may end the LDPC correction process. Therefore, in at least one iteration after the first iteration (e.g., each iteration after the first iteration), the parity check component 113 uses a criterion based at least in part on the previous iteration or partial iteration of the LDPC correction process. For example, the second iteration may use a criterion based on the first iteration, the third iteration may use a criterion based on the second iteration, and so on. Depending on the embodiment, the energy of a given bit may represent the number of unsatisfied parity check equations associated with the bit or the number of unsatisfied parity check equations plus the XOR of the current bit value with its original value (eg, before the first iteration).

[0041] In another embodiment, the parity check component 113 determines the number of parity check equation results that are in an unsatisfied state for each bit of the sense word, and determines the maximum number of parity check equation results that are in an unsatisfied state for any bit of the sense word. If the current iteration is one of a threshold number of iterations after the first iteration of the iterative LDPC correction process (e.g., one of the first 3 or 4 iterations after the first iteration), the parity check component 113 may flip any bits in the sense word or corrected word where the number of parity check equation results that are in an unsatisfied state is greater than or equal to the maximum number of parity check equation results that are in an unsatisfied state for any bit of the sense word or corrected word from the previous iteration minus one, and flip each of the parity check equation results associated with those bits. If the current iteration is an iteration after a threshold number of iterations (e.g., not one of the first 3 or 4 iterations after the first iteration), the parity check component 113 may flip any bits in the corrected word where the number of parity check equation results in an unsatisfied state is equal to the maximum number of parity check equation results in an unsatisfied state for any bit of the corrected word from the previous iteration, and flip each of the parity check equation results associated with those bits. The parity check component 113 further determines whether the number of iterations performed in the iterative LDPC correction process satisfies the iteration criteria (e.g., less than the threshold number of iterations), and if so, continues the LDPC correction process by moving to the next iteration. In response to the number of iterations performed not satisfying the iteration criteria (e.g., satisfying or exceeding the threshold number of iterations), the parity check component 113 may end the LDPC correction process. Therefore, after the threshold number of iterations, the parity check component 113 may adjust the criteria for determining whether to flip a given bit of the corrected word based at least in part on the previous iteration of the LDPC correction process. Additional details regarding the operation of parity check component 113 are described below.

[0042] Figure 2 200 is a flowchart of an example method for configuring iterative error correction parameters using criteria from previous iterations according to some embodiments of the present disclosure. Method 200 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 200 is performed by Figure 1The parity check component 113 of the embodiment of the present invention is performed. Although it is shown in a specific sequence or order, unless otherwise specified, the order of the process can be modified. Therefore, it should be understood that the illustrated embodiment is only an example, and the illustrated process can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, all processes are not required in each embodiment. Other process flows are also possible.

[0043] At operation 205, processing logic receives a request from a requestor to read data from a memory device, such as memory device 130. In one embodiment, memory subsystem controller 115 receives the request from host system 120 or from some other component connected to or within memory subsystem 110. The request may identify data to be read from memory device 130 of memory subsystem 110.

[0044] At operation 210, processing logic reads a sense word from memory device 130. In one embodiment, the sense word includes a sequence of bits representing the data requested at operation 205. In one embodiment, parity check component 113 identifies a physical address in memory device 130 where the requested data is stored, reads the sense word from memory device 130, and temporarily stores the sense word in a buffer or other storage location while parity checking and / or error correction processes may be performed. Figure 3 An example sense word 310 is shown in FIG. Sense word 310 is shown as including a sequence of eight sense word bits (i.e., SWB0-SWB7), but it should be understood that this is merely an example for illustrative purposes. In other embodiments, the sense word may include any number of bits, such as thousands of bits (e.g., 36k bits).

[0045] At operation 215, the processing logic performs several parity check equations on the corresponding subsets of the sense word. In one embodiment, each of the parity check equations corresponds to a different bit subset of the sense word, but different subsets may share one or more bits. For example, in one embodiment, a subset may include 40 bits from 36k bits in the sense word. There may be, for example, thousands (e.g., 3k) of parity check equations each configured to operate on different subsets of 40 bits. Each parity check equation generates a parity check equation result indicating whether the number of bits set to the value '1' in the corresponding subset of the sense word is an even number or an odd number. In one embodiment, if the number of bits set to the value '1' in the corresponding subset is an even number, the parity check equation result is said to be in a satisfied state, and if the number of bits set to the value '1' in the corresponding subset is an odd number, the parity check equation result is said to be in an unsatisfied state. In another embodiment, these values ​​(i.e., logic states) may be reversed. Since any bit of the sense word can be part of multiple different subsets, the bit can contribute to or be associated with multiple parity check equation results. In one embodiment, each bit of the sense word is part of the same number of subsets used by the parity check equations (e.g., 4 subsets).

[0046] At operation 220, processing logic determines a syndrome of the sensed word using the determined parity check equation results. In one embodiment, parity check component 113 logically combines the parity check equation results to determine the syndrome, such as by appending or concatenating the parity check equation results. Figure 3 An example syndrome 320 is shown in FIG. Syndrome 320 is shown as comprising a sequence of eight syndrome bits (ie, SB0-SB7), but it should be understood that this is merely an example for illustrative purposes. In other embodiments, the syndrome may comprise any number of bits, such as thousands of bits (eg, 3k bits).

[0047] Figure 3is a block diagram illustrating a sense word syndrome matrix 300 for configuring iterative error correction parameters according to some embodiments of the present disclosure. As described above, sense word 310 includes a number of bits read from a memory device, and syndrome 320 includes a number of bits representing the results of a parity check equation. In the example shown, there are eight parity check equations, each corresponding to a different subset of the bits of sense word 310. For example, a first subset represented by SB0 includes SWB0, SWB1, SWB2, and SWB4. A second subset represented by SB1 includes SWB0, SWB1, SWB2, and SWB5. A third subset represented by SB2 includes SWB0, SWB1, SWB2, and SWB6. There are additional subsets represented by each bit of syndrome 320. In matrix 300 , a value of '1' may indicate that a given bit of sense word 310 is part of the subset represented by the bits of syndrome 320 , while a value of '0' may indicate that the bit of sense word 310 is not part of the subset.

[0048] In one embodiment, the parity check equations each identify the logic state of the bits of the sense word 310 that are part of each corresponding subset, add those bits together and determine whether the result is an even number or an odd number. In other words, each parity check equation determines whether the number of bits of the sense word 310 that are part of the corresponding subset and have a particular logic state is an even number or an odd number. For example, the parity check component 113 may determine whether the number of bits set to a logic value of '1' in the corresponding subset of the sense word 310 is an even number or an odd number. In one embodiment, if the number of bits set to a logic value of '1' in the corresponding subset of the sense word 310 is an even number, the parity check equation result may be '0', indicating that the parity check equation is satisfied. If the number of bits set to a logic value of '1' in the corresponding subset of the sense word 310 is an odd number, the parity check equation result may be '1', indicating that the parity check equation is not satisfied. Each bit of the syndrome 320 represents one of these parity check equation results. Therefore, for SB0, because SWB0 is set to a value of '1', SWB1 is set to a value of '0', SWB2 is set to a value of '1', and SWB4 is set to a value of '0', there are two bits of the sense word 310 set to a value of '1' in the corresponding subset. The two bits are even, so the parity check equation represented by SB0 results in '0', indicating that the corresponding parity check equation is satisfied. For example, for SB2, because SWB0 is set to a value of '1', SWB1 is set to a value of '0', SWB2 is set to a value of '1', and SWB6 is set to a value of '1', there are three bits of the sense word 310 set to a value of '1' in the corresponding subset. The three bits are odd, so the parity check equation represented by SB0 results in '1', indicating that the corresponding parity check equation is not satisfied.

[0049] See again Figure 2 , at operation 225, processing logic determines whether the syndrome of the sense word satisfies the LDPC check criterion. In one embodiment, the parity check component 113 determines whether the parity check equation results in the syndrome are all in a satisfied state (e.g., having a value of '0'). In one embodiment, if the parity check equation results in the syndrome are all in a satisfied state, the parity check component 113 determines that the syndrome satisfies the LDPC check criterion. On the contrary, if the parity check equation results in the syndrome are not all in a satisfied state (e.g., one or more have a value of '1'), the parity check component 113 determines that the syndrome does not satisfy the LDPC check criterion. If the syndrome of the sense word does satisfy the codeword criterion, the parity check component 113 determines that there is no error in the sense word, and at operation 230, the sense word is transmitted back to the requester as the requested data.

[0050] However, if the syndrome of the sense word does not satisfy the codeword criteria, the parity check component 113 determines that there are one or more errors in the sense word, and at operation 235, an iterative LDPC correction process is performed. In one embodiment, at least one iteration after the first iteration uses a criterion based at least in part on a previous iteration or a partial iteration of the LDPC correction process. The criterion is used to determine which bits of the corrected word are flipped (i.e., changed from '1' to '0' or from '0' to '1'), and may include, for example, the maximum number of parity check equation results that are in an unsatisfied state for any bit of the corrected word from the previous complete iteration (i.e., the iteration performed immediately before the current iteration). In another embodiment, the criterion may be based on a partial iteration. For example, if a full iteration includes checking 2000 bits, the maximum number of parity check equation results (or maximum energy) energy may be determined from only 1000 of those bits (i.e., one-half of the iteration) or some other fraction (e.g., one-third, one-quarter, etc.). If the parity check component 113 has checked a certain fraction of the bits that make up the complete iteration in the current iteration, then the bits from this partial iteration of the current iteration can be used for the criterion. The parity check component 113 can perform multiple iterations of the LDPC correction process until the syndrome of the corrected word meets the codeword criterion at operation 225, or until a threshold number of iterations is reached. Figure 4 Additional details of the iterative LDPC correction process are described.

[0051] Figure 4is a flow chart of an example method of an iterative error correction process in which one or more parameters are configured using criteria from a previous iteration according to some embodiments of the present disclosure. Method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, by Figure 1 The parity check component 113 execution method 400 of the embodiment of the present invention is shown in a specific sequence or order, but unless otherwise specified, the order of the process can be modified. Therefore, it should be understood that the illustrated embodiment is only an example, and the illustrated process can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, all processes are not required in each embodiment. Other process flows are also possible.

[0052] At operation 405, processing logic determines whether the syndrome of the sense word satisfies the LDPC check criteria. If the syndrome of the sense word does satisfy the codeword criteria, then at operation 410, processing logic determines that there are no errors in the sense word. However, if the syndrome of the sense word does not satisfy the codeword criteria, then parity check component 113 determines that there are one or more errors in the sense word and initiates an iterative LDPC correction process. The iterative LDPC correction process may include several iterations, starting with a first iteration and continuing to one or more subsequent iterations.

[0053] At operation 415, processing logic determines the number of parity check equation results that are not satisfied for each bit of the sense word. Figure 3, SWB0 of sense word 310 is a portion of a subset corresponding to SB0, SB1, SB2, and SB3 of syndrome 320, and SWB1 of sense word 310 is a portion of a subset corresponding to SB0, SB1, SB2, and SB4 of syndrome 320, and SWB7 of sense word 310 is a portion of a subset corresponding to SB3, SB5, SB6, and SB7 of syndrome 320. The extra bits of sense word 310 are portions of different subsets represented by each bit of syndrome 320. For SWB0, because SB0 is set to a value of '0', SB1 is set to a value of '0', SB2 is set to a value of '1', and SB3 is set to a value of '1', there are two bits of syndrome 320 that are set to a value of '1', indicating that the corresponding parity check equation results are in an unsatisfied state. For SWB1, because SB0 is set to a value of '0', SB1 is set to a value of '0', SB2 is set to a value of '1', and SB4 is set to a value of '0', there is one bit of the syndrome 320 set to a value of '1', indicating that the corresponding parity check equation result is in an unsatisfied state. For SWB7, because SB3 is set to a value of '1', SB5 is set to a value of '1', SB6 is set to a value of '0', and SB7 is set to a value of '1', there are three bits of the syndrome 320 set to a value of '1', indicating that the corresponding parity check equation result is in an unsatisfied state. In another embodiment, processing logic determines an energy for each bit of the sense word. Depending on the embodiment, the energy of a given bit may represent the number of unsatisfied parity check equations associated with the bit or the number of unsatisfied parity check equations plus the XOR of the current bit value with its original value.

[0054] At operation 420, processing logic determines the maximum number of parity check equation results that are in an unsatisfied state for any bit of the sense word. Because SWB0 has two unsatisfied parity check equations, SWB1 has one unsatisfied parity check equation, and SWB7 has three unsatisfied parity check equations, the parity check component 113 can determine that the maximum number in the current iteration is three unsatisfied parity check equations. The parity check component 113 can store (e.g., in local memory 119 or elsewhere in memory subsystem 110) an indication of this maximum number for use in subsequent iterations. In another embodiment, processing logic determines the maximum energy for any bit of the sense word.

[0055] At operation 425, processing logic determines whether the current iteration of the LDPC correction process is the first iteration. If the current iteration is the first iteration, then at operation 430, processing logic flips any bits in the sense word where the number (or energy level) of parity check equation results in an unsatisfied state satisfies the energy threshold condition, and flips each of the parity check equation results associated with those bits. In one embodiment, the energy threshold condition is satisfied when the energy level is greater than or equal to the threshold energy level. In one embodiment, the threshold energy level is equal to the maximum number of parity check equation results in an unsatisfied state for any bit of the sense word, as determined at operation 425. Therefore, in the above example, the parity check component 113 may flip the value of SWB7 of the sense word 310 from '0' to '1', and flip the values ​​of SB3, SB5, SB6, and SB7 of the syndrome 320. The resulting matrix 500 is Figure 5 As shown, SWB7 of sense word 510 has a value of '1', SB3 of syndrome 520 has a value of '0', SB5 has a value of '0', SB6 has a value of '1', and SB7 has a value of '0'. After flipping the bits at operation 430, processing logic returns to operation 405 and determines whether the updated syndrome meets the codeword criteria.

[0056] However, if the processing logic determines at operation 425 that the current iteration is not the first iteration, then at operation 435, the processing logic flips any bits in the corrected word where the number (or energy) of parity check equation results in an unsatisfied state is greater than or equal to the maximum number (or maximum energy) of parity check equation results in an unsatisfied state for any bit of the corrected word from the previous iteration, and flips each of the parity check equation results associated with those bits. In one embodiment, the parity check component 113 checks the number of unsatisfied parity check equation results from the updated syndrome 520 for each bit of the corrected word 510 and compares them to the maximum number (e.g., 3) of unsatisfied parity check equation results from the previous iteration (as determined at operation 420). The parity check component 113 may flip any identified bits in the corrected word 510. If such identified bits do not exist in the corrected word 510, the bits in the current iteration are not flipped.

[0057] At operation 440, processing logic determines whether the number of iterations performed in the iterative LDPC correction process meets the iteration criteria (e.g., less than a threshold number of iterations). In one embodiment, parity check component 113 maintains a counter, which is incremented after performing each iteration. Parity check component 113 can compare the value of the counter with a threshold value (e.g., 30) to determine whether to meet the iteration criteria. If the number of iterations does meet the iteration criteria, then processing logic continues the LDPC correction process by determining whether the syndrome after the update meets the codeword criteria and moves to the next iteration. However, if the number of iterations performed does not meet the iteration criteria (e.g., the number of iterations meets or exceeds a threshold number of iterations), then parity check component 113 can determine at operation 445 that it is impossible to fully correct the correction word and end the LDPC correction process.

[0058] Figure 6 is a flow chart of an example method for iterative error correction with adjustable parameters after a threshold number of iterations according to some embodiments of the present disclosure. Method 600 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, by Figure 1 The parity check component 113 of the embodiment of the present invention performs method 600. Although it is shown in a specific sequence or order, unless otherwise specified, the order of the process can be modified. Therefore, it should be understood that the illustrated embodiment is only an example, and the illustrated process can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, all processes are not required in each embodiment. Other process flows are also possible.

[0059] At operation 605, processing logic receives a request from a requestor to read data from a memory device, such as memory device 130. In one embodiment, memory subsystem controller 115 receives the request from host system 120 or from some other component connected to or within memory subsystem 110. The request may identify data to be read from memory device 130 of memory subsystem 110.

[0060] At operation 610, processing logic reads a sense word from memory device 130. In one embodiment, the sense word includes a sequence of bits representing the data requested at operation 205. In one embodiment, parity check component 113 identifies a physical address in memory device 130 where the requested data is stored, reads the sense word from memory device 130, and temporarily stores the sense word in a buffer or other storage location while parity checking and / or error correction processes may be performed. Figure 3An example sense word 310 is shown in FIG. Sense word 310 is shown as including a sequence of eight sense word bits (i.e., SWB0-SWB7), but it should be understood that this is merely an example for illustrative purposes. In other embodiments, the sense word may include any number of bits, such as thousands of bits (e.g., 36k bits).

[0061] At operation 615, the processing logic performs several parity check equations on the corresponding subsets of the sense word. In one embodiment, each of the parity check equations corresponds to a different bit subset of the sense word, but different subsets may share one or more bits. For example, in one embodiment, a subset may include 40 bits from 36k bits in the sense word. There may be, for example, thousands (e.g., 3k) of parity check equations each configured to operate on different subsets of 40 bits. Each parity check equation generates a parity check equation result indicating whether the number of bits set to the value '1' in the corresponding subset of the sense word is an even number or an odd number. In one embodiment, if the number of bits set to the value '1' in the corresponding subset is an even number, the parity check equation result is said to be in a satisfied state, and if the number of bits set to the value '1' in the corresponding subset is an odd number, the parity check equation result is said to be in an unsatisfied state. In another embodiment, these values ​​(i.e., logic states) may be reversed. Since any bit of the sense word can be part of multiple different subsets, the bit can contribute to or be associated with multiple parity check equation results. In one embodiment, each bit of the sense word is part of the same number of subsets used by the parity check equations (e.g., 4 subsets).

[0062] At operation 620, processing logic determines a syndrome of the sense word using the determined parity check equation results. In one embodiment, parity check component 113 logically combines the parity check equation results to determine the syndrome, such as by appending or concatenating the parity check equation results. Figure 3 An example syndrome 320 is shown in FIG. Syndrome 320 is shown as comprising a sequence of eight syndrome bits (ie, SB0-SB7), but it should be understood that this is merely an example for illustrative purposes. In other embodiments, the syndrome may comprise any number of bits, such as thousands of bits (eg, 3k bits).

[0063] At operation 625, processing logic determines whether the syndrome of the sense word satisfies the LDPC check criterion. In one embodiment, parity check component 113 determines whether the parity check equation results in the syndrome are all in a satisfied state (e.g., having a value of '0'). In one embodiment, if the parity check equation results in the syndrome are all in a satisfied state, then parity check component 113 determines that the syndrome satisfies the LDPC check criterion. On the contrary, if the parity check equation results in the syndrome are not all in a satisfied state (e.g., one or more have a value of '1'), then parity check component 113 determines that the syndrome does not satisfy the LDPC check criterion. If the syndrome of the sense word does satisfy the codeword criterion, then parity check component 113 determines that there is no error in the sense word, and at operation 630, the sense word is transmitted back to the requester as the requested data.

[0064] However, if the syndrome of the sense word does not satisfy the codeword criteria, the parity check component 113 determines that there are one or more errors in the sense word, and at operation 635, an iterative LDPC correction process is performed. In one embodiment, each iteration of the first threshold number of iterations after the first iteration uses a first criterion based at least in part on the previous iteration of the LDPC correction process. The criterion is used to determine which bits of the corrected word are flipped (i.e., changed from '1' to '0' or from '0' to '1'), and may include, for example, a number less than the maximum number of parity check equation results that are in an unsatisfied state for any bit of the corrected word from the previous iteration (i.e., the iteration performed immediately before the current iteration). For any iteration performed after the first threshold number of iterations has been reached, the LDPC correction process may use a second criterion, which is also based at least in part on the previous iteration of the LDPC correction process, but may be different from the first criterion. For example, the second criterion may include the maximum number of parity check equation results that are in an unsatisfied state for any bit of the corrected word from the previous iteration.

[0065] The parity check component 113 may perform multiple iterations of the LDPC correction process until the syndrome of the corrected word satisfies the codeword criteria at operation 225, or until a second threshold number of iterations is reached. Figure 7 Additional details of the iterative LDPC correction process are described.

[0066] Figure 7is a flow chart of an example method of an iterative error correction process in which one or more parameters are adjusted after a threshold number of iterations according to some embodiments of the present disclosure. Method 700 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, by Figure 1 The parity check component 113 execution method 700 of the embodiment of the present invention is shown in a specific sequence or order, but unless otherwise specified, the order of the process can be modified. Therefore, it should be understood that the illustrated embodiment is only an example, and the illustrated process can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, all processes are not required in each embodiment. Other process flows are also possible.

[0067] At operation 705, processing logic determines whether the syndrome of the sense word satisfies the LDPC check criteria. If the syndrome of the sense word does satisfy the codeword criteria, then at operation 410, processing logic determines that there are no errors in the sense word. However, if the syndrome of the sense word does not satisfy the codeword criteria, then parity check component 113 determines that there are one or more errors in the sense word and initiates an iterative LDPC correction process. The iterative LDPC correction process may include several iterations, starting with a first iteration and continuing to one or more subsequent iterations.

[0068] At operation 715, processing logic determines the number of parity check equation results that are not satisfied for each bit of the sense word. Figure 3, SWB0 of sense word 310 is a portion of a subset corresponding to SB0, SB1, SB2, and SB3 of syndrome 320, and SWB1 of sense word 310 is a portion of a subset corresponding to SB0, SB1, SB2, and SB4 of syndrome 320, and SWB7 of sense word 310 is a portion of a subset corresponding to SB3, SB5, SB6, and SB7 of syndrome 320. The extra bits of sense word 310 are portions of different subsets represented by each bit of syndrome 320. For SWB0, because SB0 is set to a value of '0', SB1 is set to a value of '0', SB2 is set to a value of '1', and SB3 is set to a value of '1', there are two bits of syndrome 320 that are set to a value of '1', indicating that the corresponding parity check equation results are in an unsatisfied state. For SWB1, because SB0 is set to a value of '0', SB1 is set to a value of '0', SB2 is set to a value of '1', and SB4 is set to a value of '0', there is one bit of the syndrome 320 set to a value of '1', indicating that the corresponding parity check equation result is in an unsatisfied state. For SWB7, because SB3 is set to a value of '1', SB5 is set to a value of '1', SB6 is set to a value of '0', and SB7 is set to a value of '1', there are three bits of the syndrome 320 set to a value of '1', indicating that the corresponding parity check equation result is in an unsatisfied state. In another embodiment, processing logic determines an energy for each bit of the sense word. Depending on the embodiment, the energy of a given bit may represent the number of unsatisfied parity check equations associated with the bit or the number of unsatisfied parity check equations plus the XOR of the current bit value with its original value.

[0069] At operation 720, processing logic determines the maximum number of parity check equation results that are in an unsatisfied state for any bit of the sense word. Because SWBO has two unsatisfied parity check equations, SWB1 has one unsatisfied parity check equation, and SWB7 has three unsatisfied parity check equations, the parity check component 113 can determine that the maximum number in the current iteration is three unsatisfied parity check equations. The parity check component 113 can store (e.g., in local memory 119 or elsewhere in memory subsystem 110) an indication of this maximum number for use in subsequent iterations. In another embodiment, processing logic determines the maximum energy for any bit of the sense word.

[0070] At operation 725, processing logic determines whether the current iteration of the LDPC correction process is the first iteration. If the current iteration is the first iteration, then at operation 730, processing logic flips any bits in the sense word where the number (or energy level) of parity check equation results in an unsatisfied state meets the energy threshold condition, and flips each of the parity check equation results associated with those bits. In one embodiment, the energy threshold condition is met when the energy level is greater than or equal to the threshold energy level. In one embodiment, the threshold energy level is equal to the maximum number of parity check equation results in an unsatisfied state for any bit of the sense word, as determined at operation 425. Therefore, in the above example, the parity check component 113 may flip the value of SWB7 of the sense word 310 from '0' to '1', and flip the values ​​of SB3, SB5, SB6, and SB7 of the syndrome 320. The resulting matrix 500 is Figure 5 As shown, SWB7 of sense word 510 has a value of '1', SB3 of syndrome 520 has a value of '0', SB5 has a value of '0', SB6 has a value of '1', and SB7 has a value of '0'. After flipping the bits at operation 730, processing logic returns to operation 705 and determines whether the updated syndrome meets the codeword criteria.

[0071] However, if the processing logic determines at operation 725 that the current iteration is not the first iteration, then at operation 735, the processing logic determines whether the number of iterations performed in the iterative LDPC correction process satisfies the adjustment threshold criteria (e.g., less than the adjustment threshold number of iterations). In one embodiment, the parity check component 113 maintains a counter that is incremented after each iteration is performed. The parity check component 113 may compare the value of the counter with an adjustment threshold (e.g., 3 or 4) to determine whether the adjustment threshold criteria are met.

[0072] If the number of iterations does satisfy the adjustment threshold criteria, then at operation 740, the processing logic flips any bits in the sense word where the number of parity check equation results in an unsatisfied state is greater than or equal to the maximum number of parity check equation results in an unsatisfied state (or threshold energy level) for any bit of the sense word from the previous iteration minus one, and flips each of the parity check equation results associated with those bits. Because the maximum number of unsatisfied parity check equations from the previous iteration determined at operation 720 is three, the parity check component may look for any bit of the sense word 510 that has a number of unsatisfied checks equal to two (i.e., =3-1). Therefore, in the above example, the parity check component 113 may flip the value of SWB6 of the sense word 510 from '0' to '1', and flip the values ​​of SB2, SB3, SB4, and SB6 of the syndrome 520. The resulting matrix 800 is Figure 88. As shown, SWB6 of corrected word 810 has a value of '0', SB2 of syndrome 820 has a value of '0', SB3 has a value of '1', SB4 has a value of '1', and SB6 has a value of '0'. In other embodiments, some other criterion may be used, such as two less, three less, etc., than the maximum number of unsatisfied parity check equations from the previous iteration. After flipping the bits at operation 740, processing logic returns to operation 705 and determines whether the updated syndrome satisfies the codeword criteria.

[0073] However, if the number of iterations performed does not satisfy the adjustment threshold criteria (e.g., the number of iterations meets or exceeds the adjustment threshold number of iterations), then at operation 745, the processing logic flips any bits in the corrected word where the number (or energy) of parity check equation results that are in an unsatisfied state is greater than or equal to the maximum number (or maximum energy) of parity check equation results that are in an unsatisfied state for any bit of the corrected word from the previous iteration, and flips each of the parity check equation results associated with those bits.

[0074] At operation 750, processing logic determines whether the number of iterations performed in the iterative LDPC correction process meets the iteration criteria (e.g., less than a threshold number of iterations). In one embodiment, parity check component 113 maintains a counter, which is incremented after performing each iteration. Parity check component 113 can compare the value of the counter with a threshold value (e.g., 30) to determine whether to meet the iteration criteria. If the number of iterations does meet the iteration criteria, then processing logic continues the LDPC correction process by determining whether the syndrome after the update meets the codeword criteria and moves to the next iteration. However, if the number of iterations performed does not meet the iteration criteria (e.g., the number of iterations meets or exceeds a threshold number of iterations), then parity check component 113 can determine at operation 755 that it is impossible to fully correct the correction word and end the LDPC correction process.

[0075] Fig. 9 An example machine of computer system 900 is shown, within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, computer system 900 may correspond to a host system (e.g., Figure 1 1) a host system 120 that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110 of the controller may be used to execute the operation of the controller (for example, execute the operating system to execute the corresponding Figure 1In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0076] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. In addition, while a single machine is described, the term "machine" shall also be construed to include any collection of machines that individually or jointly execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0077] The example computer system 900 includes a processing device 902, a main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), a static memory 906 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 918, which communicate with each other via a bus 930.

[0078] The processing device 902 represents one or more general processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 902 can also be one or more special processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 902 is configured to execute instructions 926 for performing the operations and steps discussed herein. The computer system 900 may further include a network interface device 908 to communicate on a network 920.

[0079] The data storage system 918 may include a machine-readable storage medium 924 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 926 or software embodying any one or more of the methods or functions described herein. The instructions 926 may also reside, in whole or in part, within the main memory 904 and / or within the processing device 902 during execution thereof by the computer system 900, the main memory 904 and the processing device 902 also constituting machine-readable storage media. The machine-readable storage medium 924, the data storage system 918, and / or the main memory 904 may correspond to Figure 1 Memory subsystem 110.

[0080] In one embodiment, instruction 926 includes implementing a Figure 1 The functional instructions of the parity check component 113 of the present invention. Although the machine-readable storage medium 924 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should accordingly be understood to include (but not limited to) solid-state memory, optical media, and magnetic media.

[0081] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively convey the substance of their work to other persons skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that result in a desired result. An operation is an operation that requires physical manipulation of physical quantities. Typically (but not necessarily), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been demonstrated that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc., primarily for common reasons.

[0082] It should be borne in mind, however, that all of these and similar terms will be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may be directed to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0083] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0084] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used in conjunction with the programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of various these systems will be presented as set forth in the description below. In addition, the present disclosure is described without reference to any particular programming language. It should be appreciated that the teachings of the present disclosure as described herein may be implemented using various programming languages.

[0085] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, and the instructions may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. The machine-readable medium includes any mechanism for storing information in a machine (e.g., computer) readable form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a disk storage medium, an optical storage medium, a flash memory component, etc.

[0086] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims

1. A system comprising: Memory device; as well as A processing device operatively coupled to the memory device to perform operations comprising: reading a sense word from the memory device; performing a plurality of parity check equations on corresponding subsets of the sense words to determine a plurality of parity check equation results; determining a syndrome of the sense word using the plurality of parity check equation results; determining whether the syndrome of the sensed word satisfies a codeword criterion; as well as In response to the syndrome of the sense word not satisfying the codeword criterion, performing an iterative low density parity check (LDPC) correction process, wherein at least one criterion of the iterative LDPC correction process uses a first criterion based at least in part on a threshold number of iterations of a previous iteration after a first iteration, and uses a second criterion based at least in part on the previous iteration after performing the threshold number of iterations.

2. The system of claim 1 , wherein performing the iterative LDPC correction process comprises: determining an energy level associated with each bit of the sense word; determining a maximum energy level associated with any bit of the sense word; Determining whether a current iteration of the LDPC correction process is a first iteration; as well as In response to the current iteration being the first iteration, any bits in the sense word where an energy level satisfies an energy threshold condition are flipped.

3. The system of claim 2, wherein performing the iterative LDPC correction process further comprises: In response to the current iteration not being the first iteration, determining whether the current iteration is one of the threshold number of iterations; as well as Responsive to the current iteration being one of the threshold number of iterations, flipping any bit in the sense word having an associated energy level greater than or equal to the maximum energy level associated with any bit of the sense word from a previous iteration minus one.

4. The system of claim 3, wherein the energy level associated with a given bit of the sense word represents the number of parity check equation results that are not satisfied for the bit plus an XOR of a current value of the bit and an original value of the bit.

5. The system of claim 3, wherein performing the iterative LDPC correction process further comprises: Responsive to the current iteration not being one of the threshold number of iterations, flipping any bit in the sense word having an associated energy level greater than or equal to the maximum energy level associated with any bit of the sense word from the previous iteration.

6. The system of claim 1, wherein the processing device is configured to perform further operations comprising: receiving, from a requestor, a request to read data from the memory device, wherein the sense word is associated with the data; and In response to the syndrome of the sensed word satisfying the codeword criterion, the sensed word is returned to the requestor as the requested data.

7. The system of claim 1 , wherein each of the plurality of parity check equations corresponds to a different subset of the sensed word, and wherein each of the plurality of parity check equation results indicates whether the number of bits set to the value ‘1’ in the corresponding subset of the sensed word is even or odd, wherein determining the syndrome of the sensed word comprises logically combining the plurality of parity check equation results, and wherein determining whether the syndrome of the sensed word satisfies the codeword criterion comprises determining whether all of the plurality of parity check equation results in the syndrome are in a satisfied state.

8. The system of claim 1, wherein the processing device is configured to perform further operations comprising: Determining whether the number of iterations performed in the iterative LDPC correction process satisfies an iteration criterion; In response to the number of iterations performed satisfying the iteration criterion, continuing the LDPC correction process; as well as In response to the number of iterations performed not satisfying the iteration criterion, the LDPC correction process is terminated.

9. A method comprising: Read the sense word; performing a plurality of parity check equations on corresponding subsets of the sense words to determine a plurality of parity check equation results; determining a syndrome of the sense word using the plurality of parity check equation results; determining whether the syndrome of the sensed word satisfies a codeword criterion; as well as In response to the syndrome of the sense word not satisfying the codeword criterion, an iterative low density parity check (LDPC) correction process is performed, wherein at least one criterion in the iterative LDPC correction process uses a first criterion based at least in part on a threshold number of iterations of a previous iteration after a first iteration, and uses a second criterion based at least in part on the previous iteration after performing the threshold number of iterations.

10. The method of claim 9, wherein performing the iterative LDPC correction process comprises: determining an energy level associated with each bit of the sense word; determining a maximum energy level associated with any bit of the sense word; Determining whether a current iteration of the LDPC correction process is a first iteration; as well as In response to the current iteration being the first iteration, any bits in the sense word where an energy level satisfies an energy threshold condition are flipped.

11. The method of claim 10, wherein performing the iterative LDPC correction process further comprises: In response to the current iteration not being the first iteration, determining whether the current iteration is one of the threshold number of iterations; as well as Responsive to the current iteration being one of the threshold number of iterations, flipping any bit in the sense word having an associated energy level greater than or equal to the maximum energy level associated with any bit of the sense word from a previous iteration minus one.

12. The method of claim 11, wherein the energy level associated with a given bit of the sense word represents the number of parity check equation results that are not satisfied for the bit plus the XOR of the current value of the bit and the original value of the bit.

13. The method of claim 11, wherein performing the iterative LDPC correction process further comprises: Responsive to the current iteration not being one of the threshold number of iterations, flipping any bit in the sense word having an associated energy level greater than or equal to the maximum energy level associated with any bit of the sense word from the previous iteration.

14. The method according to claim 9, further comprising: receiving a request from a requestor to read data, wherein the sense word is associated with the data; as well as In response to the syndrome of the sensed word satisfying the codeword criterion, the sensed word is returned to the requestor as the requested data.

15. The method of claim 9, wherein each of the plurality of parity check equations corresponds to a different subset of the sensed word, and wherein each of the plurality of parity check equation results indicates whether the number of bits set to the value '1' in the corresponding subset of the sensed word is even or odd, wherein determining the syndrome of the sensed word comprises logically combining the plurality of parity check equation results, and wherein determining whether the syndrome of the sensed word satisfies the codeword criterion comprises determining whether all of the plurality of parity check equation results in the syndrome are in a satisfied state.

16. The method of claim 9, further comprising: Determining whether the number of iterations performed in the iterative LDPC correction process satisfies an iteration criterion; In response to the number of iterations performed satisfying the iteration criterion, continuing the LDPC correction process; as well as In response to the number of iterations performed not satisfying the iteration criterion, the LDPC correction process is terminated.

17. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: reading a sense word from a memory device; performing a plurality of parity check equations on corresponding subsets of the sense words to determine a plurality of parity check equation results; determining whether the plurality of parity check equation results indicate an error in the sense word; as well as In response to the parity check equation result indicating an error in the sense word: performing a first iteration of an error correction process; performing a threshold number of iterations of the error correction process, wherein the threshold number of iterations includes flipping any bits in the sense word for which the number of parity check equation results that are not satisfied is greater than or equal to a maximum number of parity check equation results that are not satisfied for any bit of the sense word from a previous iteration minus one; and One or more subsequent iterations of the error correction process are performed after the threshold number of iterations, wherein the one or more subsequent iterations include flipping any bits in the sense word for which the number of parity check equation results that are in an unsatisfied state is equal to a maximum number of parity check equation results that are in an unsatisfied state for any bit of the sense word from the previous iteration.

18. The non-transitory computer-readable storage medium of claim 17, wherein each of the plurality of parity-check equations corresponds to a different subset of the sense words, and wherein each of the plurality of parity-check equation results indicates whether the number of bits set to a value of '1' in the corresponding subset of the sense words is an even number or an odd number.

19. The non-transitory computer-readable storage medium of claim 17, wherein determining whether the plurality of parity check equation results indicate an error in the sense word comprises determining whether the plurality of parity check equation results are all in a satisfied state.

20. The non-transitory computer-readable storage medium of claim 17, wherein performing the first iteration of the error correction process comprises: determining the number of parity check equation results that are not satisfied for each bit of the sense word; determining a maximum number of parity check equation results that are not satisfied for any bit of the sense word; as well as Any bits in the sense word where the number of parity check equation results in an unsatisfied state meets an energy threshold condition are flipped.

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