Data processing device, data driving device and system for driving a display device

Abstract

The present invention relates to a data processing device, a data driving device and a system for driving a display device, and more particularly to a data processing device, a data driving device and a system for accelerating data communication in a display device.

Description

Technical Field

[0001] The present invention relates to a technology for driving a display device. Background Art

[0002] On the display panel, a plurality of pixels are arranged in a matrix, and each pixel includes a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. Each sub-pixel emits light according to a grayscale value obtained from image data to display an image on the display panel.

[0003] Image data is sent from a data processing device called a timing controller to a data driving device called a source driver. The image data is sent in the form of a digital signal, and the data driving device converts the image data received in the form of a digital signal into an analog voltage to drive each pixel.

[0004] Since each image data represents the grayscale value of each pixel, the amount of image data increases as the number of pixels arranged on the display panel increases. In addition, as the frame rate increases, the amount of image data to be transmitted per unit time increases.

[0005] Recently, there is a trend that as the resolution of a display panel becomes higher, the number of pixels arranged on the display panel and the frame rate both increase. In order to process the increased amount of image data, data communication in the display device needs to be accelerated. Summary of the invention

[0006] In this context, an aspect of the present invention is to provide a technique for accelerating data communication in a display device.

[0007] To this end, on one hand, the present invention provides a data driving device, comprising: a low-speed communication circuit for performing low-speed clock training using a low-speed communication clock signal received from a data processing device in a low-speed communication mode, and outputting a low-speed communication status signal of a first level after completing the low-speed clock training; a high-speed communication circuit for performing high-speed clock training using a high-speed communication clock signal received from the data processing device in a clock training section in a high-speed communication mode, and outputting the high-speed communication status signal after adjusting the level of the high-speed communication status signal according to the result of the high-speed clock training; and a locking control circuit for generating a locking signal based on the low-speed communication status signal and the high-speed communication status signal to send the locking signal to the data processing device, and maintaining the level of the locking signal from the end of the low-speed communication mode until the clock training section in the high-speed communication mode.

[0008] The locking control circuit may send the locking signal of the second level before the low-speed communication circuit completes the low-speed clock training, change the level of the locking signal to the first level to send the locking signal to the data processing device when the low-speed communication status signal received from the low-speed communication circuit is at the first level, and send the locking signal fixed at the first level from the end of the low-speed communication mode until the clock training section.

[0009] The lock control circuit may generate the lock signal according to the low-speed communication status signal in the low-speed communication mode, and according to the high-speed communication status signal after the clock training section in the high-speed communication mode.

[0010] The high-speed communication circuit may include a clock recovery circuit and an equalizer. The high-speed communication circuit may perform high-speed clock training in the clock recovery circuit and output the high-speed communication status signal to the lock control circuit.

[0011] In the equalizer tuning section before the clock training section, the clock recovery circuit may repeatedly perform clock initialization and high-speed clock training for equalizer tuning. Here, the clock recovery circuit may output the high-speed communication status signal of the second level during the clock initialization, and output the high-speed communication status signal of the first level when the high-speed clock training is completed.

[0012] In the equalizer tuning section, the lock control circuit may transmit the lock signal fixed at a first level regardless of a change in a level of the high-speed communication status signal received from the clock recovery circuit to the data processing device.

[0013] The clock recovery circuit may include an oscillator. In a clock recovery circuit tuning section before the clock training section, the clock recovery circuit may change a setting value of the oscillator at predetermined times during high-speed clock training, output a high-speed communication status signal of a first level when the high-speed clock training is completed, and output a high-speed communication status signal of a second level when the high-speed clock training is not completed.

[0014] The lock control circuit may transmit the lock signal fixed to the first level regardless of changes in the level of the high-speed communication status signal received from the clock recovery circuit to the data processing device.

[0015] The oscillator may be one of a current controlled oscillator and a voltage controlled oscillator, and the set value may include a current value of a reference current input to the current controlled oscillator or a voltage value of a reference voltage input to the voltage controlled oscillator.

[0016] In the low-speed communication mode, after the low-speed communication circuit outputs the low-speed communication status signal of the first level, in the event of any abnormality in the low-speed communication with the data processing device, the low-speed communication circuit may change the low-speed communication status signal from the first level to the second level and output the signal, and the locking control circuit may change the level of the locking signal to the second level and send the locking signal to the data processing device.

[0017] When the high-speed communication status signal input into the locking control circuit immediately after the clock training section is at a first level, the locking control circuit may maintain the locking signal at the first level, and when the high-speed communication status signal input into the locking control circuit immediately after the clock training section is at a second level, the locking control circuit may change the locking signal to the second level and send the locking signal to the data processing device.

[0018] On the other hand, the present invention provides a data processing device, comprising: a lock monitoring circuit for receiving a lock signal from a data driving device and checking the level of the lock signal; a sending circuit for sending a low-speed communication clock signal and a setting data signal to the data driving device in a low-speed communication mode, and then sending a high-speed communication clock signal to the data driving device after changing the mode to a high-speed communication mode, wherein the setting data signal includes data for setting a high-speed communication environment in the data driving device; and a control circuit for enabling the low-speed communication mode to send the low-speed communication clock signal using the sending circuit when power is supplied, sending the setting data signal using the sending circuit after the lock monitoring circuit confirms that the level of the lock signal changes from the second level to the first level when the sending circuit sends the low-speed communication clock signal, and enabling the high-speed communication mode to send the high-speed communication clock signal using the sending circuit when the lock monitoring circuit confirms that the level of the lock signal is maintained at the first level.

[0019] In the high-speed communication mode, the control circuit may use the transmission circuit to transmit one or more signals for causing high-speed clock training to be repeated in the data driving device before using the transmission circuit to transmit the high-speed communication clock signal.

[0020] When the lock monitoring circuit confirms that the level of the lock signal is maintained at the first level from the start until the end of the transmission of the one or more signals, the control circuit may transmit the high-speed communication clock signal using the transmission circuit.

[0021] In a case where the lock monitoring circuit confirms that the level of the lock signal is maintained at the first level from the time point when the level of the lock signal changes to the first level until the time point when the sending circuit completes the sending of the setting data signal, the control circuit can enable the high-speed communication mode, and in a case where the lock monitoring circuit confirms that the level of the lock signal is maintained at the first level until a predetermined amount of time has passed from the time point when the high-speed communication mode is enabled, the control circuit can use the sending circuit to send the high-speed communication clock signal.

[0022] On the other hand, the present invention provides a system comprising: a data processing device, which is used to enable a low-speed communication mode to send a low-speed communication clock signal and then send a setting data signal when power is supplied, and enable a high-speed communication mode to send a high-speed communication clock signal when a locking signal of a first level is continuously received, wherein the data processing device sends the setting data signal when the locking signal of the first level is received during the sending of the low-speed communication clock signal; and a data driving device, which is used to receive the low-speed communication clock signal to perform low-speed clock training, send the locking signal of the first level to the data processing device when the low-speed clock training is completed, and receive the high-speed communication clock signal to perform high-speed clock training, wherein the data driving device continuously sends the locking signal of the first level to the data processing device from the receipt of the setting data signal in the low-speed communication mode until the high-speed clock training is performed.

[0023] The data driving device may include a clock recovery circuit and an equalizer, and the data processing device may send one or more of a clock recovery circuit tuning signal and an equalizer tuning signal to the data driving device before sending the high-speed communication clock signal in the high-speed communication mode.

[0024] The clock recovery circuit tuning signal may include a high-speed communication clock, and the data driving device may perform high-speed clock training multiple times when tuning the clock recovery circuit using the clock recovery circuit tuning signal. Here, the data driving device may send the lock signal fixed at the first level to the data processing device regardless of the multiple high-speed clock trainings.

[0025] The equalizer tuning signal may include a high-speed communication clock, and the data driving device may perform high-speed clock training multiple times when tuning the equalizer using the equalizer tuning signal. Here, the data driving device may send the lock signal fixed at the first level to the data processing device regardless of the multiple high-speed clock trainings.

[0026] As described above, the present invention allows data communication in a display device to be accelerated. In addition, the present invention improves the accuracy of feedback by simplifying feedback of low-speed communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a structural diagram of a display device according to an embodiment;

[0028] Figure 2 is a block diagram of a system according to an embodiment;

[0029] Figure 3 is a diagram showing processing of a first protocol signal in a data processing device and a data driving device according to an embodiment;

[0030] Figure 4 is a diagram showing a general signal sequence between a data processing device and a data driving device according to an embodiment;

[0031] Figure 5 is a diagram showing processing of a second protocol signal in a data processing device and a data driving device according to an embodiment;

[0032] Figure 6 and Figure 7 is a diagram showing a clock recovery circuit tuning section according to an embodiment, the clock recovery circuit tuning section further included in a signal sequence preceding a clock training section;

[0033] Figure 8 is a diagram showing an equalizer tuning section according to an embodiment, the equalizer tuning section further included in a signal sequence before a clock training section; and

[0034] Fig.9A and Fig. 9B is a diagram showing signal sequences in a clock recovery circuit tuning section and an equalizer tuning section. DETAILED DESCRIPTION

[0035] Figure 1 is a structural diagram of a display device according to an embodiment.

[0036] refer to Figure 1 The display device 100 may include a display panel 110 , a data driving device 120 , a gate driving device 130 , and a data processing device 140 .

[0037] On the display panel 110, a plurality of data lines DL and a plurality of gate lines GL may be arranged, and a plurality of pixels may also be arranged. Each pixel may include a plurality of sub-pixels SP. The sub-pixels may be red (R) sub-pixels, green (G) sub-pixels, blue (B) sub-pixels, and white (W) sub-pixels. The pixel may include RGB sub-pixels SP, RGBG sub-pixels SP, or RGBW sub-pixels SP. For ease of description, the case where a pixel includes RGB sub-pixels will be described below.

[0038] The data driving device 120 , the gate driving device 130 , and the data processing device 140 are used to generate signals for displaying an image on the display panel 110 .

[0039] The gate driving device 130 may supply an on voltage or an off voltage as a gate driving signal via the gate line GL. When the on voltage as the gate driving signal is supplied to the sub-pixel SP, the sub-pixel SP is connected to the data line DL. When the off voltage as the gate driving signal is supplied to the sub-pixel SP, the sub-pixel is disconnected from the data line DL. The gate driving device 130 may be referred to as a gate driver.

[0040] The data driving device 120 may supply the data voltage Vp to the sub-pixel via the data line DL. The data voltage Vp supplied via the data line DL may be supplied to the sub-pixel according to the gate driving signal. The data driving device 120 may be referred to as a source driver.

[0041] The data driving device 120 may include at least one integrated circuit, and the at least one integrated circuit may be connected to a bonding pad of the display panel 110 in a tape automated bonding (TAB) type or a chip on glass (COG) type, wherein the at least one integrated circuit may be directly formed on the display panel 110 or integrated on the display panel 110 according to circumstances. In addition, the data driving device 120 may be formed in a chip on film (COF) type.

[0042] The data processing device 140 may supply control signals to the gate driving device 130 and the data driving device 120. For example, the data processing device 140 may send a gate control signal GCS to initiate scanning to the gate driving device 130, output image data to the data driving device 120, and send a data control signal to control the data driving device 120 to supply a data voltage Vp to each sub-pixel SP. The data processing device 140 may be referred to as a timing controller.

[0043] The data processing device 140 may transmit the image data and the data control signal using the first protocol signal PS1 embedded with a clock.

[0044] The data driving device 120 may use the auxiliary communication signal ALP to transmit the training state of the clock embedded in the first protocol signal PS1 to the data processing device 140 .

[0045] The data processing device 140 and the data driving device 120 can use the first protocol signal PS1 to perform high-speed data communication. High-speed data communication may have a relatively high data loss rate compared to low-speed data communication. For this reason, the data processing device 140 can use low-speed data communication to transmit the data of various settings of the data driving device 120 required for the high-speed data communication to the data driving device 120.

[0046] In other words, the data processing device 140 transmits the setting data of the data driving device 120 to the data driving device 120 using low-speed data communication with a low data loss rate, so that the data driving device 120 can accurately receive the setting data.

[0047] The setting data of the data driving device 120 may include a basic gain level of an equalizer included in the data driving device 120, scrambling information, or line polarity information, etc. The scrambling information may be information on whether the data processing device 140 transmits data as it is, or scrambled data when transmitting data to the data driving device 120, and the line polarity information may be information indicating the polarity of a first line of pixels.

[0048] The data processing device 140 may perform low-speed data communication using the second protocol signal PS2. The data processing device 140 may transmit the first protocol signal PS1 and the second protocol signal PS2 to the data driving device 120 via the first communication line LN1.

[0049] The data processing device 140 may transmit a signal for optimizing high-speed data communication to the data driving device 120 via the first communication line LN1. For example, the data processing device 140 may transmit a tuning signal for an equalizer of the data driving device 120, and the data driving device 120 may use such a tuning signal to tune the gain of the equalizer to be optimized.

[0050] The data driving device 120 may use the auxiliary communication signal ALP to feed back the state of the data driving device 120 to the data processing device 140. The data driving device 120 may use the auxiliary communication signal ALP to feed back the clock training state for low-speed data communication and the clock training state for high-speed data communication to the data processing device 140. The auxiliary communication signal ALP related to the clock training state for low-speed data communication and the clock training state for high-speed data communication may be referred to as a locking signal LOCK. The data driving device 120 may send the locking signal to the data processing device 140 via the second communication line LN2.

[0051] The data driving device 120 can use the auxiliary communication signal ALP to feed back the reception status of the signal to the data processing device 140 via the first communication line LN1. The data driving device 120 can use the auxiliary communication signal ALP to send feedback of the reception status of specific information transmitted by the first protocol signal PS1 and / or the second protocol signal PS2. The data driving device 120 can generate status data related to the reception status and include the status data in the auxiliary communication signal ALP to send (feed back) the status data to the data processing device 140.

[0052] According to an embodiment, the first protocol signal PS1 and the second protocol signal PS2 may be sent or received via the first communication line LN1, and the auxiliary communication signal ALP may be sent or received via the second communication line LN2. The first communication line LN1 may be an AC differential signal line, and the second communication line LN2 may be a transistor-transistor line TTL or a single communication line including an open drain circuit.

[0053] The data processing device 140 and the data driving device 120 may perform 1:1 communication via the first communication line LN1 or perform cascade communication in a chain form via the second communication line LN2 .

[0054] For example, in the case where there are multiple data driving devices 120, the multiple data driving devices 120 can be connected to each other in a cascade form by connecting adjacent data driving devices via the second communication line LN2, and at least one of the multiple data driving devices can be connected to the data processing device 140 via the second communication line LN2.

[0055] The structures of the first communication line LN1 and the second communication line LN2 will be described in detail below.

[0056] Figure 2 is a structural diagram of a system according to an embodiment.

[0057] refer to Figure 2The system may include at least one data processing device 140 and a plurality of data driving devices 120a, 120b, 120c, and 120d.

[0058] The data processing device 140 may be disposed on the first printed circuit board PCB1. The data processing device 140 may be connected to the plurality of data driving devices 120a, 120b, 120c, 120d via the first communication line LN1 and the second communication line LN2.

[0059] The first communication line LN1 and the second communication line LN2 may reach the plurality of data driving devices 120a, 120b, 120c, 120d via the first printed circuit board PCB1 and the second printed circuit board PCB2. The first printed circuit board PCB1 and the second printed circuit board PCB2 may be connected to each other through a first film FL1 made of a flexible material, and the first communication line LN1 and the second communication line LN2 may extend from the first printed circuit board PCB1 to the second printed circuit board PCB2 via the first film FL1.

[0060] The data driving devices 120a, 120b, 120c, and 120d may each be arranged on the second film FL2 in a chip-on-film (COF) type. The second film FL2 may be a support substrate made of a flexible material connecting the second printed circuit board PCB2 and the panel 110. The first communication line LN1 and the second communication line LN2 may extend from the second printed circuit board PCB2 to each of the data driving devices 120a, 120b, 120c, and 120d via the second film FL2.

[0061] The first communication lines LN1 may connect the data processing device 140 and each of the data driving devices 120 a , 120 b , 120 c , and 120 d in a 1:1 manner.

[0062] The second communication lines LN2 may connect adjacent data driving devices 120a, 120b, 120c, 120d or the data driving device 120d and the data processing device 140, respectively, without overlapping with the first communication lines LN1. For example, the first data driving device 120a may be connected to the second data driving device 120b via the second communication line LN2, and the second data driving device 120b may be connected to the third data driving device 120c via the second communication line LN2. Here, the second data driving device 120b and the third data driving device 120c may be connected to different second printed circuit boards PCB2, respectively. Therefore, the second communication line LN2 arranged between the second data driving device 120b and the third data driving device 120c may connect the two via the second printed circuit board PCB2, the first film FL1, the first printed circuit board PCB1, the first film FL1, and the second printed circuit board PCB2. The third data driving device 120 c may be connected to the fourth data driving device 120 d via the second communication line LN2 , and the fourth data driving device 120 d may be connected to the data processing device 140 via the second communication line LN2 .

[0063] Figure 3 is a diagram illustrating processing of a first protocol signal in a data processing device and a data driving device according to an embodiment.

[0064] refer to Figure 3 The data processing device 140 may include a scrambler 312, an encoder 314, a first transmitting circuit 318 and a second transmitting circuit 319, and the data driving device 120 may include a first receiving circuit 328, a byte arrangement circuit 325, a decoder 324, a descrambler 322, a pixel arrangement circuit 321 and a second receiving circuit 329.

[0065] The data (e.g., image data) is scrambled by the scrambler 312. Scrambling is a process of confusing the bits of the data to be transmitted. This makes it possible to prevent the same at least K (K is a natural number of 2 or more) bits (e.g., 1 or 0) from being arranged continuously in the transmission stream of the data. Scrambling is performed according to a previously specified protocol. The descrambler 322 of the data driver 120 can restore the data in the stream whose bits are scrambled to its original state.

[0066] The scrambler 312 may selectively scramble a portion of the data of the first protocol signal PS1. For example, the scrambler 312 may scramble only a zero data portion of a tuning signal for an equalizer (hereinafter referred to as an "equalizer tuning signal") and transmit the zero data portion.

[0067] The encoder 314 may encode P bits in the transmission stream of data into Q bits. For example, P may be 8 and Q may be 10. Encoding 8 bits of data into 10 bits of data may be referred to as 8B10B encoding. 8B10B encoding is a method of encoding in the form of a DC balanced code.

[0068] Encoder 314 can encode data so that the transmission stream of the data includes an increased number of bits. The encoded data can be decoded by decoder 324 into a DC balanced code (e.g., 8B10B). On the other hand, the encoded data can be restored by decoder 324 to have the original number of bits.

[0069] The encoder 314 may use a run length limited coding (LRLC) method when encoding data. "Run length" means that the same bits are arranged continuously, and according to the LRLC method, specific bits of the data are controlled at certain intervals so that the size of the "run length" is not greater than a predetermined size.

[0070] In the case where the encoder 314 encodes the data using the LRLC method, the decoder 314 may decode the data using the LRLC method used by the encoder 314 .

[0071] Data transmitted in parallel in the data processing device 140 may be serially converted to be transmitted between the data processing device 140 and the data driving device 120. In the data processing device 140, the serial-parallel conversion of data may be performed by a serialization circuit ( Figure 5 The parallelization circuit 526 of the data driving device 120 can convert the serially received data into parallel data.

[0072] The serially converted data may be transmitted to the data driving device 120 by the first transmitting circuit 318 of the data processing device 140. In this case, the data may be transmitted via the first communication line LN1 in the form of a first protocol signal PS1.

[0073] The data received by the data driving device 120 may be sent to the first receiving circuit 328 , the byte alignment circuit 325 , the decoder 324 , the descrambler 322 , and the pixel alignment circuit 321 .

[0074] The first transmitting circuit 318 may transmit data via at least one first communication line LN1. Each first communication line LN1 may include two signal lines to transmit a signal using a differential method. In the case of using a plurality of first communication lines LN1, the first transmitting circuit 318 may disperse the data to transmit the data via the plurality of first communication lines LN1. The first receiving circuit 328 may collect signals received in a dispersed state via the plurality of first communication lines LN1 to form data.

[0075] The data driver 120 can train the link clock (eg, symbol clock or pixel clock) according to the link data included in the first protocol signal PS1. The byte alignment circuit 325 and the pixel alignment circuit 321 can arrange the data by byte (eg, by symbol) and by pixel according to the trained data link.

[0076] The byte arrangement circuit 325 can arrange the data by byte. A byte, which is a basic unit for forming information included in the data, can be, for example, 8 bits or 10 bits. The byte arrangement circuit 325 can arrange the serially transmitted data so that the data can be read by byte.

[0077] The pixel arrangement circuit 321 may arrange data by pixel. The data may include information arranged sequentially corresponding to RGB sub-pixels, etc. The pixel arrangement circuit 321 may arrange the data transmitted in series so that the data may be read by pixel.

[0078] When the pixel arrangement circuit 321 arranges the image data on a pixel-by-pixel basis, grayscale data (image data) for each sub-pixel can be generated.

[0079] The second transmitting circuit 319 of the data processing device 140 may use the second protocol signal PS2 to transmit the setting data and the like to the data driving device 120. The data driving device 120 may receive the second protocol signal PS2 through the second receiving circuit 329 and check the setting data and the like included in the second protocol signal PS2.

[0080] The first protocol signal PS1 and the second protocol signal PS2 can be transmitted through the same communication line ( Figure 3 However, the first protocol signal PS1 and the second protocol signal PS2 may be sent at different times.

[0081] Figure 4 is a diagram showing a general signal sequence between a data processing device and a data driving device according to an embodiment.

[0082] When the driving voltage VCC is supplied to the data processing device 140 , the data processing device 140 may enable the low speed communication mode LS mode. Then, the data processing device 140 may transmit the second protocol signal PS2 to the data driving device 120 within a predetermined time.

[0083] In other words, the data processing device 140 and the data driving device 120 can perform low-speed data communication via the first communication line LN1.

[0084] After a predetermined amount of time has passed (e.g., Figure 4), the data processing device 140 may enable the high-speed communication mode HS mode and send the first protocol signal PS1 to the data driving device 120.

[0085] In other words, the data processing device 140 and the data driving device 120 can perform high-speed data communication via the first communication line LN1.

[0086] Here, the second protocol signal PS2, which is a signal based on the second protocol specified between the data processing device 140 and the data driving device 120, is a signal according to the low-speed data communication protocol, and the first protocol signal PS1, which is a signal based on the first protocol specified between the data processing device 140 and the data driving device 120, is a signal according to the high-speed data communication protocol.

[0087] The communication frequency of the first protocol signal PS1 may be 10 times higher than the communication frequency of the second protocol signal PS2. According to such characteristics, the first protocol signal PS1 may be classified in the high-speed data communication protocol, and the second protocol signal PS2 may be classified in the low-speed data protocol.

[0088] On the other hand, in high-speed data communication, the data loss rate may greatly change or communication may not be performed smoothly depending on the setting of the data driving device 120 as the receiving section.

[0089] According to an embodiment, before performing high-speed data communication between the data processing device 140 and the data driving device 120, setting data for performing smooth high-speed data communication may be transmitted to the data driving device 120 using the second protocol signal PS2 corresponding to low-speed data communication. The reason for this is that there is no large difference in data loss rate according to the setting of the data driving device 120 in the low-speed data communication, and thus the setting data may be transmitted to the data driving device 120 relatively accurately.

[0090] According to an embodiment, the segments in which the data processing device 140 and the data driving device 120 send and receive the second protocol signal PS2, that is, the segments corresponding to the low-speed communication mode of the data processing device 140 and the data driving device 120 can be a preamble segment, a CFG data segment, and a CFG Done segment.

[0091] In the preamble section, the data processing device 140 may transmit the low-speed communication clock signal as the second protocol signal PS2 to the data driving device 120. Here, in the case where an AC coupling capacitor is added to the first communication line LN1, the data processing device 140 may encode the low-speed communication clock signal in the form of a DC balanced code such as a Manchester code or an 8B10B code.

[0092] The data driving device 120 may perform low-speed clock training using the low-speed communication clock signal, and receive low-speed data using the trained low-speed communication clock.

[0093] In the CFG data section, the data processing device 140 may send a setting data signal as a second protocol signal PS2 to the data driving device 120. In the CFG data section, the data driving device 120 may receive the setting data signal using the above-mentioned low-speed communication clock, and use the setting data included in the setting data signal to set the circuit part for high-speed data communication. Here, the setting data may include a basic gain level, scrambling information, and line polarity information of an equalizer included in the data driving device 120. In addition, the setting data may also include a plurality of equalizer (EQ) setting information used in the equalizer tuning section described below.

[0094] In the CFG completion section, the second protocol signal PS2 may include a message indicating the end of the low-speed communication mode. The data driver 120 may check such a message and end the communication using the second protocol signal PS2, i.e., end the low-speed communication mode. Here, the message indicating the end of the low-speed communication mode may include a signal in which the voltage level is maintained high and lasts for a predetermined amount of time.

[0095] On the other hand, the locking signal, which is an auxiliary communication signal ALP sent by the data driving device 120 to the data processing device 140 via the second communication line LN2, can be maintained at the second level after the data driving device 120 starts working, and then changed to the first level when the low-speed clock training for the low-speed communication clock signal is completed.

[0096] In other words, the data driving device 120 may maintain the lock signal at the second level when the driving voltage VCC is supplied, and change the level of the lock signal to the first level when the low-speed clock training for the low-speed communication clock signal is completed in the preamble section. After the level of the lock signal has been changed to the first level, the data processing device 140 may send a setting data signal including setting data to the data driving device 120. Here, the second level may be a low level (low voltage level), and the first level may be a high level (high voltage level).

[0097] In the case where there is any abnormal situation or any unexpected communication error after changing the level of the lock signal to the first level in the data driving device 120, the data driving device 120 may change the level of the lock signal to the second level. For example, in the case where the set data signal is not received in the CFG data section or the CFG completion section or the clock is in an abnormal state, the data driving device 120 may change the level of the lock signal to low (see Figure 4 FT1 in ).

[0098] On the other hand, the data processing device 140 and the data driving device 120 may end the low-speed communication mode in the CFG completion section, and then enable the high-speed communication mode and perform high-speed communication using the first protocol signal PS1.

[0099] Here, the section corresponding to the high-speed communication mode may be a clock training section, a link training section, and a display section DP. One of a clock recovery circuit tuning section and an equalizer tuning section may also be added.

[0100] In the clock training section, the first protocol signal PS1 may include a high-speed communication clock signal.

[0101] In other words, the data driving device 120 may receive the high-speed communication clock signal from the data processing device 140 in the clock training section.

[0102] In addition, the data driving device 120 may perform high-speed clock training using the high-speed communication clock signal, and receive high-speed data using the trained high-speed communication clock.

[0103] In the link training section, the first protocol signal PS1 may include link data. The data driving device 120 may train a link clock such as a symbol clock or a pixel clock according to the link data.

[0104] In the display section DP, the first protocol signal PS1 may include image data and control data. The data driving device 120 may set parameters required to drive the display according to the control data, and check the grayscale value of each pixel according to the image data to drive the pixel.

[0105] In the case of any abnormal situation or any unexpected communication error in the high-speed communication mode in the data driving device 120, the data driving device 120 may change the level of the lock signal to the second level. For example, in the case where the high-speed clock training for the clock (high-speed communication clock) is not completed (failed) in the clock training section, the data driving device 120 may change the level of the lock signal to the second level (see Figure 4For another example, when the link clock training fails in the link training section, the data driving device 120 may change the level of the auxiliary communication signal ALP to low (see Figure 4 For another example, when the high-speed communication clock is in an abnormal state due to, for example, electrostatic discharge (ESD), or when any abnormal situation exists in the data driving device 120, the data driving device 120 may change the level of the lock signal to the second level (see Figure 4 FT4 in ).

[0106] As described above, according to an embodiment, only when there is any abnormal situation or any unexpected communication error in the data driving device (not in each section), the data driving device can use the locking signal as the auxiliary communication signal ALP to feed back its condition to the data processing device. On the contrary, according to conventional technology, the data driving device uses the auxiliary communication signal in each section to feed back its condition to the data processing device. According to such a manner, the feedback signal cannot be well transmitted to the data processing device, and thus there is a problem that the normal condition is considered to be an abnormal condition. In particular, in the case where the second communication line LN2 through which the auxiliary communication signal ALP is sent is connected in a cascade form, such a problem is more likely to occur. However, according to an embodiment of the present invention, the feedback using the auxiliary communication signal ALP is simplified, and this reduces the possibility of such a problem. This will be described in detail below.

[0107] Figure 5 is a diagram illustrating processing of a second protocol signal in a data processing device and a data driving device according to an embodiment.

[0108] refer to Figure 5 The data driving device 120 may include a low-speed communication circuit 510 , a high-speed communication circuit 520 , a receiving control circuit 530 , and a locking control circuit 540 .

[0109] The low-speed communication circuit 510 can perform low-speed data communication with the data processing device 140 via the first communication line LN1 .

[0110] In other words, the low-speed communication circuit 510 can use the low-speed communication clock signal received from the data processing device 140 to perform low-speed clock training in the low-speed communication mode, and can output a first level low-speed communication status signal CMD_L to the locking control circuit 540 after completing the low-speed clock training.

[0111] In the case where the low-speed clock training is not completed (failed), the low-speed communication circuit 510 may output a low-speed communication status signal of the second level to the lock control circuit 540. The low-speed communication circuit 510 may output a low-speed communication status signal of the second level to the lock control circuit 540. Figure 4A low speed communication clock signal is received in the preamble segment shown.

[0112] After completing the low-speed clock training, the low-speed communication circuit 510 may receive a setting data signal related to the high-speed communication environment from the data processing device 140 .

[0113] The low-speed communication circuit 510 may process the setting data signal (eg, signal decoding or data arrangement, etc.) into setting data, and send the setting data to the reception control circuit 530. The low-speed communication circuit 510 may process the setting data signal (eg, signal decoding or data arrangement, etc.) into setting data, and send the setting data to the reception control circuit 530. Figure 4 The setup data signal is received in the CFG data section shown.

[0114] In the event of any abnormality in the low-speed communication with the data processing device after the low-speed communication circuit 510 completes the low-speed clock training, the low-speed communication circuit 510 may change and output the low-speed communication status signal from the first level to the second level.

[0115] Then, the low-speed communication circuit 510 may re-receive the low-speed communication clock signal from the data processing device 140 .

[0116] When power is supplied to the data driving device 120, the low-speed communication circuit 510 may be enabled by the control of the reception control circuit 530. Figure 4 When the low-speed communication mode ends in the CFG completion section shown, the low-speed communication circuit 510 may be disabled by the control of the reception control circuit 530 .

[0117] When the low-speed communication mode ends and the high-speed communication mode HS mode starts, the high-speed communication circuit 520 may be enabled by the control of the reception control circuit 530 .

[0118] Then, the high-speed communication circuit 520 can perform high-speed communication with the data processing device 140 via the first communication line LN1. In this way, the high-speed communication circuit 520 can receive the image data signal from the data processing device 140. For example, the high-speed communication circuit 530 can Figure 4 The display segment DP shown receives the image data signal.

[0119] The high-speed communication circuit 520 may process the image data signal into image data.

[0120] High-speed communication circuit 520 may include an equalizer 522 , a clock recovery circuit 524 , and a parallelization circuit 526 .

[0121] The high-speed communication circuit 520 may receive a high-speed communication clock signal from the data processing device 140 before receiving the image data signal in the high-speed communication mode. Figure 4The high speed communication clock signal is received in the clock training section shown.

[0122] The high-speed communication circuit 520 may perform high-speed clock training using the high-speed communication clock signal, and adjust the level of the high-speed communication status signal CDR_L according to the result of the high-speed clock training to output the level to the lock control circuit 540 .

[0123] For example, when the high-speed communication circuit 520 completes the high-speed clock training, the high-speed communication circuit 520 may output a high-speed communication status signal of a first level. When the high-speed communication circuit 520 does not complete (fail) the high-speed clock training, the high-speed communication circuit 520 may output a high-speed communication status signal of a second level. Here, the high-speed communication status signal may be output from the clock recovery circuit 524.

[0124] In an embodiment, the section in the high-speed communication mode may be one or more of a clock recovery circuit tuning section (CDR Tuning) and an equalizer tuning section (EQ Tuning) before the clock training section.

[0125] The high-speed communication circuit 520 may receive a clock recovery circuit tuning signal from the data processing device 140 in a clock recovery circuit tuning section prior to the clock training section.

[0126] The clock recovery circuit tuning signal may include, for example, Figure 6 The clock recovery circuit 524 included in the high-speed communication circuit 520 can change the setting value of the oscillator every predetermined time Ts when performing high-speed clock training.

[0127] When the clock recovery circuit 524 changes the setting value of the oscillator every predetermined time Ts, as shown in FIG. Figure 7 The cycle of the feedback clock FEB_CLK for high-speed clock training shown may be changed every predetermined time Ts. Here, the feedback clock may be obtained by multiplying the cycle of the oscillation clock output from the oscillator by a predetermined ratio.

[0128] The clock recovery circuit 524 may process the high-speed communication clock into an input clock IN_CLK, detect a phase difference between the input clock and the feedback clock at every predetermined time Ts, determine a result of high-speed clock training according to the phase difference, and adjust the level of the high-speed communication status signal to a first level or a second level according to the result of high-speed clock training. Here, the input clock IN_CLK may have a period obtained by multiplying the period of the high-speed communication clock by a predetermined ratio.

[0129] According to an embodiment, the oscillator included in the clock recovery circuit 524 can be any one of a current-controlled oscillator and a voltage-controlled oscillator, and the setting value of the oscillator can include a current value of a reference current input into the current-controlled oscillator or a voltage value of a reference voltage input into the voltage-controlled oscillator.

[0130] The high-speed communication circuit 520 may receive an equalizer tuning signal from the data processing device 140 in the equalizer tuning section before the clock training section.

[0131] Here, the equalizer tuning signal may include Figure 8 The tuning sequence shown is repeated every time period Tp. The tuning sequence may include a flag signal Flag for indicating the division of the time period, an EQ clock training signal EQCP arranged at the end of the flag signal, and an EQ test signal EQTP arranged at the end of the EQ clock training signal. Here, the communication frequency of the EQ clock training signal may be the same as the communication frequency of the high-speed communication clock signal.

[0132] exist Figure 5 In the case where an AC coupling capacitor (not shown) is added to the first communication line LN1, the flag signal may be a signal having a frequency lower than the communication frequency of the EQ clock training signal, and in which Fig.9A As shown, the first level (eg, high level) and the second level (eg, low level) alternate with each other.

[0133] exist Figure 5 In the case where no AC coupling capacitor (not shown) is added to the first communication line LN1, the flag signal may be as follows: Fig. 9B A signal with a uniform level (eg, a high level) is shown.

[0134] The EQ test signal EQTP may include a pseudo-random binary sequence (PRBS) pattern. The PRBS pattern may be implemented as a PRBS7 pattern, a PRBS9 pattern, a PRBS10 pattern, or the like.

[0135] Alternatively, the EQ test signal EQTP may include test data encoded in a DC balance code method. The test data encoded in a DC balance code method may include a plurality of code groups, wherein the number of "0" and "1" is the same in each code group.

[0136] The high-speed communication circuit 520 may change the setting of the equalizer 522 in each time period according to the plurality of EQ setting information during the plurality of time periods in which the equalizer tuning signal is received. Here, the clock recovery circuit 524 of the high-speed communication circuit 520 may repeatedly perform the following operation in each time period, which is used to initialize the trained clock when the flag signal is received, and then perform high-speed clock training using the EQ clock training signal.

[0137] Each of the plurality of EQ setting information may include a gain level of the equalizer 522, and may also include the number of taps of the equalizer 522. Such a plurality of EQ setting information may be included in the setting data, and the reception control circuit 530 may extract the plurality of EQ setting information from the stored setting data.

[0138] According to an embodiment, the clock recovery circuit 524 of the high-speed communication circuit 520 may repeatedly perform high-speed clock training in the clock recovery circuit tuning section and the equalizer tuning section.

[0139] Therefore, the clock recovery circuit 524 can alternately output the high-speed communication status signal of the first level and the second level in the clock recovery circuit tuning section and the equalizer tuning section.

[0140] The reception control circuit 530 may control operations of the low-speed communication circuit 510 and the high-speed communication circuit 520 .

[0141] In other words, when power is applied to the data driving device 120 , the reception control circuit 530 may enable the low-speed communication circuit 510 by transmitting the enable information LS_E to the low-speed communication circuit 510 .

[0142] In this way, low-speed data communication via the first communication line LN1 can be performed.

[0143] The reception control circuit 530 may establish a high-speed communication environment according to the setting data transmitted from the low-speed communication circuit 510. Here, the reception control circuit 530 may establish the equalizer 522 according to the basic gain level of the equalizer 522 included in the setting data.

[0144] Then, the reception control circuit 530 may enable the equalizer 522 , the clock recovery circuit 524 , and the parallelization circuit 526 by transmitting enable information HS_E to the high-speed communication circuit 520 .

[0145] In this way, high-speed data communication via the first communication line LN1 can be performed.

[0146] Here, the reception control circuit 530 may optimize the setting of the clock recovery circuit 524 through the tuning process of the clock recovery circuit 524 in the clock recovery circuit tuning section.

[0147] In other words, the reception control circuit 530 can check the result of the high-speed clock training of the clock recovery circuit 524 in each time period. Figure 7 There are multiple time periods (eg, Ts1 to Ts4) as shown, and in the event that there is a time period in which the clock recovery circuit 524 completes high-speed clock training, the reception control circuit 530 may tune the oscillator according to a setting value corresponding to the time period.

[0148] In the case where there are two or more time periods in which the clock recovery circuit 524 completes the high-speed clock training, the reception control circuit 530 may tune the oscillator at a median value of two or more setting values ​​corresponding to the two or more time periods.

[0149] The reception control circuit 530 may optimize the settings of the equalizer 522 through such tuning processing of the equalizer 522 in the equalizer tuning section.

[0150] In other words, the receiving control circuit 530 can evaluate the receiving performance of the high-speed communication circuit 520 for receiving the equalizer tuning signal in multiple time periods in each time period, and then tune the equalizer 522 using the EQ setting information corresponding to the time period in which the high-speed communication circuit 520 has the best receiving performance.

[0151] Here, the reception control circuit 530 may calculate the bit error rate of the EQ test signal related to the PRBS pattern in each time period, and tune the equalizer 522 using the EQ setting information corresponding to the time period in which the bit error rate is the lowest.

[0152] The reception control circuit 530 may check for errors in the test data included in the EQ test signal in each time period and tune the equalizer 522 using the EQ setting information corresponding to the time period in which the minimum error occurs.

[0153] According to an embodiment, the reception control circuit 530 may deactivate the low-speed communication circuit 510 by transmitting disable information to the low-speed communication circuit 510 when transmitting the enable information HS_E to the high-speed communication circuit 520 .

[0154] Before the low-speed communication circuit 510 completes the low-speed clock training, that is, before the locking control circuit 540 receives a first-level low-speed communication status signal from the low-speed communication circuit 510, the locking control circuit 540 can generate a second-level locking signal and send it to the locking monitoring circuit 640 in the data processing device 140.

[0155] Upon receiving the low-speed communication status signal of the first level from the low-speed communication circuit 510, the lock control circuit 540 may change the level of the lock signal to the first level and transmit it to the data processing device 140. Here, the level may mean a voltage level.

[0156] After the level of the lock signal is changed to the first level in the low-speed communication mode, in the case where there is an abnormality in the low-speed data communication between the low-speed communication circuit 510 and the data processing device 140, the lock control circuit 540 may receive a low-speed communication status signal of the second level from the low-speed communication circuit 510. In this case, the lock control circuit 540 may change the level of the lock signal to the second level and send it to the data processing device 140.

[0157] As described above, in the low-speed communication mode, the lock control circuit 540 may change the level of the lock signal to the same level as that of the low-speed communication condition signal.

[0158] On the other hand, the lock control circuit 540 may maintain the level of the lock signal from the end of the low-speed communication mode until the clock training section.

[0159] The reason is that, in the high-speed communication mode, the locking control circuit 540 may receive a high-speed communication status signal whose level alternately changes to the first level or the second level from the clock recovery circuit 524 of the high-speed communication circuit 520 in the clock recovery circuit tuning section or the equalizer tuning section before the clock training section, and if the locking control circuit 540 frequently changes the level of the locking signal according to the level of the high-speed communication status signal, the possibility of locking signal sending errors increases.

[0160] For example, the clock recovery circuit 524 may change the setting value of the oscillator at every predetermined time when performing high-speed clock training in the clock recovery tuning section before the clock training section. The clock recovery circuit 524 outputs a high-speed communication status signal of a first level when the high-speed clock training is completed, and outputs a high-speed communication status signal of a second level when the high-speed clock training is not completed. However, regardless of the level of the high-speed communication status signal input from the clock recovery circuit 524, the locking control circuit 540 may maintain the level of the locking signal at the first level.

[0161] For another example, the clock recovery circuit 524 may repeatedly perform clock initialization and high-speed clock training multiple times in the equalizer tuning section before the clock training section to perform equalizer tuning. The clock recovery circuit 524 outputs a high-speed communication status signal of the second level during clock initialization, and outputs a high-speed communication status signal of the first level when the high-speed clock training is completed. However, regardless of the level of the high-speed communication status signal input from the clock recovery circuit 524, the locking control circuit 540 can maintain the level of the locking signal at the first level.

[0162] The lock control circuit 540 may maintain the level of the lock signal until the clock training section, and change the level of the lock signal to be the same as the level of the high-speed communication status signal after the clock training section.

[0163] Specifically, if the level of the high-speed communication status signal input into the lock control circuit 540 immediately after the clock training section is the first level, the lock control circuit 540 may maintain the lock signal at the first level. If the level of the high-speed communication status signal input into the lock control circuit 540 immediately after the clock training section is the second level, the lock control circuit 540 may change the level of the lock signal to the second level and send the lock signal to the data processing device 140.

[0164] refer to Figure 5 , the data processing device 140 may include a lock monitoring circuit 610 , a transmission control circuit 620 , a serialization circuit 630 , and a transmission circuit 640 .

[0165] The lock monitoring circuit 610 may receive a lock signal from the data driving device 120 and check a level of the lock signal. Here, the lock monitoring circuit 610 may receive the lock signal via the second communication line LN2.

[0166] According to an embodiment, in a case where the display device 100 includes a plurality of data driving devices and the second communication line LN2 is connected in a cascade method, the number of data driving devices to be connected to the lock monitoring circuit 610 may be one.

[0167] When power is supplied to the data processing device 140 , the transmission control circuit 620 may enable the low-speed communication mode.

[0168] Then, the transmission control circuit 620 may use the transmission circuit 640 to transmit the low-speed communication clock signal to the data driving device 120 .

[0169] When the lock monitoring circuit 610 confirms that the level of the lock signal changes from the second level to the first level during the transmission of the low-speed communication clock signal, the transmission control circuit 620 can use the transmission circuit 640 to send a setting data signal including the setting data to the data driving device 120. Here, the low-speed communication clock signal and the setting data signal can be the second protocol signal PS2. In the case of adding an AC coupling capacitor to the first communication line LN1, the transmission control circuit 620 can use a DC balance code to encode the low-speed communication clock signal and the setting data signal, and the DC balance code can be any one of a Manchester code and an 8B10B code.

[0170] After the transmission circuit 640 transmits the setting data signal, the transmission control circuit 620 may generate a second protocol signal PS2 including a message indicating the end of the low-speed communication mode, and transmit the second protocol signal PS2 to the data driving device 120 using the transmission circuit 640. In this way, the transmission control circuit 620 may end the low-speed communication mode.

[0171] When the lock monitoring circuit 610 confirms that the level of the lock signal is maintained at the first level, the transmission control circuit 620 may enable the high-speed communication mode and transmit the high-speed communication clock signal as the first protocol signal PS1 to the data driving device 120 using the transmission circuit 640 .

[0172] Specifically, when the lock monitoring circuit 610 confirms that the level of the lock signal is maintained at the first level from the time point when the level of the lock signal changes to the first level until the sending circuit 640 completes the sending of the setting data signal, the sending control circuit 620 can determine that the data driving device 120 is in a normal condition.

[0173] In this case, the transmission control circuit 620 may enable the high-speed communication mode.

[0174] In addition, when the lock monitoring circuit 610 confirms that the level of the lock signal is maintained at the first level until a predetermined time has passed from the time point when the high-speed communication mode is enabled, the transmission control circuit 620 may determine that the data driving device 120 is in a normal situation.

[0175] In this case, the transmission control circuit 620 may generate a high-speed communication clock signal and transmit the high-speed communication clock signal to the data driving device 120 using the transmission circuit 640 .

[0176] When the lock signal received and checked by the lock monitoring circuit 610 has a first level after transmitting the high-speed communication clock signal, the transmission control circuit 620 may transmit the first protocol signal including image data and control data to the data driving device 120 using the transmission circuit 640 .

[0177] On the other hand, according to an embodiment, the transmission control circuit 620 may generate one or more signals to cause high-speed clock training to be repeated in the data driving device 120 before transmitting the high-speed communication clock signal in the high-speed communication mode, and transmit the one or more signals to the data driving device 120 using the transmission circuit 640. Here, the one or more signals may include a clock recovery circuit tuning signal and an equalizer tuning signal, and the transmission control circuit 620 may start transmitting the signal using the transmission circuit 640 immediately after the high-speed communication mode has been enabled, and end transmitting the signal when a predetermined amount of time has passed from the start.

[0178] In the event that the transmission circuit 640 transmits one or more signals to the data driving circuit 120 for a predetermined amount of time, the data driving circuit 120 may transmit a lock signal fixed at a first level to the lock monitoring circuit 610 .

[0179] Therefore, if the lock monitoring circuit 610 confirms that the level of the lock signal is maintained at the first level until a predetermined amount of time has passed from the point in time when the high-speed communication mode has been enabled, the transmission control circuit 620 can determine that the data driving device 120 is in a normal situation.

[0180] In other words, when the level of the lock signal is maintained at the first level from the start of transmission of one or more signals until the end thereof, the transmission control circuit 620 may determine that the data driving device 120 is in a normal situation.

[0181] Conversely, if the lock monitoring circuit 610 does not receive any lock signal or the received lock signal does not have the first level until a predetermined amount of time has passed from the time point when the high-speed communication mode has been enabled, the transmission control circuit 620 can determine that the data driving device 120 is in an abnormal situation.

[0182] In this case, the transmission control circuit 620 may re-enable the low-speed communication mode and transmit the low-speed communication clock signal and the setting data signal to the data driving device 120 using the transmission circuit 640 .

[0183] The serialization circuit 630 may convert the signal in the form of parallel data among the second protocol signal PS2 and the first protocol signal PS1 generated by the transmission control circuit 620 into a signal in the form of serial data, and transmit the signal to the transmission circuit 640 .

[0184] The transmission circuit 640 may be connected to the data driving device 120 via the first communication line LN1. Through this line, the transmission circuit 640 may transmit a low-speed communication clock signal and a setting data signal to the data driving device 120 in a low-speed communication mode.

[0185] The transmission circuit 640 may convert its mode into a high-speed communication mode (low-speed data communication→high-speed data communication) and transmit a high-speed communication clock signal to the data driving device 120 .

[0186] After transmitting the high-speed communication clock signal, the transmitting circuit 640 may transmit the first protocol signal including the image data and the control data to the data driving device 120 .

[0187] On the other hand, before transmitting the high-speed communication clock signal, the transmitting circuit 640 may transmit one or more signals for causing the high-speed clock training to be repeated in the data driving device 120 to the data driving device 120 .

[0188] The transmitting circuit 640 may include Figure 3 The first transmitting circuit and the second transmitting circuit are shown.

[0189] As described above, according to an embodiment, the data processing device 140 may send one or more signals for causing high-speed clock training to be repeated in the data driving device 120 before sending the high-speed communication clock signal to the data driving device 120. Here, the one or more signals may be one or more of a clock recovery circuit tuning signal and an equalizer tuning signal to optimize the high-speed communication environment of the data driving device 120.

[0190] The data driving device 120 may perform high-speed clock training multiple times using a clock recovery circuit tuning signal, and transmit a lock signal fixed at a first level regardless of the multiple high-speed clock trainings to the data processing device 140 .

[0191] In addition, the data driving device 120 may perform high-speed clock training multiple times using the equalizer tuning signal, and transmit a lock signal fixed at the first level regardless of the multiple high-speed clock trainings to the data processing device 140 .

[0192] In the case where the data driving device 120 continuously sends the lock signal of the first level, the data processing device 140 can determine that the data driving device 120 is in a normal situation according to a predetermined protocol. Therefore, even when the data driving device 120 repeats high-speed clock training to optimize the high-speed communication environment, the data processing device 140 can accurately determine the status of the data driving device 120, and this allows smooth high-speed data communication between the data processing device 140 and the data driving device 120.

[0193] CROSS-REFERENCE TO RELATED APPLICATIONS

[0194] This application claims priority to Korean Patent Application No. 10-2020-0026473, filed on Mar. 3, 2020, and Korean Patent Application No. 10-2020-0086030, filed on Jul. 13, 2020, which are hereby incorporated by reference in their entirety.

Claims

1. A data driving device, comprising: A low-speed communication circuit, configured to perform low-speed clock training using a low-speed communication clock signal received from a data processing device in a low-speed communication mode, and output a low-speed communication status signal of a first level after completing the low-speed clock training; a high-speed communication circuit for performing high-speed clock training using a high-speed communication clock signal received from the data processing device in a clock training section in a high-speed communication mode, and outputting the high-speed communication status signal after adjusting a level of the high-speed communication status signal according to a result of the high-speed clock training; as well as A lock control circuit is used to generate a lock signal based on the low-speed communication status signal and the high-speed communication status signal to send the lock signal to the data processing device, and maintain the level of the lock signal from the end of the low-speed communication mode until the clock training section in the high-speed communication mode.

2. The data driving device according to claim 1, wherein: The locking control circuit sends the locking signal of the second level before the low-speed communication circuit completes the low-speed clock training, changes the level of the locking signal to the first level to send the locking signal to the data processing device when the low-speed communication status signal received from the low-speed communication circuit is at the first level, and sends the locking signal fixed at the first level from the end of the low-speed communication mode until the clock training section.

3. The data driving device according to claim 1, wherein: The lock control circuit generates the lock signal according to the low-speed communication status signal in the low-speed communication mode and according to the high-speed communication status signal after the clock training section in the high-speed communication mode.

4. The data driving device according to claim 1, wherein: The high-speed communication circuit includes a clock recovery circuit and an equalizer, the clock recovery circuit performs high-speed clock training, and then the high-speed communication status signal is output to the lock control circuit.

5. The data driving device according to claim 4, wherein: In the equalizer tuning section before the clock training section, the clock recovery circuit repeatedly performs clock initialization and high-speed clock training for equalizer tuning, wherein the clock recovery circuit outputs the high-speed communication status signal of the second level during the clock initialization, and outputs the high-speed communication status signal of the first level when the high-speed clock training is completed.

6. The data driving device according to claim 5, wherein: In the equalizer tuning section, the lock control circuit transmits the lock signal fixed at a first level regardless of changes in the level of the high-speed communication status signal received from the clock recovery circuit to the data processing device.

7. The data driving device according to claim 4, wherein: The clock recovery circuit includes an oscillator, and in a clock recovery circuit tuning section before the clock training section, the clock recovery circuit changes a setting value of the oscillator at every predetermined time during high-speed clock training, outputs the high-speed communication status signal of a first level when the high-speed clock training is completed, and outputs the high-speed communication status signal of a second level when the high-speed clock training is not completed.

8. The data driving device according to claim 7, wherein: The lock control circuit transmits the lock signal fixed to a first level regardless of changes in the level of the high-speed communication status signal received from the clock recovery circuit to the data processing device.

9. The data driving device according to claim 7, wherein: The oscillator is one of a current controlled oscillator and a voltage controlled oscillator, and the set value includes a current value of a reference current input to the current controlled oscillator or a voltage value of a reference voltage input to the voltage controlled oscillator.

10. The data driving device according to claim 1, wherein: In the low-speed communication mode, after the low-speed communication circuit outputs the low-speed communication status signal of the first level, in the event of any abnormality in the low-speed communication with the data processing device, the low-speed communication circuit changes the level of the low-speed communication status signal from the first level to the second level and outputs the signal, and the locking control circuit changes the level of the locking signal to the second level and sends the locking signal to the data processing device.

11. The data driving device according to claim 1, wherein: In a case where the high-speed communication status signal input into the locking control circuit immediately after the clock training section has a first level, the locking control circuit maintains the level of the locking signal at the first level, and in a case where the high-speed communication status signal input into the locking control circuit immediately after the clock training section has a second level, the locking control circuit changes the level of the locking signal to the second level and sends the locking signal to the data processing device.

12. A data processing device, comprising: A lock monitoring circuit, configured to receive a lock signal from a data driving device and check a level of the lock signal; a transmitting circuit for transmitting a low-speed communication clock signal and a setting data signal to the data driving device in a low-speed communication mode, and then transmitting a high-speed communication clock signal to the data driving device after changing the mode to a high-speed communication mode, wherein the setting data signal includes data for setting a high-speed communication environment in the data driving device; as well as A control circuit for enabling the low-speed communication mode to send the low-speed communication clock signal using the sending circuit when power is supplied, sending the setting data signal using the sending circuit after the lock monitoring circuit confirms that the level of the lock signal changes from the second level to the first level when the sending circuit sends the low-speed communication clock signal, and enabling the high-speed communication mode to send the high-speed communication clock signal using the sending circuit when the lock monitoring circuit confirms that the level of the lock signal is maintained at the first level.

13. The data processing apparatus according to claim 12, wherein: In the high-speed communication mode, the control circuit uses the transmission circuit to transmit one or more signals for causing high-speed clock training to be repeated in the data driving device before using the transmission circuit to transmit the high-speed communication clock signal.

14. The data processing apparatus according to claim 13, wherein: When the lock monitoring circuit confirms that the level of the lock signal is maintained at the first level from the start to the end of the transmission of the one or more signals, the control circuit transmits the high-speed communication clock signal using the transmission circuit.

15. The data processing apparatus according to claim 12, wherein: When the lock monitoring circuit confirms that the level of the lock signal is maintained at the first level from the time point when the level of the lock signal changes to the first level until the time point when the sending circuit completes the sending of the setting data signal, the control circuit enables the high-speed communication mode, and when the lock monitoring circuit confirms that the level of the lock signal is maintained at the first level until a predetermined amount of time has passed from the time point when the high-speed communication mode is enabled, the control circuit uses the sending circuit to send the high-speed communication clock signal.

16. A system comprising: a data processing device for enabling a low-speed communication mode to transmit a low-speed communication clock signal and then transmitting a setting data signal when power is supplied, and enabling a high-speed communication mode to transmit a high-speed communication clock signal if a lock signal of a first level is continuously received, wherein the data processing device transmits the setting data signal if the lock signal of the first level is received during the transmission of the low-speed communication clock signal; and A data driving device is used to receive the low-speed communication clock signal to perform low-speed clock training, send the locking signal of the first level to the data processing device when the low-speed clock training is completed, and receive the high-speed communication clock signal to perform high-speed clock training, wherein the data driving device continuously sends the locking signal of the first level to the data processing device from the time the setting data signal is received in the low-speed communication mode until the high-speed clock training is performed.

17. The system of claim 16, wherein: The data driving device includes a clock recovery circuit and an equalizer, and the data processing device sends one or more of a clock recovery circuit tuning signal and an equalizer tuning signal to the data driving device before sending the high-speed communication clock signal in the high-speed communication mode.

18. The system of claim 17, wherein: The clock recovery circuit tuning signal includes a high-speed communication clock, and the data driving device performs high-speed clock training multiple times when tuning the clock recovery circuit using the clock recovery circuit tuning signal, wherein the data driving device sends the lock signal fixed at a first level regardless of the multiple high-speed clock trainings to the data processing device.

19. The system of claim 17, wherein: The equalizer tuning signal includes a high-speed communication clock, and the data driving device performs high-speed clock training multiple times when tuning the equalizer using the equalizer tuning signal, wherein the data driving device sends the lock signal fixed at a first level regardless of the multiple high-speed clock trainings to the data processing device.

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