Semiconductor structure and method of forming a semiconductor structure

Abstract

The semiconductor structure includes: a semiconductor substrate; a fin active region protruding above the semiconductor substrate; and a gate stack disposed on the fin active region, wherein the gate stack includes a high-k dielectric material layer and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a cross-sectional view, has a first dimension D1 at the top surface, has a second dimension D2 at the bottom surface, and has a third dimension D3 at a position between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3. Embodiments of the present application also relate to a method of forming a semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming semiconductor structures. Background Art

[0002] In advanced technology nodes of the integrated circuit industry, high-k dielectric materials and metals are used to form gate stacks of field effect transistors (FETs) such as metal oxide semiconductor field effect transistors (MOSFETs). In existing methods of forming metal gate stacks, metal gates are formed in a gate replacement process in which a dummy gate is removed and a gate material is filled in a gate trench. Due to high packaging density and small component sizes, achieving proper gap filling and profile control is challenging, especially for FETs with 3D structures, such as 3D fin field effect transistors (FINFETs). In addition, device performance and product yield are challenged. Therefore, a structure of a metal gate stack and a method for manufacturing the same are needed to address the above problems. Summary of the invention

[0003] Some embodiments of the present application provide a semiconductor structure, comprising: a semiconductor substrate; a fin active region protruding above the semiconductor substrate; and a gate stack disposed on the fin active region, wherein the gate stack comprises a high-k dielectric material layer and various metal layers disposed on the high-k dielectric material layer, wherein the gate stack comprises an uneven profile in a cross-sectional view, wherein a first dimension D1 is provided at a top surface, a second dimension D2 is provided at a bottom surface, and a third dimension D3 is provided at a position between the top surface and the bottom surface, and wherein each of D1 and D2 is larger than D3.

[0004] Other embodiments of the present application provide a semiconductor structure, including: a semiconductor substrate; a first fin active region and a second fin active region, formed on the semiconductor substrate, surrounded by an isolation component and protruding above the isolation component, wherein the first fin active region and the second fin active region are oriented in a first direction and spaced apart in a second direction substantially orthogonal to the first direction; and a gate stack, oriented in the second direction and extending above the first fin active region and the second fin active region, wherein the gate stack includes a segment in the interval between the first fin active region and the second fin active region, and the segment of the gate stack has an hourglass shape in a cross-sectional view and a gourd shape in a top view.

[0005] Some other embodiments of the present application provide a method for forming a semiconductor structure, comprising: forming a fin active region on a semiconductor substrate; depositing a dummy gate material layer on the fin active region and the semiconductor substrate; performing a first etching process on the dummy gate material layer to form a patterned gate material layer; performing surface modification by injecting into the sidewalls of the patterned gate material layer; and thereafter, performing a second etching process on the patterned gate material layer to form a patterned gate stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for the sake of clarity of discussion, the size of the various components can be arbitrarily increased or reduced.

[0007] Figure 1 and Figure 2 is a perspective view of a semiconductor structure at various stages of fabrication constructed according to various aspects of the present disclosure in some embodiments.

[0008] Figure 3A and Figure 3B are perspective and cross-sectional views of semiconductor structures at stages of fabrication constructed according to various aspects of the present disclosure in some embodiments.

[0009] Figure 4A is a perspective view of a semiconductor structure constructed according to various aspects of the present disclosure in some embodiments.

[0010] Figure 4B , Figure 4C , Figure 4D and Figure 4E is a device in various stages of manufacture constructed in accordance with various aspects of the present invention in some embodiments Figure 4A Cross-sectional view of a semiconductor structure.

[0011] Figure 4F In some embodiments, the invention is constructed according to various aspects of the invention. Figure 4E Partial cross-sectional view of a semiconductor structure.

[0012] Figure 5 is a perspective view of a semiconductor structure at a stage of fabrication constructed according to various aspects of the present disclosure in some embodiments.

[0013] Fig. 6A and Figure 6B are perspective and cross-sectional views of semiconductor structures at stages of fabrication constructed according to various aspects of the present disclosure in some embodiments.

[0014] Figure 7is a cross-sectional view of a semiconductor structure at a stage of fabrication constructed in accordance with various aspects of the present disclosure in some embodiments.

[0015] Fig. 8A , Figure 8B and Figure 8C are perspective and cross-sectional views of semiconductor structures at stages of fabrication constructed according to various aspects of the present disclosure in some embodiments.

[0016] Fig. 9A and Fig. 9B are top view and perspective views of a semiconductor structure at stages of fabrication constructed according to various aspects of the present disclosure in some embodiments.

[0017] Fig. 9C In some embodiments, the invention is constructed according to various aspects of the invention. Fig. 9A Partial top view of a semiconductor structure.

[0018] Fig.9D In some embodiments, the invention is constructed according to various aspects of the invention. Fig. 9A A partial three-dimensional image of a semiconductor structure.

[0019] Fig.9E and Fig.9F In some embodiments, the invention is constructed according to various aspects of the invention. Fig. 9A Partial top view and cross-sectional view of a semiconductor structure.

[0020] Fig. 10A is a top view of a semiconductor structure constructed according to various aspects of the present disclosure in some embodiments.

[0021] Fig. 10B , Fig. 10C , Fig. 10D and Fig.10E In some embodiments, the invention is constructed according to various aspects of the invention. Fig. 10A Partial cross-sectional view of a semiconductor structure.

[0022] Fig. 10B 'and Fig. 10C ' is constructed according to various aspects of the present invention in some embodiments Fig. 10A Partial top view of a semiconductor structure.

[0023] Fig.11 is a flow chart of a method of fabricating a semiconductor structure according to some embodiments.

[0024] Fig. 12A and Fig. 12B shows a structure constructed according to some embodiments Fig. 9A A cross-sectional view of a gate stack.

[0025] Fig.13 is a cross-sectional view of a semiconductor structure constructed according to various aspects of the present disclosure in some embodiments. DETAILED DESCRIPTION

[0026] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0027] In addition, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or other) elements or components as shown in the figures. In addition to the orientation shown in the figures, spatially relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. In addition, when "about," "approximately," etc. are used to describe a value or a range of values, the term is intended to cover values ​​within + / - 10% of the described value, unless otherwise stated. For example, the term "about 5nm" covers a size range from 4.5nm to 5.5nm.

[0028] The present invention provides various embodiments of a semiconductor structure having a fin active region and a field effect transistor (FET) formed on the fin active region, which transistors are also referred to as fin FETs (FinFETs). In particular, the semiconductor structure having a FinFET includes a gate stack having an uneven cross-section and a top view. More specifically, the gate stack includes a segment in the interval between two adjacent fin active regions, and the segment of the gate stack has an hourglass shape in a cross-sectional view and a gourd shape in a top view. The present invention also provides a method for manufacturing the same according to some embodiments. The disclosed semiconductor structure and its manufacturing method provide better gate fill windows, production yield gains, and device performance enhancements, including reduced parasitic capacitance and gate control enhancements.

[0029] Figures 1 to 10E are perspective, cross-sectional, and top views of a semiconductor structure 100 at various stages of fabrication constructed in accordance with some embodiments. Fig.11is a flow chart of one embodiment of a method 200 of fabricating a semiconductor structure 100 . Fig. 12A and Fig. 12B is a cross-sectional view of a gate stack in a semiconductor structure 100 constructed according to various embodiments. Fig.13 is a cross-sectional view of a semiconductor structure 100 constructed according to some embodiments. Figures 1 to 13 A semiconductor structure 100 and a method 200 of manufacturing the same are collectively described.

[0030] The method 200 begins at 202 by providing a semiconductor structure 100 having a semiconductor substrate 102. The semiconductor substrate 102 includes silicon. Optionally, the semiconductor substrate 102 includes germanium or silicon germanium. In other embodiments, the semiconductor substrate 102 may use another semiconductor material, such as diamond, silicon carbide, gallium arsenide, GaAsP, AlInAs, AlGaAs, GaInP, or other suitable combinations thereof.

[0031] The semiconductor substrate 102 also includes various doped regions such as n-wells and p-wells formed by appropriate techniques such as ion implantation. The semiconductor substrate 102 also includes various isolation features 108, such as shallow trench isolation (STI) features, formed in the substrate to define the active region 104 and to separate various devices on the active region. Forming the STI features may include: etching trenches in the substrate; and filling the trenches with insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The filled trenches may have a multi-layer structure, such as a thermal oxide liner layer with silicon nitride filling the trenches. In one embodiment, the STI features may be created using a processing sequence such as the following: growing a pad oxide; forming a low pressure chemical vapor deposition (LPCVD) nitride layer; patterning the substrate using a photoresist and a mask to form a trench; etching a trench in the substrate; optionally growing a thermal oxide trench liner to improve the trench interface; filling the trenches with silicon oxide by chemical vapor deposition (CVD); and using chemical mechanical planarization (CMP) for polishing and planarization.

[0032] In some embodiments, the top surface of semiconductor substrate 102 and the top surface of STI features 108 are substantially coplanar, thereby producing a common top surface. This is referred to as a planar structure. In some embodiments, the top surface of semiconductor substrate 102 and the top surface of STI features 108 are not coplanar, thereby producing a three-dimensional structure, such as Figure 1The fin structure 104 in the semiconductor structure 100 is shown. In the semiconductor structure 100, the active region 104 extends above the top surface of the STI component 108, and is therefore referred to as a fin structure or a fin active region. Therefore, various devices are formed on the fin structure 104. In particular, a field effect transistor (FET) is formed on the fin structure 104, and the corresponding gate of the FET is coupled to a channel from multiple surfaces (top surface and sidewalls) of the fin structure, thereby enhancing device performance. Therefore, the FET formed on the fin structure 104 is called a FinFET.

[0033] The disclosed semiconductor structure 100 and the method for manufacturing the same 200 thereof provide improvements to integrated circuits, particularly to FinFETs. The fin structure 104 may be formed by various techniques. In some embodiments, the fin structure 104 is formed by recessing the STI feature 108, such as by selective etching. In some other embodiments, the fin structure 104 is formed by selective epitaxial growth (SEG). In the SEG process, the fin structure 104 is formed using a semiconductor material (such as silicon) that is the same as the material of the substrate 102, or optionally a different semiconductor material (such as silicon germanium or silicon carbide) to further achieve other functions (e.g., strain effects). The fins may be patterned by any suitable method. For example, one or more lithography processes including double patterning or multiple patterning processes may be used to pattern the fins. Typically, the double patterning or multiple patterning processes combine lithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a pitch that is smaller than that obtainable using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed and the remaining spacers or mandrels can then be used to pattern the fins.

[0034] Still reference Figure 1 , various doped wells may be formed in one or more fin active regions 104. In some embodiments, the fin active region 104 is intended to form a FET, such as a p-type FET (pFET) or an n-type FET (nFET). In some instances, a pFET is formed on the fin active region 104, and the doped well includes an n-type dopant, such as phosphorus (P). In some other instances, an nFET is formed on the fin active region 104, and the doped well includes a p-type dopant, such as boron (B), distributed in the active region. Dopants may be introduced into the doped wells through openings in the mask layer by a suitable doping process such as one or more ion implantations. The STI features 108 are also used to confine dopants to the desired active regions. In some embodiments, nFETs and pFETs are formed on the substrate 102, such as in a complementary metal oxide semiconductor (CMOS) circuit.

[0035] The method 200 enters operation 204 by forming one or more gate stacks 110' on the semiconductor substrate 102. Since the gate stack 110' will be replaced by a metal gate stack at a later stage, it is also called a dummy gate stack 110'. The gate stack 110' may include a gate dielectric layer and a gate conductive layer. Forming the dummy gate stack 110' includes depositing a dummy gate material 110 and patterning the dummy gate material 110. Patterning also includes a photolithography process and etching. A hard mask layer can be further used to pattern the gate material 110. In particular, the disclosed method 200 forms a gate stack 110' having a specific gate profile (including shape, size, and ratio) for enhancing device performance and improving yield. Operation 204 includes a plurality of processing steps (or sub-operations) 220-232, and is further described in detail below according to some embodiments.

[0036] refer to Figure 2 , the method 200 includes an operation 220 to deposit one or more gate material layers (or gate materials) 110 on the fin active region 104 and the STI component 108. The top surface of the fin active region 104 is represented by the reference numeral 104a, which is located above the top surface of the STI component 108. A gate material layer 110 extending above the top surface 104a of the fin active region 104 is deposited on the fin active region 104 and the STI component 108. In the depicted embodiment, the gate material layer 110 includes a polysilicon layer, or alternatively includes a silicon oxide layer and a polysilicon layer on the silicon oxide layer. The silicon oxide layer can be formed by thermal oxidation, and the polysilicon layer can be formed by suitable deposition such as CVD, flowable CVD (FCVD). In one example, the polysilicon layer is undoped. In another example, the polysilicon layer has a thickness ranging between about 500 angstroms and about 1000 angstroms. After deposition, a chemical mechanical polishing (CMP) process may be applied to planarize the top surface.

[0037] refer to Figure 3A and Figure 3B, the method 200 may include an operation 222 to form a patterned mask layer 112 on the gate material layer 110 by deposition and photolithography processes. The patterned mask layer 112 is used as an etching mask for patterning the gate material layer 110. The patterned mask layer 112 defines various gate regions and includes various openings that expose portions of the gate material layer 110 to be removed. The patterned mask layer 112 includes a hard mask such as one or more dielectric materials, or alternatively includes a soft mask such as a photoresist. In the depicted embodiment, a patterned mask layer 112 including a silicon nitride film 112a and a silicon oxide film 112b on the silicon nitride film 112a is used, and 112a and 112b are collectively represented by the reference numeral 112. As an example, the silicon nitride film 112a and the silicon oxide film 112b can be deposited on the polysilicon layer by a low pressure chemical vapor deposition (LPCVD) process or other suitable deposition. The silicon nitride layer and the silicon oxide layer are further patterned using a patterning procedure. The patterning process may include a photolithography process to form a patterned photoresist layer 114 (eg, Figure 3A As shown), and an etching process to etch the silicon oxide film 112b and the silicon nitride film 112a in the opening of the patterned photoresist layer 114, thereby forming a patterned mask layer 112, as shown Figure 3B As shown. An exemplary photolithography process may include the processing steps of photoresist coating, soft baking, mask alignment, exposure, post-exposure baking, developing photoresist, and hard baking. The photolithography exposure process may also be implemented or replaced by other appropriate methods, such as maskless lithography, electron beam writing, ion beam writing, and molecular imprinting. The patterned photoresist layer 114 may be removed by a suitable method such as wet stripping or plasma ashing after forming the patterned mask layer 112. It should be noted that Figure 3A The patterned photoresist layer 114 is shown with only one exemplary rectangular feature, while the patterned mask layer 112 includes four exemplary features. These are for illustration only and are not intended to be limiting. Similar exemplary features are shown in the following figures without limitation.

[0038] refer to Figure 4A The method 200 further includes patterning the gate material layer 110 to form a gate stack 110'. One or more etching processes are applied to the gate material layer 110 through the openings of the patterned mask 112. The etching process may include dry etching, wet etching, other suitable etching, or a combination thereof. The method 200 includes a patterning procedure 121, which also includes a plurality of etching steps and a surface modification process intended to pattern the gate material 110 and to form a gate stack 110' having a gate profile with a desired geometry, size, and aspect ratio, such as 4A to 4F After gate replacement, the final metal gate stack has a gate profile including geometric shape, size and size ratio. Figure 4F is a cross-sectional view of a gate stack 110'. The gate stack 110' includes Figure 4F 104a of the fin active region 104 and a middle portion 110b and a lower portion 110c below the top surface of the fin active region 104. The upper portion 110a of the gate stack 110' has a height H1 in the range of 100nm to 150nm and spans a first width in the range of 10nm to 20nm. The middle portion 110b of the gate stack 110' has a height H2 in the range of 40nm to 80nm and spans a second width in the range of 10nm to 20nm at the bottom and a third width in the range of 10nm to 15nm at the top. The lower portion 110c of the gate stack 110' has a height H3 in the range of 20nm to 40nm. In some embodiments, the ratio H1 / H2 is in the range between 2.5 and 3.5, and the ratio H2 / H3 is in the range between 1.5 and 2. The minimum width of the gate stack 110' is located at the interface between the upper portion 110a and the middle portion 110b of the gate stack 110'. Figure 4B , Figure 4C , Figure 4D and Figure 4E The gate stack 110 ′ is further described along with the patterning procedure 121 including various etching processes (such as 224 , 228 , and 230 ) and surface modifications (such as 226 ). Figure 4B , Figure 4C , Figure 4D and Figure 4E 1 is a cross-sectional view of the semiconductor structure 100 cut along the X direction on the STI feature 108 at various manufacturing stages. Therefore, the gate material layer 110 includes some portions above the top surface 104a of the fin active region 104 and other portions below, such as Figure 4A shown.

[0039] refer to Figure 4B, the method 200 includes an operation 224 of performing a first etching process on the gate material layer 110, thereby producing a trench 126 formed in the gate material layer 110. In the depicted embodiment, the first etching process applies a first etchant including sulfur dioxide (SO2) and hydrogen (H2) in operation 224. In a further embodiment, the first etchant includes oxygen (O2), SO2, nitrogen (N2), and H2. The first etching process includes: a gas pressure in a range between 10atm and 500atm; an etching temperature in a range between 10°C and 120°C; an etching plasma power in a range between 5W and 1500W; and a carrier gas of argon (Ar). The first etching process is controlled to etch an upper portion of the gate material layer 110 above the top surface 104a of the fin active area 104, which can be controlled by etching duration or other suitable endpoint control methods.

[0040] refer to Figure 4C , the method 200 includes an operation 226 of performing a surface modification process on the sidewalls of the gate material layer 110 in the trench 126. The surface modification process is intended to modify the surface characteristics of the gate material layer 110 (e.g., polysilicon in the present embodiment), thereby forming a processed surface layer 128 of the gate material layer 110. More specifically, the surface modification process is intended to modify the surface of the gate material layer 110 so that it resists (or is not affected by) the subsequent etching process. In the depicted embodiment, the surface modification process introduces carbon (C), nitrogen (N2), or both into the sidewall surface of the gate material layer 110 in the trench 126 by ion implantation, thereby forming the processed surface layer 128. In the present embodiment, the processed surface layer 128 includes silicon and at least one of carbon and nitrogen. In some examples, the processed surface layer 128 includes silicon, carbon, and nitrogen. In some embodiments, the processed surface layer 128 has a thickness ranging between 0.5nm and 1nm. In some embodiments, during the ion implantation, the concentrations of N2 and carbon in the treated surface layer 128 are controlled by the partial pressures of the corresponding gases, such as controlling N2 with a partial pressure in the range of 5 mt (mTorr) to 10 mt and controlling the carbon-containing gas with a partial pressure in the range of 20 mt to 50 mt, thereby forming CF4. In some further embodiments, the ion implantation in operation 226 is performed with a total gas pressure in the range of 200 mt to 500 mt and a power in the range of 5 W to 1500 W. In some embodiments, the precursors in the ion implantation include HBr, Cl, N2, NF3, and CF4. In the depicted embodiment, the treated surface layer 128 extends downward from the top surface of the gate material layer 110 on the sidewalls of the gate material layer 110 to a level matching the top surface 104a of the fin active region 104.

[0041] refer to Figure 4D, the method 200 includes an operation 228 of performing a second etching process on the gate material layer 110. The second etching process is different from the first etching process because the second etching process uses a different etchant and is applied after the operation 226 of the surface modification process. The second etching process applies a second etchant including hydrogen bromide (HBr), chlorine (Cl) and fluorine (F) in operation 228. In a further embodiment, the second etchant includes HBr, Cl2, O2, N2, nitrogen fluoride (NF3) and fluorocarbon (CF4). The etchant of the second etching process is intended to selectively etch the gate material layer 110, while it does not substantially etch (or has minimal etching effect) the treated surface layer 128. In some embodiments, the etchant of the second etching process includes Br, Cl and F, and the treated surface layer 128 also includes Br, Cl and F, thereby increasing the etching resistance of the treated surface layer 128 to the second etching process. In some examples, the second etching process includes a gas pressure in a range between 10mt and 500mt; an etching temperature in a range between 10°C and 120°C; an etching plasma power in a range between 5W and 1500W; and a carrier gas of argon (Ar). In some examples, the second etching process includes gas flow rates: an HBr flow rate in a range between 10sccm and 1200sccm; a Cl2 flow rate in a range between 10sccm and 800sccm; an O2 flow rate in a range between 10sccm and 800sccm; an N2 flow rate in a range between 10sccm and 800sccm; an NF3 flow rate in a range between 10sccm and 800sccm; and a CF4 flow rate in a range between 10sccm and 200sccm. The second etching process extends the trench 126 below the top surface 104a of the fin active area 104. The second etching process is controlled to etch a lower portion of the gate material layer 110 below the top surface 104 a of the fin active region 104 .

[0042] In operation 228, first the processed surface layer 128 is penetrated at the bottom so that the second etching process can etch to the lower portion of the gate material layer 110 below the top surface 104a. This can be achieved by designing a second etching process with a directional etching effect toward the bottom. For example, the second etching process is designed to have a sufficiently large bias power to penetrate the processed surface layer 128 at the bottom without (or minimally) affecting the processed surface layer 128 on the sidewall of the gate material layer 110. In some embodiments, the second etching process has a bias power P2 greater than 50W or in the range of 50W to 1500W.

[0043] During the second etching process, the upper portion of the gate material layer 110 is protected by the treated surface layer 128, which resists the second etching process. Therefore, the second etching process etches down into the lower portion of the gate material layer 110 below the top surface 104a, while having no (or minimal) etching effect on the upper portion of the gate material layer 110, such as Figure 4D shown.

[0044] refer to Figure 4E , the method 200 includes an operation 230 of performing a third etching process on the gate material layer 110, thereby forming a gate stack 110'. The third etching process is designed to have a bias power lower than those of the first etching process and the second etching process and a high lateral etching rate. In particular, the bias power P3 of the third etching process is substantially lower than the bias power P2 of the second etching process, such as P3 is lower than 50W or in the range between 5W and 45W. In some embodiments, the ratio of P2 / P3 is in the range between 10 and 30. The third etching process applies a third etchant similar to the second etchant but with a lower bias power. In some embodiments, the third etchant includes hydrogen bromide (HBr), chlorine (Cl) and fluorine (F). In a further embodiment, the third etchant includes HBr, Cl2, O2, N2, nitrogen fluorine (NF3) and fluorocarbon (CF4). In some examples, the third etching process includes a gas pressure in a range between 10mt and 500mt; an etching temperature in a range between 10°C and 120°C; an etching plasma power in a range between 5W and 1500W; and a carrier gas of argon (Ar). In some examples, the third etching process includes gas flow rates: an HBr flow rate in a range between 10 and 1200sccm; a Cl2 flow rate in a range between 10sccm and 800sccm; an O2 flow rate in a range between 10sccm and 800sccm; an N2 flow rate in a range between 10sccm and 800sccm; an NF3 flow rate in a range between 10sccm and 800sccm; and a CF4 flow rate in a range between 0sccm and 200sccm. The third etching process is intended to laterally expand the trench 216 in a portion of the gate material layer 110 below the top surface 104a of the fin active region 104, thereby forming a gate stack 110' having an uneven profile.

[0045] During the third etching process, the upper portion of the gate material layer 110 is protected by the processed surface layer 128, and the third etching process has a limited etching effect on the upper portion of the gate material layer 110 and an enhanced lateral etching effect on the lower portion of the gate material layer 110, so that the trench 126 has the maximum lateral etching at a position flush with the top surface 104a of the fin active area 104. This is because the gate material at level 104a experiences more lateral etching in the trench 126 at level 104a between the upper portion 110a and the middle portion 110b, which behaves similarly to the top opening during the second etching process and the third etching process because the upper portion of the gate material layer 110 is substantially protected from etching by the processed surface layer 128. Therefore, the trench 126 has a profile with the maximum width at a position flush with the top surface 104a of the fin active area 104. Therefore, the gate stack 110' includes as Figure 4F Hourglass shape shown. Figure 4F The gate stack 110' in FIG. 1 is directly present on the STI feature 108, such as Figure 4A shown.

[0046] refer to Figure 5 The method 200 includes an operation 232 to form a gate spacer 122 on the sidewalls of the gate stack 110'. The gate spacer 122 includes one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or combinations thereof. The gate spacer 122 is formed by deposition (such as CVD) and anisotropic etching (such as plasma etching).

[0047] Still reference Figure 5 The method 200 includes operation 206 to form source and drain (S / D) features 116 on the fin active region 104. The S / D features 116 are formed on the fin active region 104 with the gate stack 110' interposed therebetween.

[0048] In some examples, the S / D component 116 includes a dopant introduced into the fin active region 104 by a suitable technique such as ion implantation. In one embodiment, the gate stack 110' is configured in an active region for an n-type field effect transistor (nFET), and the dopant of the S / D component 116 is an n-type dopant, such as phosphorus or arsenic. In another embodiment, the gate stack 110' is configured in an active region for a p-type field effect transistor (pFET), and the dopant of the S / D component 116 is a p-type dopant, such as boron or gallium. In yet another embodiment, the S / D component 116 includes a lightly doped drain (LDD) component and a heavily doped S / D component, collectively referred to as S / D components or simply source and drain 116. The LDD component and the heavily doped S / D component can be formed by corresponding ion implantation. One or more thermal annealing processes are then performed to activate the dopant.

[0049] In some embodiments, the S / D component 116 is formed by epitaxial growth to enhance device performance, such as for strain effects to enhance mobility. In further embodiments, forming the S / D component 116 includes: selectively etching the fin 104 in the S / D region to form a groove; and epitaxially growing one or more semiconductor materials in the groove to form the S / D component 116. The groove can be formed using a wet and / or dry etching process to selectively etch the semiconductor material of the fin active region 104. In further embodiments, the gate stack 110', the gate spacer 122 and the STI component 108 are used together as an etching hard mask to form a groove in the S / D region. In some instances, an etchant such as carbon tetrafluoride (CF4), chlorine (Cl2), other suitable etchants, or combinations thereof are used to form the groove.

[0050] Afterwards, the groove is filled with semiconductor material by epitaxially growing the S / D component 116 with a crystalline structure. Epitaxial growth may include in-situ doping to form S / D with appropriate dopants. In some embodiments, epitaxial growth is a selective deposition process including etching during epitaxial growth, so that the semiconductor material grows substantially on the semiconductor surface in the groove. In particular, the selective deposition process includes chlorine for etching effect, and the deposition is selective. The selective deposition process is designed and adjusted to epitaxially grow so that the S / D component 116 formed in the groove includes a semiconductor material with a crystalline structure. The semiconductor material of the S / D component 116 may be different from the semiconductor material of the fin active area 104. For example, the semiconductor material of the S / D component 116 includes silicon carbide or silicon germanium, while the fin active area 104 is a silicon component. In some embodiments, the semiconductor material of the S / D component 116 is selected to produce an appropriate strain effect in the channel region, so that the corresponding carrier mobility is increased. In one example, the active region 104 is configured for a pFET, the semiconductor material of the S / D feature 116 is silicon germanium doped with boron, and the fin active region 104 is a silicon feature. In another example, the active region 104 is configured for an nFET, the semiconductor material of the S / D feature 116 is silicon carbide doped with phosphorus, and the fin active region 104 is a silicon feature.

[0051] In yet another embodiment, a silicide feature may be further formed on the S / D feature 116 to reduce contact resistance. The silicide feature may be formed by a technique called self-aligned silicide (SASI), which includes: metal deposition (such as nickel deposition) on a silicon substrate; thermal annealing to react the metal with silicon to form silicide; and etching to remove unreacted metal.

[0052] refer to Fig. 6A and Figure 6B , the method 200 proceeds to operation 208 by forming an interlayer dielectric (ILD) layer 136 on the substrate and the gate stack 110'. The ILD 136 is deposited by an appropriate technique such as CVD, flowable CVD (FCVD) or other suitable deposition method. The ILD layer 136 includes one or more dielectric materials, such as silicon oxide, low-k dielectric materials, or a combination thereof. Then, a chemical mechanical polishing (CMP) process can be applied to planarize the surface of the ILD layer 136. In one example, the gate stack 110' is exposed by the CMP process for subsequent processing steps. In another example where the hard mask used to pattern the gate stack 110' is not removed in the previous operation, the CMP process also removes the hard mask. Optionally, the CMP process stops on the hard mask and the hard mask is then removed by an etching process.

[0053] refer to Figure 7, the method 200 proceeds to operation 210 by partially or completely removing the gate stack 110', thereby creating the gate trench 142. Operation 210 includes one or more etching steps to selectively remove the gate electrode layer or optionally the gate stack 110' by a suitable etching process such as one or more wet etches, dry etches, or combinations thereof.

[0054] refer to Fig. 8A , Figure 8B and Figure 8C The method 200 proceeds to operation 212 by filling various gate material layers in the gate trenches 142 , thereby forming a metal gate stack 146 in the gate trenches 142 . Fig. 8A The semiconductor structure 100 is shown in a perspective view. Figure 8B is a cross-sectional view of the semiconductor structure 100 cut over the isolation feature 108, and Figure 8C is a cross-sectional view of the semiconductor structure 100 cut above the fin active region 104. In particular, in some embodiments, the processed surface layer 128 is not removed and is present in the final gate stack 146. In this case, the processed surface layer 128 is inserted between the gate stack 146 and the gate spacer 122. The processed surface layer 128 extends from the top surface of the gate stack and does not exist below 104a. The processed surface layer 128 is different in composition from the gate stack 146 and the ILD layer 136. In the depicted embodiment, the gate stack 146 includes a high-k dielectric layer and various metal layers surrounded by a high-k dielectric layer (a layer to be described further); the ILD layer 136 includes an etch stop layer (such as silicon nitride), silicon oxide, or a low-k dielectric layer surrounded by an etch stop layer; and the processed surface layer 128 includes silicon, carbon, and nitrogen.

[0055] refer to Fig. 12A and Fig. 12B The gate stack 146 is further depicted in the cross-sectional view. In some embodiments, such as in a high-k last process, the gate material layer includes a gate dielectric layer 150 and a gate conductive layer (or gate electrode) 152. The gate dielectric layer 150 includes a high-k dielectric material, which may include a metal oxide, a metal nitride, a metal silicate, a transition metal oxide, a transition metal nitride, a transition metal silicate, a metal oxynitride, a metal aluminate, a zirconium silicate, or a zirconium aluminate, such as HfO2, ZrO2, ZrO x N y , HfO x N y 、HfSi x O y 、ZrSi x O y 、HfSi x Oy N z 、ZrSi x O y N z , Al2O3, TiO2, Ta2O5, La2O3, CeO2, Bi4Si2O12, WO3, Y2O3, LaAlO3, Ba 1-x Sr x TiO3, PbTiO3, BaTiO3, SrTiO3, PbZrO3, PST, PZN, PZT, PMN and combinations thereof.

[0056] The gate conductive layer 152 includes a metal. In some embodiments, the gate conductive layer 152 includes multiple layers, such as a capping layer, a work function metal layer, a barrier layer, and a fill metal layer (such as aluminum or tungsten). The gate material layer may further include an interface layer 148 between the active region 104 and the high-k dielectric material, such as silicon oxide. The interface layer 148 is part of the gate dielectric layer. The various gate material layers are filled in the gate trench 142 by deposition such as CVD, physical vapor deposition (PVD), plating, atomic layer deposition (ALD), or other suitable techniques.

[0057] The high-k dielectric layer 150 includes a dielectric material having a dielectric constant higher than the dielectric constant of thermal silicon oxide (about 3.9). The high-k dielectric layer 150 is formed by a suitable process such as ALD. Other methods of forming the high-k dielectric material layer include metal organic chemical vapor deposition (MOCVD), PVD or UV-ozone oxidation. In one embodiment, the high-k dielectric material includes HfO2. Optionally, the high-k dielectric material layer 150 includes a metal nitride, a metal silicate or other metal oxide.

[0058] exist Fig. 12A In one embodiment shown in the middle cross-sectional view, the gate electrode 152 includes a capping layer 152A, a barrier layer 152B, a work function metal layer 152C, another barrier layer 152D, and a filling metal layer 152E. In a further embodiment, the capping layer 152A includes titanium nitride, tantalum nitride, or other suitable materials formed by a suitable deposition technique such as ALD. The barrier layer 152B includes titanium nitride, tantalum nitride, or other suitable materials formed by a suitable deposition technique such as ALD.

[0059] The work function metal layer 152C includes a conductive layer of a metal or metal alloy having an appropriate work function, so that the device performance of the corresponding FET is enhanced. For pFET and nFET, which are respectively referred to as n-type WF metal and p-type WF metal, the work function (WF) metal layer 152C is different. The selection of WF metal depends on the FET to be formed on the active area 104. For example, the semiconductor structure 100 includes a first active area 104 for nFET and another active area for pFET, and therefore, n-type WF metal and p-type WF metal are formed in the corresponding gate stack, respectively. In particular, the n-type WF metal is a metal having a first work function, so that the threshold voltage of the associated nFET is reduced. The n-type WK metal is close to the silicon conduction band energy (Ec) or a lower work function, showing easier electron escape. For example, the n-type WF metal has a work function of about 4.2eV or less. The p-type WF metal is a metal having a second work function, so that the threshold voltage of the associated pFET is reduced. The p-type WF metal is close to the silicon valence band energy (Ev) or has a higher work function, showing strong electron bonding energy to the nucleus. For example, the p-type work function metal has a WF of about 5.2 eV or higher.

[0060] In some embodiments, the n-type WF metal includes tantalum (Ta). In other embodiments, the n-type WF metal includes titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), or a combination thereof. In other embodiments, the n-metal includes Ta, TiAl, TiAlN, tungsten nitride (WN), or a combination thereof. The n-type WF metal may include various metal-based films as stacked pieces for optimizing device performance and processing compatibility. In some embodiments, the p-type WF metal includes titanium nitride (TiN) or tantalum nitride (TaN). In other embodiments, the p-metal includes TiN, TaN, tungsten nitride (WN), titanium aluminum (TiAl), or a combination thereof. The p-type WF metal may include various metal-based films as stacked pieces for optimizing device performance and processing compatibility. The work function metal is deposited by a suitable technique such as PVD.

[0061] The barrier layer 152D includes titanium nitride, tantalum nitride or other suitable materials formed by a suitable deposition technique such as ALD. In various embodiments, the fill metal layer 152E includes aluminum, tungsten or other suitable metals. The fill metal layer 152E is deposited by a suitable technique such as PVD or plating.

[0062] In some embodiments, Fig. 12AThe gate stack 146 shown is formed by a high-k last process, and the high-k dielectric material layer 150 is U-shaped. Alternatively, the gate stack 146 is formed in a high-k first process, and the high-k dielectric material layer 150 (and the interface layer 148) are formed using the dummy gate stack 110' and remain in the metal gate stack 146. In this case, the shape of the high-k dielectric material layer 150 is different, such as Fig. 12B shown.

[0063] Method 200 includes other manufacturing operations 214 performed before, during, or after the above operations. For example, operation 214 includes forming an interconnect structure including various conductive components, such as contacts, metal lines, and vias, to electrically connect various components (such as gate electrodes and S / D components) to form an integrated circuit. An interconnect structure is formed on a substrate to couple various transistors and other devices to form a functional circuit. The interconnect structure includes various conductive components, such as metal lines for horizontal connections and contacts / vias for vertical connections. Various conductive materials including copper, tungsten, and silicide can be implemented in various interconnect components. In one example, a damascene process is used to form a copper-based multilayer interconnect structure. In another embodiment, tungsten is used to form a tungsten plug in a contact hole.

[0064] Reference in top view, perspective view or cross-section view Fig. 9A , Fig. 9B , Fig. 9C , Fig.9D , Fig.9E and Fig.9F , further describing the shape and profile of the gate stack 146. More specifically, Fig. 9A is a top view of the semiconductor structure 100 showing the gate stack 146 and the fin active region 104 . Fig. 9B is a perspective view of the semiconductor structure 100 showing the gate stack 146 , the fin active region 104 , and the isolation feature 108 . Fig. 9C is a top view of a portion 156 of the semiconductor structure 100 showing the gate stack 146 and the fin active region 104 . Fig.9D 1 is a perspective view of the semiconductor structure 100 showing the gate stack 146. In particular, the gate stack 146 includes a segment 158 ​​in the space between adjacent fin active regions 104. In some embodiments, the S / D features 116 in adjacent fin active regions 104 are merged together, such as Fig. 9A An exemplary S / D component 116 is shown in FIG. Fig.9E is a top view of the gate stack 146 in segment 158, and Fig.9F is a cross-sectional view of the gate stack 146 in segment 158 ​​.

[0065] The gate stack 146 formed by the disclosed method has a non-uniform profile in top view, such as Fig. 9C The gate stack 146 has a size (along the X direction) that varies from the edge of one fin active region 104 to the edge of another fin active region 104, with a minimum size in the middle between the two fin active regions. The cross section of the gate stack 146 also has a non-uniform profile, such as Fig.9F The gate stack 146 has a varying dimension (along the X direction) from the top surface to the bottom surface, with the smallest dimension at a height that is flush with the top surface 104 a of the fin active region 104 .

[0066] like Fig.9F As shown, the gate stack 146 has a non-uniform shape in a cross-sectional view, spanning three dimensions D1, D2, and D3 at different levels. In particular, the gate stack 146 spans a first dimension D1 at the top surface, a second dimension D2 at the bottom surface, and a third dimension D3 as a minimum dimension at a position that makes the top surface 104a of the fin active area 104 flush. Each of D1 and D2 is greater than D3. In the depicted embodiment, the second dimension D2 is greater than the first dimension D1. In some embodiments, those dimensions define respective ratios. The first ratio D1 / D3 is in a range between about 1.4 and about 1.6; and according to some embodiments, the second ratio D2 / D3 is in a range between about 1.7 and about 1.9. In this embodiment, Fig.9F The height of each portion of the gate stack 146 in FIG. Figure 4F 1 and 2. The height ratio of the gate stack 110 ' in FIG. 1 corresponds to the height of the gate stack 110 ' in FIG. 1 . For example, the upper portion between D1 and D3 corresponds to the upper portion 110a having a height H1; the middle portion between D3 and D2 corresponds to the middle portion 110b having a height H2; and the lower portion below D2 corresponds to the lower portion 110c having a height H3. According to the present embodiment, the height ratio is retained in the gate stack 14. For example, the ratio H1 / H2 is in a range between 2.5 and 3.5, and the ratio H2 / H3 is in a range between 1.5 and 2.

[0067] The segment 156 in the interval between the first and second adjacent fin active regions 104 has a non-uniform shape in top view, such as Fig. 9C and Fig.9E As shown. The non-uniform shape is called a gourd shape. The gate stack 146 in the segment 156 spans a fourth dimension D4 at the edge of the first fin active area, a fifth dimension D5 at the edge of the second fin active area, and a sixth dimension D6 at a mid-position between the edges of the first fin active area and the second fin active area along the X direction. Each of the fourth dimension D4 and the fifth dimension D5 is smaller than the sixth dimension D6. In addition, the fifth dimension D5 is equal to the fourth dimension D4, so that the shape is symmetrical and has a minimum dimension D6 in the middle. In some embodiments, the ratio D6 / D4 is in a range between about 0.7 and about 0.9.

[0068] By the disclosed method 200 and the semiconductor structure 100 manufactured by the method 200, the gate stack 146 has a well-designed shape, and the corresponding transistors and circuits have enhanced circuit performance (e.g., ring oscillator performance) and generation yield. More particularly, in the top view, the gourd shape of the gate stack 146 provides device performance gains, including reducing parasitic capacitance by reducing D6, and enhancing gate control by increasing D4 and D5. This is because the middle portion of the gate associated with D6 in the top view contributes to the capacity, but does not contribute or contributes minimally to the gate control, and reducing its size can reduce the parasitic capacitance without compromising the coupling between the gate and the channel. The edge portion of the gate associated with D4 and D5 has an increased size, which brings benefits including an increased channel length, thereby increasing the coupling between the gate and the channel. The hourglass shape of the gate stack 146 provides various performance enhancements and improved gate control in the cross-sectional view. In particular, the wider dimension at the bottom can provide device performance gains by reducing drain induced barrier lowering (DIBL) and reducing fin bottom leakage; the narrow dimension in the middle reduces parasitic capacitance; and the wide dimension at the top increases the gate fill window and increases yield gains.

[0069] Reference in top view or cross-section view respectively Fig. 10A , Fig. 10B , Fig. 10B '、 Fig. 10C , Fig. 10C '、 Fig. 10D and Fig.10E , further describing the gate stack 146 in the portion 156 according to various embodiments. By adjusting various etching processes in operation 204, other profiles of the gate stack 146 may be achieved, such as FIG. 10B to FIG. 10E The gate stacks 146 in the segment 156 have different shapes and sizes. These shapes and sizes are achieved by adjusting various processing parameters of the operation 204, particularly the etching time and the etchant of the second etching process 228 and the third etching process 230. The different shapes and sizes of the gate stacks 146 can be used to form specific devices for performance enhancement and / or to compensate for device characteristic variations, depending on the individual application.

[0070] In one embodiment, the gate stack 146 in the segment 156 has a Fig. 10B The cross-sectional view shown and Fig. 10B ' is shown as a top view. This is similar to 9A to 9DThe gate stack 146 has a non-uniform profile with a narrow waist. In particular, the gate stack 146 spans three dimensions C, D, and E at different levels. The first ratio C / D is in a range between about 1.4 and about 1.6; and according to some embodiments, the second ratio E / D is in a range between about 1.7 and about 1.9.

[0071] In another embodiment, the gate stack 146 in the segment 156 has a Fig. 10C The cross-sectional view shown and Fig. 10C ' is a top view shown in FIG. The gate stack 146 has a non-uniform profile having a dimension that increases from the bottom surface to the top surface. In particular, the gate stack 146 spans dimensions F and D at the top surface and the bottom surface, respectively. The ratio F / G is in a range between about 1.1 and about 1.4.

[0072] In yet another embodiment, the gate stack 146 in the segment 156 has a Fig. 10D The gate stack 146 has a non-uniform profile with a decreasing dimension from the bottom surface to the top surface. In particular, the gate stack 146 spans dimensions H and I at the top surface and the bottom surface, respectively. The ratio I / H is in a range between about 1.4 and about 1.6.

[0073] In yet another embodiment, the gate stack 146 in the segment 156 has a Fig.10E 1. The gate stack 146 has a non-uniform profile with a wider waist. In particular, the gate stack 146 spans dimensions J, K, and L at the top surface, at a height flush with the top surface of the fin, and at the bottom surface. The first ratio K / J is in a range between about 1.4 and about 1.6; and the second ratio K / L is in a range between about 1.4 and about 1.6.

[0074] The semiconductor structure 100 may be formed on a structure having multiple channels stacked vertically, such as Fig.13 The one shown. Fig.13 is a partial cross-sectional view of a semiconductor structure 100 constructed according to some embodiments. Fig.13, the integrated circuit 100 has a vertically stacked channel structure in which a plurality of channels are vertically stacked. In particular, the semiconductor structure 100 includes a substrate 602 and a plurality of channels 604 formed above the substrate 602. The semiconductor structure 100 also includes a gate stack 606 formed around the channels 604 and a source / drain (S / D) component 608 disposed on both sides of the gate stack 606. In particular, the gate stack 606 wraps each of the vertically stacked plurality of channels 604 spanning between the S / D components 608 disposed on both sides of the gate stack 606. The semiconductor structure 100 also includes other components, such as an internal spacer 610 (of one or more dielectric materials) between the gate stack 606 and the S / D components 608; a gate spacer 612 disposed on the sidewall of the gate stack 606; a doped wall 614 (such as an N-well or a P-well); and an interlayer dielectric (ILD) layer 616. The gate stack 606 includes a gate dielectric layer and a gate electrode. The gate dielectric layer includes one or more dielectric materials, such as high-k dielectric materials. The gate dielectric layer may further include an interface layer (such as silicon oxide) located below the high-k dielectric material. The gate electrode includes one or more conductive materials, such as a capping layer, a work function metal, and a fill metal. In particular, the gate stack 606 is similar to the gate stack 146 having the geometric shape described above and is formed in a similar manner. For example, the portion of the gate stack 606 above the plurality of channels 604 has a shape similar to the shape of the gate stack 146.

[0075] The present invention is not limited to applications where the semiconductor structure includes field effect transistors such as metal oxide silicon (MOS) transistors, and can be extended to other integrated circuits with metal gate stacks. For example, the semiconductor structure 100 may include logic circuits, analog circuits, imaging sensor circuits, static random access memory (SRAM) cells, dynamic random access memory (DRAM) cells, single electron transistors (SETs), and / or other microelectronic devices (collectively referred to herein as microelectronic devices). Of course, aspects of the present invention are also applicable and / or easily applicable to other types of transistors and can be employed in many different applications, including sensor cells, memory cells, logic cells, etc.

[0076] Although embodiments of the present invention have been described in detail, it will be appreciated by those skilled in the art that various variations, substitutions, and changes may be made herein without departing from the spirit and scope of the present invention. In one embodiment, the gate electrode may optionally or additionally include other suitable metals. The basic procedure may implement other effective cleaning procedures. The disclosed method is used for, but is not limited to, forming a transistor, such as an n-type metal oxide semiconductor field effect transistor (nMOSFET). For example, a plurality of nMOSFETs and a plurality of p-type metal oxide semiconductor field effect transistors (pMOSFETs) are formed on the same substrate, and nMOSFETs and pMOSFETs are formed in a common procedure for forming some components separately. In a specific example, an n-type WF metal is formed in the nMOSFET region, and the deposition of the n metal covers the pMOSFET region.

[0077] In another embodiment, the semiconductor substrate may include an epitaxial layer. For example, the substrate may have an epitaxial layer located above a bulk semiconductor. In addition, the substrate may include a semiconductor-on-insulator (SOI) structure, such as a buried dielectric layer. Alternatively, the substrate may include a buried dielectric layer, such as a buried oxide (BOX) layer, such as a buried dielectric layer formed by a technique called isolation by implanted oxygen (SIMOX), wafer bonding, selective epitaxial growth (SEG), or other suitable methods.

[0078] The present invention provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure 100 includes a gate stack 146 having a non-uniform shape. The gate stack has an hourglass shape in a cross-sectional view, and a section between two adjacent fin active regions 104 has a gourd shape in a top view.

[0079] Various advantages may exist in one or more embodiments of the method 200 and the semiconductor structure 100. Through the disclosed method 200 and the semiconductor structure 100 manufactured by the method 200, the gate stack 146 has a well-designed shape, and the corresponding transistors and circuits have enhanced circuit performance and production yield. More specifically, the gourd shape of the gate stack 146 in the top view provides device performance gains including reduced parasitic capacitance and enhanced gate control, while the hourglass shape of the gate stack 146 in the cross-sectional view provides reduced drain-induced barrier lowering (DIBL), with increased device performance gains and increased gate fill window, with increased yield gains.

[0080] In one aspect, the present invention provides a semiconductor structure comprising: a semiconductor substrate; a fin active region protruding above the semiconductor substrate; and a gate stack disposed on the fin active region, wherein the gate stack comprises a high-k dielectric material layer and respective metal layers disposed on the high-k dielectric material layer, wherein the gate stack comprises an uneven profile in a cross-sectional view, having a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a position between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

[0081] In some embodiments, the third dimension D3 is the minimum dimension at a position that makes the top surface of the fin active area flush. In some embodiments, the second dimension D2 is greater than the first dimension D1. In some embodiments, the first ratio D1 / D3 is between about 1.4 and about 1.6; and the second ratio D2 / D3 is between about 1.7 and about 1.9. In some embodiments, the fin active area includes a first fin active area and a second fin active area oriented in a first direction and spaced apart in a second direction substantially orthogonal to the first direction; the gate stack extends over the first fin active area and the second fin active area along the second direction; and the first dimension, the second dimension, and the third dimension are measured along the second direction. In some embodiments, the gate stack includes a segment disposed on a shallow trench isolation feature and between the first fin active area and the second fin active area, and wherein the segment of the gate stack has an uneven shape in a top view. In some embodiments, in top view, the segment of the gate stack spans a fourth dimension D4 at an edge of the first fin active area, a fifth dimension D5 at an edge of the second fin active area, and a sixth dimension D6 at an intermediate position between the edges of the first fin active area and the second fin active area along the first direction, and wherein each of the fourth dimension D4 and the fifth dimension D5 is less than the sixth dimension D6. In some embodiments, the fifth dimension D5 is equal to the fourth dimension D4. In some embodiments, the ratio D4 / D6 is in a range between about 0.7 and about 0.9.

[0082] In another aspect, the present invention provides a semiconductor structure, comprising: a semiconductor substrate; a first fin active region and a second fin active region formed on the semiconductor substrate, surrounded by an isolation component and protruding above the isolation component, wherein the first fin active region and the second fin active region are oriented in a first direction and spaced apart in a second direction substantially orthogonal to the first direction; and a gate stack oriented in a second direction and extending above the first fin active region and the second fin active region. The gate stack includes a segment in the interval between the first fin active region and the second fin active region. The segment of the gate stack has an hourglass shape in a cross-sectional view and a gourd shape in a top view.

[0083] In some embodiments, the segment of the gate stack spans a first dimension D1 at the top surface, a second dimension D2 at the bottom surface, and a third dimension D3 at a position between the top surface and the bottom surface along the second direction, and wherein each of D1 and D2 is greater than D3. In some embodiments, the third dimension D3 is the minimum dimension at a position where the top surface of the fin active area is flush; and the second dimension D2 is greater than the first dimension D1. In some embodiments, the first ratio D1 / D3 is between about 1.4 and about 1.6; and the second ratio D2 / D3 is between about 1.7 and about 1.9. In some embodiments, in a top view, the segment of the gate stack spans a fourth dimension D4 at an edge of the first fin active area, a fifth dimension D5 at an edge of the second fin active area, and a sixth dimension D6 at an intermediate position between the edges of the first fin active area and the second fin active area along the first direction; each of the fourth dimension D4 and the fifth dimension D5 is less than the sixth dimension D6; and the fifth dimension D5 is equal to the fourth dimension D4. In some embodiments, the ratio D4 / D6 is in a range between about 0.7 and about 0.9.

[0084] In another aspect, the present invention provides a method for forming a semiconductor structure. The method includes: forming a fin active region on a semiconductor substrate; depositing a dummy gate material layer on the fin active region and the semiconductor substrate; performing a first etching process on the dummy gate material layer to form a patterned gate material layer; performing surface modification by implanting into the sidewall of the patterned gate material layer; and then performing a second etching process on the patterned gate material layer to form a patterned gate stack.

[0085] In some embodiments, the method further comprises: forming an interlayer dielectric layer on the patterned gate stack and the semiconductor substrate; selectively removing the patterned gate stack to generate a gate trench in the interlayer dielectric layer; and forming a metal gate stack comprising a high-k dielectric material layer and a metal. In some embodiments, depositing the gate material layer comprises depositing a polysilicon layer; and performing the surface modification comprises performing an ion implantation process to introduce at least one of carbon and nitrogen into the sidewall of the patterned gate material layer of polysilicon. In some embodiments, performing the first etching process comprises performing the first etching process using a first etchant comprising sulfur dioxide (SO2) and hydrogen (H2); and the step of performing the second etching process comprises performing the second etching process using a second etchant comprising hydrogen bromide (HBr), chlorine (Cl) and fluorine (F). In some embodiments, the method further comprises: performing a third etching process on the patterned gate material layer after the second etching process, wherein the third etching process has a bias power less than that of the second etching process and a lateral etching rate greater than that of the second etching process, respectively.

[0086] The features of several embodiments are summarized above. It will be appreciated by those skilled in the art that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments described herein. It will also be appreciated by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure comprising: Semiconductor substrate; a fin active region protruding above the semiconductor substrate; as well as a gate stack disposed on the fin active region, wherein the gate stack includes a high-k dielectric material layer and respective metal layers disposed on the high-k dielectric material layer, wherein the gate stack includes a non-uniform profile in a cross-sectional view, wherein a first dimension D1 is provided at a top surface, a second dimension D2 is provided at a bottom surface, and a third dimension D3 is provided at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3; The gate stack has a size that varies from an edge of one fin active region to an edge of another fin active region in a top view, and has a smallest size in the middle between the two fin active regions.

2. The semiconductor structure according to claim 1, wherein: The third dimension D3 is a minimum dimension at a position where the top surface of the fin active region is flush.

3. The semiconductor structure according to claim 2, wherein: The second dimension D2 is greater than the first dimension D1.

4. The semiconductor structure according to claim 3, wherein: The first ratio D1 / D3 is between 1.4 and 1.6; and the second ratio D2 / D3 is between 1.7 and 1.

9.

5. The semiconductor structure according to claim 3, wherein: The first ratio D1 / D3 is between 1.4* (1-10%) and 1.6* (1+10%); and the second ratio D2 / D3 is between 1.7* (1-10%) and 1.9* (1+10%).

6. The semiconductor structure according to claim 1, wherein The fin active region includes a first fin active region and a second fin active region oriented in a first direction and spaced apart in a second direction substantially orthogonal to the first direction; A gate stack extends over the first fin active region and the second fin active region along the second direction; as well as The first dimension, the second dimension, and the third dimension are measured along the second direction.

7. The semiconductor structure according to claim 6, wherein: The gate stack includes a segment disposed on a shallow trench isolation feature and between the first fin active region and the second fin active region, and wherein the segment of the gate stack has a non-uniform shape in a top view.

8. The semiconductor structure according to claim 7, wherein: In the top view, the segment of the gate stack spans a fourth dimension D4 at an edge of the first fin active area, a fifth dimension D5 at an edge of the second fin active area, and a sixth dimension D6 at a midpoint between the edges of the first fin active area and the second fin active area along the first direction, and wherein each of the fourth dimension D4 and the fifth dimension D5 is greater than the sixth dimension D6.

9. The semiconductor structure according to claim 8, wherein: The fifth dimension D5 is equal to the fourth dimension D4.

10. The semiconductor structure according to claim 9, wherein: The ratio D6 / D4 is in the range between 0.7 and 0.

9.

11. The semiconductor structure according to claim 9, wherein: The ratio D6 / D4 ranges between 0.7* (1-10%) and 0.9* (1+10%).

12. A semiconductor structure comprising: Semiconductor substrate; a first fin active region and a second fin active region formed on the semiconductor substrate, surrounded by an isolation feature and protruding above the isolation feature, wherein the first fin active region and the second fin active region are oriented in a first direction and spaced apart in a second direction substantially orthogonal to the first direction; and a gate stack oriented in the second direction and extending over the first fin active region and the second fin active region, wherein The gate stack includes a segment in a space between the first fin active region and the second fin active region, and The segment of the gate stack has an hourglass shape in a cross-sectional view and a gourd shape in a top view; The gate stack has a size varying from an edge of the first fin active region to an edge of the second fin active region in a top view, and has a smallest size in the middle between the first fin active region and the second fin active region.

13. The semiconductor structure according to claim 12, wherein: The segment of the gate stack spans a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface along the second direction, and wherein each of D1 and D2 is greater than D3.

14. The semiconductor structure according to claim 13, wherein: The third dimension D3 is a minimum dimension at a position where the top surface of the fin active region is flush; and The second dimension D2 is greater than the first dimension D1.

15. The semiconductor structure according to claim 14, wherein: The first ratio D1 / D3 is between 1.4 and 1.6; and the second ratio D2 / D3 is between 1.7 and 1.

9.

16. The semiconductor structure according to claim 14, wherein: The first ratio D1 / D3 is between 1.4* (1-10%) and 1.6* (1+10%); and the second ratio D2 / D3 is between 1.7* (1-10%) and 1.9* (1+10%).

17. The semiconductor structure according to claim 12, wherein: In the top view, the segment of the gate stack spans a fourth dimension D4 at an edge of the first fin active area, a fifth dimension D5 at an edge of the second fin active area, and a sixth dimension D6 at a midpoint between the edges of the first fin active area and the second fin active area along the first direction; Each of the fourth dimension D4 and the fifth dimension D5 is greater than the sixth dimension D6; as well as The fifth dimension D5 is equal to the fourth dimension D4.

18. The semiconductor structure according to claim 17, wherein: The ratio D6 / D4 is in the range between 0.7 and 0.

9.

19. The semiconductor structure according to claim 17, wherein: The ratio D6 / D4 ranges between 0.7* (1-10%) and 0.9* (1+10%).

20. A method of forming a semiconductor structure, comprising: forming a fin active region on a semiconductor substrate; Depositing a dummy gate material layer on the fin active area and the semiconductor substrate; Performing a first etching process on the dummy gate material layer to form a patterned gate material layer; Performing surface modification by implanting into the sidewalls of the patterned gate material layer; as well as Then, performing a second etching process on the patterned gate material layer to form a patterned gate stack; The patterned gate stack has a size that varies from an edge of one fin active region to an edge of another fin active region in a top view, and has a smallest size in the middle between the two fin active regions.

21. The method according to claim 20, further comprising: forming an interlayer dielectric layer on the patterned gate stack and the semiconductor substrate; selectively removing the patterned gate stack to produce a gate trench in the interlayer dielectric layer; as well as A metal gate stack including a high-k dielectric material layer and a metal is formed.

22. The method according to claim 20, wherein: Depositing the gate material layer includes depositing a polysilicon layer; and Performing the surface modification includes performing an ion implantation process to introduce at least one of carbon and nitrogen into the sidewalls of the patterned gate material layer of polysilicon.

23. The method according to claim 20, wherein: Performing the first etching process includes performing the first etching process using a first etchant including sulfur dioxide (SO2) and hydrogen (H2); as well as The step of performing the second etching process includes performing the second etching process using a second etchant including hydrogen bromide (HBr), chlorine (Cl), and fluorine (F).

24. The method of claim 20, further comprising: After the second etching process, a third etching process is performed on the patterned gate material layer, wherein the third etching process has a bias power smaller than that of the second etching process and a lateral etching rate larger than that of the second etching process.

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