Semiconductor device and method of forming the same

Abstract

Disclosed is a semiconductor structure including a first wire and a first power rail and a first transistor structure disposed between the first wire and the first power rail. The first wire and the first power rail are separated from each other in a first direction. The first transistor structure includes a first active region coupled to the first wire by a first via; and a second active region coupled to the first power rail by a second via; a first gate structure between the first active region and the second active region and configured to receive a first control signal. The first transistor structure transmits a signal between the first wire and the first power rail in response to the first control signal. Embodiments of the invention also disclose a semiconductor device and a method of forming the same.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a semiconductor device and a method of forming the same. BACKGROUND

[0002] Integrated circuits have been widely used for various applications. There is a growing demand for faster processing speed, lower power consumption, and smaller size. Various units including digital units and analog units are designed for manufacturing integrated circuits. For analog units, due to small geometry size, the resistance of metal wiring coupled between active devices and power rails in an integrated circuit is large. SUMMARY

[0003] According to an aspect of an embodiment of the present application, there is provided a semiconductor device, comprising: a first wire and a first power rail separated from each other in a first direction, the first direction being a normal direction of a layout of the semiconductor device; and a first transistor structure disposed between the first wire and the first power rail, and comprising: a first active region coupled to the first wire by a first via; a second active region coupled to the first power rail by a second via; and a first gate structure interposed between the first active region and the second active region and configured to receive a first control signal; wherein the first transistor structure is configured to transfer a signal between the first wire and the first power rail in response to the first control signal.

[0004] According to another aspect of an embodiment of the present application, there is provided a semiconductor device, comprising: at least one first unit comprising: a first active region of a first conductivity type in a first layer; a first power rail in a second layer below the first layer; and a first via coupled between the first active region and the first power rail; and at least one second unit adjoining a first side of the at least one first unit, wherein the at least one second unit comprises: a second active region of a second conductivity type different from the first conductivity type in the first layer; a second power rail in the second layer; and a second via coupled between the second active region and the second power rail; wherein the at least one second unit is a mirror image of the at least one first unit across a mirror line.

[0005] According to another aspect of embodiments of the present application, there is provided a method of forming a semiconductor device, comprising: identifying a connection configuration between a first node and a second node in an integrated circuit; and in response to the connection configuration indicating that the first node is configured to receive a supply voltage from the second node, generating a layout design of the integrated circuit, comprising: generating a first wire extending in a first direction in a first layer of a front side of the integrated circuit and configured to be coupled to the first node; generating a supply rail extending in the first direction in a second layer of a back side of the integrated circuit below the first layer and configured to be coupled to the second node; generating an active region extending in the first direction in a third layer between the first layer and the second layer; generating a first via coupled between a first region of the active region and the first wire, and generating a second via coupled between a second region of the active region and the first wire; and generating a third via coupled between the first region of the active region and the supply rail, and generating a fourth via coupled between the second region of the active region and the supply rail. BRIEF DESCRIPTION OF DRAWINGS

[0006] Various aspects of the present application can be best understood with reference to the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that the various features are not necessarily drawn to scale and that the dimensions of various features can be arbitrarily increased or decreased for the clarity of discussion and illustration purposes.

[0007] FIG. 1A is a layout diagram in a plan view of a semiconductor device according to various embodiments.

[0008] FIG. 1B is a cross-sectional view of a portion of a semiconductor device along line A-A' in FIG. 1A

[0009] FIG. 1C is an equivalent circuit corresponding to a portion of a semiconductor device of FIGS. 1A-1B

[0010] FIG. 2A is a layout diagram in a plan view of a semiconductor device according to various embodiments.

[0011] FIG. 2B is a cross-sectional view of a portion of a semiconductor device along line B-B' in FIG. 2A

[0012] FIG. 2C is an equivalent circuit corresponding to a portion of a semiconductor device of FIGS. 2A-2B

[0013] ​​​​FIG. 3A is a layout in a plan view of a semiconductor device according to various embodiments.

[0014] FIG. 3B is a layout in a plan view of a semiconductor device according to various embodiments. FIG. 3A is a cross-sectional view of a portion of a semiconductor device in

[0015] FIG. 3C is an equivalent circuit corresponding to a portion of a semiconductor device of FIGS. 3A-3B

[0016] FIG. 4 is a schematic diagram of an integrated circuit according to various embodiments.

[0017] FIG. 5A is a layout in a plan view of a semiconductor device according to various embodiments.

[0018] FIG. 5B is a cross-sectional view of a portion of a semiconductor device in FIG. 5A along line D-D' according to various embodiments.

[0019] FIG. 6A is a layout in a plan view of a semiconductor device according to various embodiments.

[0020] FIG. 6B is a cross-sectional view of a portion of a semiconductor device in FIG. 6A along line E-E according to various embodiments.

[0021] FIG. 6C is an equivalent circuit corresponding to a portion of a semiconductor device of FIGS. 6A-6B

[0022] FIG. 7A is a layout in a plan view of a semiconductor device according to various embodiments.

[0023] FIG. 7B is a cross-sectional view of a portion of a semiconductor device in FIG. 7A along line F-F' according to various embodiments.

[0024] FIG. 7C is an equivalent circuit corresponding to a portion of a semiconductor device of FIGS. 7A-7B

[0025] FIG. 8A is another equivalent circuit corresponding to a portion of a semiconductor device of FIGS. 6A-6B

[0026] FIG. 8B is an equivalent circuit corresponding to a portion of a semiconductor device of FIGS. 7A-7B ​​​​another equivalent circuit of a portion of a semiconductor device.

[0027] FIG. 9A is a layout in a plan view of a semiconductor device according to various embodiments.

[0028] FIG. 9B is a layout in a plan view of a semiconductor device according to various embodiments. FIG. 9A an equivalent circuit of a portion of a semiconductor device.

[0029] FIG. 10A is a layout in a plan view of a semiconductor device according to various embodiments.

[0030] FIG. 10B is a layout in a plan view of a semiconductor device according to various embodiments. FIG. 10A an equivalent circuit of a portion of a semiconductor device.

[0031] FIG. 11 is a layout in a plan view of a semiconductor device according to various embodiments.

[0032] FIG. 12A is a layout in a plan view of a semiconductor device according to various embodiments.

[0033] FIG. 12B is a layout in a plan view of a semiconductor device according to various embodiments. FIG. 12A an equivalent circuit of a portion of a semiconductor device.

[0034] FIG. 13A is a flowchart of a method of forming an integrated circuit according to some embodiments of the disclosure.

[0035] FIG. 13B is a flowchart of a method of manufacturing a semiconductor device according to some embodiments of the disclosure.

[0036] FIG. 14 is a block diagram of a system for designing an integrated circuit layout design according to some embodiments of the disclosure.

[0037] FIG. 15 is a block diagram of an integrated circuit manufacturing system and an integrated circuit manufacturing flow associated therewith according to some embodiments. DETAILED DESCRIPTION

[0038] The following disclosure provides a number of different embodiments or examples for implementing different features of the present application. Specific embodiments or examples of components and arrangements are described below to simplify the present application. These are, of course, merely examples and are not intended to limit the application in any way. For example, in the following description, the formation of a first component over or on a second component can include embodiments in which the first component and the second component are formed in direct contact, and can also include embodiments in which additional components can be formed between the first component and the second component, such that the first component and the second component can not be in direct contact. Furthermore, the application can be repeated with various example reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0039] The terms used in this specification generally have their ordinary meanings in the art, and in the specific context of each term the ordinary meaning is intended. Any examples of a term in this specification are provided solely for the purpose of illustrating a more particular implementation, and are not intended to limit the scope of the disclosure or any exemplary term. Also, the disclosure is not limited to the various embodiments given in this specification.

[0040] In addition, for the purpose of convenience and brevity, the spatial terms, such as "below", "under", "lower", "above", "upper" and the like, can be used herein for describing the orientation of one element or component with respect to another element or component as illustrated in the figures. Such spatial terms are intended to encompass different orientations of the device in its operation or use, in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0041] As used herein, "about", "approximately", "almost", or "substantially" shall generally mean any approximation of a given value or range, wherein the approximation of the given value or range varies depending on the different fields to which it pertains, and the range thereof shall be consistent with the broadest interpretation of the term as understood by those skilled in the art to encompass all such modifications and similar structures. In some embodiments, it generally means within twenty percent of the given value or range, preferably within ten percent, and more preferably within five percent. Numerical values given herein are approximate, meaning that the term "about", "approximately", "almost", or "substantially" or other approximation can be inferred if not expressly stated, or other approximation.

[0042] In some layout designs of analog circuits, pick-up regions are positioned in a cell to conductively connect specific dopant type wells in the cell to voltage sources. More specifically, in various embodiments, n-type pick-up regions are used to conductively connect n-type wells in the cell to a first supply voltage VDD, and / or p-type pick-up regions are used to connect p-type wells in the cell to a second supply voltage VSS. Embodiments described below provide analog cells including transistor structures that couple front-side metal layers to back-side power rails in order to reduce cell area and parasitic resistance and capacitance caused by metal routing. In some embodiments, at least one transistor structure configured by vias coupling a doped region of a transistor to both front-side and back-side metal layers is referred to as a via pillar to connect back-side power components, such as bumps, super high density metal insulator metal (SHD-MIM), and inductors, to front-side components, such as metal oxide metal (MOM) capacitors, gates of MOSFETs, and high resistance elements. It significantly reduces parasitic resistance of metal routing between front-side and back-side metal layers. Furthermore, the grounded gate of the aforementioned transistor structure includes a decoupling capacitor to save area. Conversely, since the gate of the transistor structure is floating to achieve lowest parasitic capacitance, higher operating speed is achieved. In another embodiment, a differential pair switch of a current mirror circuit includes another transistor structure having a first doped region coupled to a front-side metal and a second doped region coupled to a back-side power rail, the other transistor structure serving as a mirror switch in the current mirror circuit. In yet another embodiment, a standard cell, such as a cell including an inverter, is composed of a combination of analog cells overlapping with at least two halves of a front-side metal trace and different numbers of, for example, P-type MOS or N-type MOS. Compared to some approaches of back-side power rail configuration, with the configuration of the present disclosure, operating speed and cell area of analog surges are reduced.

[0043] FIGS. 1A-3C Semiconductor devices 100-300 are depicted, each of which is a component of one or more of IC 400 or semiconductor devices 500, 600, 700, 900, 1000, 1100, or 1200 discussed below with reference to FIGS. 4-12B

[0044] Reference is now made to FIG. 1A . FIG. 1A is a layout diagram in plan view of semiconductor device 100 according to various embodiments. In some embodiments, semiconductor device 100 is implemented, for example, in an analog circuit that includes at least one output signal whose analog value is a continuous function of analog values of input signals of the analog circuit. As FIG. 1A ​As shown, the semiconductor device 100 includes a power rail (i.e., a back-side metal null layer, BMO) 111, active regions (i.e., oxide diffusion, OD) 121-122, gate structures 131-133, conductors (i.e., metal null layers (MO)) 141-143, and vias VB1, VD1, and VG1. In some embodiments, the power rail 111 is disposed in a first layer. The active regions 121-122 and the gate structures 131-133 are disposed in a second layer above the first layer. The conductors 141-143 are disposed in a third layer above the second layer. The via VB1 is disposed between the first and second layers. The vias VD1 and VG1 are disposed between the second and third layers.

[0045] For illustration, power rail 111 extends along the x-direction. Gate structures 131-133 extend in the y-direction and intersect with power rail 111 in the layout. Gate structures 131-133 are separated from each other in the x-direction. Gate structure 132 is located between active regions 121-122. Conductors 141-143 extend in the x-direction and are separated from each other in the y-direction. In the layout, at least one of conductors 141-143 overlaps with power rail 111. In other words, power rail 111 and conductor 141 are on opposite sides of active regions 121-122 and gate structure 132.

[0046] In some embodiments, such as FIG. 1A As shown, the width of the via VB1 along the y-direction is substantially the same as the width of the active region 122. In various embodiments, the width of the via VB1 along the y-direction is between the width of the active region 122 and the width of the active region 122. In various embodiments, the via VB1 has a tapered shape.

[0047] In some embodiments, power rails 111, active regions 121-122, gate structures 131-133, vias VD1 and VB1, wires 141-142, and half of wire 143 are included in analog cell CELL1 (cell 1). In some embodiments, wires 141-143 are arranged in three metal rails in semiconductor device 100. The configuration of analog cell CELL1 is given for illustrative purposes. Various implementations are within the scope of this disclosure. For example, in some embodiments, analog cell CELL1 includes wires arranged in 1, 1.5, 2, 2.5, 3… or 100 metal rails.

[0048] In some embodiments, the power rail 111 includes copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), molybdenum (Mo), nickel (Ni), tungsten (W), etc. In various embodiments, the power rail 111 is used as a power rail (e.g., VDD or VSS) on the back side of the semiconductor device 100, and therefore the power rail 111 is interchangeably referred to as a back-side power line or a back-side power rail.

[0049] In some embodiments, the conductive lines 141-143 include copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), molybdenum (Mo), nickel (Ni), tungsten (W), etc.

[0050] In some embodiments, the conductive lines 141-143 are included in a first conductive layer of a plurality of conductive layers. In some embodiments, the plurality of conductive layers includes one or more layers, in some embodiments, the material in the conductive layers is referred to as a Hi R material having a resistivity greater than or equal to about 5 micro-ohm centimeters. In some embodiments, the Hi R material is included in a metal plate that is part of a capacitor device. In some embodiments, one or more of the plurality of conductive layers includes W, TiN, TaN, Co, Mo, Mn, Ru, Ta, TiW, Ta-Si-N, TiZrN, CoTix, AlC, TiGeN, Cr, CrAsC, TiAlC, WNx, or other suitable materials.

[0051] In some embodiments, the via VD1, the via VB1, and the via VG1 include a conductive material, such as tungsten (W). Other conductive materials can be used for the via VD1, the via VB1, and the via VG1, such as copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), molybdenum (Mo), nickel (Ni), etc.

[0052] In some embodiments, the active regions 121-122 include n-type dopants (including, for example, phosphorus, arsenic, or a combination thereof), or p-type dopants (including, for example, boron, indium, aluminum, gallium, or a combination thereof).

[0053] In some embodiments, as shown in FIG. 1A, the gate structures 131-133 include a channel region 132a, a spacer layer 132b, a metal gate layer 132c, and an inner spacer material layer 132d. FIG. 1B FIG. 1B is a cross-sectional view of a portion of the semiconductor device 100 along line A-A’ in FIG. 1A, in accordance with various embodiments. FIG. 1A

[0054] ​​The channel region 132a includes nanosheet channels extending in the x-direction and separated in the y-direction. The term nanosheet is used herein to refer to any material portion having a nanoscale or even a micrometer scale dimension and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term refers to both circular and substantially circular cross-sectional elongated material portions, as well as to beam-shaped or strip-shaped material portions including, for example, cylindrical or substantially rectangular cross-sections. In various embodiments, the channel region 132a includes a material such as germanium, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof.

[0055] The spacer layer 132b is over the channel region 132a. In some embodiments, the spacer layer 132b is conformally arranged on top and configured as a sidewall of the gate structure 132. The spacer layer 132b includes a dielectric material, for example, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, a SiCN film, silicon oxycarbide, a SiOCN film, and / or combinations thereof.

[0056] The metal gate layer 132c is disposed between the spacer layer 132b and surrounded by the channel region 132a. In some embodiments, the metal gate layer 132c includes a p-type work function metal or an n-type work function metal and is deposited by CVD, PVD, and / or other suitable processes. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. One or more metal layers use aluminum (Al), tungsten (W), copper (Cu), cobalt (Co), and / or other suitable materials; and are formed by CVD, PVD, electroplating, and / or other suitable processes.

[0057] The inner spacer material layer 132d is formed to isolate the metal gate layer 132c from the active regions 121-122. In some embodiments, the inner spacer material layer 132d is a low-K dielectric material, such as SiO2, SiN, SiCN, or SiOCN, and can be formed by suitable deposition methods such as ALD. In various embodiments, the sidewalls of the inner spacer material layer 132d are aligned with the sidewalls of the channel region 132a.

[0058] In some embodiments, each gate structure 131-133 also includes an interface layer (not shown) wrapped around each channel region 132a, and a gate dielectric layer (not shown) covering the interface layer. In various embodiments, the interface layer includes a dielectric material including, for example, silicon oxide (Si02) or silicon oxynitride (SiON), and can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. In some embodiments, the gate dielectric layer uses a high-k dielectric material including, for example, hafnium oxide (Hf02), AI2O3, lanthanide oxides, Ti02, HfZrO, Ta203, HfSi04, Zr02, ZrSi02, combinations thereof, or other suitable materials. The gate dielectric layer is then formed by ALD and / or other suitable methods. The metal gate layer includes a p-type work function metal or an n-type work function metal, and is deposited by CVD, PVD, and / or other suitable processes. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr other suitable n-type work function materials, or combinations thereof. One or more metal layers use aluminum (Al), tungsten (W), copper (Cu), cobalt (Co), and / or other suitable materials; and are formed by CVD, PVD, electroplating, and / or other suitable processes.

[0059] The formations and / or materials associated with the gate structures 131-133 are given for illustrative purposes. Various formations and / or materials associated with the gate structures 131-133 are within the contemplated scope of the present disclosure.

[0060] With continued reference to FIG. 1B , the semiconductor device 100 also includes conductive segments (i.e., metal on oxide defined regions (“M0OD” or “MD”)) 151-152. In some embodiments, the conductive segments 151-152 are patterns formed over the active region pattern to define electrical connections from active devices formed by the active regions to external circuitry.

[0061] As shown in FIG. 1B , the conductive segments 151-152 are disposed on the active regions 121-122, respectively. The via VD1 is coupled between the wire 141 and the conductive segment 151, and thus, the active region 121 is coupled to the wire 141 through the via VD1 and the conductive segment 151. The via VB1 is coupled between the power rail 111 and the active region 122.

[0062] Referring to FIG. 1CAs shown, FIG. 1C It is according to various embodiments corresponding to FIGS. 1A-1B The equivalent circuit of a portion of the semiconductor device 100. In some embodiments, active regions 121-122 and gate structure 132 are included. FIG. 1C In the structure used as transistor Tr, conductive segment 151 corresponds to the first terminal (i.e., the source or drain terminal) of transistor Tr, and conductive segment 152 corresponds to the second terminal (i.e., the drain or source terminal) of transistor Tr. Gate structure 132 corresponds to the control terminal of transistor Tr.

[0063] In some embodiments, resistor R1 represents the resistance contributed by a portion of wiring arranged to couple the first terminal of transistor Tr to wire 141. This portion of wiring includes, for example, via VD1 and conductive segment 151. Similarly, resistor R2 represents the resistance contributed by a further portion of wiring arranged to couple the second terminal of transistor Tr to power rail 111. This further portion of wiring includes, for example, via VB1. Details regarding the configuration of resistors R1 and R2 will be discussed in the following paragraphs.

[0064] Based on the above discussion, in operation, for example, gate structure 132 receives control signal CS through wire 143 and via VG1. Therefore, in response to control signal CS, transistor Tr is configured to transmit signal VS from power rail 111 to wire 141 through via VB1, conductive segment 151, and via VD1. In some embodiments, the aforementioned signal VS is a voltage signal having a power supply voltage level for operating the device coupled to transistor Tr. In various embodiments, the aforementioned signal VS is a data signal transmitted from another element in semiconductor device 100. The configuration of operation of semiconductor device 100 is given for illustrative purposes. Various implementations are within the scope of this disclosure. For example, in some embodiments, signal VS received from other elements in semiconductor device 100 is transmitted from wire 141 to power rail 111.

[0065] In some methods, additional pickup regions are integrated into the semiconductor device to connect a specific doped well or the substrate of an active device (e.g., the body of the active device, such as a transistor) to a voltage source. In such methods, the pickup regions are arranged adjacent to the active device in a layout view. Conversely, using the configuration of this disclosure, the active device is connected to the voltage source from a power rail 111 in a layer below the active device. Therefore, compared to this method, the cell area is reduced, and the overall cell height is smaller.

[0066] Furthermore, in various methods, the power supply voltage is transmitted in a power metal layer above the active device (e.g., a ten-layer metal arrangement above a zero-layer metal layer). In such an arrangement, the voltage signal is subjected to parasitic resistance caused by the wiring of the layers. With the configuration of this disclosure, compared to other methods, the power rail 111 is disposed on the back side of the active device and closer to the active device. In other words, the wiring is shortened, and the resistance represented by the resistor unit R2 is correspondingly reduced. In addition, the parasitic capacitance between the layers experienced by the metal layer is also reduced. Therefore, the performance (i.e., speed) of the semiconductor device 100 is improved.

[0067] For illustrative purposes, the following is given: FIGS. 1A-1C The configuration is as follows. Various implementations are within the scope of this disclosure. For example, in some embodiments, a via VG1 is coupled between wire 142 and gate structure 132.

[0068] Now for reference FIGS. 2A-2C . FIG. 2A This is a top view layout diagram of semiconductor device 200. FIG. 2B yes FIG. 2A A cross-sectional view of the semiconductor device 200 along line B-B'. FIG. 2C It is according to various embodiments corresponding to FIGS. 2A-2B The equivalent circuit of a portion of the semiconductor device 200. Regarding... FIGS. 1A-1C The embodiments, for ease of understanding, are as follows, FIGS. 2A-2C The same reference numerals are designated as the same reference numerals. For the sake of brevity, the specific operation of similar elements has been discussed in detail above, and will be omitted here unless it is necessary to introduce similar reference numerals. FIGS. 2A-2C The cooperative relationship of the components shown.

[0069] and FIG. 1A In comparison, such as FIGS. 2A-2B As shown, instead of a via VB1, semiconductor device 200 does not have a via VB1. In some embodiments, semiconductor device 200 receives signals transmitted from other semiconductor devices (e.g., semiconductor device 100) via wire 141. In various embodiments, the active region 122 of semiconductor device 200 is coupled to other elements (i.e., conductive segments 152 pass through other active regions or wires). FIG. 2C As shown, since there is no via VB1, there is no equivalent resistance between transistor Tr and power rail 111.

[0070] Now for reference FIGS. 3A-3C . FIG. 3A This is a top view layout diagram of semiconductor device 300. FIG. 3B yes FIG. 3A A cross-sectional view of the semiconductor device 300 along line CC'. FIG. 3Cis a partial equivalent circuit of the semiconductor device 300 according to various embodiments FIG. 3A and FIG. 3B . Regarding the embodiments of FIGS. 1A-2C , for ease of understanding, the same reference numerals are designated as the same reference numerals as FIGS. 3A-3C .

[0071] In comparison with FIG. 1A , the semiconductor device 300 further includes vias VD2 and VB2. In some embodiments, for example, the vias VD2 and VB2 are configured with respect to the vias VD1 and VB2, respectively. As shown in FIG. 3A , the vias VD1 and VB2 overlap each other. The vias VD2 and VB1 overlap each other. For illustration, the vias VB1-VB2 have the same width in the y direction.

[0072] In comparison with FIG. 1B , the via VB2 is coupled between the active region 121 and the power rail 111, and thus, the active region 121 is further coupled to the power rail 111. In some embodiments, the resistance contributed by the wiring of the via VB2 is denoted as another resistance unit R2 in FIG. 3C . The via VD2 is coupled between the conductive segment 152 and the wire 141, and thus, the active region 122 is further coupled to the wire 141. In some embodiments, the resistance contributed by the wiring of the via VD2 is denoted as another resistance unit R1 in FIG. 3C .

[0073] Based on the above discussion, in operation, regardless of the transistor Tr being turned off in response to the control signal CS, the signal VS is transmitted from the power rail 111 to the wire 141 through a first path Path1 including the via VB1, the conductive segment 152, and the via VD2, and a second path Path2 including the via VB2, the conductive segment 151, and the via VD1, as shown in FIG. 3B . In other words, due to the two transmission paths, the total resistance of the resistance unit R3 between the wire 141 and the power rail 111 (denoted by the resistance units R1 and R2 in FIG. 3C ) is reduced.

[0074] The configuration of FIGS. 2A-3C is given for illustration purposes. Various implementations are within the intended scope of the present disclosure. For example, in some embodiments, the resistances of the vias VB1-VB2 and / or VD1-VD2 are different from each other.

[0075] Reference is now made to FIG. 4 . FIG. 4is a schematic diagram of an integrated circuit 400 according to various embodiments. In some embodiments, the integrated circuit 400 comprises at least one of the semiconductor devices 100-300, for example. For illustration, the integrated circuit 400 comprises a differential pair switch T1-T2, a current mirror unit T3, and a resistive unit R4-R5. Each of the differential pair switch T1-T2 has a first terminal coupled to one of the resistive unit R5 and a second terminal coupled to the current mirror unit T3. The resistive unit R4 is coupled between a voltage terminal V1 (i.e., the voltage terminal V1 is referred to as a terminal that supports a voltage V1) and the resistive unit R5. The current mirror unit T3 is coupled between a voltage terminal V2 (i.e., the voltage terminal V2 is referred to as a terminal that supports a voltage V2) and the differential pair switch T1-T2. In some embodiments, the voltages V1-V2 are different from each other. In various embodiments, the voltage V1 is greater than the voltage V2 (e.g., ground).

[0076] In some embodiments, the resistive unit R4 comprises a structure implemented by the semiconductor device 300. For example, the resistive unit R4 is implemented by the resistive unit R3 in FIG. 3C . Thus, as shown in FIG. 3B , the resistive unit R4 receives the voltage V1 from the power supply rail 111 and transmits a corresponding signal VS to the differential pair switch T1-T2 through a wire 141. In various embodiments, the resistive unit R5 corresponds to a metal wiring between one of the resistive unit R4 and one of the differential pair switch T1-T2.

[0077] The differential pair switch T1-T2 is configured to receive the signal VS from the resistive unit R5 in response to control signals S1-S2, respectively. In some embodiments, the differential pair switch T1-T2 comprises a structure implemented by the semiconductor device 200. For example, the differential pair switch T1-T2 is implemented by the transistor Tr in FIG. 2C . Thus, the differential pair switch T1-T2 receives the signal VS from the wire 141 coupled to the resistive unit R5 in response to the control signals S1-S2 received at its gate structure 132. In some embodiments, the differential pair switch T1-T2 is configured to output a corresponding output signal OS at its conductive section 152, as shown in FIG. 2B . The output signal OS is further sent to the current mirror unit T3.

[0078] The current mirror unit T3 is configured to receive the output signal OS from the differential pair switch T1-T2 in response to a control signal S3. In some embodiments, the current mirror unit T3 comprises a structure implemented by the semiconductor device 100. For example, the current mirror unit T3 is implemented as FIG. 1Cthe transistor Tr in the current mirror unit T3. Thus, the current mirror unit T3 receives the signal OS from the differential pair switch T1-T2 through the wire 141 coupled thereto in response to the control signal S3 received at its gate structure 132, and sends a corresponding signal to the voltage terminal V2.

[0079] The configuration of FIG. 4 is given for illustration purposes. Various implementations are within the intended scope of the present disclosure. For example, in some embodiments, the current mirror unit T3 is configured to operate as a current source.

[0080] Reference is now made to FIG. 5A . FIG. 5A is a layout diagram in a plan view of the semiconductor device 500 according to various embodiments. For illustration, the semiconductor device 500 includes a power rail 511, an active region 520, a gate strip 531, wires 541-542, a conductive section 551, vias VD3, VB3, and VG2. In some embodiments, the power rail 511 is configured with respect to, for example, the power rail 111. The active region 520 includes a plurality of active regions configured with respect to, for example, the active regions 121-122. The gate strip 531 is configured with respect to, for example, the gate structures 131-133. The wire 541 is configured with respect to, for example, the wire 141, and the wire 542 is configured with respect to, for example, the wire 143. The conductive section 551 is configured with respect to, for example, the conductive sections 151-152. The via VD3 is configured with respect to, for example, the vias VD1-VD2. The via VB3 is configured with respect to, for example, the vias VB1-VB2. The via VG2 is configured with respect to, for example, the via VG1. In some embodiments, the power rail 511 is disposed in a first layer. The active region 520 and the gate strip 531 are disposed in a second layer above the first layer. The conductive section 551 is above the active region 520. The wires 541-542 are disposed in a third layer above the second layer. The via VB3 is disposed between the first layer and the second layer. The vias VD3 and VG2 are disposed between the second layer and the third layer.

[0081] In some embodiments, the wire 541 is referred to as a wire coupled to a node nd3 (as shown in FIG. 6C ), and the power rail 511 is referred to as a power rail coupled to a node nd4 (as shown in FIG. 6C ), where the nodes nd3-nd4 are nodes in an integrated circuit included in the semiconductor device. In some embodiments, the node nd3 is configured to receive a supply voltage transmitted from the node nd4. In some embodiments, the wire 542 is configured to receive, in operation, a control signal (e.g., the control signal CS) to control a transistor structure including the gate strip 531. Detailed configurations will be discussed in the following paragraphs.

[0082] As FIG. 5AAs shown, power rail 511 and active region 520 extend in the x-direction, and active region 520 overlaps power rail 511 in the layout. Gate strips 531 extend in the y-direction and cross power rail 511. Gate strips 531 are separated from each other in the x-direction. Wires 541-542 extend in the x-direction and are separated from each other in the y-direction. Wires 541-542 partially overlap power rail 511. In some embodiments, the width of power rail 511 is greater than the width of active region 520 and wires 541-542 in the y-direction.

[0083] In some embodiments, as FIG. 5A shown, via VB3 has a width in the y-direction that is substantially the same as the width of active region 520. In various embodiments, the width of via VB3 in the y-direction is between the width of active region 520 and the width of active region 520. In various embodiments, via VB3 has a tapered shape.

[0084] Reference is now made to FIG. 5B . FIG. 5B is a cross-sectional view of a portion of semiconductor device 500 along line D-D' in FIG. 5A , in accordance with various embodiments. As FIG. 5B shown, conductive segment 551 is disposed on active region 521 of active region 520. Via VD3 is coupled between wire 541 and conductive segment 551, and thus, active region 521 is coupled to via VD3 and conductive segment 551 through active region 521. Via VB3 is coupled between power rail 511 and active region 521.

[0085] In some embodiments, the resistance contributed by the wiring structures including, for example, vias VD3, VB3, active region 521, and conductive segment 551 between power rail 511 and wire 541 is denoted as resistance unit R6. In some embodiments, resistance unit R6 corresponds to a combination of resistance units R1-R2 of FIG. 3C .

[0086] The configuration of FIGS. 5A-5B is presented for illustrative purposes. Various implementations are within the contemplation of the present disclosure. For example, in some embodiments, semiconductor device 500 further includes multiple vias configured with respect to vias VD3 and VB3, and other active regions coupled to conductive segment 551 and active region 520. Thus, more than one conductive path is created between power rail 511 and wire 541.

[0087] Reference is now made to FIG. 6A . FIG. 6A is a layout in a plan view of semiconductor device 600, in accordance with various embodiments. With respect to embodiments of FIGS. 5A-5B , for ease of understanding, reference is made to FIG. 6AThe same reference numerals are designated as the same reference numerals.

[0088] and FIG. 5A In comparison, semiconductor device 600 includes more gate bands 531 and conductive segments 551. Additionally, the power rail corresponding to power rail 511 has two portions, including power rails 511a-511b in semiconductor device 600. For example... FIG. 6A As shown, power rails 511a-511b are separated from each other in the x-direction. Conductor 541 overlaps with the two power rails 511a-511b. Instead of having one via VD3 and one via VB3, semiconductor device 600 also includes two vias VD3 and two vias VB2 disposed at two portions of semiconductor device 600. Furthermore, each gate strip 531 is coupled to conductor 542 through a via VG2.

[0089] Now for reference FIG. 6B . FIG. 6B According to various embodiments FIG. 6A A cross-sectional view of the semiconductor device 600 along line E-E'. (See diagram below.) FIG. 6B As shown, power rail 511a is coupled to wire 541 through vias VD3, VB3, active region 521, and conductive segment 551 above power rail 511a. Similarly, power rail 511b is coupled to wire 541 through vias VD3, VB3, active region 521, and conductive segment 551 above power rail 511b. In other words, two conductive paths are created for transmitting signals from wire 541 to power rails 511a-511b and from power rails 511a-511b to wire 541.

[0090] like FIG. 6B As shown, in some embodiments, a gate band 531 and an active region 521 on the opposite side of the gate band 531 are included in a structure serving as a transistor Ts. (See reference...) FIGS. 6B-6C , FIG. 6C It is according to various embodiments corresponding to FIGS. 6A-6B The equivalent circuit of a portion of the semiconductor device 600. For example... FIG. 6C As shown, semiconductor device 600 includes a plurality of transistors Ts coupled in series.

[0091] In some embodiments, FIG. 6B The active region 521 can be coupled to the via VB3 above the power rail 511a, which is included in the via VB3 used for power rails 511a. FIG. 6C In the structure of the first transistor terminal of transistor Ts. FIG. 6B Another active region 521 is coupled to via VB3 above power rail 511b, which is included in the via used for... FIG. 6Cthe structure of the terminal of the second transistor of the transistor Ts that is different from the first transistor. The gate strap 531 corresponds to the gate terminal of the transistor Ts.

[0092] In some embodiments, during operation, the gate terminal of the transistor Ts is coupled to ground through the via VG2 and the wire 542. Thus, the structure of the transistor Ts is configured to include a decoupling capacitance while the signal is a current transmitted between the wire 541 and the power rail 511a-511b. In other words, the transistor Ts arranged next to the resistive unit R6 or the transistor Ts arranged between the resistive units R6 is connected to include a decoupling capacitance with the resistive units R6.

[0093] In some approaches, additional area is needed in the integrated circuit for the decoupling capacitance and transmitting the voltage from the front side metal layer. With the configuration of the present disclosure, the functions of transmitting and decoupling are integrated in the semiconductor device 600.

[0094] Reference is now made to FIG. 7A . FIG. 7A is a layout diagram in a plan view of a semiconductor device 700 according to various embodiments. Regarding FIGS. 6A-6B embodiments of FIG. 7A the same reference numerals are designated as the same reference numerals.

[0095] In contrast to FIG. 6A instead of having a continuous wire 541 and two pieces of the power rail 511a-511b, the semiconductor device 700 includes a wire corresponding to the wire 541 of FIG. 6A having two portions including the wires 541a-541b. As FIG. 7A indicated, the wires 541a-541b are separated from each other in the x-direction. Both wires 541a-541b overlap the power rail 511.

[0096] Reference is now made to FIGS. 7B-7C . FIG. 7B is a cross-sectional view of a portion of the semiconductor device 700 in FIG. 7A along the line F-F'. FIG. 7C is an equivalent circuit corresponding to a portion of the semiconductor device 700 of FIGS. 7A-7B as FIG. 7B indicated, the power rail 511 is coupled to the wire 541a through the via VD3, VB3, the active region 521, and the conductive segment 551 under the wire 541a. Similarly, the power rail 511 is also coupled to the wire 541b through the via VD3, VB3, the active region 521, and the conductive segment 551 under the wire 541b. In other words, in some embodiments, as FIG. 7C indicated, the power rail 511 outputs / receives signals to two devices through the separate wires 541a-541b.

[0097] The configuration of FIGS. 6A-7C is given for illustrative purposes. Various implementations are within the intended scope of the present disclosure. Reference is now made to FIGS. 8A-8B . FIGS. 8A-8B are equivalent circuits corresponding to portions of the semiconductor devices 600-700, respectively, in accordance with various embodiments. For example, in some embodiments, as shown in FIGS. 8A-8B , during operation, the gate terminals of the transistors Ts arranged next to the resistive unit R6 are floating. Thus, the parasitic capacitances in the semiconductor devices 600-700 are minimized, and the low parasitic capacitance leads to high operation speed. In another embodiment, the gate terminals of the transistors Ts arranged between the resistive units R6 are floating. In yet another embodiment, FIGS. 8A-8B the gate terminals of the transistors Ts of

[0098] Reference is now made to FIG. 9A . FIG. 9A is a layout diagram in a plan view of a semiconductor device 900 in accordance with various embodiments. With respect to the embodiments of FIGS. 1A-8B , the same reference numerals are designated as the same reference numerals. FIG. 9A As shown in

[0099] , the semiconductor device 900 includes a unit CELL1 corresponding to one of FIG. 9A and a unit CELL2 adjoining the unit CELL1 in the y direction. In some embodiments, FIG. 9A the unit CELL1 of FIG. 9A may include an active region 921 including the active regions 121-122. The unit CELL2 includes an active region 922. In some embodiments, the unit CELL2 is a mirror image across a mirror line 910 extending in the x direction. In other words, the power supply rail 112 is configured with respect to the power supply rail 111 in the unit CELL1, and the power supply rails 111-112 are on opposite sides of the mirror line 910 and aligned with each other. The active region 922 is configured with respect to the active region 921 in the unit CELL1, and the active regions 921-922 are on opposite sides of the mirror line 910 and aligned with each other. The via VD4 is configured with respect to the via VD1 in the unit CELL1, and the vias VD1 and VD4 are on opposite sides of the mirror line 910 and aligned with each other. The via VB4 is configured with respect to the via VB1 in the unit CELL1, and the vias VB1 and VB4 are on opposite sides of the mirror line 910 and aligned with each other. The conductive lines 144 and 145 are configured with respect to the conductive lines 142 and 141, respectively, and the conductive line 143 is shared by the units CELL1-CELL2. The gate structures 131-133 are shared by the units CELL1-CELL2.

[0100] In some embodiments, adjacent cells CELL1-CELL2 are included in cell CELL3 (e.g., a standard cell) for transmitting signals between power rails 111-112 and wires 141 and 145. FIG. 9B As shown, cell CELL3 includes wires 141-145 arranged in 5 metal tracks, and each cell CELL1-CELL2 includes wires in 2.5 metal tracks. In other words, the number of metal traces included in each cell CELL1-CELL2 is not an integer, and the total number of metal traces included in cells CELL1-CELL2 is an integer. The configuration of cells CELL1-CELL3 is given for illustrative purposes. Various embodiments are contemplated within the scope of this disclosure. For example, in some embodiments, the number of metal traces included in each cell CELL1-CELL2 is an integer.

[0101] In some embodiments, active regions 921-922 have different conductivity types. Active region 921 is a first conductivity type, for example, P-type. Active region 922 is a second conductivity type, for example, N-type.

[0102] FIG. 9A It is according to various embodiments corresponding to FIGS. 9A-9B The equivalent circuit of a portion of the semiconductor device 900. Now refer to... FIGS. 9A-9B As shown. In some embodiments, cell CELL1 corresponds to a P-type transistor P1 coupled to power rail 111 and wire 141, and cell CELL2 corresponds to an N-type transistor N1 coupled to power rail 112 and wire 145. In operation, according to some embodiments, a shared gate structure 132 corresponds to the gate terminals of transistors P1 and N1. Control signal S4 is transmitted to transistors P1 and N1 via wire 143. In some embodiments, when control signal S4 has a high logic state (i.e., logic 1), transistor N1 is turned on to receive a voltage (e.g., voltage VSS, which is ground in some embodiments) and provides that voltage to other devices (not shown) coupled to semiconductor device 900 via wire 145. Similarly, when control signal S4 has a low logic state (e.g., logic 0), transistor P1 is turned on to receive another voltage (e.g., voltage VDD, which is greater than voltage VSS in some embodiments) and provides that voltage to other devices (not shown) coupled to semiconductor device 900.

[0103] Provided for illustrative purposes FIGS. 2A-2C The configuration. Various implementations are within the scope of this disclosure. For example, in some embodiments, cells CELL1-CELL2 in cell CELL3 are composed of FIGS. 3A-3C Semiconductor devices 200 FIG. 10Aat least one of the semiconductor devices 300 in the array or a combination thereof is implemented.

[0104] Reference is now made to FIG. 10A . FIGS. 1A-9B is a layout diagram in a plan view of the semiconductor device 1000 according to various embodiments. With respect to embodiments of FIG. 10A , like reference numerals are designated like reference numerals. FIG. 9A

[0105] In contrast to FIG. 10A , instead of having one cell CELL1 and one cell CELL2 in the cell CELL3, the cell CELL3 of the semiconductor device 1000 further comprises a plurality of cells CELL1 and a plurality of cells CELL2. For illustration, the cells CELL1 and the cells CELL2 are interleaved. As shown in FIG. 10A , the semiconductor device 1000 further comprises the wires 1001-1010 and the power rails 113-114. In some embodiments, the wires 1001-1010 are configured with respect to, for example, the wires 141-145. The power rails 113-114 are configured with respect to, for example, the power rails 111-112.

[0106] For illustration, the wires 1001-1005 are included in the cells CELL1-CELL2 of the upper portion of the cell CELL3, and the wires 1006-1010 are included in the cells CELL1-CELL2 of the bottom portion of the cell CELL3. The power rails 113-114 are included in the cells CELL1-CELL2 of the bottom portion of the cell CELL3, respectively. The gate structures 131-133 are further shared by all of the cells in the cell CELL3.

[0107] As shown in FIG. 10B , the semiconductor device 1000 further comprises an active region 921 in the cell CELL1 and an active region 922 in the cell CELL2. In some embodiments, the active region 921 is P-type, and the active region 922 is N-type.

[0108] Reference is now made to FIG. 10B . FIG. 10A is an equivalent circuit of a portion of the semiconductor device 1000 corresponding to FIG. 10A , according to various embodiments. Reference is now made to FIGS. 10A-10B ​In some embodiments, the cells CELL1-CELL2 of the upper portion of the cell CELL3 correspond to P-type transistors PI and N-type transistors N1 coupled to power rail 111 and wire 1001, and power rail 112 and wire 1005, respectively. Similarly, the cells CELL1-CELL2 of the bottom portion of the cell CELL3 correspond to P-type transistors P2 and N-type transistors N2 coupled to power rail 113 and wire 1006, and power rail 114 and wire 1010, respectively.

[0109] In operation, according to some embodiments, the shared gate structure 132 corresponds to the gate terminals of the transistors PI-P2 and N1-N2. A control signal S4 is transmitted to the transistors PI-P2 and N1-N2 through wire 1003 and / or wire 1008. In some embodiments, when the control signal S4 has a high logic state (e.g., logic 1), then the transistors N1-N2 are turned on to receive a voltage (e.g., voltage VSS, which in some embodiments is ground) and provide that voltage to other devices (not shown) coupled to the semiconductor device 1000 through wires 1005 and 1010. Similarly, when the control signal S4 has a low logic state (e.g., logic 0), the transistors PI-P2 are turned on to receive another voltage (e.g., voltage VDD, which in some embodiments is greater than voltage VSS) and provide that voltage to other devices (not shown) coupled to the semiconductor device 1000 through wires 1001 and 1006.

[0110] The configuration of FIG. 11 is given for illustrative purposes. Various implementations are within the intended scope of the present disclosure. For example, in some embodiments, the number of cells CELL1 is equal to the number of cells CELL2, which ranges from 2-4. In some embodiments, the number of cells CELL1 is equal to the number of cells CELL2 is greater than four.

[0111] In various embodiments, the active regions 921-922 in the cells CELL1-CELL2 of the upper portion of the cell CELL3 are P-type, and the active regions 921-922 in the cells CELL1-CELL2 of the bottom portion of the cell CELL3 are N-type. In other words, the active regions 921-922 in the cell CELL3 are a combination of P-type active regions and N-type active regions in any order. For example, in some embodiments, the sequence of the types of active regions 921-922 from the top of the cell CELL3 to the bottom of the cell CELL3 can be PPNP, PNNP, PPPN, NPNP, NPPN, NPPP, or any other suitable arrangement.

[0112] Reference is now made to FIG. 11 . FIGS. 1A-10Bis a layout diagram in a plan view of a semiconductor device 1100 according to various embodiments. Regarding FIG. 11 embodiments of FIG. 9A the same reference numerals are designated to the same components.

[0113] In comparison to FIG. 11 instead of the cells CELL1-CELL2 having wires arranged in 2.5 metal tracks, the cells CELL1-CELL2 in the cell CELL4 have wires arranged in 3 metal tracks in the semiconductor device 1100, as shown in FIG. 12A For illustration, the cell CELL1 comprises the wires 141, 142, half of the wire 143 and half of the wire 146. Similarly, the cell CELL2 comprises the wires 144, 145, half of the wire 143 and half of the wire 147.

[0114] Reference is now made to FIG. 12A . FIGS. 1A-11 is a layout diagram in a plan view of a semiconductor device 1200 according to various embodiments. Regarding FIG. 12A embodiments of FIG. 11 the same reference numerals are designated to the same components.

[0115] For illustration, in comparison to the semiconductor device 1000 and the cell CELL4 of FIG. 12A the semiconductor device 1200 further comprises the wires 1011-1013. In some embodiments, FIG. 11 the wires 1001-1005 and 1011-1012 of FIG. 12A may be configured with respect to the wires 141-147 of

[0116] For illustration, the cell CELL1 of the cell CELL4 comprises the wires 1001, 1002, half of the wire 1003 and half of the wire 1011. Similarly, the cell CELL2 of the cell CELL4 comprises the wires 1004, 1005, half of the wire 1003 and half of the wire 1012.

[0117] Furthermore, the semiconductor device 1200 further comprises another cell CELL1 which is not comprised in the cell CELL4 and which is arranged on the opposite side from the cell CELL1 in the cell CELL4 of the cell CELL2, as shown in FIG. 10A For illustration, the other cell CELL1 comprises the wires 1006, 1007, half of the wire 1008 and half of the wire 1013.

[0118] As mentioned above, in comparison to FIG. 12AIn contrast, in some embodiments, instead of cells CELL1 and CELL2 having equal proportions in cell CELL3, semiconductor device 1200 includes cells of different conductivity types in different proportions. For illustration, FIG. 12B The semiconductor device 1200 includes two cells CELL1 and one cell CELL2. In some embodiments, the active region 921 is P-type and the active region 922 is N-type.

[0119] refer to FIG. 12B . FIG. 12A It is according to various embodiments corresponding to FIGS. 12A-12B The equivalent circuit of a portion of the semiconductor device 1200. Now refer to... FIGS. 12A-12B In some embodiments, units CELL1-CELL2 of unit CELL4 correspond to a P-type transistor P1 coupled to power rail 111 and wire 1001, and an N-type transistor N1 coupled to power rail 112 and wire 1005, respectively. Unit CELL1 excluded from unit CELL4 corresponds to a P-type transistor P2 coupled to power rail 113 and wire 1006.

[0120] In operation, according to some embodiments, the shared gate structure 132 corresponds to the gate terminals of transistors P1-P2 and N1. Control signal S4 is transmitted to transistors P1-P2 and N1 via wires 1003 and / or 1008. In some embodiments, when control signal S4 has a high logic state (e.g., logic 1), transistor N1 is turned on to receive a voltage (e.g., voltage VSS, which is ground in some embodiments) and provides this voltage to other devices (not shown) coupled to semiconductor device 1200 via wire 1005. When control signal S4 has a low logic state (e.g., logic 0), transistors P1-P2 are turned on to receive another voltage (e.g., voltage VDD, which is greater than voltage VSS in some embodiments) and provide this voltage to other devices (not shown) coupled to semiconductor device 1200 via wires 1001 and 1006.

[0121] For illustrative purposes, the following is given: FIG. 13A The configuration is as follows. Various implementations are within the scope of this disclosure. For example, in some embodiments, the semiconductor device 1200 includes a greater number of P-type transistors or a greater number of N-type transistors. In some embodiments, the number of the first type of P-type or N-type transistors is two to four, and the number of the second type of P-type or N-type transistors is one to three.

[0122] Now for reference FIG. 13A . FIG. 13AThis is a flowchart of method 1300A for forming an integrated circuit included in a semiconductor device (e.g., 300-600 or 700) according to some embodiments of this disclosure. It should be understood that... FIG. 4 Additional operations are provided before, during, and / or after the illustrated process. For other embodiments of the method, some of the operations described below may be replaced or eliminated. The order of operations / processes may be interchanged. Similar reference numerals are used to indicate similar elements throughout the various views and illustrative embodiments. Method 1300A includes the following references FIGS. 6A-6C Integrated circuit 400 and FIG. 14 The operations 1310, 1320 and 1321-1325 described in the semiconductor device 600 are provided as non-limiting examples.

[0123] In some embodiments, some or all of method 1300A is executed by the processor of a computer. In some embodiments, some or all of method 1300A is executed by the processor 1402 of the electronic design automation (EDA) system 1400, as referred to below. FIG. 4 Let's have a discussion.

[0124] In operation 1310, for FIG. 3A The connection configuration between nodes nd1 and nd2 in the integrated circuit 400 shown is identified. For illustration, node nd1 receives voltage V1 and is coupled to nd2 through resistor unit R4.

[0125] In operation 1320, in response to the connection configuration indicating that node nd2 is configured to receive voltage Vl transmitted from node nd1, for example, as FIG. 3A As shown in the section, the layout design for generating integrated circuits is generated.

[0126] Furthermore, in some embodiments, generating the layout design includes operation 1321, wherein a wire 141 extending in the x-direction in the first layer on the front side of the integrated circuit 400 is generated to couple to node nd2, such as FIGS. 3A-3B As shown.

[0127] Subsequently, in some embodiments, the generation layout design also includes operation 1322, wherein a power rail 111 extending in the x-direction in a second layer below the first layer on the back side of the integrated circuit 400 is generated to couple to node nd1.

[0128] The generation of the layout design also includes operation 1323, in some embodiments, wherein an active region 120 extending in the x-direction is generated in a third layer between the first and second layers.

[0129] Generating the layout design further includes operation 1324, in some embodiments, where a via VD1 is generated to be coupled between the active region 121 and the wire 141, and in some embodiments, a via VD2 is generated to be coupled between the active region 122 and the wire 141, as shown in FIGS. 3A-3B

[0130] Generating the layout design further includes operation 1325, in some embodiments, where a via VB1 is generated to be coupled between the active region 122 and the power rail 111, and in some embodiments, a via VB2 is generated to be coupled between the active region 121 and the power rail 111, as shown in FIG. 3A FIG. 6A

[0131] In some embodiments, as shown in FIG. 6A Generating the layout design of the method 1300A further includes generating a plurality of gate strips 531 extending along the y-direction and generating a wire 542. For illustration, the gate strips 531 extend in the y-direction and are inserted between the vias VD3 coupling the active region 521 to the wire 541. The gate strips 531 are coupled to the wire 542 through vias VG2.

[0132] In some embodiments, as shown in FIG. 6A Generating the power rail 511 includes generating a power rail 511a (a first portion of the power rail 511) and a power rail 511b (a second portion of the power rail 511, separate from the first portion), in some embodiments. In some embodiments, the patterns corresponding to the power rail 511a, the vias VD3, VB3 above the power rail 511a, overlap with each other in FIG. 6A Similarly, in some embodiments, the patterns corresponding to the power rail 511b and the vias VD3, VB3 above the power rail 511b overlap with each other in FIG. 15

[0133] In some embodiments, the method 1300A further includes one or more operations of fabricating at least one element of an integrated circuit (e.g., the integrated circuit 400) based on the layout design, as part of an IC fabrication flow, which corresponds to the IC fabrication system 1500 discussed below with reference to FIG. 13B

[0134] Reference is now made to FIG. 13B . FIG. 13B ​​​​​is a flowchart of a method 1300B of fabricating semiconductor devices 100-700 or 900-1200 according to some embodiments of the present disclosure. It should be understood that additional operations can be provided before, during, and / or after the procedures shown. Some of these operations described below can be replaced or eliminated, in whole or in part. The order of the operations can be interchanged. Like reference numerals are used to designate like elements throughout the various figures and illustrative embodiments. The method 1300B includes operations 1301-1305 described below as non-limiting examples with reference to the semiconductor device 500. FIG. 15 Additional operations can be provided before, during, and / or after the procedures shown. Some of these operations described below can be replaced or eliminated, in whole or in part. The order of the operations can be interchanged. Like reference numerals are used to designate like elements throughout the various figures and illustrative embodiments. The method 1300B includes operations 1301-1305 described below as non-limiting examples with reference to the semiconductor device 500.

[0135] In some embodiments, the method 1300B can be used by an IC fabrication system as part of an IC fabrication flow, such as described below with reference to FIG. 5B the IC fabrication system 1500 discussed.

[0136] In operation 1301, an active region, such as the active region 520, is formed on a first side of the semiconductor device 500 (e.g., a front side above the via VB) and extends in the x-direction, as shown. FIG. 5B

[0137] In some embodiments, the method 1300B further includes forming one or more conductive segments, such as the conductive segments 551, on the active region, such as the active region 520.

[0138] In operation 1302, a via, such as the via VD3, is formed on the conductive segments, such as the conductive segments 551, above the active region of the active region, such as the active region 521 of the active region 520.

[0139] In operation 1303, a wire, such as the wire 541, is formed on the via and coupled to the active region through the via, such as the active region 520 through the via VD3. The wire, such as the wire 541, extends in the x-direction.

[0140] In some embodiments, after the fabrication process for the components (i.e., active devices) on the front side of the semiconductor device (e.g., the semiconductor device 500) is completed, the substrate (not shown) is removed and the wafer is flipped over to perform fabrication processes on the back side of the semiconductor device (e.g., the semiconductor device 500).

[0141] In operation 1304, a backside via, such as the via VB3, is formed on a second side of the semiconductor device 500 opposite the first side (i.e., a backside below the active region 520).

[0142] ​In operation 1305, a power rail (e.g., power rail 511) is formed under a backside via (e.g., via VB3) and coupled to an active region (e.g., active region 520) through the backside via, as shown in FIG. 6B In some embodiments, the power rail is formed over the backside via after flipping the wafer.

[0143] In some embodiments, the method 1300B further includes forming a plurality of backside vias, e.g., a plurality of vias VB3, in operation 1304. As shown in FIG. 11 One of the vias VB3 is formed to couple an active region 521 and a power rail 511a, and another is formed to couple another active region 510 and a power rail 511b, as shown in

[0144] In some embodiments, the method 1300B further includes forming wires arranged in a plurality (e.g., three) metal tracks over the power rail. For example, as shown in FIG. 12A Wires 141-142 and 146 are arranged in three metal tracks over the power rail 111. Similarly, wires 144-145 and 147 are arranged in three metal tracks over the power rail 112.

[0145] In some embodiments, the method 1300B further includes forming a plurality of active regions of a first conductivity type and a plurality of active regions of a second conductivity type different from the first conductivity type. For example, as shown in FIG. 14 Active regions 921 are P-type and active regions 922 are N-type. The number of active regions 921 (e.g., 2) is greater than the number of active regions 922 (e.g., 1).

[0146] Reference is now made to FIG. 14 . FIG. 13A is a block diagram of an EDA system 1400 capable of designing an integrated circuit layout design according to some embodiments of the present disclosure. The EDA system 1400 is configured to implement one or more operations of the method 1300A disclosed in FIGS. 1A-12B and is further explained in connection with FIGS. 1A-12B In some embodiments, the EDA system 1400 includes an APR system.

[0147] In some embodiments, the EDA system 1400 is a general-purpose computing device that includes a hardware processor 1402 and a non-transitory computer-readable storage medium 1404. Among other things, the storage medium 1404 is encoded (i.e., stored) with computer program code (instructions) 1406 (i.e., a set of executable instructions). The instructions 1406 executed by the hardware processor 1402 represent (at least in part) an EDA tool that implements part or all of a method (e.g., the method 1300A).

[0148] The processor 1402 is electrically coupled via the bus 1408 to a computer readable storage medium 1404. The processor 1402 is also electrically coupled via the bus 1408 to an I / O interface 1410 and a fabrication tool 1416. A network interface 1412 is also electrically connected to the processor 1402 via the bus 1408. The network interface 1412 is connected to a network 1414, enabling the processor 1402 and the computer readable storage medium 1404 to communicate via the network 1414 to external elements. The processor 1402 is configured to execute computer program code 1406 encoded in the computer readable storage medium 1404, in order to make the EDA system 1400 available for performing part or all of the mentioned processes and / or methods. In one or more embodiments, the processor 1402 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0149] In one or more embodiments, the computer readable storage medium 1404 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer readable storage medium 1404 includes semiconductor or solid-state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid disk, and / or an optical disk. In one or more embodiments using an optical disk, the computer readable storage medium 1404 includes a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0150] In one or more embodiments, the storage medium 1404 stores computer program code 1406 configured to make the EDA system 1400 (where such execution (at least partially represents an EDA tool) available for performing part or all of the mentioned processes and / or methods. In one or more embodiments, the storage medium 1404 also stores information that facilitates performing part or all of the mentioned processes and / or methods. In one or more embodiments, the storage medium 1404 stores an IC layout map 1420 including standard cells of such standard cells as disclosed herein, e.g., the above discussed cells included in the semiconductor devices 100-700 and 900-1200. FIGS. 1A-12B

[0151] The EDA system 1400 includes an I / O interface 1410. The I / O interface 1410 is coupled to external circuits. In one or more embodiments, the I / O interface 1410 includes a keyboard, a keypad, a mouse, a trackball, a touchpad, a touch screen, and / or a cursor direction key for communicating information and commands to the processor 1402.

[0152] ​The EDA system 1400 also includes a network interface 1412 coupled to the processor 1402. The network interface 1412 allows the EDA system 1400 to communicate with a network 1414 to which one or more other computer systems are connected. The network interface 1412 includes a wireless network interface such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE- 1364. In one or more embodiments, portions or all of the processes and / or methods are implemented in two or more systems 1400.

[0153] In some embodiments, the EDA system 1400 also includes a manufacturing tool 1416 coupled to the processor 1402. The manufacturing tool 1416 is configured to manufacture integrated circuits, for example, FIG. 15 The illustrated semiconductor devices 100-700 and 900-1200 are in accordance with design files processed by the processor 1402.

[0154] The EDA system 1400 is configured to receive information through the I / O interface 1410. The information received through the I / O interface 1410 includes one or more of instructions, data, design rules, a library of standard cells, and / or other parameters. The information is transferred to the processor 1402 through the bus 1408. The EDA system 1400 is configured to receive information related to a UI through the I / O interface 1410. The information is stored in the computer-readable medium 1404 as design specifications 1422.

[0155] In some embodiments, portions or all of the processes and / or methods are implemented as a standalone software application for execution by a processor. In some embodiments, portions or all of the processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, portions or all of the processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the referenced processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, portions or all of the processes and / or methods are implemented as a software application used by the EDA system 1400. In some embodiments, a tool such as a tool is used to generate a layout map that includes standard cells. The tool is available from CADENCE DESIGN SYSTEMS, Inc. or other suitable layout generation tool.

[0156] In some embodiments, these processes are implemented as functions of programs stored in a non-transitory computer-readable recording medium. Examples of the non-transitory computer-readable recording medium include, but are not limited to, one or more of external / removable and / or internal / built-in storage or storage units, e.g., one or more of optical disks such as DVDs, magnetic disks such as hard disks, semiconductor memory such as ROMs, RAMs, memory cards, and the like.

[0157] FIG. 15 is a block diagram of an IC manufacturing system 1500 and IC manufacturing flow associated therewith, in accordance with some embodiments. In some embodiments, based on a layout, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is manufactured using the IC manufacturing system 1500.

[0158] In FIG. 1B , the IC manufacturing system 1500 includes entities that interact with each other, e.g., a design house 1520, a mask house 1530, and an IC manufacturer / fabricator (“FAB”) 1550, during a design, development, and manufacturing cycle. Services or services related to manufacturing IC devices 1560. The entities in the IC manufacturing system 1500 are connected through a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is various different networks, e.g., an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design house 1520, the mask house 1530, and the IC FAB 1550 are owned by a single larger company. In some embodiments, two or more of the design house 1520, the mask house 1530, and the IC FAB 1550 coexist in a common facility and use common resources.

[0159] The design house (or design team) 1520 generates an IC design layout 1522. The IC design layout 1522 includes various geometric patterns, e.g., FIG. 2B , FIG. 3B , FIG. 5A , FIG. 6A , FIG. 7A , FIG. 9A , FIG. 10A , FIG. 11 , FIG. 12A and / or FIGS. 1A-12B the layout design depicted in FIG. 15semiconductor devices 100-700 and 900-1200 in FIGS. 1-9. The geometric patterns correspond to the patterns of metal, oxide, or semiconductor layers that make up various components of the IC device 1560 to be fabricated. The various layer combinations form various IC functions. For example, portions of the IC design layout 1522 include various IC components, such as active regions, gate electrodes, source and drain electrodes, conductive segments or interconnect vias, to form various material layers in and on a semiconductor substrate, such as a silicon wafer. The design room 1520 implements appropriate design procedures to form the IC design layout 1522. The design procedures include one or more of logic design, physical design, or placement and routing. The IC design layout 1522 is represented in one or more data files with geometric pattern information. For example, the IC design layout 1522 can be expressed in a GDSII file format or a DFII file format.

[0160] The mask room 1530 includes data preparation 1532 and mask fabrication 1544. The mask room 1530 uses the IC design layout 1522 to fabricate one or more masks 1545 to fabricate various layers of the IC device 1560 according to the IC design layout 1522. The mask room 1530 performs mask data preparation 1532 in which the IC design layout 1522 is converted into a representative data file (“RDF”). The mask data preparation 1532 provides the RDF to the mask fabrication 1544. The mask fabrication 1544 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1545 or a semiconductor wafer 1553. The IC design layout 1522 is manipulated by the mask data preparation 1532 to conform to the particular characteristics of the mask writer and / or requirements of the IC FAB 1550. In ​ In FIG. 15, the data preparation 1532 and the mask fabrication 1544 are shown as separate elements. In some embodiments, the data preparation 1532 and the mask fabrication 1544 can be collectively referred to as mask data preparation.

[0161] In some embodiments, the data preparation 1532 includes optical proximity correction (OPC) that uses lithography enhancement techniques to compensate for image errors, such as those that can result from diffraction, interference, other processing effects, etc. The OPC adjusts the IC design layout 1522. In some embodiments, the data preparation 1532 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, inverse lithography techniques (ILT) are also used, which treat OPC as an inverse imaging problem.

[0162] In some embodiments, data preparation 1532 includes a mask rule checker (MRC) that checks the IC design layout 1522 that has already been processed in the OPC using a set of mask creation rules that contain certain geometric and / or connectivity restrictions to ensure sufficient margins to address variability in the semiconductor manufacturing process, among other issues. In some embodiments, the MRC modifies the IC design layout 1522 to compensate for limitations during mask fabrication 1544, which can undo some of the modifications performed by the OPC to satisfy the mask creation rules.

[0163] In some embodiments, data preparation 1532 includes a lithography process check (LPC) that simulates the processing to be performed by the IC FAB 1550 to fabricate the IC device 1560. The LPC emulates the processing based on the IC design layout 1522 to create a simulated manufactured product. The processing parameters in the LPC simulation can include parameters related to various processes of the IC fabrication cycle, parameters related to tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, or combinations thereof. In some embodiments, after a simulated manufactured device has been created by the LPC, if the simulated device is not close enough in shape to satisfy the design rules, the OPC and / or the MRC are repeated to further refine the IC design layout 1522.

[0164] It should be appreciated that the above description of data preparation 1532 has been simplified for clarity. In some embodiments, data preparation 1532 includes additional features, such as a logic operation (LOP), to modify the IC design layout 1522 according to manufacturing rules. Additionally, the processing applied to the IC design layout 1522 during data preparation 1532 can be performed in various different orders.

[0165] After data preparation 1532 and during mask manufacturing 1544, a mask 1545 or a set of masks 1545 is manufactured based on the modified IC design layout 1522. In some embodiments, mask manufacturing 1544 includes one or more photolithography exposures based on the IC design layout 1522. In some embodiments, based on the modified IC design layout 1522, an e-beam or multiple e-beams mechanism is used to form a pattern on a mask (photomask or reticle) 1545. The mask 1545 can be formed in various techniques. In some embodiments, the mask 1545 is formed using binary techniques. In some embodiments, the mask pattern includes opaque regions and transparent regions. A beam of radiation (e.g., ultraviolet (UV) beam) used to expose an image- sensitive material layer (e.g., photoresist) that has been coated on a wafer is blocked by the opaque regions and transmitted through the transparent regions. In an example, a binary mask version of the mask 1545 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, the mask 1545 is formed using phase shift techniques. In a phase shift mask (PSM) version of the mask 1545, various features in the pattern formed on the phase shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask generated by mask manufacturing 1544 is used in a variety of processes. For example, such a mask is used in an ion implantation process to form various doped regions in a semiconductor wafer 1553, in an etching process to form various etched regions in a semiconductor wafer 1553, and / or in other suitable processes.

[0166] The IC FAB 1550 includes wafer fabrication 1552. The IC FAB 1550 is an IC manufacturing enterprise that includes one or more manufacturing facilities for fabricating a variety of different IC products. In some embodiments, the IC FAB 1550 is a semiconductor foundry. For example, there can be one manufacturing plant for front-end fabrication (front-end-of-line (FEOL) fabrication) of multiple IC products, while a second manufacturing plant can provide back-end fabrication of IC products for interconnection and packaging (back-end-of-line (BEOL) fabrication), and a third manufacturing plant can provide other services for the foundry business.

[0167] In some embodiments, the IC FAB 1550 includes fabrication tools configured to perform various fabrication operations on the semiconductor wafer 1553 to fabricate the IC devices 1560 according to the masks such as the mask 1545. In various embodiments, the fabrication tools include a wafer stepper, an ion implant machine, a photoresist coater, a process chamber (e.g., a CVD chamber or an LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other one or more of fabrication devices to perform one or more suitable fabrication processes herein.

[0168] The IC FAB 1550 uses the mask 1545 fabricated by the mask room 1530 to fabricate the IC devices 1560. Thus, the IC FAB 1550 uses the IC design layout 1522, at least indirectly, to fabricate the IC devices 1560. In some embodiments, the semiconductor wafer 1553 is fabricated by the IC FAB 1550 using the mask 1545 to form the IC devices 1560. In some embodiments, the IC fabrication includes one or more photolithography exposures based, at least indirectly, on the IC design layout 1522. The semiconductor wafer 1553 includes a silicon substrate or other suitable substrate having material layers formed thereon. The semiconductor wafer 1553 further includes one or more of various doped regions, dielectric components, multilayer interconnects, etc. (formed in subsequent fabrication steps).

[0169] As above, the semiconductor devices in the present disclosure provide a backside power rail in an analog unit to transmit a power signal to active devices on the front side. With the configuration of the present disclosure, the shorter wiring between the active devices and the power rail results in faster performance speed. Further, by placing the power rail at the backside of the semiconductor device, the front side area can be more efficiently utilized.

[0170] In some embodiments, a semiconductor device is disclosed that includes a first wire and a first power rail and a first transistor structure disposed between the first wire and the first power rail. The first wire and the first power rail are separated from each other in a first direction, the first direction being a normal direction of a layout of the semiconductor device. The first transistor structure includes a first active region coupled to the first wire by a first via; a second active region coupled to the first power rail by a second via; a first gate structure between the first active region and the second active region and configured to receive a first control signal. The first transistor structure is configured to transmit a signal between the first wire and the first power rail in response to the first control signal. In some embodiments, the first active region coupled to the first active region and the first power rail, the first via, and a third via are configured as a first conductive path, the first conductive path being configured to transmit the signal, and the second active region, the second via, and a fourth via coupled to the second active region and the first wire are configured as a second conductive path, the second conductive path being configured to transmit the signal. In some embodiments, the semiconductor device further includes a second wire and a second power rail separated from each other in the first direction and separated from the first wire and the first power rail in a second direction different from the first direction. The second wire is configured to receive the signal transmitted through the first wire. A second transistor structure is configured to transmit the signal between the second wire and the second power rail in response to a second control signal different from the first control signal and disposed between the second wire and the second power rail. The second transistor structure includes a third active region coupled to the second wire by a third via; a fourth active region coupled to the second power rail by a fourth via; and a second gate structure between the third active region and the fourth active region and configured to receive the second control signal. In some embodiments, a first voltage received by the first power rail is substantially different from a second voltage received by the second power rail. In some embodiments, the first control signal is floating. In some embodiments, the first wire is on a front side of the semiconductor device and the first power rail is on a back side of the semiconductor device. In some embodiments, the first transistor structure further includes a plurality of first transistors coupled in series. The first active region is included in a structure that serves as a terminal of a first transistor of the plurality of first transistors, and the second active region is included in a structure that serves as a terminal of a second transistor of the plurality of first transistors. In some embodiments, gate terminals of the plurality of first transistors are floating or coupled to ground. In some embodiments, the first wire includes a first portion and a second portion separated from the first portion in a second direction different from the first direction. The first portion of the first wire is coupled to the first active region by the first via, and the second portion of the first wire is coupled to the second active region by the third via. In some embodiments, the first wire and the first power rail extend in the second direction different from the first direction. In a third direction different from the first direction and the second direction, a width of the first power rail is greater than a width of the first wire.

[0171] Also disclosed is a semiconductor device including at least one first cell and at least one second cell. The at least one first cell includes: a first active region of a first conductivity type, in a first layer; a first power rail, in a second layer below the first layer; and a first via coupled between the first active region and the first power rail. The at least one second cell is adjacent to a first side of the at least one first cell. The at least one second cell includes: a second active region of a second conductivity type different from the first conductivity type, in the first layer; a second power rail, in the second layer; and a second via coupled between the second active region and the second power rail. The at least one second cell is a mirror of the at least one first cell across a mirror line. In some embodiments, the at least one first cell includes a plurality of first cells, and the at least one second cell includes a plurality of second cells. The plurality of first cells and the plurality of second cells are interleaved. In some embodiments, the semiconductor device includes a third cell disposed at a second side of the at least one first cell opposite the first side. The third cell includes: a third active region of the first conductivity type, in the first layer; a third power rail, in the second layer; and a third via coupled between the third active region and the third power rail. In some embodiments, the first conductivity type is P-type and the second conductivity type is N-type. In some embodiments, a number of metal traces included in the at least one first cell is a non-integer, and a total number of metal traces included in the at least one first cell and the at least one second cell is an integer.

[0172] Also disclosed is a method including operations of: identifying a connection configuration between a first node and a second node in an integrated circuit; and

[0173] In response to the connection configuration indicating that the first node is configured to receive a supply voltage from the second node, generating a layout design of the integrated circuit includes: generating a first wire that extends in a first direction in a first layer of a front side of the integrated circuit and is configured to be coupled to the first node; generating a supply rail that extends in the first direction in a second layer below the first layer of a back side of the integrated circuit and is configured to be coupled to the second node; generating an active region that extends in the first direction in a third layer between the first layer and the second layer; generating a first via coupled between a first region of the active region and the first wire and generating a second via coupled between a second region of the active region and the first wire; and generating a third via coupled between the first region of the active region and the supply rail and generating a fourth via coupled between the second region of the active region and the supply rail. In some embodiments, in a second direction different from the first direction, the active region, the third via, and the fourth via have a same width. In some embodiments, generating the layout design of the integrated circuit further includes: generating a plurality of gate strips that extend in a second direction different from the first direction in the layout design and are interposed between the first via and the second via; and generating a second wire that extends in the first direction, wherein the second wire is separated from the first wire in the second direction and is coupled to the plurality of gate strips. In some embodiments, generating the supply rail includes: generating a first portion of the supply rail and a second portion of the supply rail separated from the first portion in the first direction, wherein, in the layout view, the first via and the third via overlap the first portion of the supply rail and the second via and the fourth via overlap the second portion of the supply rail. In some embodiments, in the layout view, the first via and the third via overlap each other and the second via and the fourth via overlap each other.

[0174] The foregoing summarizes features of several embodiments in order that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions, and alterations thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device comprising: a first wire and a first power rail separated from each other in a first direction and extending in a second direction perpendicular to the first direction, the first direction being a normal direction of a layout of the semiconductor device; and a first transistor structure disposed between the first wire and the first power rail and comprising: a first active region coupled to the first wire by a first via, the first via overlapping and being entirely above the first active region in the first direction; a second active region coupled to the first power rail by a second via, the second via being directly connected under the second active region and on the first power rail; and a first gate structure between the first active region and the second active region and configured to receive a first control signal, the first transistor structure configured to transfer a signal between the first wire and the first power rail in response to the first control signal; a second wire and a second power rail separated from each other in the first direction and from the first wire and the first power rail in the second direction, wherein the second wire is configured to receive the signal transferred through the first wire; and a second transistor structure configured to transfer the signal between the second wire and the second power rail in response to a second control signal different from the first control signal and disposed between the second wire and the second power rail, the second transistor structure comprising: a third active region coupled to the second wire by a third via; a fourth active region coupled to the second power rail by a fourth via; and a second gate structure between the third active region and the fourth active region and configured to receive the second control signal, wherein the first control signal is floating, wherein the second power rail and the first power rail are on a same layer in the first direction. the first active region, the first via, and the third via coupled to the first active region and the first power rail are configured as a first conductive path configured to transfer the signal, and the second active region, the second via, and the fourth via coupled to the second active region and the first wire are configured as a second conductive path configured to transfer the signal.

2. The semiconductor device of claim 1, wherein, the first gate structure comprises a p-type work function metal or an n-type work function metal.

3. The semiconductor device of claim 1, wherein, a first voltage received by the first power rail is substantially different from a second voltage received by the second power rail.

4. The semiconductor device of claim 1, wherein, the first active region is P-type and the second active region is N-type.

5. The semiconductor device of claim 1, wherein, the first wire is on a front side of the semiconductor device and the first power rail is on a back side of the semiconductor device.

6. The semiconductor device of claim 1, wherein, the first transistor structure further comprises a plurality of first transistors coupled in series, 7. The semiconductor device of claim 1, wherein, wherein the first active region is included in a structure serving as a terminal of a first transistor of the plurality of first transistors, and the second active region is included in a structure serving as a terminal of a second transistor of the plurality of first transistors. ​ 8. The semiconductor device of claim 7, wherein, Gate terminals of the plurality of first transistors are floating.

9. The semiconductor device of claim 7, wherein, The first wire includes a first portion and a second portion separated from the first portion in a second direction different from the first direction, wherein the first portion of the first wire is coupled to the first active region through the first via, and the second portion of the first wire is coupled to the second active region through a third via.

10. The semiconductor device of claim 1, wherein The first wire and the first power rail extend in a second direction different from the first direction; wherein, along a third direction different from the first direction and the second direction, a width of the first power rail is greater than a width of the first wire.

11. A semiconductor device, comprising: at least one first cell comprising: a first active region of a first conductivity type in a first layer; a first power rail in a second layer below the first layer; and a first via coupled between the first active region and the first power rail, the first via directly connected under the first active region and on the first power rail; and at least one second cell adjacent to a first side of the at least one first cell, wherein the at least one second cell comprises: a second active region of a second conductivity type different from the first conductivity type in the first layer; a second power rail in the second layer; and a second via coupled between the second active region and the second power rail, the second via directly connected under the second active region and on the second power rail; a first gate structure between the first active region and the second active region and configured to receive a first control signal; a third cell and a fourth cell disposed at a second side of the at least one first cell opposite the first side, and the third cell comprises: a third active region of the first conductivity type in the first layer; a third power rail in the second layer; and a third via coupled between the third active region and the third power rail; the fourth cell comprises: a fourth active region of the second conductivity type in the first layer; a second gate structure between the third active region and the fourth active region and configured to receive a second control signal, wherein the first control signal is floating; wherein the at least one second cell is a mirror of the at least one first cell across a mirror line.

12. The semiconductor device of claim 11, wherein, The at least one first cell comprises a plurality of first cells, and the at least one second cell comprises a plurality of second cells, wherein the plurality of first cells and the plurality of second cells are interleaved.

13. The semiconductor device of claim 11, wherein, The first active region comprises P-type dopants, and the second active region comprises N-type dopants.

14. The semiconductor device of claim 11, wherein, The first conductivity type is P-type, and the second conductivity type is N-type.

15. The semiconductor device of claim 11, wherein, A number of metal traces included in the at least one first cell is a non-integer, and a total number of metal traces included in the at least one first cell and the at least one second cell is an integer.

16. A method of forming a semiconductor device, comprising: identifying a connection configuration between a first node and a second node in an integrated circuit; and In response to the connection configuration indicating that the first node is configured to receive a supply voltage from the second node, generating a layout design of the integrated circuit, comprising: generating a first wire and a second wire, the first wire and the second wire extending in a first direction and being separated from each other in a first layer of a front side of the integrated circuit; generating a first power rail and a second power rail, the first power rail and the second power rail extending in the first direction and being separated from each other in a second layer below the first layer of a back side of the integrated circuit; generating an active region extending in the first direction in a third layer between the first layer and the second layer; generating a first via coupled between a first area of the active region and the first wire, and generating a second via coupled between a second area of the active region and the first wire, the first via and the second via respectively overlapping the first area and the second area of the active region in a vertical direction and respectively being located entirely above the first area and the second area; and generating a third via coupled between the first area of the active region and the first power rail, and generating a fourth via coupled between the second area of the active region and the second power rail, the third via being directly connected below the first area of the active region and on the first power rail, the fourth via being directly connected below the second area of the active region and on the second power rail; wherein the first area and the second area of the active region are active regions of a first transistor, a gate of the first transistor being configured to receive a first control signal, a third area and a fourth area of the active region are active regions of a second transistor, the third area being coupled to a corresponding wire in the first layer through a corresponding via, the fourth area being coupled to a corresponding power rail in the second layer through a corresponding via, a gate of the second transistor being configured to receive a second control signal, wherein the first control signal is floating.

17. The method of claim 16, wherein, In a second direction different from the first direction, the active region, the third via, and the fourth via have a same width.

18. The method of claim 17, wherein, The generating the layout design of the integrated circuit further comprises: generating a plurality of gate straps, the plurality of gate straps extending in the second direction in the layout design and being interposed between the first via and the second via, wherein the second wire is coupled to the plurality of gate straps.

19. The method of claim 16, wherein, In a layout view, the first via and the third via overlap the first power rail, and the second via and the fourth via overlap the second power rail.

20. The method of claim 16, wherein, In a layout view, the first via and the third via overlap each other, and the second via and the fourth via overlap each other.

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