Transistor gate and method of forming the same

Abstract

The present disclosure relates to transistor gates and methods for forming the same. A device includes: a first nanostructure; a second nanostructure, the second nanostructure being located above the first nanostructure; a first high-k gate dielectric, the first high-k gate dielectric being disposed around the first nanostructure; a second high-k gate dielectric, the second high-k gate dielectric being disposed around the second nanostructure; and a gate electrode, the gate electrode being located above the first high-k gate dielectric and the second high-k gate dielectric. A portion of the gate electrode located between the first nanostructure and the second nanostructure includes a first portion of a p-type work function metal filling a region between the first high-k gate dielectric and the second high-k gate dielectric.

Description

Technical Field

[0001] The present disclosure relates to transistor gates and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be solved. Summary of the invention

[0004] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a first nanostructure; a second nanostructure, wherein the second nanostructure is located above the first nanostructure; a first high-k gate dielectric, wherein the first high-k gate dielectric is arranged around the first nanostructure; a second high-k gate dielectric, wherein the second high-k gate dielectric is arranged around the second nanostructure; and a gate electrode, wherein the gate electrode is located above the first high-k gate dielectric and the second high-k gate dielectric, wherein a portion of the gate electrode located between the first nanostructure and the second nanostructure includes a first portion of a p-type work function metal filling a region between the first high-k gate dielectric and the second high-k gate dielectric.

[0005] According to another embodiment of the present disclosure, a transistor is provided, comprising: a first nanostructure, wherein the first nanostructure is located on a semiconductor substrate; a second nanostructure, wherein the second nanostructure is located on the first nanostructure; a gate dielectric, wherein the gate dielectric surrounds the first nanostructure and the second nanostructure; and a gate electrode, wherein the gate electrode is located on the gate dielectric, wherein the gate electrode comprises: a p-type work function metal, wherein the p-type work function metal extends continuously from a first portion of the gate dielectric located on the first nanostructure to a second portion of the gate dielectric located on the second nanostructure; an adhesion layer, wherein the adhesion layer is located on the p-type work function metal; and a filling metal, wherein the filling metal is located on the adhesion layer.

[0006] According to another embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: depositing a gate dielectric around a first nanostructure and a second nanostructure, the first nanostructure being disposed above the second nanostructure; and depositing a p-type work function metal above the gate dielectric, wherein depositing the p-type work function metal comprises: depositing a first portion of the p-type work function metal on a top surface of the second nanostructure, and depositing a second portion of the p-type work function metal on a bottom surface of the second nanostructure; and continuing to deposit the p-type work function metal until the first portion of the p-type work function metal merges with the second portion of the p-type work function metal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When with Figure 1 When read together, various aspects of the present disclosure will be best understood from the following detailed description. It should be noted that, in accordance with industry standard practice, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 An example of a nanostructured field effect transistor (nanoFET) in a three-dimensional view is shown in accordance with some embodiments.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 11C , Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.13A , Fig. 13B , Fig. 13C , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig.19C , Fig.19D , Fig.22A , Fig. 22B , Fig.23A , Fig. 23B , Fig.23C , Fig.24A , Fig. 24B , Fig.24C , Fig.25A , Fig.25B and Fig.25C are cross-sectional and top-down views of intermediate stages in fabricating a nanoFET, according to some embodiments.

[0010] Fig. 20 is a cross-sectional view of a nanoFET according to some embodiments.

[0011] Fig.21 is a cross-sectional view of a nanoFET according to some embodiments.

[0012] Fig.26A , Fig.26B and Fig.26C is a cross-sectional view of a nanoFET according to some embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for realizing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another (or multiple) element or feature as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0015] The thickness of the work function metal (WFM) layer(s) in the transistor gate stack affects the threshold voltage (V TH). However, it has been determined that thickness variations due to merging regions of the WFM layer (e.g., between nanowires of a nanoFET) may not significantly affect the electrical characteristics of the transistor. In addition, by not depositing a barrier layer around the WFM layer (e.g., to prevent partial merging of the WFM layer), ease of manufacturing may be improved. This is particularly true in advanced semiconductor nodes with small feature sizes because barrier layer materials (e.g., tantalum nitride, etc.) may be difficult to deposit in small spaces. Therefore, by omitting such a barrier layer in the gate stack and allowing the WFM layer to merge in certain areas, ease of manufacturing may be improved and manufacturing defects (e.g., caused by poor barrier layer deposition) may be reduced without significantly affecting the electrical performance of the resulting transistor.

[0016] Figure 1 An example of a nanoFET (e.g., a nanowire FET, a nanosheet FET, etc.) in a three-dimensional view according to some embodiments is shown. The nanoFET includes a nanostructure 55 (e.g., a nanosheet, a nanowire, etc.) located on a fin 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 acts as a channel region of the nanoFET. The nanostructure 55 may include a p-type nanostructure, an n-type nanostructure, or a combination thereof. An isolation region 68 is disposed between adjacent fins 66, and the fins 66 may protrude from between and above adjacent isolation regions 68. Although the isolation region 68 is described / illustrated as being separate from the substrate 50, as used herein, the term "substrate" may refer to a semiconductor substrate alone or to a combination of a semiconductor substrate and an isolation region. In addition, although the bottom portion of the fin 66 is illustrated as a single, continuous material with the substrate 50, the bottom portion of the fin 66 and / or the substrate 50 may contain a single material or multiple materials. In this case, the fin 66 refers to a portion extending between adjacent isolation regions 68.

[0017] The gate dielectric 100 is located on the top surface of the fin 66 and along the top surface, sidewalls and bottom surface of the nanostructure 55. The gate electrode 102 is located on the gate dielectric 100. The epitaxial source / drain regions 92 are disposed on the fin 66 on opposite sides of the gate dielectric 100 and the gate electrode 102.

[0018] Figure 1Reference cross sections used in subsequent figures are also shown. Cross section AA' is along the longitudinal axis of gate electrode 102 and in a direction, e.g., perpendicular to the direction of current flow between epitaxial source / drain regions 92 of the nanoFET. Cross section BB' is perpendicular to cross section AA' and parallel to the longitudinal axis of fins 66 of the nanoFET and in a direction of current flow, e.g., between epitaxial source / drain regions 92 of the nanoFET. Cross section CC' is parallel to cross section AA' and extends through the epitaxial source / drain regions of the nanoFET. For clarity, subsequent figures refer to these reference cross sections.

[0019] Some embodiments discussed herein are discussed in the context of nano FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Additionally, some embodiments contemplate various aspects used in planar devices such as planar FETs or fin field effect transistors (FinFETs).

[0020] Figures 2 to 24C is a cross-sectional view of an intermediate stage in fabricating a nanoFET according to some embodiments. Figures 2 to 5 , Fig. 6A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20 , Fig.21 , Fig.22A , Fig.23A , Fig.24A , Fig.25A and Fig.26A Shows Figure 1 Reference section AA' is shown. Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 11C , Fig. 12B , Fig.12D , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 22B , Fig. 23B , Fig. 24B , Fig.25B and Fig.26B Shows Figure 1 Reference section BB' is shown. Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig. 12C , Fig. 13C , Fig.23C , Fig.24C , Fig.25C and Fig.26C Shows Figure 1 Reference section CC' shown.

[0021] exist Figure 2 In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., using p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide layer (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or a combination thereof.

[0022] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, such as an n-type nano FET, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, such as a p-type nano FET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by the separator 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be set between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0023] Further in Figure 2In the embodiment of the present invention, a multilayer stack 64 is formed on the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-C (collectively referred to as second semiconductor layers 53). For the purpose of illustration and as discussed in more detail below, the second semiconductor layer 53 will be removed and the first semiconductor layer 51 will be patterned to form a channel region of the nanoFET in the p-type region 50P. In addition, the first semiconductor layer 51 will be removed and the second semiconductor layer 53 will be patterned to form a channel region of the nanoFET in the n-type region 50N. However, in some embodiments, the first semiconductor layer 51 can be removed and the second semiconductor layer 53 can be patterned to form a channel region of the nanoFET in the n-type region 50N, and the second semiconductor layer 53 can be removed and the first semiconductor layer 51 can be patterned to form a channel region of the nanoFET in the p-type region 50P.

[0024] In still other embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of a nanoFET in both the n-type region 50N and the p-type region 50P. In other embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of a nanoFET in both the n-type region 50N and the p-type region 50P. In such embodiments, the channel regions in both the n-type region 50N and the p-type region 50P may have the same material composition (e.g., silicon, etc.) and may be formed simultaneously. Fig.26A , Fig.26B and Fig.26C The resulting structure of such an embodiment is shown in which the channel regions in both the p-type region 50P and the n-type region 50N include, for example, silicon.

[0025] For the purpose of illustration, the multilayer stack 64 is shown as including three layers of each of the first semiconductor layer 51 and the second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for a p-type nano FET (e.g., silicon germanium, etc.), and the second semiconductor layer 53 may be formed of a second semiconductor material suitable for an n-type nano FET (e.g., silicon, silicon carbon, etc.). For the purpose of illustration, the multilayer stack 64 is shown as having a bottommost semiconductor layer suitable for a p-type nano FET. In some embodiments, the multilayer stack 64 may be formed so that the bottommost layer is a semiconductor layer suitable for an n-type nano FET.

[0026] The first semiconductor material and the second semiconductor material can be materials with high etching selectivity to each other. In this way, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material in the n-type region 50N, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the n-type NSFET. Similarly, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material in the p-type region 50P, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the p-type NSFET. In other embodiments, the channel regions in the n-type region 50N and the p-type region 50P can be formed simultaneously and have the same material composition, such as silicon, silicon germanium, etc. Fig.26A , Fig.26B and Fig.26C The resulting structure of such an embodiment is shown in which the channel regions in both the p-type region 50P and the n-type region 50N include, for example, silicon.

[0027] Reference now Figure 3 According to some embodiments, fins 66 are formed in substrate 50 and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50, respectively, by etching trenches in multilayer stack 64 and substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. Etching can be anisotropic. Forming nanostructure 55 by etching multilayer stack 64 can further define first nanostructures 52A-C (collectively referred to as first nanostructures 52) from first semiconductor layer 51, and define second nanostructures 54A-C (collectively referred to as second nanostructures 54) from second semiconductor layer 53. First nanostructure 52 and second nanostructure 54 can be further collectively referred to as nanostructure 55.

[0028] The fins 66 and nanostructures 55 may be patterned by any suitable method. For example, the fins 66 and nanostructures 55 may be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. In general, double patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing patterns to be created with, for example, a smaller pitch than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins 66.

[0029] For illustration purposes, Figure 3The fins 66 in the n-type region 50N and the p-type region 50P are shown as having substantially equal widths. In some embodiments, the width of the fins 66 in the n-type region 50N may be greater than or less than the fins 66 in the p-type region 50P. In addition, although each of the fins 66 and the nanostructures 55 are shown as having a uniform width, in other embodiments, the fins 66 and / or the nanostructures 55 may have tapered sidewalls such that the width of each of the fins 66 and / or the nanostructures 55 increases continuously in a direction toward the substrate 50. In such embodiments, each of the nanostructures 55 may have different widths and be trapezoidal in shape.

[0030] exist Figure 4 In the embodiment, a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material on the substrate 50, the fin 66 and the nanostructure 55 and between adjacent fins 66. The insulating material can be an oxide (e.g., silicon oxide), a nitride, etc., or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), etc., or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In an embodiment, the insulating material is formed so that excess insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown separately) can be first formed along the surface of the substrate 50, the fin 66 and the nanostructure 55. Thereafter, a filling material such as described above can be formed on the liner.

[0031] A removal process is then applied to the insulating material to remove excess insulating material above the nanostructures 55. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), a deep etching process, a combination thereof, etc. may be utilized. The planarization process exposes the nanostructures 55 so that the top surfaces of the nanostructures 55 and the insulating material are flush after the planarization process is completed.

[0032] The insulating material is then recessed to form STI regions 68. The insulating material is recessed so that the upper portions of the fins 66 in regions 50N and 50P protrude from between adjacent STI regions 68. In addition, the top surface of the STI regions 68 can have a flat surface (as shown), a convex surface, a concave surface (e.g., a dished shape), or a combination thereof. The top surface of the STI regions 68 can be formed to be flat, convex, and / or concave by appropriate etching. The STI regions 68 can be recessed using an acceptable etching process that is selective to the material of the insulating material (e.g., a material that etches the insulating material at a faster rate than the material of the fins 66 and the nanostructures 55). For example, the oxide can be removed using, for example, dilute hydrofluoric acid (dHF).

[0033] The above about Figures 2 to 4 The process described is only one example of how the fin 66 and nanostructure 55 may be formed. In some embodiments, the fin 66 and / or nanostructure 55 may be formed using a mask and epitaxial growth process. For example, a dielectric layer may be formed above the top surface of the substrate 50, and a trench may be etched through the dielectric layer to expose the underlying substrate 50. The epitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the epitaxial structure protrudes from the dielectric layer to form the fin 66 and / or nanostructure 55. The epitaxial structure may include the alternating semiconductor materials described above, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxially grown epitaxial structures, the epitaxially grown material may be doped in situ during growth, which may avoid prior and / or subsequent implantation, although in situ doping and implantation doping may be used together.

[0034] In addition, for the purpose of illustration only, the first semiconductor layer 51 (and the resulting first nanostructure 52) and the second semiconductor layer 53 (and the resulting second nanostructure 54) shown and discussed herein include the same material in the p-type region 50P and the n-type region 50N. Thus, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials or formed in a different order in the p-type region 50P and the n-type region 50N.

[0035] Further in Figure 4In the embodiment with different well types, a photoresist or other mask (not shown separately) can be used to implement different implantation steps of the n-type region 50N and the p-type region 50P. For example, a photoresist can be formed over the fins 66 and the STI regions 68 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed by using a spin coating technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implantation is performed in the p-type region 50P, and the photoresist can act as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurity can be phosphorus, arsenic, antimony, etc., which is implanted into the region, and its concentration ranges from about 10 13 Atom / cm 3 To about 10 14 Atom / cm 3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0036] After or before implanting the p-type region 50P, a photoresist or other mask (not separately shown) is formed over the fins 66, nanostructures 55, and STI regions 68 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed by using a spin coating technique, and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can act as a mask to substantially prevent the p-type impurity from being implanted into the p-type region 50P. The p-type impurity can be boron, boron fluoride, indium, etc., which is implanted into the region, and its concentration ranges from about 10 13 Atom / cm 3 To about 10 14 Atom / cm 3 After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0037] After implanting n-type region 50N and p-type region 50P, annealing may be performed to repair implant damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the grown epitaxial fin material may be in-situ doped during growth, which may avoid implantation, although in-situ doping and implantation doping may be used together.

[0038] exist Figure 5In the embodiment of the present invention, a dummy dielectric layer 70 is formed on the fin 66 and / or the nanostructure 55. The dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and may be deposited or thermally grown according to an acceptable technique. A dummy gate layer 72 is formed on the dummy dielectric layer 70, and a mask layer 74 is formed on the dummy gate layer 72. The dummy gate layer 72 may be deposited on the dummy dielectric layer 70, and then planarized, for example, by CMP. The mask layer 74 may be deposited on the dummy gate layer 72. The dummy gate layer 72 may be a conductive or non-conductive material, and may be selected from a group including: amorphous silicon, polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. The dummy gate layer 72 may be made of other materials having high etch selectivity from etching the isolation region. The mask layer 74 may include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed on the n-type region 50N and the p-type region 50P. Note that the dummy dielectric layer 70 is shown to cover only the fin 66 and the nanostructure 55 for illustration purposes only. In some embodiments, the dummy dielectric layer 70 may be deposited so that the dummy dielectric layer 70 covers the STI region 68 so that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

[0039] FIG. 6A to FIG. 18B Various additional steps in fabricating example devices are shown. Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig. 12C , Fig.13A , Fig. 13C , Fig.14A , Fig.15A and Fig.18B Features in region 50N or region 50P are shown. Fig. 6A and Figure 6B In the embodiment, the mask layer 74 (see Figure 5 ) can be patterned using acceptable photolithography and etching techniques to form a mask 78. The pattern of mask 78 can then be transferred to dummy gate layer 72 and dummy dielectric layer 70 to form dummy gate 76 and dummy gate dielectric 71, respectively. Dummy gate 76 covers the corresponding channel region of fin 66. The pattern of mask 78 can be used to physically separate each dummy gate 76 from adjacent dummy gates 76. Dummy gate 76 can also have a longitudinal direction substantially perpendicular to the longitudinal direction of the corresponding fin 66.

[0040] exist Fig. 7A and Figure 7B In Fig. 6A and Figure 6B A first spacer layer 80 and a second spacer layer 82 are formed on top of the structure shown. The first spacer layer 80 and the second spacer layer 82 will be patterned later to serve as spacers for forming self-aligned source / drain regions. Fig. 7A and Figure 7B , a first spacer layer 80 is formed on the following: the top surface of the STI region 68; the top surface and sidewalls of the fin 66, the nanostructure 55, and the mask 78; and the sidewalls of the dummy gate 76 and the dummy gate dielectric 71. A second spacer 82 is deposited on the first spacer layer 80. The first spacer layer 80 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc. using a technique such as thermal oxidation, or deposited by CVD, ALD, etc. The second spacer layer 82 can be formed of a material having a different etch rate from the material of the first spacer layer 80 (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.), and can be deposited by CVD, ALD, etc.

[0041] After forming the first spacer layer 80 and before forming the second spacer layer 82, an implantation for lightly doped source / drain (LDD) regions (not shown separately) may be performed. Figure 4 As discussed in the implantation, a mask (e.g., photoresist) may be formed over the n-type region 50N while exposing the p-type region 50P, and an appropriate type (e.g., p-type) of impurities may be implanted into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask may then be removed. Subsequently, a mask (e.g., photoresist) may be formed over the p-type region 50P while exposing the n-type region 50N, and an appropriate type (e.g., n-type) of impurities may be implanted into the exposed fins 66 and nanostructures 55 in the n-type region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities previously discussed, and the p-type impurity may be any of the p-type impurities previously discussed. The impurity concentration of the lightly doped source / drain region may be in the range of from about 1x10 15 Atom / cm 3 To about 1x10 19 Atom / cm 3 Annealing can be used to repair implant damage and activate the implanted impurities.

[0042] exist Fig. 8A and Figure 8B, the first spacer layer 80 and the second spacer layer 82 are etched to form the first spacer 81 and the second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 act to self-align the subsequently formed source / drain regions, and to protect the sidewalls of the fin 66 and / or the nanostructure 55 during subsequent processing. The first spacer layer 80 and the second spacer layer 82 can be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), etc. In some embodiments, the material of the second spacer layer 82 has a different etching rate than the material of the first spacer layer 80, so that the first spacer layer 80 can act as an etching stop layer when the second spacer layer 82 is patterned, and so that the second spacer layer 82 can act as a mask when the first spacer layer 80 is patterned. For example, the second spacer layer 82 may be etched using an anisotropic etching process, wherein the first spacer layer 80 acts as an etch stop layer, wherein the remaining portion of the second spacer layer 82 forms the second spacer layer 83, such as Fig. 8A Thereafter, the second spacer layer 83 acts as a mask when etching the exposed portion of the first spacer layer 80, thereby forming Fig. 8A The first spacer 81 is shown.

[0043] like Fig. 8A As shown, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55. Figure 8B As shown, in some embodiments, the second spacer layer 82 may be removed from above the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, the dummy gate 76, and the dummy gate dielectric 71. In other embodiments, a portion of the second spacer layer 82 may remain above the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71.

[0044] It should be noted that the above disclosure generally describes the process of forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be used (for example, the first spacer 81 can be patterned before the second spacer layer 82 is deposited), additional spacers can be formed and removed, etc. In addition, different structures and steps can be used to form n-type and p-type devices.

[0045] exist Fig.9A and Fig. 9BIn some embodiments, a first recess 86 is formed in the fin 66, the nanostructure 55, and the substrate 50. An epitaxial source / drain region will be subsequently formed in the first recess 86. The first recess 86 may extend through the first nanostructure 52 and the second nanostructure 54 and extend into the substrate 50. Fig.9A As shown, the top surface of the STI region 68 can be flush with the bottom surface of the first recess 86. In various embodiments, the fin 66 can be etched so that the bottom surface of the first recess 86 is disposed below the top surface of the STI region 68, etc. The first recess 86 can be formed by etching the fin 66, the nanostructure 55, and the substrate 50 using an anisotropic etching process such as RIE, NBE, etc. During the etching process for forming the first recess 86, the first spacer 81, the second spacer 83, and the mask 78 shield portions of the fin 66, the nanostructure 55, and the substrate 50. Each layer of the nanostructure 55 and / or the fin 66 can be etched using a single etching process or a multiple etching process. A timed etching process can be used to stop etching the first recess 86 after the first recess 86 reaches a desired depth.

[0046] exist Fig. 10A and Fig. 10B In the embodiment, the sidewalls of each layer of the multilayer stack 64 formed of the first semiconductor material (e.g., the first nanostructure 52) are etched at portions exposed by the first grooves 86 to form sidewall grooves 88 in the n-type region 50N, and the sidewalls of each layer of the multilayer stack 64 formed of the second semiconductor material (e.g., the second nanostructure 54) are etched at portions exposed by the first grooves 86 to form sidewall recesses 88 in the p-type region 50P. Although the sidewalls of the first nanostructure 52 and the second nanostructure 54 in the grooves 88 are not exposed by the first grooves 86, the sidewall recesses 88 are not exposed by the first grooves 86. Fig. 10B50N, but the sidewalls may be concave or convex. The sidewalls may be etched using an isotropic etching process such as wet etching. A mask (not shown) may be used to protect the p-type region 50P while etching the first nanostructure 52 using an etchant selective to the first semiconductor material, so that the second nanostructure 54 and the substrate 50 remain relatively unetched relative to the first nanostructure 52 in the n-type region 50N. Similarly, a mask (not shown) may be used to protect the n-type region 50N while etching the second nanostructure 54 using an etchant selective to the second semiconductor material, so that the first nanostructure 52 and the substrate 50 remain relatively unetched relative to the second nanostructure 54 in the p-type region 50P. In an embodiment where the first nanostructure 52 includes, for example, SiGe and the second nanostructure 54 includes, for example, Si or SiC, the sidewalls of the first nanostructure 52 can be etched in the n-type region 50N using a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., and the sidewalls of the second nanostructure 54 can be etched in the p-type region 50P using a dry etching process using hydrogen fluoride, another fluorine-based gas, etc.

[0047] exist Figures 11A-11C In the embodiment, the first inner spacer 90 is formed in the sidewall groove 88. Fig. 10A and Fig. 10B An internal spacer layer (not shown separately) is deposited on the structure shown to form a first internal spacer 90. The first internal spacer 90 acts as an isolation feature between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in the recess 86, and the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P will be replaced by corresponding gate structures.

[0048] The inner spacer layer may be deposited by a conformal deposition process (e.g., CVD, ALD, etc.). The inner spacer layer may include a material such as silicon nitride or silicon oxynitride, although any suitable material may be utilized, such as a low dielectric constant (low-k) material having a k value of less than about 3.5. The inner spacer layer may then be anisotropically etched to form a first inner spacer 90. Although the outer sidewalls of the first inner spacer 90 are shown flush with the sidewalls of the second nanostructure 54 in the n-type region 50N and flush with the sidewalls of the first nanostructure 52 in the p-type region 50P, the outer sidewalls of the first inner spacer 90 may extend beyond or be recessed from the sidewalls of the second nanostructure 54 and / or the first nanostructure 52, respectively.

[0049] In addition, despite the Fig. 11BThe outer sidewall of the first inner spacer 90 is shown as straight, but the outer sidewall of the first inner spacer 90 can be concave or convex. As an example, Fig. 11C An embodiment is shown in which the sidewalls of the first nanostructure 52 are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed from the sidewalls of the second nanostructure 54 in the n-type region 50N. Some embodiments are also shown in which the sidewalls of the second nanostructure 54 are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed from the sidewalls of the first nanostructure 52 in the p-type region 50P. The inner spacer layer can be etched by an anisotropic etching process such as RIE, NBE, etc. The first inner spacer 90 can be used to prevent the subsequently formed source / drain regions (for example, below for Figures 12A-12C The epitaxial source / drain regions 92 in question are damaged by subsequent etching processes (eg, etching processes used to form gate structures).

[0050] exist Figures 12A-12C In the embodiment, the epitaxial source / drain region 92 is formed in the first recess 86. In some embodiments, the source / drain region 92 can apply stress to the second nanostructure 54 in the n-type region 50N and the first nanostructure 52 in the p-type region 50P, thereby improving performance. Fig. 12B As shown, epitaxial source / drain regions 92 are formed in first recesses 86 such that each dummy gate 76 is disposed between a corresponding adjacent pair of epitaxial source / drain regions 92. In some embodiments, first spacers 81 are used to separate epitaxial source / drain regions 92 from dummy gates 76, and first internal spacers 90 are used to separate epitaxial source / drain regions 92 from nanostructures 55 by an appropriate lateral distance such that epitaxial source / drain regions 92 do not short circuit with a subsequently formed gate of the resulting nanoFET.

[0051] The epitaxial source / drain region 92 in the n-type region 50N (e.g., NMOS region) can be formed by masking the p-type region 50P (e.g., PMOS region). Then, the epitaxial source / drain region 92 is epitaxially grown in the first recess 86 in the n-type region 50N. The epitaxial source / drain region 92 may include any acceptable material suitable for an n-type nanoFET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 may include a material that applies tensile strain to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 92 may have a surface that protrudes from the corresponding upper surface of the nanostructure 55 and may have a small facet.

[0052] The epitaxial source / drain region 92 in the p-type region 50P (e.g., PMOS region) can be formed by masking the n-type region 50N (e.g., NMOS region). Then, the epitaxial source / drain region 92 is epitaxially grown in the first recess 86 in the p-type region 50P. The epitaxial source / drain region 92 can include any acceptable material suitable for a p-type nano FET. For example, if the first nanostructure 52 is silicon germanium, the epitaxial source / drain region 92 can include a material that applies compressive strain to the first nanostructure 52, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain region 92 can also have a surface that protrudes from the corresponding surface of the multilayer stack 64 and can have a small facet.

[0053] The epitaxial source / drain regions 92, the first nanostructures 52, the second nanostructures 54, and / or the substrate 50 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, and then annealed. The source / drain regions may have an impurity concentration between about 1x10 19 Atom / cm 3 and about 1x10 21 Atom / cm 3 The n-type and / or p-type impurities of the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 may be doped in situ during growth.

[0054] As a result of the epitaxial process used to form epitaxial source / drain regions 92 in n-type region 50N and p-type region 50P, the upper surface of epitaxial source / drain regions 92 has facets that extend laterally outward from the sidewalls of nanostructures 55. Fig. 12A As shown, these facets allow adjacent epitaxial source / drain regions 92 of the same NSFET to merge. Fig. 12C As shown, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed. Fig. 12A and 12C In the illustrated embodiment, the first spacer 81 may be formed to the top surface of the STI region 68, thereby preventing epitaxial growth. In some other embodiments, the first spacer 81 may cover portions of the sidewalls of the nanostructure 55, thereby further preventing epitaxial growth. In some other embodiments, the spacer etch used to form the first spacer 81 may be adjusted to remove the spacer material to allow the epitaxial growth region to extend to the surface of the STI region 68.

[0055] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of a different semiconductor material and may be doped to a different dopant concentration. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration that is less than the second semiconductor material layer 92B and greater than the third semiconductor material layer 92C. In an embodiment where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited on the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited on the second semiconductor material layer 92B.

[0056] Fig.12D An embodiment is shown in which the sidewalls of the first nanostructure 52 in the n-type region 50N and the sidewalls of the second nanostructure 54 in the p-type region 50P are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed from the sidewalls of the second nanostructure 54 and the first nanostructure 52, respectively. Fig.12D As shown, the epitaxial source / drain regions 92 may be formed in contact with the first internal spacer 90 and may extend through the sidewalls of the second nanostructures 54 in the n-type region 50N and through the sidewalls of the first nanostructures 52 in the p-type region 50P.

[0057] exist Figures 13A-13C In the embodiment, the first interlayer dielectric (ILD) 96 is deposited on Fig. 6A , Fig. 12B and Fig. 12A On top of the structure shown ( Figures 7A-12D The process will not change Fig. 6A). The first ILD 96 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain regions 92, the mask 78, and the first spacer 81. The CESL 94 may include a dielectric material having an etch rate different from that of the material overlying the first ILD 96, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0058] exist Figures 14A-14B In the process, a planarization process, such as CMP, may be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76 and the portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 remain flush within the process variation range. Therefore, the top surface of the dummy gate 76 is exposed through the first ILD 96. In some embodiments, the mask 78 may remain, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0059] exist Fig.15A and 15B In the embodiment of the present invention, the dummy gate 76 and the mask 78 (if present) are removed in one or more etching steps to form a second groove 98. Portions of the dummy gate dielectric 71 in the second groove 98 are also removed. In some embodiments, the dummy gate 76 and the dummy gate dielectric 71 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using (one or more) reactive gases that selectively etches the dummy gate 76 at a faster rate than the first ILD 96 or the first spacer 81. Each second groove 98 exposes and / or covers a portion of the nanostructure 55, which acts as a channel region in a subsequently completed nanoFET. The portion of the nanostructure 55 that acts as a channel region is disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, when etching the dummy gate 76, the dummy gate dielectric 71 may serve as an etch stop layer. Then, the dummy gate dielectric 71 may be removed after the dummy gate 76 is removed.

[0060] exist Figures 16A to 21In some embodiments, nanostructures are defined in the p-type region 50P and the n-type region 50N, and a gate dielectric layer and a gate electrode are formed to replace the gate. The formation of the gate dielectric layer in the n-type region 50N and the p-type region 50P can occur simultaneously, so that the gate dielectric layer in each region is formed of the same material, and the formation of the gate electrode can occur simultaneously, so that the gate electrode in each region is formed of the same material. In some embodiments, the gate dielectric layer in each region can be formed by different processes, so that the gate dielectric layer can be a different material and / or have a different number of layers, and / or the gate electrode in each region can be formed by different processes, so that the gate electrode can be a different material and / or have a different number of layers. When different processes are used, various masking steps can be used to mask and expose appropriate areas. In the following description, the gate electrode of the n-type region 50N and the gate electrode of the p-type region 50P are formed separately.

[0061] exist Fig.16A and 16B In the embodiment, the second nanostructure 54 in the p-type region 50P can be removed by forming a mask (not shown) over the n-type region 50N and performing an isotropic etching process such as wet etching or the like using an etchant selective to the material of the second nanostructure 54, while the first nanostructure 52, the substrate 50, and the STI region 68 remain relatively unetched compared to the second nanostructure 54. In embodiments where the second nanostructure 54 includes, for example, SiGe and the first nanostructure 52 includes, for example, Si or SiC, the second nanostructure 54 in the p-type region 50P can be removed using hydrogen fluoride, another fluorine-based gas, or the like.

[0062] like Fig.16A As shown, the first nanostructure 52 may have a height H1 and a width W1, and the ratio of the height H1 to the width W1 may be in the range of about 0.05 to about 4. In some embodiments, the ratio is sufficient to avoid affecting the I of the device while still being controllable during the deposition process. 导通 For example, it has been observed that when the ratio of height H1 to width W1 is greater than 4, the channel region of the nanoFET may be too thick and affect the I of the resulting device. 导通 It has been observed that when the ratio of height H1 to width W1 is greater than 4, the channel region may be too thin to be controlled during deposition due to physical limitations of the film deposition process.

[0063] In other embodiments, the channel regions in the n-type region 50N and the p-type region 50P can be formed simultaneously, for example, by removing the first nanostructure 52 in both the n-type region 50N and the p-type region 50P or by removing the second nanostructure 54 in both the n-type region 50N and the p-type region 50P. In such embodiments, the channel regions of the n-type NSFET and the p-type NSFET can have the same material composition, such as silicon, silicon germanium, etc. Fig.26A , Fig.26B and Fig.26C 5 shows a structure resulting from an embodiment in which the channel regions in both the p-type region 50P and the n-type region 50N are provided by a second nanostructure 54 and comprise, for example, silicon. In such an embodiment, the second nanostructure 54 may have the same Fig.16A The same dimensions as discussed above for the first nanostructure 52 .

[0064] Figures 17A to 19B 1 shows that the gate dielectric 100 and the gate electrode 102 are formed in the p-type region 50P, and when the gate electrode 102 is formed in at least the p-type region 50P, the n-type region 50N may be masked (for example, as described below in Figures 18A to 19B ).

[0065] exist Fig.17A and 17B In the embodiment of the present invention, the gate dielectric 100 is conformally deposited in the second recess 98 in the p-type region 50P. The gate dielectric 100 includes one or more dielectric layers, such as oxides, metal oxides, etc., or combinations thereof. For example, in some embodiments, the gate dielectric 100 may include a first gate dielectric 101 (e.g., including silicon oxide, etc.) and a second gate dielectric 103 (e.g., including metal oxide, etc.) located above the first gate dielectric 101. In some embodiments, the second gate dielectric 103 includes a high-k dielectric material, and in these embodiments, the second gate dielectric 103 may have a k value greater than about 7.0 and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. In some embodiments, the first gate dielectric 101 may be referred to as an interfacial layer, and the second gate dielectric 103 may be referred to as a high-k gate dielectric.

[0066] In the n-type region 50N and the p-type region 50P, the structure of the gate dielectric 100 may be the same or different. For example, the n-type region 50N may be shielded or exposed while the gate dielectric 100 is formed in the p-type region 50P. In an embodiment where the n-type region 50N is exposed, the gate dielectric 100 may be simultaneously formed in the n-type region 50N. The formation method of the gate dielectric 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0067] exist Fig.18A and 18B , the conductive material 105 is conformally deposited on the gate dielectric 100 in the p-type region 50P. In some embodiments, the conductive material 105 is a p-type WFM layer including titanium nitride, tantalum nitride, tungsten nitride, molybdenum nitride, etc. The conductive material 105 may be deposited by CVD, ALD, PECVD, PVD, etc. In some embodiments, the conductive material 105 may be deposited on the exposed surface of the gate dielectric 100 to a sufficient thickness so that the conductive material 105 is merged in the region 50I between adjacent first nanostructures 52 (e.g., first nanostructures 52A, 52B, and 52C). For example, the conductive material 105 may be deposited on the surface of the first nanostructure 52 in the region 50I, and as the thickness of the conductive material 105 increases during deposition, separated portions of the conductive material 105 may contact and merge along the seam 105S. Specifically, deposition of conductive material 105 may continue until first portion 105A of conductive material 105 merges with second portion 105B of conductive material 105 in region 50I.

[0068] like Fig.18A As shown, the conductive material 105 may have a thickness T1 outside the region 50I (e.g., an unmerged region of the conductive material 105) and a thickness T2 in the region 50I (e.g., a merged region of the conductive material 105). For example, the conductive material 105 may have a thickness T1 on the sidewalls of the first nanostructure 52 and on the uppermost surface of the first nanostructure 52. The thickness T1 may have a sufficient thickness to fill the space between adjacent first nanostructures 52 (e.g., first nanostructures 52A, 52B, and 52C). For example, the thickness T1 may be at least half of the thickness T2, and the ratio of the thickness T2 to the thickness T1 may be no greater than about 2:1.

[0069] In some embodiments, the thickness T1 may be approximately To date It has been observed that when the thickness T1 is greater than about When the thickness T1 is less than about 100 mm, the volume of the conductive material 105 may not be necessarily large and limit the process window for forming a fill metal (e.g., fill metal 117 discussed below) for the gate electrode. It has been observed that when the thickness T1 is less than about When the conductive layer 10 is not fully filled in the space between adjacent nanostructures of the first nanostructure 52, this may cause the threshold voltage performance of the resulting transistor to be unstable.

[0070] At the narrowest point between the first nanostructures 52A, the conductive material 105 has a width W2. In some embodiments, the width W2 is in the range of about 10 nm to about 180 nm. It has been observed that when the width W2 is greater than about 180 nm, the process control of depositing the conductive material 105 and patterning / etching the film in the region 50I may be negatively affected (e.g., similar to the effect of a high aspect ratio). It has been observed that when the width W2 is less than about 10 nm, the effective channel length may be too short, which may have an adverse effect on the I of the resulting transistor. 导通 had a negative impact.

[0071] Furthermore, in some embodiments, the ratio of thickness T2 to width W2 is in a range of about 0.03 to about 1. It has been observed that when the ratio of thickness T2 to width W2 is greater than about 1, conductive layer 104 may be too thick, which may have an adverse effect on the I / O performance of the resulting transistor. 导通 It has been observed that when the ratio of thickness T2 to width W2 is less than about 0.03, process control for depositing conductive material 105 in region 50I may be negatively impacted (eg, similar to the effects of high aspect ratios).

[0072] Conductive material 105 fills the remaining space between first nanostructures 52. For example, region 50I spans the entire distance between adjacent nanostructures in first nanostructure 52 (e.g., between first nanostructures 52A and 52B or between first nanostructures 52B and 52C). Region 50I may be filled with a first portion of gate dielectric 100 (e.g., first gate dielectric 100A), a merged portion of conductive material 105 above and in contact with first gate dielectric 100A, and a second portion of gate dielectric 100 above and in contact with the merged portion of conductive material 105 (e.g., second gate dielectric 100B). First gate dielectric 100A includes interfacial layer 101A and high-k gate dielectric 103A, and second gate dielectric 100B includes interfacial layer 101B and high-k gate dielectric 103B. That is, the conductive material 105 can extend continuously and completely fill the region between the portions of the gate dielectric 100 on the adjacent nanostructures in the first nanostructure 52. It should be noted that there is no barrier layer separating different regions of the conductive material 105 in the region 50I. For example, the gate electrode may not have any barrier layer in the region 50I. By omitting the barrier layer in the inner region 50I, the manufacturing process can be simplified. In addition, it has been observed that the thickness variation of the conductive material 105 (e.g., the difference between the thickness T1 and T2) does not significantly affect the electrical performance of the resulting transistor. For example, in the experimental data, transistors with different thicknesses of the conductive material 105 (e.g., as Fig.18A and18B ) has an effective work function of about 4.89 V. In contrast, a transistor with a more uniform WFM layer (e.g., as provided by an intermediate barrier layer that prevents the WFM layer from merging in region 50I) has an effective work function of about 4.90 V. Thus, various embodiments allow for easier fabrication of transistors with similar effective work functions without significantly degrading the electrical performance of the resulting transistor.

[0073] exist Fig.19A , Fig.19B , Fig.19C and Fig.19D In the embodiment of the present invention, the remaining portion of the gate electrode 102 is deposited to fill the remaining portion of the second groove 98. For example, the adhesion layer 115 and the filling metal 117 can be deposited on the conductive material 105. The resulting gate electrode 102 is formed to replace the gate and can include the conductive material 105, the adhesion layer 115 and the filling metal 117. Fig.19C Shown along Fig.19B A top-down view of line XX' (e.g., in region 50I), and Fig.19D Shown along Fig.19B 1 , a top-down view of line Y-Y' (eg, through the first nanostructure 52).

[0074] In some embodiments, adhesion layer 115 is conformally deposited on conductive material 105 in p-type region 50P. In some embodiments, adhesion layer 115 includes titanium nitride, tantalum nitride, etc. Adhesion layer 115 may be deposited by CVD, ALD, PECVD, PVD, etc. Adhesion layer 115 may be alternatively referred to as a glue layer and improves adhesion between, for example, conductive material 105 and an overlying fill metal 117.

[0075] Fill metal 117 may then be deposited over adhesion layer 115. In some embodiments, fill metal 117 comprises cobalt, ruthenium, aluminum, tungsten, combinations thereof, and the like deposited by CVD, ALD, PECVD, PVD, and the like. In some embodiments, fill metal 117 may comprise tungsten deposited using a CVD process. It has been observed that CVD provides an improved deposition rate for fill metal 117. In some embodiments, the CVD process for depositing fill metal 117 may include providing a first precursor (e.g., WF6, etc.) and a second precursor (e.g., SiH4, etc.) in a CVD process chamber. In some embodiments, the first precursor and the second precursor may be supplied simultaneously during the CVD process for fill metal 117.

[0076] In the p-type region 50P, the gate dielectric 100, the conductive material 105, the adhesion layer 115, and the filling metal 117 can each be formed on the top surface, the sidewall, and the bottom surface of the first nanostructure 52. The gate dielectric 100, the conductive material 105, the adhesion layer 115, and the filling metal 117 can also be deposited on the top surface of the first ILD 96, the CESL 94, the first spacer 81, and the STI region 68. After filling the second groove 98, a planarization process such as CMP can be performed to remove excess portions of the gate dielectric 100, the conductive material 105, the adhesion layer 115, and the filling metal 117, which are located above the top surface of the first ILD 96. Therefore, the remaining portions of the gate electrode 102 and the gate dielectric 100 material form a replacement gate structure of the resulting nanoFET. The gate electrode 102 and the gate dielectric 100 can be collectively referred to as a "gate structure".

[0077] although Fig.19A and 19B The gate dielectric 100 and the gate electrode 102 are shown as having straight sidewalls and square corners, but the gate dielectric 100 and the gate electrode 102 may have different configurations. For example, Fig. 20 1 shows a cross-sectional view of a gate dielectric 100 and a gate electrode 102 according to another embodiment. Fig. 20 In the drawings, similar reference numerals indicate that the Fig.19A and 19B However, in Fig. 20 In the embodiment of the present invention, since the first nanostructure 52 has rounded corners, the gate dielectric 100 and the gate electrode 102 may also have rounded corners.

[0078] In addition, despite Fig.19A and 19B The bottommost nanostructure in the first nanostructure 52 is shown to be in contact with the bottom fin 66, but as shown in FIG. Fig.21 As shown, the bottommost nanostructure in the first nanostructures 52 (eg, the first nanostructure 52A) may be separated from the bottom fin 66. Fig. 20 In the drawings, similar reference numerals indicate that the Fig.19A and 19B The fin 66 may be formed, for example, by providing a second nanostructure 54 between the first nanostructure 52 and the fin 66 and then removing the second nanostructure 54 as described above. Fig.21 As a result, portions of the gate dielectric 100 and the conductive material 105 may be disposed between the bottommost nanostructure in the first nanostructure 52 and the fin 66 .

[0079] Fig.22A and 22BA gate stack in an n-type region 50N is shown. Forming a gate stack in the n-type region 50N may include first removing the first nanostructure 52 in the n-type region 50N. The first nanostructure 52 may be removed by forming a mask (not shown) over the p-type region 50P and performing an isotropic etching process such as a wet etch using an etchant selective to the material of the first nanostructure 52, while the second nanostructure 54, the substrate 50, and the STI region 68 remain relatively unetched compared to the first nanostructure 52. In embodiments where the first nanostructure 52A-52C includes, for example, SiGe and the second nanostructure 54A-54C includes, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to remove the first nanostructure 52 in the n-type region 50N.

[0080] A gate stack is then formed on and around the second nanostructure 54 in the n-type region 50N. The gate stack includes a gate dielectric 100 and a gate electrode 127. In some embodiments, the gate dielectric 100 in the n-type region 50N and the p-type region 50P may be formed simultaneously. In addition, the gate electrode 102 (see Fig.19A and 19B ), and at least a portion of the gate electrode 127 may be formed before or after the p-type region 50P is masked. Therefore, the gate electrode 127 may include a material different from that of the gate electrode 102. For example, the gate electrode 127 may include a conductive layer 121, a barrier layer 123, and a filling metal 125. The conductive layer 121 may be an n-type work function metal (WFM) layer, which includes an n-type metal such as titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, and combinations thereof. The conductive layer 121 may be deposited by CVD, ALD, PECVD, PVD, and the like. The barrier layer 123 may include titanium nitride, tantalum nitride, tungsten carbide, and combinations thereof, and the barrier layer 123 may further serve as an adhesion layer. The barrier layer 123 may be deposited by CVD, ALD, PECVD, PVD, and the like. The filling metal 125 may include cobalt, ruthenium, aluminum, tungsten, and combinations thereof, and the like deposited by CVD, ALD, PECVD, PVD, and the like. Fill metal 125 may or may not have the same material composition and is deposited simultaneously with fill metal 117 .

[0081] After filling the second recess 98, a planarization process such as CMP may be performed to remove excess portions of the gate dielectric 100 and the gate electrode 127 that are above the top surface of the first ILD 96. Thus, the remaining portions of the material of the gate electrode 127 and the gate dielectric 100 form a replacement gate structure of the resulting nanoFET of the n-type region 50N. The CMP processes for removing excess material of the gate electrode 102 in the p-type region 50P and for removing excess material of the gate electrode 127 in the n-type region 50N may be performed simultaneously or separately.

[0082] exist Figures 23A-23C In the embodiment, the gate structure (including the gate dielectric 100, the gate electrode 102 and the gate electrode 127) is recessed so that a groove is formed directly above the gate structure and between the opposite portions of the first spacer 81. A gate mask 104 including one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled in the groove, and then a planarization process is performed to remove excess portions of the dielectric material extending above the first ILD 96. The gate contact portion (e.g., as shown below for Fig.24A and 24B The gate contact 114 discussed penetrates the gate mask 104 to contact the top surfaces of the recessed gate electrodes 102 and 127 .

[0083] like Figures 23A-23C As further shown, the second ILD 106 is deposited over the first ILD 96 and the gate mask 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD, PECVD, etc.

[0084] exist Figures 24A-24C, the second ILD 106, the first ILD 96, the CESL 94, and the gate mask 104 are etched to form a third recess 108, thereby exposing the surface of the epitaxial source / drain region 92 and / or the gate structure. The third recess 108 may be formed by etching using an anisotropic etching process such as RIE, NBE, etc. In some embodiments, the third recess 108 may be etched through the second ILD 106 and the first ILD 96 using a first etching process; the third recess 108 may be etched through the gate mask 104 using a second etching process; and then the third recess 108 may be etched through the CESL 94 using a third etching process. A mask (e.g., a photoresist) may be formed over the second ILD 106 and patterned to mask portions of the second ILD 106 from the first etching process and the second etching process. In some embodiments, the etching process may over-etch, and therefore, the third recess 108 extends into the epitaxial source / drain region 92 and / or the gate structure, and the bottom of the third recess 108 may be flush with the epitaxial source / drain region 92 and / or the gate structure (e.g., at the same level, or having the same distance from the substrate) or lower than the epitaxial source / drain region 92 and / or the gate structure (e.g., closer to the substrate). Fig. 23B The third recess 108 is shown to expose the epitaxial source / drain regions 92 and the gate structure in the same cross section, but in various embodiments, the epitaxial source / drain regions 92 and the gate structure may be exposed at different cross sections, thereby reducing the risk of shorting subsequently formed contacts.

[0085] After forming the third recess 108, a silicide region 110 is formed on the epitaxial source / drain region 92. In some embodiments, the silicide region 110 is formed by first depositing a metal (not shown) on the exposed portion of the epitaxial source / drain region 92, the metal (e.g., nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof) capable of reacting with the semiconductor material (e.g., silicon, silicon germanium, germanium) of the underlying epitaxial source / drain region 92 to form a silicide or germanide region, and then performing a thermal annealing process to form the silicide region 110. Then, for example, by an etching process, the unreacted portion of the deposited metal is removed. Although the silicide region 110 is referred to as a silicide region, the silicide region 110 may also be a germanide region or a silicon germanide region (e.g., a region containing silicide and germanide). In an embodiment, the silicide region 110 includes TiSi and has a thickness in a range between about 2 nm and about 10 nm.

[0086] Next, in Figures 25A-25CIn the third recess 108, contacts 112 and 114 (also referred to as contact plugs) are formed. Contacts 112 and 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filling material. For example, in some embodiments, each of contacts 112 and 114 includes a barrier layer and a conductive material, and is electrically coupled to an underlying conductive feature (e.g., gate electrode 102, gate electrode 127, and / or silicide region 110 in the illustrated embodiment). Contact 114 is electrically coupled to gate electrodes 102 and 127 and may be referred to as a gate contact, and contact 112 is electrically coupled to silicide region 110 and may be referred to as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 106.

[0087] Figures 26A-26C Cross-sectional views of devices according to some alternative embodiments are shown. Fig.26A Shows Figure 1 Reference section AA' is shown. Fig.26B Shows Figure 1 Reference section BB' is shown. Fig.26C Shows Figure 1 Reference section C-C' is shown. Figures 26A-26C In the drawings, similar reference numerals denote Figures 25A-25C However, in Figures 26A-26C In the embodiment, the channel regions in the n-type region 50N and the p-type region 50P include the same material. For example, the second nanostructure 54 including silicon provides a channel region for the p-type NSFET in the p-type region 50P and the n-type NSFET in the n-type region 50N. This can be formed, for example, by the following method: Figures 26A-26C The structure of: removing the first nanostructure 52 from both the p-type region 50P and the n-type region 50N at the same time; depositing the gate dielectric 100 and the gate electrode 102 around the second nanostructure 54 in the p-type region 50P; and depositing the gate dielectric 100 and the gate electrode 127 around the second nanostructure 54 in the n-type region 50N.

[0088] Various embodiments provide a gate stack of a transistor (e.g., a nanoFET) without a barrier layer between adjacent nanostructures. It has been determined that thickness variations due to merging regions of a WFM layer (e.g., between nanowires of a nanoFET) may not significantly affect the electrical characteristics of the transistor (e.g., relatively similar effective work functions have been observed). By not depositing a barrier layer around the WFM layer (e.g., to prevent partial merging of the WFM layer), ease of manufacturing may be improved. This is particularly true in advanced semiconductor nodes where feature sizes are small, as barrier layer materials (e.g., tantalum nitride, etc.) may be difficult to deposit in small spaces. Therefore, by omitting such a barrier layer in the gate stack and allowing the WFM layer to merge in certain regions, ease of manufacturing may be improved and manufacturing defects (e.g., caused by poor barrier layer deposition) may be reduced without significantly affecting the electrical performance of the resulting transistor.

[0089] In some embodiments, a device includes: a first nanostructure; a second nanostructure, the second nanostructure is located on the first nanostructure; a first high-k gate dielectric, the first high-k gate dielectric is arranged around the first nanostructure; a second high-k gate dielectric, the second high-k gate dielectric is arranged around the second nanostructure; and a gate electrode, the gate electrode is located on the first high-k gate dielectric and the second high-k gate dielectric. The portion of the gate electrode located between the first nanostructure and the second nanostructure includes a first portion of a p-type work function metal that fills the area between the first high-k gate dielectric and the second high-k gate dielectric. Optionally, in some embodiments, the first portion of the p-type work function metal includes a seam located between the first nanostructure and the second nanostructure. Optionally, in some embodiments, the first portion of the p-type work function metal has a first thickness, wherein the second portion of the p-type work function metal located on the sidewall of the first nanostructure has a second thickness, and wherein the first thickness is greater than the second thickness. Optionally, in some embodiments, the ratio of the first thickness to the second thickness does not exceed 2:1. Optionally, in some embodiments, the second thickness is between arrive Optionally, in some embodiments, the ratio of the second thickness to the minimum width of the p-type work function metal is in the range of 0.03 to 1. Optionally, in some embodiments, the minimum width of the p-type work function metal is in the range of 10nm to 180nm. Optionally, in some embodiments, the portion of the gate electrode between the first nanostructure and the second nanostructure is free of any barrier layer. Optionally, in some embodiments, the gate electrode further comprises an adhesion layer on top of the p-type work function metal, the adhesion layer not extending between the first nanostructure and the second nanostructure. Optionally, in some embodiments, the ratio of the height of the first nanostructure to the width of the first nanostructure is in the range of 0.05 to 4.

[0090] In some embodiments, a transistor includes: a first nanostructure, the first nanostructure is located on a semiconductor substrate; a second nanostructure, the second nanostructure is located on the first nanostructure; a gate dielectric, the gate dielectric surrounds the first nanostructure and the second nanostructure; and a gate electrode, the gate electrode is located on the gate dielectric. The gate electrode includes: a p-type work function metal, wherein the p-type work function metal extends continuously from a first portion of the gate dielectric located on the first nanostructure to a second portion of the gate dielectric located on the second nanostructure; an adhesion layer, the adhesion layer is located on the p-type work function metal; and a filler metal, the filler metal is located on the adhesion layer. Optionally, in some embodiments, the p-type work function metal has a first thickness on the top surface of the second nanostructure and a second thickness between the first nanostructure and the second nanostructure, wherein the first thickness is less than the second thickness. Optionally, in some embodiments, the p-type work function metal includes a seam between the first nanostructure and the second nanostructure. Optionally, in some embodiments, the p-type work function metal includes titanium nitride. Optionally, in some embodiments, the transistor further includes an interface layer, the interface layer is located below the gate dielectric, the interface layer surrounds the first nanostructure and the second nanostructure, and the gate dielectric includes a high-k material.

[0091] In some embodiments, a method includes: depositing a gate dielectric around a first nanostructure and a second nanostructure, the first nanostructure being disposed on the second nanostructure; and depositing a p-type work function metal on the gate dielectric. Depositing the p-type work function metal includes: depositing a first portion of the p-type work function metal on a top surface of the second nanostructure, and depositing a second portion of the p-type work function metal on a bottom surface of the second nanostructure; and continuing to deposit the p-type work function metal until the first portion of the p-type work function metal merges with the second portion of the p-type work function metal. Optionally, in some embodiments, the method further includes: depositing an adhesion layer on the p-type work function metal; and depositing a fill metal on the adhesion layer. Optionally, in some embodiments, depositing the p-type work function metal includes depositing a p-type work function metal having the following characteristics: a first thickness between the first nanostructure and the second nanostructure; and a second thickness on a sidewall of the first nanostructure, the first thickness being greater than the second thickness. Optionally, in some embodiments, the ratio of the first thickness to the second thickness does not exceed 2:1. Optionally, in some embodiments, depositing the p-type work function metal includes forming a seam between the first portion of the p-type work function metal and the second portion of the p-type work function metal.

[0092] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications in the present disclosure without departing from the spirit and scope of the present disclosure.

[0093] Example 1 is a semiconductor device comprising: a first nanostructure; a second nanostructure, the second nanostructure being located above the first nanostructure; a first high-k gate dielectric, the first high-k gate dielectric being arranged around the first nanostructure; a second high-k gate dielectric, the second high-k gate dielectric being arranged around the second nanostructure; and a gate electrode, the gate electrode being located above the first high-k gate dielectric and the second high-k gate dielectric, wherein a portion of the gate electrode located between the first nanostructure and the second nanostructure includes a first portion of a p-type work function metal filling a region between the first high-k gate dielectric and the second high-k gate dielectric.

[0094] Example 2 is the device of Example 1, wherein the first portion of the p-type work function metal includes a seam between the first nanostructure and the second nanostructure.

[0095] Example 3 is the device described in Example 1, wherein the first portion of the p-type work function metal has a first thickness, wherein the second portion of the p-type work function metal located on the sidewall of the first nanostructure has a second thickness, and wherein the first thickness is greater than the second thickness.

[0096] Example 4 is the device of Example 3, wherein a ratio of the first thickness to the second thickness does not exceed 2:1.

[0097] Example 5 is the device of Example 3, wherein the second thickness is arrive within the range.

[0098] Example 6 is the device of Example 3, wherein a ratio of the second thickness to a minimum width of the p-type work function metal is in a range of 0.03 to 1.

[0099] Example 7 is the device of Example 6, wherein the minimum width of the p-type work function metal is in a range of 10 nm to 180 nm.

[0100] Example 8 is the device of Example 1, wherein the portion of the gate electrode between the first nanostructure and the second nanostructure is free of any barrier layer.

[0101] Example 9 is the device of Example 1, wherein the gate electrode further comprises an adhesion layer over the p-type work function metal, the adhesion layer not extending between the first nanostructure and the second nanostructure.

[0102] Example 10 is the device of Example 1, wherein a ratio of a height of the first nanostructure to a width of the first nanostructure is in a range of 0.05 to 4.

[0103] Example 11 is a transistor, comprising: a first nanostructure, wherein the first nanostructure is located on a semiconductor substrate; a second nanostructure, wherein the second nanostructure is located on the first nanostructure; a gate dielectric, wherein the gate dielectric surrounds the first nanostructure and the second nanostructure; and a gate electrode, wherein the gate electrode is located on the gate dielectric, wherein the gate electrode comprises: a p-type work function metal, wherein the p-type work function metal extends continuously from a first portion of the gate dielectric located on the first nanostructure to a second portion of the gate dielectric located on the second nanostructure; an adhesion layer, wherein the adhesion layer is located on the p-type work function metal; and a filling metal, wherein the filling metal is located on the adhesion layer.

[0104] Example 12 is the transistor of Example 11, wherein the p-type work function metal has a first thickness on the top surface of the second nanostructure and a second thickness between the first nanostructure and the second nanostructure, wherein the first thickness is less than the second thickness.

[0105] Example 13 is the transistor of Example 11, wherein the p-type work function metal includes a seam between the first nanostructure and the second nanostructure.

[0106] Example 14 is the transistor of Example 11, wherein the p-type work function metal comprises titanium nitride.

[0107] Example 15 is the transistor of Example 11, further comprising an interface layer, the interface layer being located below the gate dielectric, the interface layer surrounding the first nanostructure and the second nanostructure, and the gate dielectric comprising a high-k material.

[0108] Example 16 is a method for forming a semiconductor device, comprising: depositing a gate dielectric around a first nanostructure and a second nanostructure, the first nanostructure being disposed above the second nanostructure; and depositing a p-type work function metal above the gate dielectric, wherein depositing the p-type work function metal comprises: depositing a first portion of the p-type work function metal on a top surface of the second nanostructure, and depositing a second portion of the p-type work function metal on a bottom surface of the second nanostructure; and continuing to deposit the p-type work function metal until the first portion of the p-type work function metal merges with the second portion of the p-type work function metal.

[0109] Example 17 is the method of Example 16, further comprising: depositing an adhesion layer over the p-type work function metal; and depositing a fill metal over the adhesion layer.

[0110] Example 18 is the method described in Example 17, wherein depositing the p-type work function metal includes depositing the p-type work function metal having the following characteristics: a first thickness between the first nanostructure and the second nanostructure; and a second thickness on the sidewall of the first nanostructure, the first thickness being greater than the second thickness.

[0111] Example 19 is the method of Example 18, wherein a ratio of the first thickness to the second thickness does not exceed 2:1.

[0112] Example 20 is the method of Example 17, depositing the p-type work function metal comprising forming a seam between the first portion of the p-type work function metal and the second portion of the p-type work function metal.

Claims

1. A semiconductor device, comprising: First nanostructure; a second nanostructure, the second nanostructure being located on the first nanostructure; a first high-k gate dielectric disposed around the first nanostructure; a second high-k gate dielectric disposed around the second nanostructure; as well as a gate electrode disposed over the first high-k gate dielectric and the second high-k gate dielectric, wherein a portion of the gate electrode disposed between the first nanostructure and the second nanostructure comprises a first portion of a p-type work function metal filling a region between the first high-k gate dielectric and the second high-k gate dielectric, The first portion of the p-type work function metal has a first thickness, the second portion of the p-type work function metal located on the sidewall of the first nanostructure has a second thickness, and the first thickness is greater than the second thickness.

2. The semiconductor device according to claim 1, wherein The first portion of the p-type work function metal includes a seam between the first nanostructure and the second nanostructure.

3. The semiconductor device according to claim 1, wherein A ratio of the first thickness to the second thickness does not exceed 2:

1.

4. The semiconductor device according to claim 1, wherein: The second thickness is arrive within the range.

5. The semiconductor device according to claim 1, wherein A ratio of the second thickness to a minimum width of the p-type work function metal is in a range of 0.03 to 1.

6. The semiconductor device according to claim 5, wherein: The minimum width of the p-type work function metal is in the range of 10 nm to 180 nm.

7. The semiconductor device according to claim 1, wherein The portion of the gate electrode between the first nanostructure and the second nanostructure does not have any barrier layer.

8. The semiconductor device according to claim 1, wherein The gate electrode further includes an adhesion layer over the p-type work function metal, the adhesion layer not extending between the first nanostructure and the second nanostructure.

9. The semiconductor device according to claim 1, wherein: A ratio of a height of the first nanostructure to a width of the first nanostructure is in a range of 0.05 to 4.

10. A transistor comprising: a first nanostructure, wherein the first nanostructure is located on a semiconductor substrate; a second nanostructure, the second nanostructure being located on the first nanostructure; a gate dielectric surrounding the first nanostructure and the second nanostructure; as well as A gate electrode, the gate electrode being located on the gate dielectric, wherein the gate electrode comprises: a p-type work function metal, wherein the p-type work function metal extends continuously from a first portion of the gate dielectric located on the first nanostructure to a second portion of the gate dielectric located on the second nanostructure, wherein the p-type work function metal has a first thickness on a top surface of the second nanostructure and a second thickness between the first nanostructure and the second nanostructure, wherein the first thickness is less than the second thickness; an adhesive layer, the adhesive layer being located on the p-type work function metal; and A filler metal is disposed on the bonding layer.

11. The transistor according to claim 10, wherein: The p-type work function metal includes a seam between the first nanostructure and the second nanostructure.

12. The transistor according to claim 10, wherein: The p-type work function metal includes titanium nitride. 13 . The transistor of claim 10 , further comprising an interfacial layer, the interfacial layer being located below the gate dielectric, the interfacial layer surrounding the first nanostructure and the second nanostructure, and the gate dielectric comprising a high-k material.

14. A method for forming a semiconductor device, comprising: depositing a gate dielectric around a first nanostructure and a second nanostructure, the first nanostructure being disposed on the second nanostructure; as well as Depositing a p-type work function metal on the gate dielectric, wherein depositing the p-type work function metal comprises: depositing a first portion of the p-type work function metal on a top surface of the second nanostructure and a second portion of the p-type work function metal on a bottom surface of the second nanostructure; and continuing to deposit the p-type work function metal until the first portion of the p-type work function metal merges with the second portion of the p-type work function metal, Wherein, depositing the p-type work function metal comprises depositing the p-type work function metal having the following characteristics: a first thickness between the first nanostructure and the second nanostructure; and A second thickness on a sidewall of the first nanostructure, the first thickness being greater than the second thickness.

15. The method according to claim 14, further comprising: depositing an adhesion layer over the p-type work function metal; as well as A fill metal is deposited over the adhesion layer.

16. The method according to claim 14, wherein: A ratio of the first thickness to the second thickness does not exceed 2:

1. 17 . The method of claim 14 , depositing the p-type work function metal comprising forming a seam between the first portion of the p-type work function metal and the second portion of the p-type work function metal.

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