Semiconductor device and method of manufacturing the semiconductor device

Abstract

A semiconductor device and a method for manufacturing the semiconductor device are disclosed. The semiconductor device includes a substrate comprising a first region having a first trench and a second region having a second trench. A first buried insulating layer pattern is disposed in the first trench. The second trench includes a first buried insulating layer pattern, a second buried insulating layer pattern, and a third buried insulating layer pattern stacked therein sequentially. A first buffer insulating layer is disposed on the substrate in the first and second regions and has a flat upper surface. A second buffer insulating layer is disposed on the first buffer insulating layer. A bit line structure is disposed in the first and second regions. A first portion of the bit line structure is disposed on the second buffer insulating layer and has a flat lower surface. A second portion of the bit line structure directly contacts the surface of the substrate in the first region.

Description

Technical Field

[0001] This invention relates to semiconductor devices and methods of manufacturing such semiconductor devices. More specifically, this invention relates to dynamic random access memory (DRAM) devices and methods of manufacturing such DRAM devices. Background Technology

[0002] As the integration density of DRAM devices increases, the operating characteristics of memory cells can change depending on the surface consistency and / or morphology of the layers on the substrate. When the surface of the layers is inconsistent, defects in the patterns formed on the layers may occur. Summary of the Invention

[0003] Exemplary implementations provide semiconductor devices with improved characteristics.

[0004] Exemplary embodiments provide a method for manufacturing a semiconductor device with improved properties.

[0005] According to an exemplary embodiment of the present invention, a semiconductor device includes a substrate comprising a first region having a first trench and a second region having a second trench. A first buried insulating layer pattern is disposed in the first trench. A first buried insulating layer pattern, a second buried insulating layer pattern, and a third buried insulating layer pattern are sequentially stacked in the second trench. A first buffer insulating layer is disposed on the substrate in the first and second regions and has a flat upper surface. A second buffer insulating layer is disposed on the first buffer insulating layer. A bit line structure is disposed in the first and second regions. A first portion of the bit line structure is disposed on the second buffer insulating layer and has a flat lower surface. A second portion of the bit line structure directly contacts the surface of the substrate in the first region.

[0006] According to an exemplary embodiment of the present invention, a semiconductor device includes a substrate comprising a first region having a first trench and a gate trench, and a second region having a second trench. A first buried insulating layer pattern is disposed in the first trench. A first buried insulating layer pattern, a second buried insulating layer pattern, and a third buried insulating layer pattern are sequentially stacked in the second trench. A first buffer insulating layer is disposed on the substrate in the first and second regions, the first buffer insulating layer having a flat upper surface. A second buffer insulating layer is disposed on the first buffer insulating layer. A gate structure is disposed in the gate trench. A bit line structure is disposed in the first and second regions. The bit line structure extends from the first region to the second region. A first portion of the bit line structure is disposed on the second buffer insulating layer, and the first portion of the bit line structure has a flat lower surface. A second portion of the bit line structure directly contacts the surface of the substrate in the first region. The bit line structure disposed in the second region has a flat upper surface and a flat lower surface.

[0007] According to an exemplary embodiment of the present invention, a method of manufacturing a semiconductor device includes etching a substrate comprising a first region and a second region to form a first trench in the first region and a second trench in the second region. A first buried insulating layer pattern is formed in the first trench. A first buried insulating layer pattern, a second buried insulating layer pattern, and a third buried insulating layer pattern are sequentially stacked in the second trench. A first buffer insulating layer is formed on the substrate in the first and second regions. The first buffer insulating layer has a flat upper surface. A second buffer insulating layer is formed on the first buffer insulating layer. A bit line structure is formed in the first and second regions. A first portion of the bit line structure is formed on the second buffer insulating layer, and the first portion of the bit line structure has a flat lower surface.

[0008] In an exemplary embodiment of the present invention, the surface of the layer on the substrate can be flat, such that the structures and / or patterns formed on the layer can be uniformly formed across the entire substrate. Furthermore, the surface of the layer on the substrate may be free of protrusions at the edge portions of the memory cell region. Therefore, cutting defects in the bitline structure due to protrusions at the edge portions can be reduced. Attached Figure Description

[0009] Exemplary embodiments of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. Figures 1 to 16 and Figures 18 to 24 Exemplary, non-limiting implementations as described herein are shown. Figure 17 Comparative examples are shown.

[0010] Figure 1 , Figure 3-10 , Figure 12-16 , Figure 18-19 and Figure 21-22 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the concept of the present invention.

[0011] Figure 17 This is a cross-sectional view showing a comparative example of a method for manufacturing a semiconductor device.

[0012] Figure 2 , Figure 11 and Figure 20 This is a plan view illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the concept of the present invention.

[0013] Figure 23 This is an enlarged cross-sectional view of a bitline structure based on an exemplary embodiment of the present invention.

[0014] Figure 24 This is a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention, and a cross-sectional view of the semiconductor device. Detailed Implementation

[0015] Figures 1 to 16 and Figures 18 to 24 These are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the concept of the present invention. Specifically, Figure 2 , Figure 11 and Figure 20 This is a plan view of an exemplary embodiment of the present invention. Figure 1 , Figures 3 to 10 , Figures 12 to 16 , Figures 18 to 19 , Figures 21 to 22 and Figure 24 These are cross-sectional views of exemplary embodiments of the present invention. Each of these cross-sectional views includes a section taken along lines A-A', B-B', and C-C' of the plan view. Figure 23 This is an enlarged cross-sectional view of a bitline structure based on an exemplary embodiment of the present invention. Figure 17 A comparative example is shown in which the protrusion remains in the second region.

[0016] Reference Figure 1 and Figure 2 In an exemplary embodiment, substrate 100 may include cell regions and core / peripheral regions. Cell regions may be regions for forming memory cells, and core / peripheral regions may be regions for forming peripheral circuitry and core circuitry. Hereinafter, for ease of explanation, only cell regions will be described.

[0017] A cell region may include a first region I in which memory cells are formed and a second region II surrounding the edge of the first region I in which dummy cells are formed. For example, the first region I of the cell region may include multiple memory cells, and the second region II of the cell region may include multiple dummy cells. For example, the second region II may be located between the first region I and the core / peripheral region. In each cross-sectional view, sections A-A' and B-B' show the first region I, and section C-C' shows both the first region I and the second region II.

[0018] A first mask pattern can be formed on the substrate 100. The first mask pattern can be used as an etching mask to etch the substrate 100 to form the first to fourth trenches 102a, 102b, 102c, and 102d. The upper portion of the substrate 100 where the first to fourth trenches 102a, 102b, 102c, and 102d are not formed can be used as an active region. In the following text, for ease of description, the active regions formed in the first region I and the second region II are referred to as the first active pattern 104. Figure 2As shown in the exemplary embodiment, the first active pattern 104 can be arranged in a plane defined by a first direction and a second direction that are parallel to the upper surface of the substrate 100 and intersect each other. For example, as Figure 2 As shown in the exemplary embodiments, the first direction and the second direction can be perpendicular to each other. However, the exemplary embodiments of the present invention are not limited thereto.

[0019] The internal width of each of the first to fourth trenches 102a, 102b, 102c, 102d may be different from each other, depending on the spacing between the first active patterns 104. For example, the internal width of each of the first to fourth trenches 102a, 102b, 102c, 102d may vary depending on the position of the substrate 100.

[0020] like Figure 2 As shown in the exemplary embodiment, in the first region I, the trench has a portion having a first width W1 and a portion having a second width W2 that is greater than the first width W1.

[0021] In the cross-sectional view, the first to fourth trenches 102a, 102b, 102c, and 102d may have different widths from each other. For ease of description, in each cross-sectional view, the trench shown in the section taken along line A-A' is referred to as the first trench 102a, and the trench shown in the section taken along line B-B' is referred to as the second trench 102b. Among the trenches shown in the section taken along line C-C', the trench formed in the second region II is referred to as the third trench 102c, and the trench formed in the first region I is referred to as the fourth trench 102d. The third trench 102c formed in the second region II may have a width greater than the width of each of the first trench 102a, the second trench 102b, and the fourth trench 102d formed in the first region I. In an exemplary embodiment, the third trench 102c may have a width greater than the maximum width of the trench formed in the first region I (e.g., the second width W2). The second groove 102b may have a width greater than that of the first groove 102a.

[0022] Reference Figure 3 In an exemplary embodiment, a polysilicon layer may be conformally formed on the inner surfaces of the first to fourth trenches 102a, 102b, 102c, and 102d, and on the upper surface of the substrate 100. In an exemplary embodiment, thermal oxidation of the polysilicon layer may be performed to form a first oxide layer.

[0023] A first insulating layer 112 can be formed on the first oxide layer. For example... Figure 3As shown in the exemplary embodiment, the first insulating layer 112 can be formed to completely fill the first trench 102a and the fourth trench 102d. However, the first insulating layer 112 may not completely fill the second trench 102b and the third trench 102c, which have a width greater than that of the first trench 102a. The first insulating layer 112 can be conformally formed on the inner surfaces of the second trench 102b and the third trench 102c, as well as on the upper surface of the substrate 100.

[0024] In an exemplary embodiment, the first insulating layer 112 may include at least one compound selected from silicon oxide, silicon nitride, etc. The first insulating layer 112 may be formed as a single layer or as a stacked structure of two or more layers. For example, the first insulating layer 112 may include silicon oxide. In this embodiment, the first insulating layer 112 may include the same material as the first oxide layer. For example, the first insulating layer 112 and the first oxide layer may be merged together.

[0025] Reference Figure 4 In an exemplary embodiment, a second insulating layer comprising a material different from that of the first insulating layer 112 may be conformally formed on the first insulating layer 112. The second insulating layer may completely fill the second trench 102b. However, the second insulating layer may not completely fill the third trench 102c. The second insulating layer may be conformally formed on the inner surface of the third trench 102c. In an exemplary embodiment, the second insulating layer may include a silicon nitride.

[0026] Subsequently, the second insulating layer can be removed to a predetermined thickness. In an exemplary embodiment, the removal process may include an isotropic etching process or a cleaning process. However, the exemplary embodiments of the present invention are not limited thereto.

[0027] In the removal process, the first trench 102a and the fourth trench 102d formed in the first region I, the second insulating layer on the substrate 100, and the second insulating layer formed in the second region II can be removed. However, the second insulating layer filling the second trench 102b can be relatively thick in the vertical direction, so the second insulating layer can be retained only in the second trench 102b. Therefore, as... Figure 4 As shown in the exemplary embodiment, a second insulating layer pattern 114 may be formed in the second trench 102b. The second insulating layer pattern 114 retained in the second trench 102b may not completely fill the second trench 102b. In this exemplary embodiment, the upper surface of the second insulating layer pattern 114 may be lower than the upper surface of the first active pattern 104 adjacent to the second insulating layer pattern 114.

[0028] Reference Figure 5In an exemplary embodiment, a third insulating layer may be formed on the upper surface of the first insulating layer 112 in the first region I and the second region II, and on the upper surface of the second insulating layer pattern 114 in the second trench 102b in the first region I.

[0029] The third insulating layer may not completely fill the third trench 102c. For example, the third insulating layer may be conformally formed on the inner surface of the third trench 102c. In an exemplary embodiment, the third insulating layer may include silicon oxide.

[0030] The third insulating layer can be formed to fill the second trench 102b. For example, the third insulating layer can be disposed above the second insulating layer pattern 114 to completely fill the second trench 102b. Due to the step difference between the second insulating layer pattern 114 and the first insulating layer 112, a recessed portion can be formed on the upper surface of the third insulating layer. For example, the upper surface of the third insulating layer can be uneven and can be locally curved.

[0031] In an exemplary embodiment, the first insulating layer 112 and the third insulating layer may comprise the same material, such that the first insulating layer 112 and the third insulating layer can be merged together. Hereinafter, the merged layer of the first insulating layer and the third insulating layer is referred to as the first buried insulating layer 116. The first buried insulating layer 116 is conformally disposed in the third trench 102c in the second region II.

[0032] Reference Figure 6 In an exemplary embodiment, a second buried insulation layer 118 comprising a material different from that of the first buried insulation layer 116 may be formed on the first buried insulation layer 116 in the first region I and the second region II.

[0033] like Figure 6 As shown in the exemplary embodiment, the second buried insulating layer 118 may not completely fill the third trench 102c. For example, the second buried insulating layer 118 may be conformally formed on the inner surface of the third trench 102c. In the exemplary embodiment, the second buried insulating layer 118 may include silicon nitride.

[0034] A third buried insulation layer 120 comprising a material different from that of the second buried insulation layer 118 can be formed on the second buried insulation layer 118 in the first region I and the second region II.

[0035] The third buried insulating layer 120 may be formed to completely fill the third trench 102c. The third buried insulating layer 120 may include an insulating material with excellent gap-filling properties. For example, in an exemplary embodiment, the third buried insulating layer 120 may include silicon oxide.

[0036] The second buried insulating layer 118 and the third buried insulating layer 120 may not be formed in the first trench 102a, the second trench 102b, and the fourth trench 102d in the first region I. The second insulating layer pattern 114 may be formed in the second trench 102b in the first region I. The first buried insulating layer 116 may be formed in the first trench 102a and the fourth trench 102d in the first region I.

[0037] The first to third buried insulating layers 116, 118 and 120 can be stacked sequentially in the third trench 102c of the second region II.

[0038] Reference Figure 7 In an exemplary embodiment, the third buried insulating layer 120 may be planarized until the second buried insulating layer 118 is exposed. In an exemplary embodiment, the planarization process may be performed by a chemical mechanical polishing (CMP) process and / or an etch-back process. However, the exemplary embodiments of the present invention are not limited thereto.

[0039] like Figure 7 As shown in the exemplary embodiment, the third buried insulation layer 120 on the first region I can be completely removed by a planarization process, exposing the second buried insulation layer 118. However, the third buried insulation layer 120 formed in the third trench 102c in the second region II can be retained. Therefore, the third buried insulation layer 120 retained in the third trench 102c can form a third buried insulation layer pattern 120a. Figure 7 As shown in the exemplary embodiment, the upper surface of the third buried insulating layer pattern 120a may be higher than the upper surface of the substrate 100.

[0040] Reference Figure 8 In an exemplary embodiment, the upper portion of the second buried insulating layer 118 may be removed until the first buried insulating layer 116 on the first region I is exposed. In an exemplary embodiment, the removal process of the second buried insulating layer 118 may be performed by a wet etching or wet cleaning process. However, the exemplary embodiments of the present invention are not limited thereto.

[0041] In this exemplary embodiment, the second buried insulation layer 118 on the first region I can be completely removed to expose the first buried insulation layer 116. However, after the removal process, the second buried insulation layer 118 formed in the third trench 102c in the second region II can be retained. Therefore, the second buried insulation layer 118 retained in the third trench 102c can form a second buried insulation layer pattern 118a.

[0042] Therefore, as Figure 8As shown in the exemplary embodiment, the upper surfaces of the first buried insulating layer 116, the second buried insulating layer pattern 118a, and the third buried insulating layer pattern 120a can be exposed in the second region II. The first buried insulating layer 116, the second buried insulating layer pattern 118a, and the third buried insulating layer pattern 120a can be formed to substantially fill the third trench 102c of the second region II.

[0043] The first buried insulating layer 116 can fill the first trench 102a and the fourth trench 102d in the first region I. The first buried insulating layer 116 and the second insulating layer pattern 114 can fill the second trench 102b in the first region I.

[0044] When an etching process is performed to completely remove the second buried insulating layer 118 on the first region I, the second buried insulating layer 118 formed above the third trench 102c can also be partially removed. Therefore, in the third trench 102c, the upper surface of the second buried insulating layer pattern 118a can be lower than the upper surface of the third buried insulating layer pattern 120a. For example, as... Figure 8 As shown in the exemplary embodiment, the upper part of the third buried insulation layer pattern 120a can protrude from the upper surface of the second buried insulation layer pattern 118a.

[0045] In the second buried insulating layer 118 on the second region II, the portion in contact with the third buried insulating layer pattern 120a can have a relatively low etching rate. Therefore, the second buried insulating layer pattern 118a on the second region II can remain more prominently in the portion in contact with the third buried insulating layer pattern 120a. Consequently, the closer the upper surface of the second buried insulating layer pattern 118a is to the third buried insulating layer pattern 120a, the higher this surface can be. For example, as... Figure 8 As shown in the exemplary embodiment, the upper surface of the second buried insulation pattern 118a may have an uneven shape, such as a recessed shape in which the side closest to the third buried insulation pattern 120a is higher than the rest of the upper surface of the second buried insulation pattern 118a.

[0046] Reference Figure 9 In an exemplary embodiment, a second mask pattern 119 may be formed on a first buried insulating layer 116 on a first region I and on a first buried insulating layer 116, a second buried insulating layer pattern 118a, and a third buried insulating layer pattern 120a on a second region II. In an exemplary embodiment, the second mask pattern 119 may include silicon oxide.

[0047] The second mask pattern 119 can be formed to expose a portion of the first buried insulating layer 116 on the first region I. The second mask pattern 119 on the first region I can extend in a first direction. Furthermore, the second mask pattern 119 can cover all of the following: the first buried insulating layer 116 on the second region II and the second buried insulating layer pattern 118a and the third buried insulating layer pattern 120a in the third trench 102c on the second region II.

[0048] The second mask pattern 119 can be used as an etching mask to etch the upper part of the substrate 100, the first buried insulating layer 116, and the second insulating layer pattern 114 in the first region I to form a gate trench 121 extending in the first direction.

[0049] A gate insulating layer 122 may be conformally formed on the inner surface of the gate trench 121, and a gate electrode layer may be formed on the gate insulating layer 122. Subsequently, the gate electrode layer may be etched back to form a gate electrode 124 at the lower portion of the gate trench 121. In an exemplary embodiment, the gate electrode 124 may include a barrier pattern and a metal pattern. In an exemplary embodiment, a polysilicon pattern 126 may be further formed on the gate electrode 124.

[0050] Subsequently, a first capping layer 128 can be formed on the second mask pattern 119 in the first region I and the second region II. The first capping layer 128 can be formed over the polysilicon pattern 126 to completely fill the gate trench 121. In an exemplary embodiment, the first capping layer 128 may include silicon nitride.

[0051] Reference Figure 10 and Figure 11 In an exemplary implementation, the first capping layer 128 can be etched back so that the first capping layer 128 remains only in the gate trench 121. Therefore, a first capping layer pattern 128a can be formed in the gate trench 121. For example... Figure 10 As shown in the exemplary embodiment, the upper surface of the first cover layer pattern 128a may have a level that is substantially the same as the level of the upper surface of the first active pattern 104.

[0052] In the etch-back process, it may be difficult to provide consistent etching of the first capping layer 128 in the gate trench 121. Generally, the etch rate of the portion of the first capping layer 128 closer to the second mask pattern 119 may be lower than the etch rate of the rest of the first capping layer 128. Therefore, the upper surface of the first capping layer pattern 128a formed in the gate trench 121 may be uneven and may include recessed or pitted portions 132 (hereinafter, pitted portions). For example, as Figure 10As shown in the exemplary embodiment, the upper surface of the first cover layer pattern 128a may have a generally recessed shape, wherein the recessed portion 132 is located in the central portion of the upper surface of the first cover layer pattern 128a.

[0053] The first cover layer pattern 128a on the first region I may have a line shape extending in the first direction, and multiple first cover layer patterns 128a may be arranged in the second direction. Therefore, the pit portion 132 may be disposed on the entire upper part of the substrate 100 in the first direction, and the upper surface of the layer formed on the upper part of the substrate 100 may be inconsistent.

[0054] like Figure 10-11 As shown in the exemplary embodiment, by performing the above process, a gate structure 130 including a gate insulating layer 122, a gate electrode 124, a polysilicon pattern 126 and a first capping layer pattern 128a can be formed in the gate trench 121, and multiple gate structures 130 can be arranged in the second direction.

[0055] Reference Figure 12 In an exemplary embodiment, the second mask pattern 119 can be removed in the first region I and the second region II. Subsequently, the upper portion of the first buried insulating layer 116 can be partially removed until the upper surface of the substrate 100 in the first region I is exposed. In an exemplary embodiment, the removal process may include a wet etching or wet cleaning process. However, the exemplary embodiments of the present invention are not limited thereto.

[0056] When the removal process is performed, the upper surface of the first active pattern 104 can be exposed at the first region I. The first buried insulating layer 116 on the substrate 100 can be etched to form the first buried insulating layer pattern 116a in the first trench 102a and the fourth trench 102d.

[0057] In the removal process of the second mask pattern 119, the same material as the second mask pattern 119 (e.g., a layer including silicon oxide) can be removed together. Therefore, the upper portion of the third buried insulating layer pattern 120a formed in the third trench 102c of the second region II can also be partially removed. The second buried insulating layer pattern 118a in the third trench 102c can have a greater height than the third buried insulating layer pattern 120a and can protrude from the third buried insulating layer pattern 120a. The portion of the second buried insulating layer pattern 118a that protrudes from the first buried insulating layer pattern 116a and the third buried insulating layer pattern 120a is referred to as protrusion A.

[0058] When the above process is performed, the upper surfaces of the substrate 100, the first buried insulating layer pattern 116a, and the first capping layer pattern 128a can be exposed in the first region I. Furthermore, the upper surface of the substrate 100 and the upper surfaces of the first to third buried insulating layer patterns 116a, 118a, and 120a in the third trench 102c can be exposed in the second region II. In an exemplary embodiment, a portion of the insulating layer can remain on the substrate 100 in the second region II.

[0059] When the cleaning process is performed, the exposed upper surface of the first buried insulation pattern 116a in the first to fourth trenches 102a, 102b, 102c and 102d may be uneven. For example, in an exemplary embodiment, the exposed upper surface of the first buried insulation pattern 116a may have a recessed portion and may have a generally recessed shape.

[0060] Reference Figure 13 In an exemplary embodiment, a preliminary first buffer insulating layer 134 is formed on the upper surfaces of the substrate 100, the first buried insulating layer pattern 116a, and the first cover layer pattern 128a in the first region I, and on the upper surfaces of the substrate 100 and the first to third buried insulating layer patterns 116a, 118a, and 120a in the second region II. The preliminary first buffer insulating layer 134 may be formed to insulate conductive patterns (e.g., bit lines or contacts) formed on the upper and lower portions. In an exemplary embodiment, the preliminary first buffer insulating layer 134 may comprise silicon oxide. In an exemplary embodiment, the preliminary first buffer insulating layer 134 may be formed using an atomic layer deposition (ALD) process.

[0061] In an exemplary embodiment, the initial first buffer insulation layer 134 may have a thickness of about 1.5 to about 3 times the target thickness of the subsequently formed first buffer insulation layer. If the thickness of the initial first buffer insulation layer 134 is less than about 1.5 times the target thickness of the first buffer insulation layer, the polishing thickness of the initial first buffer insulation layer 134 may be reduced in the planarization process. Therefore, it may be difficult to control the planarization process to achieve the target thickness of the buffer insulation layer. If the thickness of the initial first buffer insulation layer 134 is greater than about 3 times the target thickness of the first buffer insulation layer, the polishing thickness of the initial first buffer insulation layer 134 may be increased in the planarization process. Therefore, it may be difficult to control the planarization process. In an exemplary embodiment, the thickness of the initial first buffer insulation layer 134 may be greater than about 1.5 to about 3 times the target thickness of the first buffer insulation layer. to approximately The target thickness within the specified range.

[0062] In an exemplary embodiment, the initial thickness of the first buffer insulation layer 134 can be approximately to approximately Within the range.

[0063] The initial first buffer insulating layer 134 may have an inconsistent thickness at the recessed portion 132 on the upper surface of the first cover layer pattern 128a. The recessed portion 132 may be transferred onto the upper surface of the initial first buffer insulating layer 134, and the recessed portion may be formed in the portion of the upper surface of the initial first buffer insulating layer 134 that overlaps with the recessed portion 132 on the upper surface of the first cover layer pattern 128a. Therefore, the upper and lower surfaces of the initial first buffer insulating layer 134 formed on the first cover layer pattern 128a may be inconsistent.

[0064] Furthermore, the upper surface of the first buried insulation layer pattern 116a on the first region I may be uneven, so the upper and lower surfaces of the preliminary first buffer insulation layer 134 formed on the first buried insulation layer pattern 116a may be inconsistent.

[0065] As described above, the surface of the layer below the initial first buffer insulation layer 134 in the first region I may be inconsistent, such that the morphology of the upper surface of the initial first buffer insulation layer 134 may be inconsistent.

[0066] The initial first buffer insulation layer 134 can be conformally formed on the protrusion A in the second region II, such that the upper surface of the initial first buffer insulation layer 134 formed on the protrusion A can be relatively higher than other portions of the upper surface of the initial first buffer insulation layer 134.

[0067] Reference Figure 14 In an exemplary embodiment, the upper portion of the initial first buffer insulation layer 134 can be planarized to form a first buffer insulation layer 134a, which has a thickness smaller than that of the initial first buffer insulation layer 134. For example, the first buffer insulation layer 134a may have a thickness equal to the target thickness. Through a planarization process, the upper surface of the first buffer insulation layer 134a can be substantially flat.

[0068] In an exemplary embodiment, the thickness of the first buffer insulating layer 134a can be approximately to approximately Within the range. In an exemplary embodiment, the planarization process may include a chemical mechanical polishing (CMP) process.

[0069] The flatness of the upper surface of the first buffer insulating layer 134a may differ from the flatness of the lower surface of the first buffer insulating layer 134a. Due to the inconsistency of the underlying layers, the lower surface of the first buffer insulating layer 134a may have poor flatness. However, through a planarization process, the upper surface of the first buffer insulating layer 134a can be flatter than the lower surface of the first buffer insulating layer 134a. For example, the upper surface of the first buffer insulating layer 134a may be substantially flat and have a flatness greater than that of the lower surface of the first buffer insulating layer 134a.

[0070] The protrusion A can be removed during the planarization (e.g., polishing) of the preliminary first buffer insulating layer 134 on the second region II. For example, the preliminary first buffer insulating layer 134 formed on the protrusion A can be removed, and the protrusion A of the second buried insulating layer pattern 118a can also be removed. Thus, the first buffer insulating layer 134a can be formed on the upper sidewall of the second buried insulating layer pattern 118a. The first buffer insulating layer 134a can be separated by the second buried insulating layer pattern 118a (e.g., spaced apart by the second buried insulating layer pattern 118a in a second direction). By removing the protrusion A, the upper surfaces of the first buffer insulating layer 134a and the second buried insulating layer pattern 118a can be substantially coplanar with each other. For example, the upper surfaces of the first buffer insulating layer 134a and the second buried insulating layer pattern 118a can have the same height.

[0071] As described above, the step difference between the layers formed on the first region I and the second region II can be reduced by a planarization process, and the upper surfaces of these layers can be substantially flat.

[0072] Reference Figure 15 In an exemplary embodiment, a second buffer insulation layer 136 may be formed on the first buffer insulation layer 134a.

[0073] In an exemplary embodiment, the second buffer insulating layer 136 can be used as an etch stop layer. However, the exemplary embodiments of the present invention are not limited thereto. The second buffer insulating layer 136 may include an insulating material having high etch selectivity relative to silicon oxide. In an exemplary embodiment, the second buffer insulating layer 136 may include a silicon nitride. For example, the second buffer insulating layer 136 can be formed by an ALD process. However, the exemplary embodiments of the present invention are not limited thereto. In an exemplary embodiment, the thickness range of the second buffer insulating layer 136 may be the same as the target thickness range of the first buffer insulating layer 134a. For example, the second buffer insulating layer 136 may have a thickness range of approximately... to approximately The thickness is within the range.

[0074] In an exemplary embodiment, a third buffer insulating layer may be further formed on the second buffer insulating layer 136. In an exemplary embodiment, the third buffer insulating layer may include silicon oxide. However, the exemplary embodiments of the present invention are not limited thereto, and in some exemplary embodiments, a third buffer insulating layer may not be formed on the second buffer insulating layer 136.

[0075] The upper surface of the first buffer insulating layer 134a can be substantially flat, and therefore the upper and lower surfaces of the second buffer insulating layer 136 formed on the first buffer insulating layer 134a can also be substantially flat. In an exemplary embodiment that includes a third buffer insulating layer, the upper and lower surfaces of the third buffer insulating layer can also be substantially flat.

[0076] The second buffer insulation layer 136 on the second region II can be formed on the first buffer insulation layer 134a and the second buried insulation layer pattern 118a.

[0077] Reference Figure 16 In an exemplary embodiment, a first conductive layer 138 may be formed on the second buffer insulating layer 136. A third mask pattern may be formed on the first conductive layer 138. The third mask pattern may be used as an etching mask to etch the first conductive layer 138, the second buffer insulating layer 136, and the first buffer insulating layer 134a to form a first opening 140 that exposes the upper part of the first active pattern 104.

[0078] In the etching process, the upper portion of the substrate 100 exposed by the first opening 140, as well as the buried insulating layer pattern and the first capping layer pattern 128a adjacent to the substrate 100, can also be etched to form a recess. The bottom of the first opening 140 can also be referred to as a recess. In an exemplary embodiment, the first opening 140 may expose the central portion of the upper surface of the first active pattern 104 in the first region I.

[0079] A second conductive layer 142 can be formed to fill the first opening 140.

[0080] In an exemplary embodiment, a preliminary second conductive layer may be formed to fill the first opening 140, and then the upper portion of the preliminary second conductive layer may be etched back. Therefore, the upper surface of the second conductive layer 142 and the upper surface of the first conductive layer 138 may have substantially the same height.

[0081] In an exemplary embodiment, the first conductive layer 138 and the second conductive layer 142 may include polysilicon doped with impurities, and the first conductive layer 138 and the second conductive layer 142 may be merged with each other.

[0082] After removing the third mask pattern, a barrier layer 144, a first metal layer 146, and a second cover layer 148 can be sequentially formed on the first conductive layer 138 and the second conductive layer 142.

[0083] Subsequently, the second cover layer 148, the first metal layer 146, the barrier layer 144, the first conductive layer 138, and the second conductive layer 142 can be etched sequentially to form a preliminary bit line structure in the first region I and the second region II.

[0084] Spacers 150 may be formed on the sidewalls of the initial bitline structure, and a nitride liner 152 may be further formed on the spacers 150 and on the upper surface of the initial bitline structure. In an exemplary embodiment, the nitride liner 152 may include silicon nitride.

[0085] By removing the protrusion A on the substrate 100 of the second region II, the first conductive layer 138 can be formed having a substantially flat upper surface and a substantially flat lower surface. Therefore, the barrier layer 144 and the first metal layer 146 formed on the first conductive layer 138 in the second region II can also be formed having a substantially flat upper surface and a substantially flat lower surface.

[0086] Unlike the exemplary embodiments of the present invention, in Figure 17 In the comparative example shown where protrusion A is retained on the second region II, the barrier layer 144 and the first metal layer 146 formed on the first conductive layer 138 on the second region II can be formed conformally along the contour of protrusion A. Therefore, the upper surfaces of the barrier layer 144 and the first metal layer 146 formed on the first conductive layer 138 can also be inconsistent. Thus, the inconsistent surfaces in this comparative example may lead to defects in the bitline structure subsequently formed thereon.

[0087] Reference Figure 18 In an exemplary embodiment, a lower insulating interlayer pattern 154 may be formed on the second buffer insulating layer 136 on the second region II.

[0088] A third capping layer 156 may be formed on the nitride liner 152 and the lower insulating interlayer pattern 154. In an exemplary embodiment, the third capping layer 156 may include silicon nitride. The second capping layer 148, the nitride liner 152, and the third capping layer 156 may all include silicon nitride, and therefore the second capping layer 148, the nitride liner 152, and the third capping layer 156 may be merged with each other. Hereinafter, the merged structure including the second capping layer 148, the nitride liner 152, and the third capping layer 156 is referred to as the upper capping layer 160.

[0089] Reference Figure 19 and Figure 20In an exemplary embodiment, the upper cover layer 160 can be etched to form an upper cover layer pattern 160a. The upper cover layer pattern 160a can be used as an etching mask to sequentially etch the first metal layer 146, the barrier layer 144, the first conductive layer 138, and the second conductive layer 142.

[0090] Therefore, a second conductive pattern 142a, a blocking pattern 144a, a first metal pattern 146a, and an upper cover layer pattern 160a can be sequentially formed on the first active pattern 104 in the first opening 140. Additionally, as... Figure 19 As shown in the exemplary embodiment, a first conductive pattern 138a, a blocking pattern 144a, a first metal pattern 146a and an upper cover pattern 160a may be sequentially formed on a second buffer insulating layer 136 outside the first opening 140.

[0091] As described above, the first conductive layer 138 and the second conductive layer 142 can be merged with each other, so the first conductive pattern 138a and the second conductive pattern 142a can be used as conductive patterns. Figure 19-20 As shown in the exemplary embodiment, the sequentially stacked conductive pattern, barrier pattern 144a, first metal pattern 146a and upper cover pattern 160a can provide a bit line structure 162.

[0092] In an exemplary embodiment, the bit line structure 162 may extend in a second direction, and multiple bit line structures may be arranged in a first direction. For example, as Figure 19 As shown in the exemplary embodiment, a first portion of the bit line structure 162 may have a lower surface formed on the second buffer insulating layer 136. A second portion of the bit line structure 162 may have a lower surface formed on the upper surface of the first active pattern 104. For example, as... Figure 19 As shown in part B of the exemplary embodiment, a second portion of the bit line structure 162 extending in the second direction may contact the surface of the first active pattern 104 exposed by the first opening 140.

[0093] Reference Figure 21 In an exemplary embodiment, spacer structure 170 may be formed to cover the sidewalls of bit line structure 162.

[0094] like Figure 23 As shown in the exemplary embodiment, the spacer structure 170 may include a first spacer 170a covering the lateral sidewalls and upper surface of the bit line structure 162, a second spacer 170b filling the first opening 140, and a third spacer 170c and a fourth spacer 170d (e.g., in the first direction) sequentially stacked on the first spacer 170a to cover the sidewalls of the bit line structure 162.

[0095] like Figure 21As shown in the exemplary embodiment, a first insulating interlayer 180 can then be formed on the second buffer insulating layer 136 to fill the gaps between the spacer structures 170. The first insulating interlayer 180 can be planarized until the upper surface of the spacer structure 170 can be exposed. In the exemplary embodiment, the first insulating interlayer 180 may comprise silicon oxide.

[0096] Reference Figure 22 and Figure 23 In an exemplary embodiment, a fourth mask pattern may be formed on the first insulating interlayer 180 and the spacer structure 170. The fourth mask pattern may be used as an etching mask to etch the first insulating interlayer 180 to form the second opening.

[0097] In an exemplary embodiment, the fourth mask pattern may extend in a first direction, and a plurality of fourth mask patterns may be spaced apart from each other in a second direction. The second opening may overlap with the gate structure 130. Thereafter, an insulating pattern may be formed to fill the second opening. In an exemplary embodiment, the insulating pattern may include a nitride, such as a silicon nitride. However, exemplary embodiments of the present invention are not limited thereto.

[0098] like Figure 22 As shown in the exemplary embodiment, the first insulating interlayer 180 can be etched, and then the second buffer insulating layer 136, the first buffer insulating layer 134a and a portion of the substrate 100 can be etched to form a third opening 182 that exposes the surface of the substrate 100.

[0099] In the etching process, the upper part of the buried insulating layer pattern and the first cover layer pattern 128a adjacent to the first active pattern 104 can also be etched.

[0100] The upper surfaces of the first buffer insulating layer 134a and the second buffer insulating layer 136 can be aligned, allowing the first buffer insulating layer 134a and the second buffer insulating layer 136 to be etched uniformly during the etching process used to form the third opening 182. Therefore, the lowermost surface of the third opening 182 can be level with respect to each other across the entire substrate 100. Figure 23 As shown in the exemplary embodiment, the difference d between the maximum height and the minimum height of the lowermost surface of the third opening 182 can be less than approximately

[0101] As described above, the lowermost surface of the third opening 182 can be level, so that the contact plugs formed in the third opening 182 can have consistent electrical characteristics.

[0102] If the upper surfaces of the first buffer insulating layer 134a and the second buffer insulating layer 136 are not aligned, then the thicknesses of the first buffer insulating layer 134a and the second buffer insulating layer 136 may be locally different. In the etching process used to form the third opening 182, the etching amount of the first buffer insulating layer 134a and the second buffer insulating layer 136 may vary depending on their location. Therefore, the level of the lowermost surface of the third opening 182 may vary depending on the location of the substrate 100.

[0103] Reference Figure 24 In an exemplary embodiment, an upper contact plug 184 may be formed to fill the third opening 182. The upper contact plug 184 may have an upper surface that is higher than the upper surface of the bit line structure 162. An upper insulating pattern 186 may be formed to fill the space between the upper contact plugs 184.

[0104] A capacitor 190 may be formed on the upper surface of the upper contact plug 184 and the upper insulating pattern 186. The capacitor 190 may include a lower electrode 190a, an upper electrode 190c, and a dielectric layer 190b between the lower electrode 190a and the upper electrode 190c.

[0105] The previously described process provides Figure 24 The fabrication of a DRAM device is illustrated in the exemplary embodiment.

[0106] DRAM devices may have the following structural features. Most of the structural features of DRAM devices have already been described in the DRAM manufacturing process. Therefore, for ease of explanation, repeated descriptions can be omitted below, and only the important parts can be described with reference to the accompanying drawings.

[0107] Reference Figure 23 and 24 In an exemplary embodiment, the semiconductor device may be formed on a substrate. The semiconductor device may include a gate structure 130, a bit line structure 162, a spacer structure 170, an upper contact plug 184, and a capacitor 190.

[0108] The substrate 100 may include a first region I and a second region II. The substrate 100 may include first to fourth trenches 102a, 102b, 102c, and 102d, and insulating material may fill the first to fourth trenches 102a, 102b, 102c, and 102d.

[0109] In the first region I, a first buried insulating layer pattern 116a may fill the first trench 102a and the fourth trench 102d. In an exemplary embodiment, the first buried insulating layer pattern 116a may include silicon oxide. In the first region I, the first buried insulating layer pattern 116a and a second insulating layer pattern 114 may fill the second trench 102b. In an exemplary embodiment, the second insulating layer pattern 114 may include silicon nitride.

[0110] In the second region II, the first buried insulating layer pattern 116a, the second buried insulating layer pattern 118a, and the third buried insulating layer pattern 120a may fill the third trench 102c. In an exemplary embodiment, the second buried insulating layer pattern 118a may include silicon nitride. In an exemplary embodiment, the first buried insulating layer pattern 116a and the third buried insulating layer pattern 120a may include silicon oxide.

[0111] The first buried insulating layer pattern 116a, the second buried insulating layer pattern 118a, and the third buried insulating layer pattern 120a can be stacked sequentially on the surface of the third trench 102c. The upper surface of the second buried insulating layer pattern 118a can be higher than the upper surfaces of the first buried insulating layer pattern 116a and the third buried insulating layer pattern 120a. Therefore, the upper surface of the second buried insulating layer pattern 118a can protrude from the upper surfaces of the first buried insulating layer pattern 116a and the third buried insulating layer pattern 120a. The upper surface of the second buried insulating layer pattern 118a can be substantially flat.

[0112] A gate trench 121 extending in a first direction may be disposed on a substrate 100 in a first region I, and a gate structure 130 may be disposed in the gate trench 121. A portion of the gate structure 130 may be disposed on a first buried insulating layer pattern 116a and a second insulating layer pattern 114. For example, a plurality of gate structures 130 extending in the first direction may be disposed in the first region I and may be arranged in a second direction.

[0113] The gate structure 130 may include a gate insulating layer 122, a gate electrode 124, a polysilicon pattern 126, and a first capping layer pattern 128a. The upper surface of the first capping layer pattern 128a may include a pit portion 132, and the upper surfaces of the first capping layer pattern 128a may be inconsistent. Furthermore, the upper surfaces of the first active patterns 104 between the first capping layer patterns 128a may also be inconsistent. For example, the upper surface of the first active pattern 104 may also include a pit portion.

[0114] In the first region I and the second region II, a first buffer insulating layer 134a may be disposed on the substrate 100. A second buffer insulating layer 136 may be disposed on the first buffer insulating layer 134a.

[0115] The upper surface of the first buffer insulating layer 134a may be substantially flat. The first buffer insulating layer 134a may be formed on a first cover layer pattern 128a having an inconsistent upper surface. Therefore, the lower surface of the first buffer insulating layer 134a may be inconsistent.

[0116] The flatness of the upper surface of the first buffer insulating layer 134a may differ from the flatness of the lower surface of the first buffer insulating layer 134a. For example, as Figure 23-24 As shown in the exemplary embodiment, the upper surface of the first buffer insulation layer 134a may be substantially flat and may have a greater degree of flatness than the lower surface of the first buffer insulation layer 134a.

[0117] In an exemplary embodiment, the first buffer insulating layer 134a may have approximately to approximately The thickness is within the range.

[0118] The first buffer insulating layer 134a disposed on the second region II can be separated by the second buried insulating layer pattern 118a (e.g., spaced apart in a second direction by the second buried insulating layer pattern 118a). For example, the first buffer insulating layer 134a can be disposed on the upper sidewall of the second buried insulating layer pattern 118a on the second region II. The upper surfaces of the first buffer insulating layer 134a and the second buried insulating layer pattern 118a can be substantially coplanar with each other. The upper surfaces of the first buffer insulating layer 134a and the second buried insulating layer pattern 118a can have substantially the same level (e.g., height in the thickness direction of the substrate 100).

[0119] The second buffer insulation layer 136 may have a substantially flat upper surface and a substantially flat lower surface. In an exemplary embodiment, the second buffer insulation layer 136 may have approximately to approximately The thickness is within the range.

[0120] The second buffer insulation layer 136 on the second region II can be disposed on the first buffer insulation layer 134a and the second buried insulation layer pattern 118a.

[0121] In an exemplary embodiment, the first buffer insulating layer 134a may include silicon oxide, and the second buffer insulating layer 136 may include silicon nitride. In an exemplary embodiment, a third buffer insulating layer may be further disposed on the second buffer insulating layer 136.

[0122] The lower surface of the first portion of the bit line structure 162 can contact the second buffer insulating layer 136 in the first region I and the second region II, and the second portion of the bit line structure 162 can contact the first active pattern 104. For example, the bit line structure 162 can be directly disposed on the second buffer insulating layer 136 and the first active pattern 104. The bit line structure 162 may include a conductive pattern, a barrier pattern 144a, a first metal pattern 146a, and an upper cover pattern 160a stacked sequentially. The bit line structure 162 can extend from the first region I to the second region II.

[0123] The upper surface of the second buffer insulation layer 136 can be substantially flat, so the lower surface of the bit line structure 162 that contacts the second buffer insulation layer 136 can also be substantially flat.

[0124] Compared to the portion of the first active pattern 104 located below the first buffer insulating layer 134a, the portion of the first active pattern 104 that contacts the second portion of the bit line structure 162 can be recessed. A first opening 140 can be provided at the first active pattern 104, and the bottom of the first opening 140 can contact the bit line structure 162.

[0125] The spacer structure 170 can be disposed on the side wall of the bit line structure 162.

[0126] The third opening 182 can expose the first active pattern 104 between the bit line structures 162. In an exemplary embodiment, the level of the lowest surface of the third opening 182 can be substantially uniform relative to each other. For example, in an exemplary embodiment, the difference d between the maximum and minimum heights of the lowest surface of the third opening 182 can be less than approximately

[0127] The first insulating interlayer 180 can cover the bit line structure 162 to fill the space between the bit line structures 162.

[0128] The upper contact plug 184 can be disposed in the third opening 182 and can contact the first active pattern 104 exposed by the bottom surface of the third opening 182. For example... Figure 24 As shown in the exemplary embodiment, the upper surface of the upper contact plug 184 may have a height greater than the height of the upper surface of the bit line structure 162. The upper insulating pattern 186 may fill the space between the upper contact plugs 184.

[0129] Capacitor 190 can contact the upper surface of contact plug 184.

[0130] The semiconductor device may include a first buffer insulating layer 134a and a second buffer insulating layer 136 having a substantially flat upper surface. Therefore, the bottom of the bit line structure 162 disposed on the second buffer insulating layer 136 may be substantially flat.

[0131] Furthermore, the lowermost surface of the third opening 182 formed between the bit line structures 162 can be level with respect to each other. Therefore, the upper contact plug 184 filling the third opening 182 can have uniform characteristics.

[0132] The lower and upper surfaces of the bit line structure 162 in the second region can be substantially flat. For example, the second buried insulation layer pattern 118a in the second region may not include protrusions. Therefore, the bit line structure 162 may not be provided on protrusions, and cutting defects of the bit line structure 162 due to protrusions can be reduced.

[0133] The foregoing describes exemplary embodiments of the inventive concept and is not to be construed as limiting the inventive concept. Although several exemplary embodiments have been described, those skilled in the art will readily recognize that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, the clauses for "means plus function" are intended to cover not only structural equivalents but also equivalent structures, as described herein. Therefore, it will be understood that the foregoing describes a wide variety of exemplary embodiments and is not to be construed as limiting to the specific exemplary embodiments disclosed, and it will be understood that modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the appended claims.

[0134] This application claims priority to Korean Patent Application No. 10-2020-0019522, filed on February 18, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: The substrate includes a first region having a first trench and a second region having a second trench; A first buried insulating layer pattern is disposed in the first trench; A first buffer insulating layer is disposed on the substrate in the first region and the second region, the first buffer insulating layer having a flat upper surface; A second buffer insulation layer is disposed on the first buffer insulation layer; as well as Bit line structures are disposed on the first region and the second region. The first, second, and third buried insulation layer patterns are stacked sequentially in the second trench, and the upper surface of the second buried insulation layer pattern in the second region protrudes from the upper surfaces of the first and third buried insulation layer patterns. The first portion of the bit line structure is disposed on the second buffer insulating layer, and the first portion of the bit line structure has a flat lower surface. The second portion of the bit line structure directly contacts the surface of the substrate in the first region.

2. The semiconductor device of claim 1, wherein the bit line structure disposed on the second region has a flat upper surface and a flat lower surface.

3. The semiconductor device of claim 1, wherein the first buffer insulating layer is separated by the second buried insulating layer pattern in the second region.

4. The semiconductor device of claim 1, wherein the upper surface of the second buried insulating layer pattern on the second region is coplanar with the upper surface of the first buffer insulating layer.

5. The semiconductor device of claim 1, wherein the second buffer insulating layer on the second region is disposed on the pattern of the first buffer insulating layer and the second buried insulating layer.

6. The semiconductor device according to claim 1, wherein: The bitline structure includes multiple bitline structures; as well as Multiple openings are disposed between the multiple bit line structures, and the multiple openings expose portions of the substrate. The difference between the maximum and minimum heights of the lowest surfaces of the plurality of openings is less than 7. The semiconductor device according to claim 1, wherein: The first region includes multiple storage units; The second region surrounds the edge of the first region and includes a plurality of dummy units; and The width of the second groove is greater than the width of the first groove.

8. The semiconductor device according to claim 1, wherein the thickness of the first buffer insulating layer is... to Within the range.

9. A semiconductor device, comprising: The substrate includes a first region having a first trench and a gate trench, and a second region having a second trench; A first buried insulating layer pattern is disposed in the first trench; A first buffer insulating layer is disposed on the substrate in the first region and the second region. The first buffer insulating layer has a flat upper surface, and the flatness of the upper surface of the first buffer insulating layer is greater than the flatness of the lower surface of the first buffer insulating layer. A second buffer insulation layer is disposed on the first buffer insulation layer; A gate structure is disposed in the gate trench; as well as A bitline structure is disposed on the first region and the second region, the bitline structure extending from the first region to the second region. The first buried insulation layer pattern, the second buried insulation layer pattern, and the third buried insulation layer pattern are stacked sequentially in the second trench. The first portion of the bit line structure is disposed on the second buffer insulating layer, and the first portion of the bit line structure has a flat lower surface. The second portion of the bit line structure directly contacts the surface of the substrate in the first region, and The bitline structure disposed on the second region has a flat upper surface and a flat lower surface.

10. The semiconductor device of claim 9, wherein the upper surface of the second buried insulating layer pattern in the second region is coplanar with the upper surface of the first buffer insulating layer in the second region.

11. A method for manufacturing a semiconductor device, comprising: The etching includes a first region and a second region of substrate to form a first trench in the first region and a second trench in the second region; A first buried insulation layer pattern is formed in the first trench; The first buried insulation layer pattern, the second buried insulation layer pattern, and the third buried insulation layer pattern are stacked sequentially in the second trench; A first buffer insulating layer is formed on the substrate in the first region and the second region. The first buffer insulating layer has a flat upper surface, and the flatness of the upper surface of the first buffer insulating layer is greater than the flatness of the lower surface of the first buffer insulating layer. A second buffer insulation layer is formed on the first buffer insulation layer; as well as Bit line structures are formed on the first region and the second region. The first portion of the bit line structure is formed on the second buffer insulating layer, and the first portion of the bit line structure has a flat lower surface.

12. The method of claim 11, wherein the formation of the first buffer insulating layer comprises: A preliminary first buffer insulating layer is formed on the substrate in the first region and the second region; as well as The upper surface of the preliminary first buffer insulation layer is flattened to form the first buffer insulation layer.

13. The method of claim 12, wherein the preliminary first buffer insulation layer is formed to have a thickness of 1.5 to 3 times the thickness of the first buffer insulation layer.

14. The method of claim 12, wherein the planarization comprises performing a chemical mechanical polishing process.

15. The method according to claim 12, wherein: During the planarization of the initial first buffer insulation layer, the second buried insulation layer pattern on the second region is polished, and After the planarization, the upper surface of the second buried insulating layer pattern is coplanar with the upper surface of the first buffer insulating layer.

16. The method of claim 11, wherein the first buffer insulating layer is formed having in to The thickness is within the range.

17. The method of claim 11, wherein the second buffer insulation layer on the second region is formed on the pattern of the first buffer insulation layer and the second buried insulation layer.

18. The method according to claim 11, wherein: The formation of the bit line structure includes forming a plurality of bit line structures on the first region and the second region; and Etch portions between the plurality of bit line structures to form openings that expose the substrate between the plurality of bit line structures.

19. The method of claim 11, further comprising: A gate trench is formed in the first region; as well as A gate structure is formed in the gate trench.

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