Integrated circuit and method for forming the same

Abstract

Different embodiments of the present invention relate to a method for integrating an NVM device with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure divides the storage area of ​​the semiconductor substrate and further divides the peripheral area of ​​the semiconductor substrate. The peripheral area may correspond to a BCD device or a logic device, for example. A doped well is formed in the peripheral area. A dielectric sealing layer is formed to cover the storage area and the peripheral area and further cover the doped well. The dielectric sealing layer is removed from the storage area but not from the peripheral area. A storage cell structure is formed on the storage area using a thermal oxidation process. The dielectric sealing layer is removed from the peripheral area, and a peripheral device structure including a gate electrode is formed on the peripheral area. Embodiments of the present invention also provide an integrated circuit structure formed using the method.

Description

[0001] This application is a divisional application of the patent application entitled “Integrated Circuit and Method for Forming the Same” filed on July 26, 2018 and with patent application number 201810834899.5. Technical Field

[0002] Embodiments of the present application relate to the field of semiconductors, and more particularly, to methods of forming integrated circuits and integrated circuits. Background Art

[0003] The integrated circuit (IC) manufacturing industry has experienced exponential growth in the past few decades. As ICs have evolved, functional density (that is, the number of interconnected devices per chip area) has generally increased while geometry size (that is, the smallest component that can be manufactured) has generally decreased. Advances in IC development include the integration of non-volatile memory (NVM) with logic technology or bipolar complementary metal oxide semiconductor (CMOS) double diffused metal oxide semiconductor (DMOS) (BCD). BCD technology may be or include, for example, integrating bipolar junction transistors (BJTs), CMOS devices, and DMOS devices together on the same semiconductor chip. Among other applications, the integration of NVM with logic or BCD has found applications in power management, the Internet of Things (LoT), smart cards, microcontroller units (MCUs), and automotive equipment. Summary of the invention

[0004] According to one aspect of the present invention, a method for forming an integrated circuit is provided, the method comprising: providing a semiconductor substrate including a first device region and a second device region, the first device region and the second device region being separated by an isolation structure; forming a doped well in the second device region; forming a sealing layer covering the first device region and the second device region and also covering the doped well; removing the sealing layer from the first device region but not from the second device region; forming a memory cell structure on the first device region; after forming the memory cell structure, removing the sealing layer from the second device region; and forming a device structure on the second device region.

[0005] According to another aspect of the present invention, an integrated circuit is provided, comprising: a semiconductor substrate, comprising a first device region and a second device region; an isolation structure, extending into a top surface of the semiconductor substrate, wherein the isolation structure divides and separates the first device region and the second device region; a storage unit, covering the first device region; a metal oxide semiconductor (MOS) device, covering the second device region; and a dummy structure, covering the isolation structure, wherein the dummy structure comprises a dummy sealing element.

[0006] According to another aspect of the present invention, a method for forming an integrated circuit is provided, the method comprising: forming an isolation structure in a semiconductor substrate, wherein the isolation structure divides a storage area of ​​the semiconductor substrate and also divides a peripheral area of ​​the semiconductor substrate; forming a doped well in the peripheral area; forming a sealing layer covering the storage area and the peripheral area and also covering the doped well; removing the sealing layer from the storage area but not from the peripheral area; forming a gate dielectric layer in the storage area by a thermal oxidation process, wherein the thermal oxidation process causes the top surface of the semiconductor substrate to be recessed in the storage area but not in the peripheral area; forming a storage gate electrode above the gate dielectric layer; after forming the storage gate electrode, removing the sealing layer from the peripheral area; and forming a peripheral gate electrode on the peripheral area while simultaneously forming a second storage gate electrode adjacent to the storage gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1A and Figure 1B A cross-sectional view of an integrated circuit (IC) including a memory device and a bipolar complementary metal oxide semiconductor (CMOS) double diffused metal oxide semiconductor (DMOS) (BCD) or logic device is shown;

[0009] Figure 2A and Figure 2B They are shown respectively Figure 1A and Figure 1B Cross-sectional views of some more detailed embodiments of the IC;

[0010] Figures 3 to 23 A series of cross-sectional views illustrating some embodiments of a sealing method for forming an IC including a memory device and a BCD or logic device;

[0011] Fig.24 Shows Figures 3 to 23 Flow charts of some embodiments of the sealing method;

[0012] Figures 25 to 32 Shows Figures 3 to 23 A series of cross-sectional views of other embodiments of the sealing method. DETAILED DESCRIPTION

[0013] The present disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and settings are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the formation of a first feature above a second feature in the description may include an embodiment in which the first feature and the second feature are directly in contact with each other, and may also include an embodiment in which another feature may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in different examples. This repetition is for the purpose of simplification and clarity and does not itself specify the relationship between the different embodiments and / or configurations under discussion.

[0014] Further, spatially relative terms, such as "below," "beneath," "below," "above," "upper," and the like, may be used herein to simplify the specification to describe the relationship of one element or feature relative to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative terms used herein may be similarly interpreted accordingly.

[0015] A method for integrating a non-volatile memory (NVM) device with a logic device and / or a bipolar complementary metal oxide semiconductor (CMOS) double diffused metal oxide semiconductor (DMOS) (BCD) device includes: forming a shallow trench isolation (STI) structure extending into a top surface of a semiconductor substrate and dividing a storage area of ​​the semiconductor substrate, a logic area of ​​the semiconductor substrate, and a BCD area of ​​the semiconductor substrate. A BCD well and a logic well are formed in the BCD area and the logic area, respectively, and a BCD gate oxide layer is subsequently formed to cover the logic area, the BCD area, and the storage area. The BCD gate oxide layer is removed from the storage area but not from the logic and BCD areas, and a series of processes are performed to form a storage structure on the storage area. The process includes a thermal process and an oxidation process, and the storage structure includes a storage gate oxide layer. Thereafter, the BCD gate oxide layer is removed from the logic area but not from the BCD area, and a series of processes are performed to form a logic gate oxide layer on the logic area. A conductive layer is formed to cover the storage area, the logic area, and the BCD area, and the conductive layer is patterned into a storage gate electrode, a logic gate electrode, and a BCD gate electrode.

[0016] The challenge of this method is that the thermal process and oxidation process used to form the memory structure may affect the logic and BCD devices to be manufactured. For example, the oxidant used during the thermal process and oxidation process may migrate through the BCD gate oxide layer to the logic and BCD regions and promote the oxidation of the logic and BCD regions. Such oxidation partially consumes the logic and BCD regions, thereby reducing the depth of the logic and BCD wells and changing the doping profile of the logic well and the BCD well. By changing the doping profile of the logic well and the BCD well, the thermal process and oxidation process cause a huge shift in the performance parameters of the logic and BCD devices. The thermal process and oxidation process include, for example, a process performed at a temperature exceeding about 850 degrees Celsius, and / or at a temperature between about 850 and 1000 degrees Celsius, between about 750 and 950 degrees Celsius, or between about 850 and 1250 degrees Celsius. A solution to this challenge is to use a p-type metal oxide semiconductor (PMOS) one-time programmable (OTP) memory because the memory can be formed without using a thermal process and an oxidation process. However, the PMOS OTP memory is one-time programmable, thus limiting the application.

[0017] In view of the foregoing, different embodiments of the present application are directed to a sealing method for integrating an NVM device with a logic or BCD device using a sealing layer, and an integrated circuit (IC) formed by the method. According to some embodiments of the method, an isolation structure is formed on a semiconductor substrate. The isolation structure separates a storage area of ​​the semiconductor substrate from a peripheral area of ​​the semiconductor substrate. A doped well is formed in the peripheral area. The sealing layer is formed to cover the storage and peripheral areas, and further covers the doped well. The sealing layer may be, for example, a dielectric and / or may be or include, for example, silicon nitride, silicon oxynitride, silicon carbide, polysilicon (doped or undoped), or some other suitable sealing material. The sealing layer is removed from the storage area but not from the peripheral area, and a storage cell structure is formed on the storage area using a thermal process and an oxidation process. The sealing layer is removed from the peripheral area, and a logic or BCD device structure is formed on the peripheral area.

[0018] The sealing layer protects the peripheral area including the doped well from the influence of the thermal process and oxidation process used to form the memory cell structure. For example, the sealing layer can prevent the oxidant used during the thermal process and oxidation process from migrating to the peripheral area and causing oxidation and consumption of the peripheral area. Such oxidation and consumption reduce the depth of the doped well and thus change the doping profile of the doped well. Therefore, the sealing layer prevents the doping profile of the doped well from shifting, which prevents the performance of the logic or BCD device formed on the doped well from shifting. This in turn contributes to the high yield of IC mass production.

[0019] refer to Figure 1A, a cross-sectional view 100A of some embodiments of an IC including a memory cell 102 and a logic or BCD device 104 is provided. The memory cell 102 is in a first portion I of the IC, on a memory region 106 m of a semiconductor substrate 106. Further, the memory cell 102 overlies a memory well 108 in the memory region 106 m. The memory cell 102 may be, for example, a first generation embedded super flash (ESF1) device, a third generation embedded super flash (ESF3) device, a 1.5 transistor silicon oxide nitride oxide silicon (SONOS) device, a two-transistor SONOS device, a 1.5 transistor metal oxide nitride oxide silicon (MONOS) device, a two-transistor MONOS device, a single transistor floating gate device, a two-transistor floating gate device, a thin film storage (TFS) device, or some other suitable memory cell. The semiconductor substrate 106 may be or include, for example, a bulk silicon substrate, a silicon epitaxial layer, a silicon on insulator substrate (SOI), some other suitable semiconductor structure, or any combination of the foregoing. In some embodiments, the semiconductor substrate 106 includes a bulk silicon substrate (not shown) and a silicon epitaxial layer (not shown) covering the bulk silicon substrate.

[0020] The logic or BCD device 104 is located in the second portion II of the IC, on the logic or BCD region 106Lb of the semiconductor substrate 106. In some embodiments, the logic or BCD region 1061b of the semiconductor substrate 106 is located at the periphery of the IC and / or at the periphery of the storage region 106m of the semiconductor substrate 106. Further, the logic or BCD device 104 is covered on the logic or BCD well 110 in the logic or BCD region 1061b. In some embodiments, the logic or BCD well 110 has a top surface that is higher than the top surface of the storage well 108 by a distance D. The distance D may be, for example, about 10 to 100 angstroms, about 40 to 60 angstroms, or about 25 to 75 angstroms. The logic or BCD device 104 may be, for example, a metal oxide semiconductor (MOS) device, a DMOS device, a bipolar junction transistor (BJT), or some other suitable logic or BCD device.

[0021] The memory well 108 and the logic or BCD well 110 have different doping profiles, different doping concentrations, different doping types, or any combination thereof relative to each other and / or relative to the bulk 112 of the semiconductor substrate 106. In some embodiments, the memory well 108 has a single doping type and / or the logic or BCD well 110 has a single doping type. Further, the memory well 108 and the logic or BCD well 110 are surrounded by an isolation structure 114 extending into the top surface of the semiconductor substrate 106. The isolation structure 114 includes a pair of memory segments on opposite sides of the memory well 108. Similarly, the isolation structure 114 includes a pair of logic or BCD segments on opposite sides of the logic or BCD well 110. The isolation structure 114 may be or include, for example, a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, or some other suitable isolation structure.

[0022] In some embodiments, the dummy structure 116 is on the storage region 106m of the semiconductor substrate 106 and is adjacent to the memory cell 102. In some embodiments, the dummy structure 116 also covers the memory segment of the isolation structure 114. The dummy structure 116 includes a pair of dummy segments located on opposite sides of the memory cell 102. In some embodiments, the planar top layout of the dummy structure 116 extends laterally along the boundary of the memory well 108 in a closed path to completely enclose the memory well 108, and / or is continuous from one of the dummy segments to another of the dummy segments along the closed path. The closed path may be, for example, a circular ring, a square ring, a rectangular ring, or some other suitable closed path shape. Note that the closed path is in Figure 1A 100A in FIG. 100A (eg, into and out of the page), so it Figure 1A The dummy structure 116 is defined by a dummy sealing element 118d and a dummy dielectric element 120d which is located below the dummy sealing element 118d in some embodiments.

[0023] In some embodiments, the dummy sealing element 118d has a first thickness T1 of about 100 to 500 angstroms, about 100 to 250 angstroms, about 250 to 500 angstroms, about 150 to 350 angstroms, about 50 to 150 angstroms, or about 450 to 550 angstroms. In some embodiments, the dummy dielectric element 120d has a second thickness T2 of about 60 to 200 angstroms, about 60 to 130 angstroms, about 130 to 200 angstroms, about 20 to 100 angstroms, or about 160 to 240 angstroms. In some embodiments, the first thickness T1 is about 0.5 to 8.5 times the second thickness T2, about 0.25 to 0.75 times the second thickness T2, about 8 to 9 times the second thickness T2, about 1 to 5 times the second thickness T2, or about 4 to 9 times the second thickness T2.

[0024] As will be seen later, the sealing layer is used to protect the logic or BCD well 110 while performing the method for forming the IC. Further, as will be seen later, the sealing layer is mostly removed while performing the method, and the pseudo sealing element 118d is the remaining part of the sealing layer. Similarly, as will be seen later, the pseudo dielectric element is the remaining part of the dielectric layer used to form the BCD gate dielectric layer of the BCD device. The pseudo sealing element 118d may be or include materials such as silicon nitride, silicon oxynitride, silicon carbide, some other suitable dielectrics, polysilicon (doped or undoped), or any combination of the foregoing. Further, the pseudo sealing element 118d may be a material that blocks or otherwise prevents oxidants from passing through it. The pseudo dielectric element 120d may be such as silicon oxide, some other suitable oxides, high-k dielectrics, some other dielectrics, or any combination of the foregoing. As used herein, the high-k dielectric may be a dielectric such as having a dielectric constant greater than about 3.9, 5, 10, 15, or 20. In some embodiments, the dummy sealing element 118d is homogenous (eg, a single material) and / or the dummy dielectric element 120d is homogenous.

[0025] An interlayer dielectric (ILD) layer 122 covers the semiconductor substrate 106, the dummy structure 116, the memory cell 102, the logic or BCD device 104, and the isolation structure 114. Further, a contact via 124 extends through the ILD layer 122 and is electrically connected to the memory cell 102 and the logic or BCD device 104. The ILD layer 122 may be or include, for example, silicon dioxide, a low-k dielectric, silicon nitride, some other suitable dielectric, or any combination of the foregoing. As used herein, a low-k dielectric may be, for example, a dielectric having a dielectric constant k of less than about 3.9, 3, 2, or 1. The contact via 124 may be or include, for example, copper, aluminum copper, aluminum, tungsten, some other suitable metal, or any combination of the foregoing.

[0026] refer to Figure 1B , provides Figure 1A Some other embodiments of the IC are shown in cross-sectional view 100B. As shown, Figure 1B for Figure 1A A variation of Figure 1A In some such embodiments, the dummy dielectric element 120d is omitted. In some such embodiments, the dummy sealing element 118d directly contacts the isolation structure 114.

[0027] refer to Figure 2A , provides Figure 1A 200A of some more detailed embodiments of section I. Section I shows Figure 1A Some more detailed examples of Part I of FIG. Part II 'shows Figure 1ASome more detailed BCD embodiments of Section II of FIG. 1A . The BCD region 106 b of the semiconductor substrate 106 corresponds to Figure 1A The logical or BCD area 1061b in the BCD device 104b corresponds to Figure 1A The logic or BCD device 104 in the embodiment, and one or more BCD wells 110b1 to 110b5 correspond to Figure 1A The logic or BCD well 110 in the section II' shows Figure 1A Some more detailed logic embodiments of Part II of FIG. 10A . The logic region 1061 of the semiconductor substrate 106 corresponds to Figure 1A The logic or BCD area 1061b in the logic device 1041 corresponds to Figure 1A The logic or BCD device 104 in the logic well 1101 corresponds to Figure 1A The logic or BCD well 110 in the Figure 2A Both portion II' and portion II are shown, however either portion II' or portion II (but not both) may be omitted in other embodiments.

[0028] like Figure 2A As shown in part II' in FIG. 1 , the logic well 1101 is in the logic region 1061 of the semiconductor substrate 106. The logic well 1101 has a different doping profile, a different doping concentration, a different doping type, or any combination thereof relative to the bulk 112 of the semiconductor substrate 106. In some embodiments, the logic well 1101 has a single doping type. Further, the logic well 1101 is surrounded by an isolation structure 114, and the isolation structure 114 includes a pair of logic segments located on opposite sides of the logic well 1101.

[0029] The logic device 104I is overlaid on the logic well 1101 and on the logic region 1061 of the semiconductor substrate 106. The logic device 1041 may be, for example, a metal oxide semiconductor field effect transistor (MOSFET), some other suitable metal oxide semiconductor (MOS) device, an insulated gate field effect transistor (IGFET), or some other suitable logic device. In some embodiments, the logic device 1041 includes a pair of logic source / drain regions 222. For simplicity of description, only one of the logic source / drain regions 222 is labeled as 222. The logic source / drain regions 222 are respectively located on opposite sides of the logic well 1101 and are recessed into the top surface of the logic well 1101. Further, the logic source / drain regions 222 have the same doping type. In some embodiments, a pair of logic source / drain extensions 222e are also laterally located between the logic source / drain regions 222 and are recessed into the top surface of the logic well 1101. For simplicity of explanation, only one of the logic source / drain extensions 222 e is labeled as 222 e . The logic source / drain extensions 222 e extend from the logic source / drain regions 222 , respectively, and have the same doping type and a lower doping concentration than the logic source / drain regions 222 .

[0030] The selectively conductive logic channel 224 is between the logic source / drain regions 222. In some embodiments without the logic source / drain extensions 222e, the selectively conductive logic channel 224 extends uninterruptedly from one of the logic source / drain regions 222 to another of the logic source / drain regions 222. In some embodiments with the logic source / drain extensions 222e, the selectively conductive logic channel 224 extends uninterruptedly from one of the logic source / drain extensions 222e to another of the logic source / drain extensions 222e. The selectively conductive logic channel 224 is defined by the logic well 110l, and the logic well 110l has an opposite doping type to the logic source / drain regions 222. For example, the logic source / drain regions 222 may be p-type and the logic well 110l may be n-type, or vice versa.

[0031] The logic gate electrode 226 and the logic gate dielectric layer 228 are stacked on the selective conductive logic channel 224, and the logic gate electrode 226 covers the logic gate dielectric layer 228. The logic gate dielectric layer 228 can be or include materials such as oxide, high-k dielectric, some other suitable dielectric, or any combination of the foregoing. The logic gate electrode 226 can be or include materials such as doped polysilicon, metal, or some other suitable conductive material.

[0032] like Figure 2AAs shown in section II' in FIG. 1 , the BCD wells 110b1 to 110b5 are in the BCD region 106b of the semiconductor substrate 106. Each of at least some (e.g., all) of the BCD wells 110b1 to 110b5 has a different doping profile, a different doping concentration, a different doping type, or any combination thereof relative to the body 112 of the semiconductor substrate 106. Further, in some embodiments, each of at least some (e.g., all) of the BCD wells 110b1 to 110b5 has a single doping type.

[0033] In some embodiments, the first BCD well 110b1 and the second BCD well 110b2 are located in the BCD region 106b of the semiconductor substrate 106 along the top surface of the semiconductor substrate 106. The second BCD well 110b2 overlies the first BCD well 110b1 and is located on a first side of the first BCD well 110b1. The first BCD well 110b1 has a first doping type, and the second BCD well 110b2 has a second doping type opposite to the first doping type. In some embodiments, the body 112 of the semiconductor substrate 106 also has a second doping type. The first and second doping types may be, for example, p-type and n-type, respectively, or vice versa. Further, in some embodiments, the third BCD well 110b1 may be a first doping type. b3 , a fourth BCD well 110b4, a fifth BCD well 110b5, or any combination thereof are in the BCD region 106b of the semiconductor substrate 106.

[0034] In some embodiments, the third BCD well 110b3 overlies the first BCD well 110b1 and is positioned on a second side of the first BCD well 110b1, the second side being opposite to the first side of the first BCD well 110b1. In some embodiments, the fourth BCD well 110b4 is below the first and second BCD wells 110b1, 110b2, and also below the third BCD well 110b3 (if present). The third BCD well 110b3 has a first doping type, and the fourth BCD well 110b4 has a second doping type. In some embodiments, the third BCD well 110b3 has a higher doping concentration than the first BCD well 110b1. In some embodiments, the fifth BCD well 110b5 surrounds the first and second BCD wells 110b1, 110b2, and further surrounds the third BCD well 110b3 (if present) and / or the fourth BCD well 110b4 (if present). Further, the fifth BCD well 110b5 is along the top surface of the semiconductor substrate 106. The fifth BCD well 110b5 includes a pair of well segments respectively located on opposite sides of the first BCD well 110b1, so that the first and second BCD wells 110b1, 110b2 are sandwiched between the pair of well segments. In some embodiments, the third BCD well 110b3 and / or the fourth BCD well 110b4 are also sandwiched between the pair of well segments. The fifth BCD well 110b5 has a second doping type.

[0035] In some embodiments, the buried semiconductor layer 230 is below the BCD wells 110b1 to 110b5, and / or the isolation structure 114 surrounds and / or separates the BCD wells 110b1 to 110b5. In some embodiments, the buried semiconductor layer 230 has a first doping type. In some embodiments, the isolation structure 114 surrounds the first and second BCD wells 110b1, 110b2, and further surrounds the third BCD well 110b3 (if present) and / or the fourth BCD well 110b4 (if present). For example, the isolation structure 114 may include three BCD segments, some of which are only labeled 114 for simplicity of illustration. The first BCD segment of the three BCD segments and the second BCD segment of the three BCD segments may be located on opposite sides of the first BCD well 110b1, respectively. The first BCD segment may separate the second BCD well 110b2 from the fifth BCD well 110b5, and the second BCD segment may separate the third BCD well 110b3 from the fifth BCD well 110b5. Further, a third BCD segment of the three BCD segments may be between the first and second BCD segments, and may further separate the first BCD well 110 b 1 from the third BCD well 110 b 3 .

[0036] The BCD device 104b overlies the BCD wells 110b1 to 110b5 and the BCD region 106b of the semiconductor substrate 106. The BCD device 104b may be, for example, a lateral diffused MOS (LDMOS) device, some other suitable MOS device, some other suitable DMOS device, a BJT, or some other suitable BCD device. Further, the BCD device 104b may be configured to operate at a high voltage greater than about 50, 100, 200, or 500 volts.

[0037] In some embodiments, the BCD device 104b includes a pair of BCD source / drain regions 232. For simplicity of description, only one of the BCD source / drain regions 232 is labeled as 232. The BCD source / drain regions 232 overlie the first BCD well 110b1 and are respectively on opposite sides of the first BCD well 110b1 and are recessed in the top surface of the semiconductor substrate 106. The first BCD source / drain region in the BCD source / drain regions 232 further overlie the second BCD well 110b2, and the second BCD source / drain region in the BCD source / drain regions 232 further overlie the third BCD well 110b3 (if present). In some embodiments, the first BCD source / drain region also overlies a body well 234 of the semiconductor substrate 106, and the body well 234 overlies the second BCD well 110b2. The body well 234 has a second doping type and may, for example, have a different doping concentration than the second BCD well 110b2. The BCD source / drain regions 232 have the same doping type and further have the first doping type. Further, in some embodiments, the BCD source / drain region extension 232e overlies the second BCD well 110b2 and the body well 234 (if present). The BCD source / drain region extension 232e has the same doping type and a lower doping concentration than the BCD source / drain regions 232.

[0038] The selective conductive BCD channel 236 is between the first BCD source / drain region and the first BCD well 110b1 and is defined by the second BCD well 110b2. In some embodiments without the BCD source / drain region extension 232e, the selective conductive BCD channel 236 extends uninterruptedly from the first BCD source / drain region to the first BCD well 110b1. In some embodiments with the BCD source / drain region extension 232e, the selective conductive BCD channel 236 extends uninterruptedly from the BCD source / drain region extension 232e to the first BCD well 110b1. The first BCD well 110b1 and the third BCD well 110b3 (if present) serve as drift regions for the BCD device 104b. The drift region provides a conduction path from the selectively conductive BCD channel 236 to the second BCD source / drain region and has a higher resistance than the ON resistance of the selectively conductive BCD channel 236 to enable the BCD device 104b to operate at a high voltage while the drift region is conductive. The drift region has a first doping type.

[0039] The BCD gate electrode 238 and one or more BCD gate dielectric layers 240a to 240c are stacked on the selective conductive BCD channel 236, and the BCD gate electrode 238 overlies the BCD gate dielectric layers 240a to 240c. For example, the first BCD gate dielectric layer 240a overlies the second BCD gate dielectric layer 240b, the second BCD gate dielectric layer 240b overlies the third BCD gate dielectric layer 240c, and the third BCD gate dielectric layer 240c overlies the selective conductive BCD channel 236. In some embodiments, the second BCD gate dielectric layer 240b has a second thickness T2 of the pseudo dielectric element 120d. The BCD gate dielectric layers 240a to 240c can be or include materials such as oxides, high-k dielectrics, some other suitable dielectrics, or any combination of the foregoing. The BCD gate electrode 238 can be or include materials such as doped polysilicon, metals, or some other suitable conductive materials.

[0040] like Figure 2A As shown in part I of FIG. 1 , the memory well 108 is in the memory region 106 m of the semiconductor substrate 106. The memory well 108 has a different doping profile, a different doping concentration, a different doping type, or any combination thereof relative to the body 112 of the semiconductor substrate 106. Further, the memory well 108 is surrounded by an isolation structure 114. In some embodiments, the top surface of the memory well 108 is lower than the top surface of the logic well 1101, the top surfaces of the BCD wells 110b1 to 110b5, the top surface of the body 112 of the semiconductor substrate 106, or any combination thereof by a distance D. The distance D may be, for example, about 10 to 100 angstroms, about 40 to 60 angstroms, or about 25 to 75 angstroms.

[0041] The memory cell 102 overlies the memory well 108 and is on the size region 106m of the semiconductor substrate 106. In some embodiments, the memory cell includes a pair of memory source / drain regions 202. For simplicity of description, only one of the memory source / drain regions 202 is labeled as 202. The memory source / drain regions 202 are respectively located on opposite sides of the memory well 108 and are recessed in the top surface of the memory well 108. Further, the memory source / drain regions 202 have the same doping type. In some embodiments, a pair of memory source / drain extensions 202e are also laterally located between the memory source / drain regions 202 and are recessed in the top surface of the memory well 108. For simplicity of description, only one of the memory source / drain extensions 202e is labeled as 202e. The memory source / drain extensions 202e extend from the memory source / drain regions 202, respectively, and have the same doping type and a lower doping concentration than the memory source / drain regions 202.

[0042] The selectively conductive storage channel 204 is between the storage source / drain regions 202. In some embodiments without the storage source / drain extensions 202e, the selectively conductive storage channel 204 extends uninterruptedly from one of the storage source / drain regions 202 to another of the storage source / drain regions 202. In some embodiments with the storage source / drain extensions 202e, the selectively conductive storage channel 204 extends uninterruptedly from one of the storage source / drain extensions 202e to another of the storage source / drain extensions 202e. Further, the selectively conductive storage channel 204 is defined by the storage well 108, and the storage well 108 has an opposite doping type to the storage source / drain regions 202. For example, the storage source / drain regions 202 may be p-type and the storage well 108 may be n-type, or vice versa.

[0043] A floating gate hard mask 206, a floating gate electrode 208, and a floating gate dielectric layer 210 are stacked on the selective conductive storage channel 204. The floating gate hard mask 206 overlies the floating gate electrode 208, and the floating gate electrode 208 overlies the floating gate dielectric layer 210. The floating gate hard mask 206 and the floating gate dielectric layer 210 may be or include, for example, oxide, some other suitable dielectric, or any combination of the foregoing. In some embodiments, the floating gate dielectric layer 210 has a third thickness T3 of about 50 to 400 angstroms, about 75 to 125 angstroms, about 50 to 200 angstroms, or about 200 to 400 angstroms. In some embodiments, the third thickness is about 1.5 to 2.5 times the distance D, about 1.75 to 2.25 times the distance D, about 1.9 to 2.1 times the distance D, or about 2 times the distance D. The floating gate electrode 208 may be or include, for example, doped polysilicon or some other suitable conductive material.

[0044] The first selection gate dielectric layer 214 covers the selective conductive storage channel 204 up to both sides of the floating gate electrode 208, and includes a pair of selection gate dielectric segments respectively lining the opposite sidewalls of the floating gate electrode 208. For simplicity of description, only one of the selection gate dielectric segments is labeled as 214. In addition, the selection gate dielectric segments are lined on the opposite sidewalls of the floating gate dielectric layer 210, the opposite sidewalls of the floating gate dielectric layer 210 are respectively flush with the opposite sidewalls of the floating gate electrode 208, and the selection gate dielectric segments extend from the opposite sidewalls of the floating gate dielectric layer 210 toward the storage source / drain region 202. The first selection gate dielectric layer 214 can be or include, for example, silicon oxide, a high-k dielectric, some other suitable dielectric, or any combination thereof.

[0045] The select gate electrode 216 overlies the first select gate dielectric layer 214 and the selective conductive storage channel 204, and further overlies the floating gate hard mask 206. Further, a storage sidewall spacer 218 and, in some embodiments, a second select gate dielectric layer 220 are located between the first select gate dielectric layer 214 and the select gate electrode 216 and overlie the first select gate dielectric layer 214. The storage sidewall spacer 218 includes a pair of storage spacer segments, which are respectively lined on the sidewalls of the first select gate dielectric layer 214 located on opposite sides of the floating gate electrode 208. For simplicity of description, only one of the storage sidewall spacer segments is labeled as 218. The second select gate dielectric layer 220 further overlies the storage sidewall spacer 218 and the floating gate hard mask 206. The select gate electrode 216 may be or include, for example, doped polysilicon, metal, or some other suitable conductive material. The second select gate dielectric layer 220 may be or include, for example, silicon oxide, a high-k dielectric, some other suitable dielectric, or any combination thereof. The storage sidewall spacers 218 may be or include, for example, silicon oxide, silicon nitride, silicon oxynitride, some other suitable dielectric, or any combination thereof.

[0046] The dummy structure 116 is on the storage region 106m of the semiconductor substrate 106 and adjacent to the memory cell 102. The dummy structure 116 is defined by a dummy sealing element 118d and a dummy dielectric element 120d under the dummy sealing element 118d in some embodiments. The dummy sealing element 118d includes a pair of dummy sealing segments respectively located on opposite sides of the memory cell 102. Further, the dummy dielectric element 120d includes a pair of dummy dielectric segments respectively located on opposite sides of the memory device and respectively under the dummy sealing segments. For simplicity of explanation, only one of the dummy sealing segments is labeled as 118d, and only one of the dummy dielectric segments is labeled as 120d.

[0047] The main sidewall spacers 242 line the sidewalls of the memory cells 102, the dummy structures 116, the logic devices 1041, and the BCD devices 104b. For simplicity of description, only some segments of the main sidewall spacers 242 are labeled as 242. Further, the ILD layer 122 covers the semiconductor substrate 106, the main sidewall spacers 242, the dummy structures 116, the memory cells 102, the logic devices 1041, the BCD devices 104b, and the isolation structures 114. Further still, the contact vias 124 extend through the ILD layer 122 and are electrically connected to the memory cells 102, the logic devices 1041, and the BCD devices 104b. For simplicity of description, only some of the contact vias 124 are labeled as 124. The main sidewall spacers 242 may be or include, for example, silicon nitride, silicon oxide, silicon oxynitride, some other suitable dielectric, or any combination of the foregoing.

[0048] refer to Figure 2B , provides Figure 1B Some more detailed embodiments of the IC are shown in cross-sectional view 200B. As shown, Figure 2B for Figure 2A A variation of Figure 2A In some such embodiments, the dummy sealing element 118d directly contacts the isolation structure 114. Further, the third selection gate dielectric layer 144 isolates the second selection gate dielectric layer 220 from the first selection gate dielectric layer 214, and / or Figure 2A The third BCD gate dielectric layer 240c is omitted. The third select gate dielectric layer 244 may be or include, for example, silicon oxide, some other suitable dielectric, or any combination thereof.

[0049] refer to Figures 3 to 23 , cross-sectional views 300 to 2300 of some embodiments of a sealing method for forming an IC including a memory cell and a BCD or logic device are provided. The sealing method is shown with respect to an ESF1 device, however, it should be understood that the sealing method can be applied to other types of memory devices, such as a SONOS device, a MONOS device, an ESF3 device, or other suitable types of NVM devices. Further, the sealing method can be performed to form Figure 2A IC in.

[0050] like Figure 3As shown in the cross-sectional view 300 in FIG. 3 , a semiconductor substrate 106 is provided. The semiconductor substrate 106 includes a storage area 106m, a BCD area 106b, and a logic area 106l. The storage area 106m is located in the portion I of the IC to be manufactured. The BCD area 106b is located in the portion II' of the IC to be manufactured. The logic area 106l is located in the portion II' of the IC to be manufactured. The semiconductor substrate 106 may be or include a bulk silicon substrate, a silicon epitaxial layer, an SOI substrate, a III-V group element semiconductor substrate, some other suitable semiconductor structure, or any combination of the foregoing. In some embodiments, a buried semiconductor layer 230 is buried in the semiconductor substrate 106 and positioned in the BCD area 106b. Further, in some embodiments, the buried semiconductor layer 230 has a first doping type and the body 112 of the semiconductor layer 106 has a second doping type opposite to the first doping type. The first doping type pole ear second doping type may be n-type and p-type, respectively, or vice versa.

[0051] Depend on Figure 3 As also shown in the cross-sectional view 300 in FIG. 1 , an isolation structure 114 is formed in the semiconductor layer 106 to separate the storage region 106m of the semiconductor substrate 106, the BCD region 106b of the semiconductor substrate 106, and the logic region 106l of the semiconductor substrate 106. In addition, the isolation structure 114 electrically isolates the storage region 106m of the semiconductor substrate 106, the BCD region 106b of the semiconductor substrate 106, and the logic region 106l of the semiconductor substrate 106 from the surrounding environment, and vice versa. For simplicity of description, only some sections of the isolation structure 114 are labeled as 114. The isolation structure 114 may be an isolation structure such as an STI structure, a DTI structure, or some other suitable type.

[0052] In some embodiments, the process for forming the isolation structure 114 includes forming a lower liner layer 302 covering the semiconductor substrate 106, and further forming an upper liner layer 304 covering the lower liner layer 302. The lower liner layer 302 may be or include, for example, silicon dioxide, some other suitable oxide, or some other suitable dielectric. The upper liner layer 304 may be or include, for example, silicon nitride, some other suitable nitride, or some other suitable dielectric. Further, the lower liner layer 302 and the upper liner layer 304 may be formed by processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal oxidation, some other suitable growth or deposition process, or any combination of the foregoing. After forming the lower liner layer 302 and the upper liner layer 304, the lower liner layer 302 and the upper liner layer 304 are patterned to have a layout of the isolation structure 114, and then in the presence of the lower liner layer 302 and the upper liner layer 304, the semiconductor substrate 106 is etched to define a trench having a layout of the isolation structure 114 in the semiconductor substrate 106. A trench dielectric layer is formed to cover the upper liner layer 304 and fill the trench. Further, the trench dielectric layer is planarized until it reaches the upper liner layer 304, thereby forming the isolation structure 114 by the trench dielectric layer. The lower liner layer 302 and the upper liner layer 304 can be patterned, such as by a photolithography / etching process or some other suitable patterning process. The trench dielectric layer can be formed, such as by a deposition process such as CVD, PCD, sputtering, or some other suitable deposition process. Planarization may be performed, such as by chemical mechanical polishing (CMP) or some other suitable planarization process.

[0053] like Figure 4 As shown in the cross-sectional view 400, the upper liner layer ( Figure 3 106 m, the BCD region 106 b, and the logic region 106 l of the semiconductor substrate 106 are removed. The removal may be performed, for example, by planarization, an etching process, or some other suitable removal process. Planarization may be performed, for example, by CMP or some other suitable planarization process.

[0054] Depend on Figure 4As also shown in the cross-sectional view 400 in FIG. 1 , one or more BCD wells 110b1 to 110b5 are formed in the BCD region 106b of the semiconductor substrate 106. In some embodiments, the first BCD well 110b1 and the second BCD well 110b2 are formed in the BCD region 106b of the semiconductor substrate 106 along the top surface of the semiconductor substrate 106. The second BCD well 110b2 overlies the first BCD well 110b1 and is positioned on a first side of the first BCD well 110b1. The first BCD well 110b1 has a first doping type, and the second BCD well 110b2 has a second doping type opposite to the first doping type. In some embodiments, a third BCD well 110b3, a fourth BCD well 110b4, and a fifth BCD well are also formed in the BCD region 106b of the semiconductor substrate 106. The third BCD well 110b3 overlies the first BCD well 110b1 and along the top surface of the semiconductor substrate 106. Further, the third BCD well 110b3 is positioned on a second side of the first BCD well 110b1, which is opposite to the first side of the first BCD well 110b1, and has the first doping type. The fourth BCD well 110b4 is below the first BCD well 110b1, the second BCD well 110b2, and the third BCD well 110b3 and has the second doping type. The fifth BCD well 110b5 surrounds the first BCD well 110b1, the second BCD well 110b2, the third BCD well 110b3, and the fourth BCD well 110b4 and is along the top surface of the semiconductor substrate 106. Further, the fifth BCD well 110b5 includes a pair of well segments respectively located on opposite sides of the first BCD well 110b1 and has the second doping type.

[0055] In some embodiments, the process for forming the BCD wells 100b1 to 110b5 includes repeatedly performing a selective doping process to sequentially form the BCD wells 100b1 to 110b5. In some embodiments, the selective doping process sequentially includes: depositing a photolithography layer on the lower liner layer 302; patterning the photolithography layer so that the layout of the BCD well is formed; injecting dopants into the BCD region 106b of the semiconductor substrate 106 in the presence of the patterned photolithography layer; and removing the patterned photolithography layer. As used herein, the deposition of the photolithography layer may be performed, such as by spin coating or some other suitable deposition process. As used herein, the patterning of the photolithography layer may be performed, such as by a photolithography process or some other suitable patterning process. As used herein, the implantation of dopants may be performed, such as by ion implantation or some other suitable doping process. As used herein, the benefits of the photolithography layer may be performed, such as by plasma ashing or some other suitable removal process.

[0056] like Figure 5As shown in the cross-sectional view 500 in FIG. 1 , the logic well 1101 is formed in the logic region 1061 of the semiconductor substrate 106. In some embodiments, the logic well 1101 is formed with a doping type opposite to that of the main body 112 of the semiconductor substrate 106. In some embodiments, a process sequence for forming the logic well 1101 includes: depositing a photolithography layer on the lower liner layer 302; patterning the photolithography layer to have a layout of the logic well 1101; in the presence of the patterned photolithography layer, implanting a dopant into the logic region 1061 of the semiconductor substrate; and sequentially removing the patterned photolithography layer. Deposition, patterning, implantation, removal, or any combination of the foregoing may be performed, such as with respect to Figure 4 describe.

[0057] like Figure 6 As shown in the cross-sectional view 600 in FIG. 1 , the first gate dielectric layer 120 is formed to cover the storage region 106m, the BCD region 106b, and the logic region 106l of the semiconductor substrate 106. Further, the sealing layer 118 is formed to cover the first gate dielectric layer 120. The first gate dielectric layer 120 may be or include materials such as silicon oxide, some other suitable oxides, some other suitable dielectrics, or any combination of the foregoing. The sealing layer 118 is a barrier layer for oxidants used during subsequent processes, and may be or include materials such as silicon nitride, silicon oxynitride, silicon carbide, some other suitable dielectrics, polysilicon (doped or undoped), some other suitable sealing materials, or any combination of the foregoing. In some embodiments, the first gate dielectric layer 120 and the sealing layer 118 are formed by CVD, PVD, thermal oxidation, some other suitable deposition process, or any combination of the foregoing.

[0058] In some embodiments, the sealing layer 118 has a first thickness T1 of about 100 to 500 angstroms, about 100 to 250 angstroms, about 250 to 500 angstroms, about 150 to 350 angstroms, about 50 to 150 angstroms, or about 450 to 550 angstroms. In some embodiments, the first gate dielectric layer 120 has a second thickness T2 of about 60 to 200 angstroms, about 60 to 130 angstroms, about 130 to 200 angstroms, about 20 to 100 angstroms, or about 160 to 240 angstroms. In some embodiments, the first thickness T1 is about 0.5 to 8.5 times the second thickness T2, about 0.25 to 0.75 times the second thickness T2, about 8 to 9 times the second thickness T2, about 1 to 5 times the second thickness T2, or about 4 to 9 times the second thickness T2. In some embodiments, the first thickness T1 is large enough for the sealing layer 118 (e.g., about 100 angstroms or some other suitable thickness value) to protect (e.g., completely protect) the logic region 1061 and the BCD region 106b from damage by thermal processes and oxidation processes. Note that this protection is explained later. In some embodiments, the first thickness T1 is small enough (e.g., less than about 500 angstroms or some other suitable thickness value) so that the sealing layer 118 can be efficiently formed and the cost for forming the sealing layer 118 can be low.

[0059] like Figure 7 As shown in the cross-sectional view 700 in FIG. 1 , the sealing layer 118 is patterned to form a first device opening 702 overlying the first gate dielectric layer 120 on the storage region 106 m of the semiconductor 106. The patterning of the sealing layer 118 may be performed, for example, by a photolithography / etching process or some other suitable patterning process. In some embodiments, the photolithography / etching process includes: depositing a first photolithography layer 704 on the sealing layer 118; patterning the first photolithography layer 704 into a pattern having the first device opening 702; performing etching through the first photolithography layer 704 into the sealing layer 118 to transfer the patterning to the sealing layer 118, and removing the first photolithography layer 704.

[0060] Also by Figure 7 As shown in the cross-sectional view 700 in FIG. 1 , the memory well 108 is formed in the memory region 106 m of the semiconductor substrate 106. In some embodiments, the memory well 108 is formed to have a doping type opposite to that of the body 112 of the semiconductor substrate 106. Further, in some embodiments, the process for forming the memory well 108 includes ion implantation through the first device opening 702 or some other suitable doping process.

[0061] like Figure 8As shown in the cross-sectional view 800 in FIG. 8 , a first etch is performed on the first gate dielectric layer 120 and the lower liner layer 302. The first etch uses the sealing layer 118 as a mask and thus transfers the patterning of the sealing layer 118 to the first gate dielectric layer 120 and the lower liner layer 302. Further, the first etch stops on the semiconductor substrate 106, and the first device opening 702 is expanded to expose the storage well 108.

[0062] In some embodiments, although not shown, the B cleaning process is performed after the first etching. In some embodiments, the B cleaning process includes: applying a mixture of sulfuric acid / hydrogen peroxide / deionized water to the first device opening 702; applying a mixture of hydrochloric acid / deionized water to the first device opening 702; applying a mixture of ammonium hydroxide / hydrogen peroxide / deionized water to the first device opening 702; applying a mixture of hydrochloric acid / hydrogen peroxide / deionized water to the first device opening 702. Sulfuric acid / hydrogen peroxide / deionized water can, for example, remove organic residues in the first device opening 702. The mixture of hydrochloric acid / deionized water can, for example, remove a natural oxide layer in the first device opening 702. The mixture of hydrochloric acid / hydrogen peroxide / deionized water can, for example, remove organic residues and / or particles in the first device opening 702. The mixture of sulfuric acid / hydrogen peroxide / deionized water can, for example, remove organic metal ions in the first device opening 702. In some embodiments, four mixtures are sequentially applied to the first device opening 702 in the order above.

[0063] like Fig. 9 As shown in the cross-sectional view 900 in FIG. 1 , the second gate dielectric layer 902 is formed above the sealing layer 118 and covers the storage region 106m, the BCD region 106b and the logic region 106l of the semiconductor substrate 106. Further, the second gate dielectric layer 902 is formed to liner the first device opening 702 ( Figure 8 In some embodiments, the second gate dielectric layer 902 is or includes silicon dioxide, some other suitable oxide, or some other suitable dielectric. In some embodiments, the second gate dielectric layer 902 is formed by conformal deposition, and / or by thermal oxidation, CVD, PVD, or some other suitable deposition or growth process.

[0064] In some embodiments where the second gate dielectric layer 902 is formed by thermal oxidation, the memory well 106m is partially consumed by oxidation, so that the top surface of the memory well 106m is recessed by a distance D relative to the top surfaces of the BCD wells 110b1 to 110b5, the top surface of the logic well 1101, the top surface of the body 112 of the semiconductor substrate 106, or any combination thereof. The top surfaces of the BCD wells 110b1 to 110b5, the top surface of the logic well 1101, and the top surface of the body 112 of the semiconductor substrate 106 are also recessed if the sealing layer 118 is absent, because the sealing layer 118 prevents the BCD wells 110b1 to 110b5, the logic well 1101, and the body 112 of the semiconductor substrate 106 from being oxidized during thermal oxidation. The distance D may be, for example, about 10 to 100 angstroms, about 40 to 60 angstroms, or about 25 to 75 angstroms.

[0065] Further, in some embodiments where the second gate dielectric layer 902 is formed by thermal oxidation, the second gate dielectric layer 902 is formed faster on the memory well 106 m than on the sealing layer 118, so that the second gate dielectric layer 902 has a third thickness T3 on the memory well 106 m and a fourth thickness T4 less than the third thickness T3 on the sealing layer 118. For example, in the case where the sealing layer 119 is silicon nitride and the memory well 106 m is single crystal silicon, the thermal oxidation of the second gate dielectric layer 902 is formed slower on the silicon nitride of the sealing layer 118 than on the single crystal silicon of the memory well 106 m. The third thickness T3 may be, for example, about 50 to 400 angstroms, about 75 to 125 angstroms, about 50 to 200 angstroms, or about 200 to 400 angstroms. Further, the third thickness T3 may be approximately 1.5 to 2.5 times the distance D, approximately 1.75 to 2.25 times the distance D, approximately 1.9 to 2.1 times the distance D, or approximately 2 times the distance D.

[0066] Also by Fig. 9 As shown in the cross-sectional view 900 in FIG. 1 , the first gate electrode layer 904 is formed to cover the second gate dielectric layer 902, and the cap layer 906 is formed to cover the first gate electrode layer 904. The first gate electrode layer 904 may be or include materials such as doped polysilicon or some other suitable conductive material, and / or the cap layer 906 may be or include materials such as silicon nitride, some other suitable nitride, or some other suitable dielectric. In some embodiments, the cap layer 906 is the same material as the sealing layer 118. In some embodiments, the process for forming the first gate electrode layer 904 includes depositing the first gate electrode layer 904, and sequentially doping and annealing the first gate electrode layer 904. The deposition of the first gate electrode layer 904 may be performed, for example, by CVD, PVD, or some other suitable deposition process. The doping of the first gate electrode layer 904 may be performed, for example, by ion implantation or some other suitable doping process. The cap layer 906 may be formed, for example, by CVD, PVD, or some other suitable deposition process.

[0067] like Fig.10 As shown in the cross-sectional view 1000 in FIG. 1 , the cap layer 906 is patterned to form a hard mask opening 1002 overlying the first gate electrode layer 904 on the storage region 106m of the semiconductor substrate 106. The patterning of the cap layer 906 may be performed, for example, by a photolithography / etching process or some other suitable patterning process. In some embodiments, the photolithography / etching process includes: depositing a second photolithography layer 1004 on the cap layer 906; patterning the second photolithography layer 1004 using the pattern of the hard mask opening 1002; performing etching on the cap layer 906 through the second photolithography layer 1004 to transfer the pattern to the cap layer 906; and removing the second photolithography layer 1004.

[0068] like Fig.11 As shown in the cross-sectional view 1100 in FIG. 1 , the floating gate hard mask 206 is formed in the hard mask opening 1002 ( Fig.10 2). The floating gate hard mask 206 may be or include silicon oxide, some other suitable oxide, or some other suitable dielectric. Further, the floating gate hard mask 206 may be or include, for example, the same material as the second gate dielectric layer 902. In some embodiments, the floating gate hard mask 206 is formed by thermally oxidizing the portion of the first gate electrode layer 904 in the hard mask opening 1002. In other embodiments, the floating gate hard mask 206 is formed by some other suitable growth or deposition process. Further, in some embodiments, the formation of the floating gate hard mask 206 consumes the portion of the floating gate hard mask 206 in the hard mask opening 1002.

[0069] like Fig.12 As shown in the cross-sectional view 1200 in FIG. 1 , the cover layer 906 ( Fig.11 906). In some embodiments, the second etch uses the first gate electrode layer 904 as an etch stop layer. Further, in some embodiments, the second etch uses an etchant that has a higher etching rate for the capping layer 906 than the etching rate for the first gate electrode layer 904 and / or the etching rate for the floating gate hard mask 206 (e.g., 10, 20, 50, or 100 times higher).

[0070] Also through Fig.12 As shown in the cross-sectional view 1200 in FIG. 1 , a third etching is performed on the first gate electrode layer 904 in the presence of the floating gate hard mask 206 ( Fig.11The third etch may also partially clean the first device opening 702. In some embodiments, the third etch uses the second gate dielectric layer 902 as an etch stop layer. Further, in some embodiments, the third etch uses an etchant that has a higher etch rate for the first gate electrode layer 904 than the etch rate for the floating gate hard mask 206 and / or the etch rate for the second gate dielectric layer 902 (e.g., 10, 20, 50, or 100 times higher).

[0071] like Fig.13 As shown in the cross-sectional view 1300 in FIG. 1 , the second gate dielectric layer 902 ( Fig.12 The fourth etch is performed to form a floating gate dielectric layer 210 under the floating gate electrode 208 (see FIG. 1 ). The fourth etch may also clean the first device opening 702. The floating gate hard mask 206 and the floating gate electrode 208 are used as masks for the fourth etch, and in some embodiments, the semiconductor substrate 106 is used as an etch stop layer for the fourth etch. In some embodiments, the fourth etch is performed as part of a B cleaning process of the first device opening 702. An example of a B cleaning process is described above in Figure 8 Steps and Fig. 9 Described between the steps.

[0072] Also through Fig.13 As shown in the cross-sectional view 1300 in FIG. 1 , the third gate dielectric layer 1302 is formed to cover the BCD region 106 b and the logic region 106 l of the semiconductor substrate 106. Further, the third gate dielectric layer 1302 is formed to line the first device opening 702, and is formed to line the sidewalls of the floating gate electrode 208 and the sidewalls of the floating gate dielectric layer 210. In some embodiments, the third gate dielectric layer 1302 is or includes silicon oxide, high temperature oxide (HTO), some other suitable oxide, or some other suitable dielectric. Further, in some embodiments, the third gate dielectric layer 1302 is formed by thermal oxidation or some other suitable deposition process. In the case where the third gate dielectric layer 1302 is formed by a thermal oxidation process and the floating gate hard mask 206 is or includes an oxide, the third gate dielectric layer 1302 may be formed, such as minimally, on the floating gate hard mask 206 (if present).

[0073] like Fig.14 As shown in the cross-sectional view 1400 in FIG. 1 , the storage sidewall spacer 210 is formed to line the floating gate sidewall of the third gate dielectric layer 1302 adjacent to the floating gate electrode 208, and is further formed to overlie the third gate dielectric layer 1302. The storage sidewall spacer includes a pair of segments respectively located on opposite sides of the floating gate electrode 208, and may be or include, for example, silicon nitride, silicon oxide, silicon oxynitride, some other suitable dielectric, or any combination thereof.

[0074] In some embodiments, the process for forming the storage sidewall spacer 218 includes: depositing a covering Fig.13 ; and subsequently performing an etch back on the storage spacer layer. The etch back removes horizontal segments of the storage spacer layer along the floating gate sidewalls of the third gate dielectric layer 1302 without removing vertical segments of the storage spacer layer. These vertical segments define the storage sidewall spacers 218. Further, in some embodiments, the etch back removes vertical segments of the storage spacer layer along other sidewalls of the third gate dielectric layer 1302. This may be due to a long etching time for the etch back, and because the vertical segments along the floating gate sidewalls of the third gate dielectric layer 1302 have a higher height than the vertical segments along the other sidewalls of the third gate dielectric layer 1302. The deposition may be performed, such as by conformal deposition, and / or may be performed by CVD, PCD, some other suitable deposition process, or any combination of the foregoing. The third gate dielectric layer 1302 may be used, such as as an etch stop layer for the etch back.

[0075] like Fig.15 As shown in the cross-sectional view 1500 in FIG. 1 , the patterned third gate dielectric layer 1302 ( Fig.14 ) and the sealing layer 118 ( Fig.14 106b) to remove the third gate dielectric layer 1302 and the sealing layer 118 from the logic region 106l and the BCD region 106b of the semiconductor substrate 106. Further, patterning forms the first selection gate dielectric layer 214 and the dummy sealing element 118d on the storage region 106m of the semiconductor substrate 106. The patterning may be performed, for example, by a lithography / etching process or some other suitable patterning process. In some embodiments, the lithography / etching process includes: depositing a third photoresist layer 1502 on the third gate dielectric layer 1302; patterning the third photoresist layer 1502 to have a pattern of the first selection gate dielectric layer 214; performing etching on the third gate dielectric layer 1302 and the sealing layer 118 in the presence of the third photoresist layer 1502 to transfer the pattern to the third gate dielectric layer 1302 and the sealing layer 118; and removing the third photoresist layer 1502. The etching may be, for example, plasma etching or some other suitable etching.

[0076] exist Figures 7 to 14 During the step of , a thermal process and an oxidation process may be performed. The thermal process and the oxidation process may include, for example, thermal oxidation to form a second gate dielectric layer 902 ( Fig. 9 Visible), thermal oxidation to form a floating gate hard mask 206 ( Fig.11 Visible), thermal oxidation to form a third gate dielectric layer 1302 ( Fig.13 Visible), the first gate electrode layer 904 ( Fig. 9The sealing layer 118 ( Figures 7 to 14 The sealing layer 118 protects the logic region 1061 and the BCD region 106b of the semiconductor substrate 106 from damage by the thermal process and the oxidation process. For example, the sealing layer 118 can prevent the oxidant used during the thermal process and the oxidation process from migrating to the logic region 1061 and the BCD region 106b of the semiconductor substrate 106. Without the sealing layer 118, the oxidant would cause oxidation and consumption of the logic region 1061 and the BCD region 106b of the semiconductor substrate 106, which would make the logic well 1101 and the BCD wells 110b1 to 110b5 shallower and thus change the doping profile of the logic well 1101 and the BCD wells 110b1 to 110b5, respectively. This change in doping profile in turn leads to low yield and change in operating parameters of the logic and BCD devices to be manufactured on the logic well 1101 and the BCD wells 110b1 to 110b5. Therefore, the sealing layer 118 also enables high yield of the logic and BCD devices to be manufactured and prevents the deviation of the parameters of the logic and BCD devices.

[0077] Also through Fig.16 As shown in the cross-sectional view 1600 in FIG. 1 , the first gate dielectric layer 120 and the lower liner layer 302 are patterned to form a second device opening 1602 overlying and exposing the logic well 1101. The patterning of the first gate dielectric layer 120 and the lower liner layer 320 may be performed, for example, by a photolithography / etching process or some other suitable patterning process. In some embodiments, the photolithography / etching process includes: depositing a fourth photolithography layer 1604 on the first gate dielectric layer 120; patterning the fourth photolithography layer 1604 into a pattern having the second device opening 1602; performing etching on the first gate dielectric layer 120 and the lower liner layer 302 through the fourth photolithography layer 1604 to transfer the pattern to the first gate dielectric layer 120 and the lower liner layer 302; and removing the fourth photolithography layer 1604.

[0078] like Fig.17 As shown in the cross-sectional view in FIG. 1 , the fourth gate dielectric layer 1702 is formed to cover the storage region 106m, the BCD region 106b, and the logic region 106l of the semiconductor substrate 106, and further pad the second device opening 1602 ( Fig.16In some embodiments, the fourth gate dielectric layer 1702 is or includes an oxide, some other suitable oxide, a high-k dielectric, some other suitable dielectric, or any combination thereof. Further, in some embodiments, the fourth gate dielectric layer 1702 is formed by CVD, PVD, or some other suitable deposition process.

[0079] Also through Fig.17 As shown in the cross-sectional view 1700 in FIG. 1 , the second gate electrode layer 1704 is formed to cover the fourth gate dielectric layer 1702. The second gate electrode layer 1704 may be or include, for example, doped polysilicon, metal, or some other suitable conductive material. In some embodiments, the process for forming the second gate electrode layer 1704 includes depositing the second gate electrode layer 1704 by, for example, CVD, PVD, chemical plating, electroplating, or some other suitable deposition or plating process. Further, in some embodiments where the second gate electrode layer 1704 is or includes polysilicon, a dopant is added to the second gate electrode layer 1704. The dopant may be added to the second gate electrode layer 1704 by ion implantation or some other suitable doping process.

[0080] like Fig.18 As shown in the cross-sectional view 1800 in FIG. 1 , the second gate electrode layer 1704 ( Fig.17 Visible), the fourth gate dielectric layer 1702 ( Fig.17 ), the first gate dielectric layer 120 ( Fig.17 ), the lower liner layer 302 ( Fig.17), and the first selection gate dielectric layer 214. The patterning forms a logic gate electrode 226 and a logic gate dielectric layer 228 stacked on the logic well 1101, so that the logic gate electrode 226 covers the logic gate dielectric layer 228. The logic gate electrode 226 may be formed, for example, from the second gate electrode layer 1704, and / or the logic gate dielectric layer 228 may be formed, for example, from the fourth gate dielectric layer 1702. Further, the patterning forms a BCD gate electrode 238 and a plurality of BCD gate dielectric layers 240a to 240c stacked on the BCD wells 110b1 to 110b5. The first BCD gate dielectric layer 240a is located below the BCD gate electrode 238 and may be formed, for example, from the fourth gate dielectric layer 1702. The second BCD gate dielectric layer 240b is located below the first BCD gate dielectric layer 240a and may be formed, for example, from the first gate dielectric layer 120. The third BCD gate dielectric layer 240c is located below the second BCD gate dielectric layer 240b and may be formed, for example, from the lower liner layer 302. Further, the patterning forms a select gate electrode 216 and a second select gate dielectric layer 220 stacked on each other and covering the first select gate dielectric layer 214, the storage sidewall spacer 218, and the floating gate hard mask 206. The second select gate electrode 216 overlies the second select gate dielectric layer 220 and may be formed, for example, from the second gate electrode layer 1704. The second select gate dielectric layer 220 may be formed, for example, from the fourth gate dielectric layer 1702. Further, the patterning forms a dummy dielectric element 120d located below the dummy sealing element 118d and including a pair of dummy dielectric segments respectively located on opposite sides of the storage well 108. The dummy dielectric element 120d may be formed, for example, from the first gate dielectric layer 120.

[0081] The patterning may be performed, for example, by a photolithography / etching process or some other suitable patterning process. In some embodiments, the photolithography / etching process includes: depositing a fifth photolithography layer 1802 on the second gate electrode layer 1704; patterning the fifth photolithography layer 1802 using a pattern; performing etching on the second gate electrode layer 1704, the fourth gate dielectric layer 1702, the first gate dielectric layer 120, the lower liner layer 302, and the first selection gate dielectric layer 214 in the presence of the fifth photolithography layer 1802 to transfer the pattern to the second gate electrode layer 1704, the fourth gate dielectric layer 1702, the first gate dielectric layer 120, the lower liner layer 302, and the first selection gate dielectric layer 214; and removing the fifth photolithography layer 1802. In some embodiments, the dummy sealing element 118d also serves as a hard mask while performing the etching.

[0082] like Fig.19As shown in the cross-sectional view 1900 in FIG. 1 , the BCD gate electrode 238 and the plurality of BCD gate dielectric layers 240a to 240c are patterned. The patterning exposes a first portion of the second BCD well 110b2 on a first side of the second BCD well 110b2, while leaving a second portion of the second BCD well 110b2 on a second side of the second BCD well 110b2 still covered by the BCD gate electrode 238, the first side being opposite to the second side. The patterning may be performed, for example, by a photolithography / etching process or some other suitable patterning process. In some embodiments, the photolithography / etching process includes: Fig.18 A sixth photolithography layer 1902 is deposited on the structure in the embodiment of the present invention; the sixth photolithography layer 1902 is patterned to have a pattern; in the presence of the sixth photolithography layer 1902, the BCD gate electrode 238 and multiple BCD gate dielectric layers 240a to 240c are etched to transfer the pattern to the BCD gate electrode 238 and multiple BCD gate dielectric layers 240a to 240c; and the sixth photolithography layer 1902 is removed.

[0083] Also through Fig.19 As shown in the cross-sectional view 1900 in FIG. 1 , a body well 234 is formed on a first side of the second BCD well 110b2 to cover the second BCD well 110b2. In some embodiments, the body well 234 is formed to have the same doping type as the second BCD well 110b2 but a different doping concentration. Further, in some embodiments, the body well 234 is formed by a selective doping process or some other suitable doping process. In some embodiments, the selective doping process includes implanting a dopant into the semiconductor substrate 106 through the sixth lithography layer 1902. The implantation of the dopant may be performed, for example, by ion implantation or some other suitable doping process.

[0084] like Fig. 20As shown in the cross-sectional view 2000 in FIG. 1 , a pair of storage source / drain extensions 202e, a BCD source / drain extension 232e, and a pair of logic source / drain extensions 222e are formed to overlie the storage well 108, the body well 234, and the logic well 1101, respectively. For simplicity of description, only one of the storage source / drain extensions 202e is labeled as 202e. The storage source / drain extensions 202e are respectively located on opposite sides of the storage well 108, so that the gate electrode 216 and the floating gate electrode 208 are sandwiched between the storage source / drain extensions 202e. The storage source / drain extensions 202e may, for example, have a doping type opposite to that of the storage well 108. The BCD source / drain extensions 232e may, for example, have the same doping type as the first BCD well 110b1. The logic source / drain extensions 222e are located on opposite sides of the logic well 1101, respectively, so that the logic gate electrode 226 is sandwiched between the logic source / drain extensions 222e. The logic source / drain extensions 222e may, for example, have a doping type opposite to that of the logic well 1101.

[0085] In some embodiments, the process for forming the storage source / drain extension 202e, the BCD source / drain extension 232e, and the logic source / drain extension 222e includes repeatedly performing a selective doping process. For example, a first selective doping process may be performed to form the storage source / drain extension 202e, followed by a second selective doping process to form the logic source / drain extension 222e, followed by a third selective doping process to form the BCD source / drain extension 232e. In some embodiments, the selective doping process includes: performing a selective doping process at a time; ... Fig.19 depositing a photoresist layer on the structure; patterning the photoresist layer to form a layout of source / drain extensions; implanting dopants into the semiconductor substrate 106 in the presence of the patterned photoresist layer; and removing the patterned photoresist layer.

[0086] like Fig.21 As shown in the cross-sectional view 2100 in FIG. Fig. 20 The main sidewall spacers 242 are formed on the sidewalls of the structure in the embodiment. For simplicity of explanation, only some of the main sidewall spacers 242 are labeled as 242. The main sidewall spacers 242 can be or include materials such as silicon nitride, some other suitable nitride, some other suitable dielectric, or any combination of the foregoing. In some embodiments, the process for forming the main sidewall spacers 242 includes: depositing a covering Fig. 20 ; and then performing an etching on the main spacer layer. The etch back removes the horizontal segments of the main spacer layer without removing the vertical segments of the main spacer layer, so that the remaining vertical segments define the main sidewall spacers 242. The deposition can be performed, such as by conformal deposition, and / or such as by CVD, PVD, some other suitable deposition process, or any combination of the foregoing.

[0087] like Fig. 22 As shown in the cross-sectional view 2200 in FIG. 1 , a pair of storage source / drain regions 202, a pair of BCD source / drain regions 232, and a pair of logic source / drain regions 222 are formed to overlie the storage well 108, the first BCD well 110b1, and the logic well 1101, respectively. The storage source / drain regions 202 are respectively located on opposite sides of the storage well 108, so that the selection gate electrode 216 and the floating gate electrode 208 are sandwiched between the storage source / drain regions 202. Further, the storage source / drain regions 202 are respectively adjacent to the storage source / drain extensions 202e, and the storage source / drain regions 202 have the same doping type and a higher doping concentration than the storage source / drain extensions 202e. The BCD source / drain regions 232 are respectively located on opposite sides of the first BCD well 110b1, so that the BCD gate electrode 238 is sandwiched between the BCD source / drain regions 232. Further, one of the BCD source / drain regions 232 is adjacent to the BCD source / drain extension 232e, and one of the BCD source / drain regions 232 has the same doping type and a higher doping concentration than the BCD source / drain extension 232e. The logic source / drain regions 222 are respectively located on opposite sides of the logic well 1101, so that the logic gate electrode 226 is sandwiched between the logic source / drain regions 222. Further, the logic source / drain regions 222 are respectively adjacent to the logic source / drain extension 222e, and the storage source / drain region 202 has the same doping type and a higher doping concentration than the storage source / drain extension 202e.

[0088] In some embodiments, the process for forming the storage source / drain region 202, the BCD source / drain region 232, and the logic source / drain region 222 includes repeatedly performing a selective doping process. For example, a first selective doping process may be performed to form the storage source / drain region 202, followed by a second selective doping process to form the logic source / drain region 222, followed by a third selective doping process to form the BCD source / drain region 232. In some embodiments, the selective doping process includes: Fig.21 Depositing a photoresist layer on the structure in; patterning the photoresist layer to form a layout of source / drain regions; implanting dopants into the semiconductor substrate 106 in the presence of the patterned photoresist layer; and removing the patterned photoresist layer.

[0089] like Fig.23 As shown in the cross-sectional view 2300 in FIG. 23, the ILD layer 122 is formed to cover Fig. 22The structure in the embodiment of the present invention is formed, and the contact through hole 124 is formed to extend through the ILD layer 122 to the storage source / drain region 202, the BCD source / drain region 232, the logic source / drain region 222, the selection gate electrode 216, the BCD gate electrode 238, the logic gate electrode 226, or any combination of the foregoing. The ILD layer 122 may be or include materials such as silicon dioxide, silicon nitride, some other suitable dielectrics, or any combination of the foregoing. Further, the ILD layer 122 may be formed such as by depositing the ILD layer 122 and etching the top of the ILD layer 122. The deposition may be performed such as by CVD, PVD, or some other suitable deposition process. The planarization may be performed such as by CMP or some other suitable planarization process. The contact through hole 124 may be or include materials such as tungsten, copper, aluminum copper, aluminum, some other suitable metals, or some other suitable conductive materials. Further, the contact via 124 may be formed, such as by a single or dual damascene process.

[0090] Although not shown, in some embodiments, silicide pads are formed on the storage source / drain regions 202, the BCD source / drain regions 232, and the logic source / drain regions 222 before forming the ILD layer 122. The silicide pads reduce the contact resistance between the contact vias 124 and the source / drain regions and may be or include, for example, nickel silicide or some other suitable silicide.

[0091] refer to Fig.24 , provides Figures 3 to 23 Flowchart of some embodiments of the sealing method.

[0092] At step 2402, an isolation structure is formed in a semiconductor substrate to divide a storage area, a BCD area, and a logic area. For example, Figure 3 Visible in.

[0093] At step 2404, one or more BCD wells are formed in a BCD region of a semiconductor substrate. For example, Figure 4 Visible in.

[0094] At step 2406, one or more logic wells are formed in a logic region of the semiconductor substrate. For example, Figure 5 Visible in.

[0095] At step 2408, a sealing layer is formed to cover the storage area, the logic area, and the BCD area of ​​the semiconductor substrate. Figure 6 In some embodiments, the sealing layer is or includes silicon nitride or some other suitable dielectric. Further, in some embodiments, the sealing layer is a barrier layer for an oxidant used later in step 2410.

[0096] At step 2410, a memory cell structure is formed on a memory region of a semiconductor substrate. The formation of the memory cell structure includes a thermal process and / or an oxidation process. For example, Figures 7 to 14 visible.

[0097] At step 2412, the sealing layer is removed from the BCD area and the logic area. For example, Fig.15 As can be seen. The sealing layer protects the logic well and the BCD well from being damaged by the thermal process and / or oxidation process used to form the memory cell structure at step 2410. For example, the sealing layer prevents the oxidant used during the thermal process and / or oxidation process of step 2410 from oxidizing the logic well and the BCD well, thereby preventing the depth of the logic well and the BCD well from being reduced and thus changing the doping profile of the logic well and the BCD well. Therefore, the sealing layer results in high yield and stable / uniform device parameters of the logic devices and the BCD devices on the logic well and the BCD well.

[0098] At step 2414, the logic structure and the BCD structure are on the logic well and the BCD well, respectively. For example, Figures 16 to 19 In some embodiments, while forming the logic structure and the BCD structure, a storage gate electrode (eg, a selection gate electrode) is formed along a sidewall of the storage structure.

[0099] At step 2416, the source / drain regions of the storage structure, logic structure, and BCD structure are formed. For example, Figure 20 to Figure 22 visible.

[0100] At step 2418, a back-end-of-line (BEOL) interconnect structure is formed to cover the semiconductor substrate, the memory structure, the logic structure, and the BCD structure. For example, Fig.23 As can be seen, the BEOL interconnect structure includes an ILD layer and contact vias extending through the ILD layer to the source / drain regions.

[0101] exist Fig.24 Flowchart 2400 is shown and described herein as a series of steps or times, it should be appreciated that the order in which these steps or times are shown should not be interpreted in a limiting sense. For example, in addition to being shown and / or described herein, some steps may occur in a different order and / or simultaneously with other steps or times. Further, not all of the steps shown need to implement one or more aspects or embodiments described herein, and one or more steps depicted herein may be implemented in one or more independent steps and / or stages.

[0102] refer to Figures 25 to 32 , provides Figures 3 to 23 A series of cross-sectional views 2500 to 3200 of some other embodiments of the sealing method in FIG. Figures 3 to 23 Compared with the sealing method embodiment in Figures 25 to 32 In an embodiment of the sealing method in FIG. 1 , the first gate dielectric layer 120 is formed after the sealing layer 118. For example, the Figures 25 to 32 The sealing method embodiment in which the Figure 2B IC in.

[0103] like Fig.25 As shown in the cross-sectional view 2500 in FIG. 1 , the isolation structure 114 is formed in the semiconductor substrate 106 to divide the storage area 106m of the semiconductor substrate 106, the BCD area 106b of the semiconductor substrate 106, and the logic area 106l of the semiconductor substrate 106. Further, one or more BCD wells 110b1 to 110b5 are formed in the BCD area 106b of the semiconductor substrate 106, and the logic well 110l is formed in the logic area 106l of the semiconductor substrate. The isolation structure 114, the BCD wells 110b1 to 110b5, and the logic well 110l can be such as referring to FIG. Figures 3 to 5 The formation.

[0104] Also through Fig.25 As shown in the cross-sectional view 2500 in FIG. 1 , the sealing layer 118 is formed to cover the storage region 106m, the BCD region 106b, and the logic region 106l of the semiconductor substrate 106. The sealing layer 118 may be, for example, Figure 6 The formation Figure 6 , Figure 6 The first gate dielectric layer 120 is omitted.

[0105] like Fig.26 As shown in the cross-sectional view 2600 in FIG. 1 , the sealing layer 118 and the lower liner layer 302 are patterned to form a first device opening 702 on the storage region 106m of the semiconductor substrate 106. Further, the storage well 108 is formed in the storage region 106m of the semiconductor substrate 106 through the first device opening 702. The patterning and formation of the storage well 108 can refer to Figure 7 and Figure 8 Said execution.

[0106] like Fig. 27 As shown in the cross-sectional view 2700 in FIG. 1 , the floating gate dielectric layer 210, the floating gate electrode 208, and the floating gate hard mask 206 are stacked on the storage well 108. Further, the third gate dielectric layer 1302 is formed to cover the sealing layer 118 and the storage well 108. Further, the storage sidewall spacer 218 is formed on the third gate dielectric layer 1302 adjacent to the sidewall of the floating gate electrode 208. This formation can refer to, for example, Figures 9 to 14 Said execution.

[0107] like Fig.28 As shown in the cross-sectional view 2800 in FIG. 1 , the patterned third gate dielectric layer 1302 ( Fig. 27 ), sealing layer 118 ( Fig. 27 ), and the lower liner layer 302 ( Fig. 27 ) to remove the third gate dielectric layer 1302, the sealing layer 118, and the lower liner layer 302 from the logic region 1061 and the BCD region 106b of the semiconductor substrate 106. The patterning can refer to, for example, Fig.15 Compared to the execution Fig.15 , the lower liner layer 302 is also patterned.

[0108] like Fig.29 As shown in the cross-sectional view 2900 in FIG. 1 , the first gate dielectric layer 120 is formed to cover the storage region 106m, the BCD region 106b, and the logic region 106l of the semiconductor substrate 106. The first gate dielectric layer 120 may be or include, for example, silicon oxide, some other suitable oxide, some other suitable dielectric, or any combination thereof. In some embodiments, the first gate dielectric layer 120 is formed by CVD, PCD, thermal oxidation, some other suitable deposition process, or any combination thereof.

[0109] In some embodiments where the first gate dielectric layer 120 is formed by thermal oxidation, the first gate dielectric layer 120 is formed faster on the BCD region 106b and the logic region 106l than on the memory region 106m, so that the first gate dielectric layer 120 has a second thickness T2 on the BCD region 106b and the logic region 106l and has a fifth thickness T5 on the memory region 106m that is less than the second thickness T2. In some embodiments, the second thickness T2 is about 60 to 200 angstroms, about 60 to 130 angstroms, about 130 to 200 angstroms, about 20 to 100 angstroms, or about 160 to 240 angstroms. Due to the different materials being oxidized, the first gate dielectric layer 120 can be formed faster, such as on the BCD region 106b and the logic region 106l than on the memory region 106m.

[0110] like Fig.30 As shown in the cross-sectional view 3000 in FIG. 1 , the first gate dielectric layer 120 is patterned to remove the first gate dielectric layer 120 from the logic well 1101. Further, the fourth gate dielectric layer 1702 and the second gate electrode 1704 are formed to cover the storage region 106m, the BCD region 106b, and the logic region 106l of the semiconductor substrate 106. The patterning and forming may be performed as described in reference to Fig.17 and Fig.18 Execute as described.

[0111] like Fig.31 As shown in the cross-sectional view 3100 in FIG. 31, the second gate electrode layer 1704 ( Fig.30 Visible), the fourth gate dielectric layer 1702 ( Fig.30 Visible), the first gate dielectric layer 120 ( Fig.30 ), and the first selection gate dielectric layer 214. The patterning forms a logic gate electrode 226 and a logic gate dielectric layer 228 stacked on the logic well 1101. Further, the patterning forms a BCD gate electrode 238 and a plurality of BCD gate dielectric layers 240a, 240b stacked on the BCD wells 110b1 to 110b5. Further, the patterning forms a selection gate electrode 216, a second selection gate dielectric layer 220, and a third selection gate dielectric layer 244 stacked on each other and covering the first selection gate dielectric layer 214, the storage sidewall spacer 218, and the floating gate hard mask 206. The patterning and forming can be such as referring to Fig.18 Compared to Fig.18 , the patterning also forms a third select gate dielectric layer 244, but Fig.18 The third BCD gate dielectric layer 240c is omitted.

[0112] like Fig.32 As described in the cross-sectional view 3200 in FIG. 32, the BCD gate electrode 238 and the plurality of BCD gate dielectric layers 240a, 240b are further patterned, and the body well 234 is formed to overlie the second BCD well 110b2. Further, a pair of storage source / drain extensions 202e, a BCD source / drain extension 232e, and a pair of logic source / drain extensions 222e are formed to overlie the storage well 108, the body well 234, and the logic well 110l, respectively. Further, a main sidewall spacer 242 is formed, followed by forming a pair of storage source / drain regions 202, a pair of BCD source / drain regions 232, and a pair of logic source / drain regions 222. Further, an ILD layer 122 and a contact via 124 are formed. This formation may be performed as described with reference to FIG. Figures 19 to 23 Execute as described.

[0113] In some embodiments, the present disclosure discloses a method for forming an integrated circuit, the method comprising: providing a semiconductor substrate including a first device region and a second device region separated by an isolation structure; forming a doped well in the second device region; forming a sealing layer covering the first and second device regions and further covering the doped well; removing the sealing layer from the first device region but not from the second device region; forming a memory cell structure on the first device region; removing the sealing layer from the second device region after the memory cell structure is formed; and forming a device structure on the second device region. In some embodiments, the formation of the memory cell structure comprises recessing a top surface of the semiconductor substrate in the first device region but not in the second device region. In some embodiments, the method further comprises forming a gate dielectric layer on the isolation structure, the first device region, and the second device region, wherein the gate dielectric layer is a different material than the sealing layer and is formed after the sealing layer is removed from the second device region. In some embodiments, the method comprises forming a gate dielectric layer on the isolation structure, the first device region, and the second device region, wherein the gate dielectric layer is a different material than the sealing layer, and wherein the sealing layer is formed to cover the gate dielectric layer. In some embodiments, the sealing layer comprises silicon nitride, silicon carbide, polysilicon, or silicon oxynitride. In some embodiments, the memory cell structure is formed using an oxidation process. In some embodiments, the formation of the memory cell structure includes forming a memory gate dielectric layer, a memory gate electrode covering the memory gate dielectric layer, and a memory gate hard mask covering the memory gate electrode, wherein the memory gate dielectric layer is formed by an oxidation process. In some embodiments, the method further includes forming a second doped well on the first device region after the sealing layer is removed from the first device region and before the formation of the memory cell structure. In some embodiments, the method further includes: depositing a conductive layer covering the first and second device regions and further covering the memory cell structure; and patterning the conductive layer to form a device gate electrode covering the doped well and at least partially defining the device structure, and to further form a memory gate electrode adjacent to the memory cell structure.

[0114] In some embodiments, the present disclosure provides an integrated circuit, comprising: a semiconductor substrate including a first device region and a second device region; an isolation structure extending into the top surface of the semiconductor substrate, wherein the isolation structure divides and separates the first and second device regions; a memory cell covering the first device region; a MOS device covering the second device region; and a dummy structure covering the isolation structure, wherein the dummy structure comprises a dummy sealing element. In some embodiments, the dummy sealing element comprises silicon nitride, silicon carbide, silicon oxynitride, or polysilicon. In some embodiments, the dummy sealing element directly contacts the isolation structure. In some embodiments, the dummy structure further comprises a dummy dielectric element, wherein the dummy sealing element covers the dummy dielectric element. In some embodiments, the dummy structure comprises a pair of dummy segments on opposite sides of the memory cell, respectively. In some embodiments, the top surface of the semiconductor substrate has a first top surface portion in the first device region, and further has a second top surface portion in the second device region, wherein the first top surface region is recessed below the second top surface portion. In some embodiments, the memory cell comprises a memory gate dielectric layer and a memory gate electrode covering the memory gate dielectric layer, wherein the first top surface portion is recessed by a recessed depth than the second top surface portion, and the thickness of the memory gate dielectric layer is approximately 1.75 to 2.25 times the recessed depth.

[0115] In some embodiments, the present disclosure provides another method for forming an integrated circuit, the method comprising: forming an isolation structure in a semiconductor substrate, wherein the isolation structure divides a storage region of the semiconductor substrate and further divides a peripheral region of the semiconductor substrate; forming a doped well in the peripheral region; forming a sealing layer covering the storage region and the peripheral region and further covering the doped well; removing the sealing layer from the storage region but not from the peripheral region; forming a gate dielectric layer on the storage region by a thermal oxidation process, wherein the thermal oxidation process causes a top surface of the semiconductor substrate to be recessed in the storage region but not in the peripheral region; forming a storage gate electrode above the gate dielectric layer; after the storage gate electrode is formed, removing the sealing layer from the peripheral region; and forming a peripheral gate electrode on the peripheral region while simultaneously forming a second storage gate electrode adjacent to the storage gate electrode. In some embodiments, the method further comprises: forming a second gate dielectric layer covering the storage region and the peripheral region and further covering the doped well, wherein the sealing layer is formed to cover the second gate dielectric layer; and removing the second gate dielectric layer from the storage region but not from the peripheral region before the gate dielectric layer is formed. In some embodiments, the method further includes: forming a second gate dielectric layer covering the storage region and the peripheral region and further covering the doped well, wherein removing the sealing layer from the peripheral region is performed before forming the second gate dielectric layer; and patterning the second gate dielectric layer to form a peripheral gate dielectric layer on the peripheral region, wherein the peripheral gate dielectric layer covers the peripheral gate electrode. In some embodiments, patterning the second gate dielectric layer further forms a storage gate dielectric layer on the storage region, wherein the storage gate dielectric layer is located below the second storage gate electrode.

[0116] The features of several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art will appreciate that the present disclosure can be easily used as a basis for designing or modifying other processes and structures for implementing the same purpose and / or achieving the same benefits as the embodiments introduced herein. Those skilled in the art will appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that different modifications, substitutions, and replacements may be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming an integrated circuit, the method comprising: Providing a semiconductor substrate including a first device region and a second device region, wherein the first device region and the second device region are separated by an isolation structure; forming a doped well in the second device region; forming a sealing layer covering the first device region and the second device region and also covering the doped well; removing the sealing layer from the first device region but not from the second device region to form a through hole in the sealing layer; forming a memory cell structure passing through the through hole on the first device region; After forming the memory cell structure, removing the sealing layer from the second device region; as well as forming a device structure on the second device region, Wherein, forming the storage unit structure comprises: A first gate dielectric layer is formed in the first device region by a thermal oxidation process, wherein the thermal oxidation process causes a top surface of the semiconductor substrate to be recessed in the first device region but not in the second device region.

2. The method according to claim 1, wherein: The sealing layer prevents oxidation of the second device region while forming the memory cell structure.

3. The method according to claim 1, further comprising: A second gate dielectric layer is formed on the isolation structure, the first device region, and the second device region, wherein the second gate dielectric layer is a different material from the sealing layer and is formed after the sealing layer is removed from the second device region.

4. The method according to claim 1, further comprising: A third gate dielectric layer is formed on the isolation structure, the first device region, and the second device region, wherein the third gate dielectric layer is made of a material different from that of the sealing layer, and the sealing layer is formed to cover the third gate dielectric layer.

5. The method according to claim 1, wherein: The sealing layer includes silicon nitride, silicon carbide, polysilicon or silicon oxynitride.

6. The method according to claim 1, wherein: The first gate dielectric layer is also formed on the second device region at the same time, and the thickness of the first gate dielectric layer in the first device region is greater than the thickness of the first gate dielectric layer in the second device region.

7. The method according to claim 6, wherein: Forming the storage unit structure further includes: A storage gate electrode covering the first gate dielectric layer and a storage gate hard mask covering the storage gate electrode are formed.

8. The method according to claim 1, further comprising: After removing the sealing layer from the first device region and before forming the memory cell structure, a second doped well is formed in the first device region.

9. The method according to claim 1, further comprising: Depositing a conductive layer covering the first device region and the second device region and also covering the memory cell structure; as well as The conductive layer is patterned to form a device gate electrode covering the doped well and at least partially defining the device structure, and to form a storage gate electrode adjacent to the memory cell structure.

10. The method according to claim 1, wherein: The doped well overlies the bulk of the semiconductor substrate, and the doped well has a different doping concentration and / or doping type than the bulk of the semiconductor substrate, and wherein the method further comprises: A pair of source / drain regions are formed recessed into the top of the semiconductor substrate and overlying the doped well, wherein the device structure is located between and adjacent to the source / drain regions.

11. A method for forming an integrated circuit, the method comprising: forming an isolation structure in a semiconductor substrate, wherein the isolation structure divides a storage area of ​​the semiconductor substrate and also divides a peripheral area of ​​the semiconductor substrate; forming a doped well in the peripheral region; forming a sealing layer covering the storage region and the peripheral region and also covering the doped well; removing the sealing layer from the storage area but not from the peripheral area; forming a gate dielectric layer in the storage region by a thermal oxidation process, wherein the thermal oxidation process causes a top surface of the semiconductor substrate to be recessed in the storage region but not in the peripheral region; forming a storage gate electrode above the gate dielectric layer; After forming the storage gate electrode, removing the sealing layer from the peripheral area; depositing a gate electrode layer after removing the sealing layer from the peripheral region, and The gate electrode layer is selectively etched to form a peripheral gate electrode on the peripheral region while simultaneously forming a second memory gate electrode located on the memory region adjacent to the memory gate electrode.

12. The method according to claim 11, further comprising: forming a second gate dielectric layer covering the storage region and the peripheral region and also covering the doped well, wherein the sealing layer is formed to cover the second gate dielectric layer; and Before forming the gate dielectric layer, the second gate dielectric layer is removed from the storage region but not from the peripheral region.

13. The method according to claim 11, further comprising: forming a second gate dielectric layer covering the storage region and the peripheral region and also covering the doped well, wherein before forming the second gate dielectric layer, removing the sealing layer from the peripheral region is performed; and The second gate dielectric layer is patterned to form a peripheral gate dielectric layer on the peripheral region, wherein the peripheral gate dielectric layer is located below the peripheral gate electrode.

14. The method according to claim 13, wherein: Patterning the second gate dielectric layer further forms a storage gate dielectric layer on the storage region, wherein the storage gate dielectric layer is located below the second storage gate electrode.

15. The method according to claim 11, wherein: The sealing layer is removed from the peripheral region, leaving a dummy portion of the sealing layer at an edge of the storage region, and wherein the gate electrode layer covers the dummy portion and has a bottom indent at the dummy portion, wherein the dummy portion is a remaining portion of the sealing layer.

16. A method for forming an integrated circuit, the method comprising: Providing a substrate comprising a first device region and a second device region; Depositing a sealing layer covering the first device region and the second device region; performing a first etch in the sealing layer to form an opening positioned at the first device region and not covering the first device region, wherein the second device region remains covered by the sealing layer when the first etch is completed; forming a memory cell structure in the opening; Depositing a liner on the sidewalls of the sealing layer and the sidewalls of the memory cell structure in the opening, and a gate dielectric layer also covering the sealing layer; performing a second etch in the sealing layer and the gate dielectric layer to clean the sealing layer and the gate dielectric layer from the second device region but not from the first device region, wherein after the second etch, a dummy portion of the sealing layer remains covered by the gate dielectric layer on the sidewalls of the sealing layer, wherein the dummy portion is a remaining portion of the sealing layer on opposite sides of the first device region; and A device structure is formed on the second device region.

17. The method according to claim 16, wherein: The formation of the device structure cleans the gate dielectric layer from above the dummy portion of the sealing layer.

18. The method according to claim 16, further comprising: A second gate dielectric layer is formed covering the first device region and the second device region, wherein the sealing layer is formed covering the second gate dielectric layer, wherein the first etch extends into the second gate dielectric layer, and wherein the device structure is partially formed by the second gate dielectric layer. 19 . The method of claim 16 , wherein the first device region and the second device region are electrically isolated by a shallow trench isolation (STI) structure, and wherein the sealing layer directly contacts the shallow trench isolation structure and comprises a different material from the shallow trench isolation structure.

20. The method of claim 16, wherein the forming of the memory cell structure comprises oxidation, and wherein the sealing layer prevents oxidation of the second device region while the memory cell structure is formed.

21. The method according to claim 16, wherein: The forming of the memory cell structure includes oxidation, and wherein the oxidation recesses a top surface of the first device region relative to a top surface of the second device region.

22. The method of claim 16, further comprising: forming an interlayer dielectric (ILD) layer covering the memory cell structure, the device structure, and the dummy portion of the sealing layer; and A contact via is formed in the interlayer dielectric layer.

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