Memory arrays including memory cell strings and methods for forming memory arrays including memory cell strings.

Abstract

The present application relates to a memory array including a string of memory cells and a method for forming a memory array including a string of memory cells. The method includes forming laterally spaced memory blocks each including a vertical stack, the vertical stack including alternating insulating layers and conductive layers. The string of channel materials of the memory cells extends through the insulating layer and the conductive layer. The conductive layer includes metal along the sides of the memory block. Silicon is formed between the memory blocks above the metal of the conductive layer. The silicon and the metal react to form therefrom a metal silicide of the metal directly against and longitudinally along individual ones of the conductive layers. After the reaction, unreacted portions of the silicon are removed from between the memory blocks, and an intervening material is formed between the memory blocks and longitudinally along the memory blocks. Other embodiments are disclosed, including structures independent of the method.

Description

Technical Field

[0001] Embodiments disclosed herein relate to memory arrays and to methods for forming memory arrays. Background Art

[0002] A memory is an integrated circuit system and is used in computer systems to store data. The memory can be fabricated as one or more arrays of individual memory cells. The memory cells can be written to or read from using digit lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines). The sense lines can conductively interconnect the memory cells along the columns of the array, and the access lines can conductively interconnect the memory cells along the rows of the array. Each memory cell can be uniquely addressed by a combination of the sense lines and the access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for a long period of time without power. Non-volatile memory is generally designated as memory with a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory may have a retention time of a few milliseconds or less. In any case, the memory cell is configured to hold or store memory in at least two different selectable states. In a binary system, the states are considered "0" or "1". In other systems, at least some individual memory cells may be configured to store information at more than two levels or states.

[0004] A field effect transistor is an electronic component that can be used in a memory cell. These transistors include a pair of conductive source / drain regions with a semiconductive channel region between them. A conductive gate is adjacent to the channel region and is separated from the channel region by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one of the source / drain regions to the other through the channel region. When the voltage is removed from the gate, current is substantially prevented from flowing through the channel region. Field effect transistors may also include additional structures, such as a reversibly programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate.

[0005] Flash memory is a type of memory and is used extensively in modern computers and devices. For example, a modern personal computer may store the BIOS on a flash memory chip. As another example, it is increasingly common for computers and other devices to utilize flash memory in solid-state drives to replace conventional hard disk drives. As yet another example, flash memory is prevalent in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and to provide the ability to remotely upgrade devices for enhanced features.

[0006] NAND may be the basic architecture for integrated flash memory. A NAND cell device includes at least one selection device coupled in series with a series combination of memory cells (and the series combination is often referred to as a NAND string). The NAND architecture may be configured in a three-dimensional arrangement including vertically stacked memory cells that individually include vertical transistors that can be reversibly programmed. Control circuitry or other circuitry may be formed below the vertically stacked memory cells. Other volatile or non-volatile memory array architectures may also include vertically stacked memory cells that individually include transistors.

[0007] The memory array may be arranged in memory pages, memory blocks and partial blocks (e.g., sub-blocks) and memory planes, such as shown and described in any of U.S. Patent Application Publications Nos. 2015 / 0228651, 2016 / 0267984, and 2017 / 0140833. The memory blocks may at least partially define the longitudinal profiles of individual word lines in individual word line layers of vertically stacked memory cells. Connections to these word lines may occur in a so-called "staircase structure" at the ends or edges of the array of vertically stacked memory cells. The staircase structure includes individual "steps" (alternatively referred to as "steps" or "stairs") that define contact areas for individual word lines, with vertically extending conductive vias contacting the contact areas to provide electrical access to the word lines. Summary of the invention

[0008] In one aspect, the present application provides a method for forming a memory array including a string of memory cells, comprising: forming laterally spaced memory blocks each comprising a vertical stack, the vertical stack comprising alternating insulating layers and conductive layers, the string of channel materials of the memory cells extending through the insulating layers and the conductive layers, the conductive layers comprising metal along the sides of the memory blocks; forming silicon between the memory blocks above the metal of the conductive layers; reacting the silicon and the metal to form therefrom metal silicides of the metal directly against and longitudinally along individual ones of the conductive layers; and after the reaction, removing unreacted ones of the silicon from between the memory blocks and forming intermediate material between the memory blocks and longitudinally along the memory blocks.

[0009] In another aspect, the present application provides a method for forming a memory array including a string of memory cells, comprising: forming a conductor layer including a conductor material on a substrate; forming a stack including vertically alternating first and second layers above the conductor layer, the stack including laterally spaced memory blocks with horizontally elongated trenches therebetween, a string of channel material extending through the first and second layers, the material of the first layers having a composition different from that of the second layers, the lowest of the first layers being thicker than the first layers above it, the second layer material of the second layer immediately above the lowest first layer including an upper first insulating material and a lower second material below the upper first insulating material, the lower second material having a composition different from that of the upper first insulating material, a sacrificial material laterally between the channel material of the string of channel material and the lower second material in the second layer immediately above the lowest first layer, the sacrificial material being located in the lowest first layer laterally outward from the channel material of the string of channel material, the sacrificial material having a composition different from that of the lower second material; selectively etching the first layer material isotropically relative to the second layer material to forming a void space in the first layer; depositing a conductive material into the trench and into the void space in the first layer, the conductive material filling the void space in the first layer above the lowest first layer, the conductive material not completely filling the void space in the lowest first layer; etching the conductive material from the lowest first layer; exposing the sidewalls of the channel material of the string of channel materials in the lowest first layer and the second layer immediately above the lowest first layer, the exposing comprising: etching the sacrificial material in the lowest first layer; and etching the sidewalls of the string of channel materials in the second layer immediately above the lowest first layer. the sacrificial material in the second layer above the lowest first layer to form a cavity laterally between the channel material of the channel material string and the lower second material in the second layer immediately above the lowest first layer; and depositing a conductive material into the void space of the lowest first layer and into the cavity in the second layer immediately above the lowest first layer, directly against the exposed side walls of the channel material of the channel material string in the lowest first layer and the second layer immediately above the lowest first layer and directly against the uppermost surface of the conductor material of the conductor layer.

[0010] On the other hand, the present application provides a memory array including a string of memory cells, comprising: each comprising a vertical stack of laterally spaced memory blocks, the vertical stack comprising alternating insulating layers and conductive layers, the channel material strings of the memory cells extending through the insulating layers and the conductive layers, the conductive layers comprising metal; metal silicide directly abutting and longitudinally along the metal of individual ones of the conductive layers and longitudinally along opposite sides of individual ones of the memory blocks; and intervening material laterally between and longitudinally along the laterally adjacent memory blocks. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a diagrammatic cross-sectional view of a portion of a substrate under processing according to an embodiment of the present invention, and is a cross-sectional view through Figure 2 Intercepted by line 1-1 in.

[0012] Figure 2 It passes through Figure 1 A diagrammatic cross-sectional view taken along line 2-2 in FIG.

[0013] Figure 3-4 yes Figure 1 and 2 Magnified view of a portion of.

[0014] Figure 5-26 is in process according to some embodiments of the present invention Figure 1-4 Diagrammatic sequential cross-sectional, expanded, enlarged and / or partial views of the structure or parts thereof. DETAILED DESCRIPTION

[0015] Embodiments of the present invention encompass methods for forming a memory array, such as a NAND or other memory cell array that may have at least some under-array peripheral control circuitry (e.g., under-array CMOS). Embodiments of the present invention also encompass memory arrays that are independent of the manufacturing method (e.g., NAND architecture). A first example method embodiment refers to Figure 1-26 described, and can be viewed as a "gate-last" or "replacement-gate" process, beginning with Figure 1-4 .

[0016] Figure 1 and 2 A construction 10 is shown having an array or array region 12 in which vertically extending strings of transistors and / or memory cells are to be formed. Construction 10 includes a base substrate 11 having any one or more of a conductive / conductor / conductive, semiconductive / semiconductive / semiconductive, or insulating / insulator / insulating (i.e., electrically insulating in this context) material. Various materials are vertically formed on base substrate 11. The materials are Figure 1-4 11. For example, other partially or fully manufactured components of the integrated circuit system may be disposed somewhere above, around, or within the base substrate 11. Control and / or other peripheral circuitry for operating components within an array of vertically extending strings of memory cells (e.g., array 12) may also be fabricated, which may or may not be fully or partially within the array or sub-array. In addition, multiple sub-arrays may be fabricated and operated independently, sequentially, or otherwise relative to each other. In this document, a "sub-array" may also be considered an array.

[0017] The conductor material 17 (eg, WSi x A conductor layer 16 of conductively doped polysilicon (conductively doped polysilicon on top) is formed over substrate 11. Conductor layer 16 may include portions of control circuitry (e.g., peripheral under-array circuitry and / or common source lines or plates) for controlling read and write access to transistors and / or memory cells to be formed within array 12. A stack 18 including vertically alternating insulating layers 20* and conductive layers 22* is formed over conductor layer 16 (* as a suffix is ​​used to include all such components designated with the same numerical value that may or may not have other suffixes). An example thickness for each of layers 20* and 22* is 22 to 60 nanometers. Only a small number of layers 20* and 22* are shown, but stack 18 is more likely to include dozens, a hundred, or more layers 20* and 22*. Other circuitry that may or may not be part of the peripheral and / or control circuitry may be between conductor layer 16 and stack 18. For example, multiple vertically alternating layers of conductive and insulating materials of such circuitry may be below the lowest of the conductive layers 22* and / or above the uppermost of the conductive layers 22*. For example, one or more select gate layers (not shown) may be between the conductor layer 16 and the lowest conductive layer 22*, and one or more select gate layers may be above the uppermost of the conductive layers 22*. Alternatively or in addition, at least one of the depicted uppermost and lowest conductive layers 22* may be a select gate layer. Regardless, the conductive layer 22* (alternatively referred to as the first layer) may not include conductive material, and the insulating layer 20* (alternatively referred to as the second layer) may not include insulating material or be insulating when processed in conjunction with the "gate last" or "replacement gate" example method embodiments initially described herein. The example conductive layer 22* includes a first material 26 (e.g., silicon nitride) that may be fully or partially sacrificial. The example insulating layer 20* includes a second material 24 (e.g., silicon dioxide) that has a composition different from that of the first material 26 and that may be fully or partially sacrificial.

[0018] In some embodiments, the lowest first layer 22z is thicker than the first layer 22* above it, and in one such embodiment, is at least 1.5 times thicker than the first layer 22* above it. In one embodiment and as shown, the lowest first layer 22z does not directly abut the conductor material 17 of the conductor layer 16, for example, where the lowest second layer 20z is vertically between the conductor material 17 of the conductor layer 16 and the lowest first layer 22z. Alternatively, the lowest first layer can directly abut the conductor material of the conductor layer (not shown). In one embodiment, the lowest second layer 20z directly abuts the top 19 of the conductor material 17 of the conductor layer 16. In one embodiment, the lowest second layer 20z is thinner than the second layer 20* above it. In one embodiment, the second layer 20x (i.e., the next higher second layer 20x) immediately above the lowest first layer 22z is thicker than the second layer 20* above it.

[0019] The second layer material of the second layer 20x immediately above the lowest first layer 22z (i.e., no other second layer is vertically located between the lowest first layer 22z and the second layer 20x immediately above it) includes an upper first insulating material 21 and a lower second material 23 below the upper first insulating material 21, wherein the composition of the lower second material 23 is different from the composition of the upper first insulating material 21. In one such embodiment, the lower second material 23 is thinner than the upper first insulating material 21. In any case, the upper first insulating material 21 may have the same composition as the material 24. In some embodiments, the second layer material of the second layer 20x immediately above the lowest first layer 22z may be considered to include an upper insulating material 21, a lower material 27, and an intermediate material 23 vertically located between the upper insulating material 21 and the lower material 27, wherein the composition of the intermediate material 23 is different from the composition of the lower material 27 and the composition of the upper insulating material 21 (in some embodiments, the lower material 27 is optional). In some such embodiments, upper insulating material 21 and lower material 27 have the same thickness as each other. Regardless, in some embodiments, upper insulating material 21 and lower material 27 have the same composition as each other (e.g., the same composition as material 24), and in other embodiments, have different compositions from each other. In some embodiments, lower second material 23 / intermediate material 23 includes at least one of conductively doped polysilicon, non-conductively doped polysilicon, carbon-doped polysilicon, silicon nitride, undoped silicon nitride, carbon-doped silicon nitride, and a metal material.

[0020] A channel opening 25 is formed (e.g., by etching) through the insulating layer 20* and the conductive layer 22* to the conductor layer 16. The channel opening 25 may taper radially inward as one moves deeper in the stack 18 (not shown). In some embodiments, the channel opening 25 may enter the conductor material 17 of the conductor layer 16 as shown, or may stop at the top (not shown). Alternatively, as an example, the channel opening 25 may stop at the top or inside the lowest insulating layer 20. The reason for extending the channel opening 25 at least into the conductor material 17 of the conductor layer 16 is to provide an anchoring effect to the material within the channel opening 25. An etch stop material (not shown) may be within or atop the conductor material 17 of the conductor layer 16 to help stop etching of the channel opening 25 relative to the conductor layer 16 when desired. Such an etch stop material may be sacrificial or non-sacrificial.

[0021] Horizontally elongated trenches 40 are formed (e.g., by anisotropic etching) into stack 18 to form laterally spaced memory block regions 58. Trenches 40 may have respective bottoms directly against (on top of or within) conductor material 17 of conductor layer 16 (as shown), or may have respective bottoms vertically coincident with or below the bottom of conductor layer 16 or conductor material 17 (not shown). By way of example and for simplicity only, channel openings 25 are shown arranged in groups or columns of staggered rows of four and five channel openings 25 per row, and arranged in laterally spaced memory block regions 58 that will comprise laterally spaced memory blocks 58 in a finished circuit system configuration. Herein, "block" generally includes "sub-blocks". Memory block regions 58 and resulting memory blocks 58 (not yet shown) may be considered to be longitudinally elongated and, for example, oriented along direction 55, and to have sides 62. Any alternative existing or future established arrangements and configurations may be used.

[0022] The transistor channel material may be formed vertically in individual channel openings along the insulating layer and the conductive layer, thereby including individual channel material strings that are directly electrically coupled to the conductive material in the conductor layer. Individual memory cells of the formed example memory array may include a gate region (e.g., a control gate region) and a memory structure that is laterally between the gate region and the channel material. In one such embodiment, the memory structure is formed to include a charge blocking region, a storage material (e.g., a charge storage material), and an insulating charge transfer material. The storage material (e.g., a floating gate material, such as doped or undoped silicon, or a charge trapping material, such as silicon nitride, metal dots, etc.) of the individual memory cell is vertically along the individual charge blocking region. The insulating charge transfer material (e.g., a bandgap engineered structure having a nitrogen-containing material [e.g., silicon nitride] sandwiched between two insulator oxides [e.g., silicon dioxide]) is laterally between the channel material and the storage material.

[0023] Figure 1-4An embodiment is shown in which charge blocking material 30, storage material 32, and charge transfer material 34 have been formed vertically along insulating layer 20* and conductive layer 22* in individual channel openings 25. Transistor materials 30, 32, and 34 (e.g., memory cell materials) may be formed, for example, by depositing respective thin layers thereof over stack 18 and within individual openings 25 and subsequently planarizing such transistor materials back to at least the top surface of stack 18.

[0024] Channel material 36 is also formed vertically along insulating layer 20* and conductive layer 22* in channel opening 25, thereby including individual operational channel material strings 53 in channel opening 25. Channel material 36 can be considered to have a lowest surface 71. In one embodiment, there are memory cell materials (e.g., 30, 32, and 34) along the string of channel materials 53, and the second layer of material (e.g., 24) is horizontally between the immediately adjacent strings of channel materials 53. Due to the proportions, materials 30, 32, 34, and 36 are located in the same direction as the material 30. Figure 1 and 2 37. Example channel material 36 includes appropriately doped crystalline semiconductor materials, such as one or more of silicon, germanium, and so-called III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). An example thickness of each of materials 30, 32, 34, and 36 is 25 to 100 angstroms. A stamp etch may be performed to remove materials 30, 32, and 34 from a base (not shown) of channel opening 25 to expose conductor layer 16 so that channel material 36 is directly against conductor material 17 of conductor layer 16. Such a stamp etch may occur individually with respect to each of materials 30, 32, and 34 (as shown), or may occur only with respect to some of the materials (not shown). Alternatively and by way of example only, a stamp etch may not be performed, and channel material 36 may be directly electrically coupled to conductor material 17 of conductor layer 16 only through a separate conductive interconnect (not shown). Channel opening 25 is shown to include a radially central solid dielectric material 38 (eg, spin-on dielectric, silicon dioxide, and / or silicon nitride). Alternatively and by way of example only, the radially central portion within channel opening 25 may include void space (not shown) and / or be free of solid material (not shown).

[0025] In one embodiment, as shown, sacrificial material 60 is laterally located between channel material 36 of channel material string 53 and lower second material 23 in second layer 20x immediately above lowermost first layer 22z. Sacrificial material 60 has a composition different from that of lower second material 23. In one such embodiment, sacrificial material 60 and upper first insulating material 21 have the same composition as one another. Further, in one such embodiment, as shown, sacrificial material 60 has been formed longitudinally along lower second material 23 of second layer 20x immediately above lowermost first layer 22z and longitudinally along opposite sides 62 of individual memory block regions 58. Regardless, sacrificial material is also located in lowermost first layer 22z laterally outward from channel material 36 of channel material string 53. For example, and by way of example only, one or more of materials 30, 32, and 34 in lowermost first layer 22z may have the same composition as sacrificial material 60 in second layer 20x, and if so, sacrificial material is also located in lowermost first layer 22z accordingly.

[0026] The depicted sacrificial material 60 may be formed by any present or future established method. As an example, where the lower second material 23 may be susceptible to oxidation, the sacrificial material 60 may be formed as an oxide by oxidizing the lower second material 23 after or after exposure when forming the channel opening 25, adjacent to the lower second material 23 being the channel material string 53. If at least the uppermost portion of the conductor material 17 of the conductor layer 16 is oxidizable, then the exposed portion thereof may be oxidized at the bottom of the channel opening 25 (not shown). Similarly, the sacrificial material 60 may be formed as an oxide on the opposite side 62 of the memory block region 58 by oxidizing the lower second material 23 after or after forming the trench 40 (just as some of the conductor material 17 (if oxidizable) may be oxidized, and not shown). As another example, the lower second material 23 can be laterally recessed relative to the channel opening 25 and the sidewalls of the trench 40 (e.g., by selectively isotropically etching the lower second material relative to other exposed materials) and then filling the lateral recess with the sacrificial material 60 (e.g., by selectively depositing it therein or by non-selective conformal deposition and then removing the sacrificial material from the opening 25 / trench 40 outside of the lateral recess).

[0027] refer to Figure 5 and 6 , first layer material 26 (not shown) is selectively isotropically etched relative to second layer material 24 (and in one embodiment, as shown, selectively relative to materials 17, 21, 27, and 60) to form void spaces 35 in first layer 22* (e.g., using a liquid or vapor H 3 PO 4 as the primary etchant, where material 26 is silicon nitride and the other materials exposed include one or more oxides or polysilicon).

[0028] refer to Figure 7 and 8 , conductive material 48 is deposited into trench 40 and into void space 35 in first layer 22*. Conductive material 48 fills void space 35 in first layer 22* above lowest first layer 22z, and does not completely fill void space 35 in lowest first layer 22z.

[0029] refer to Figure 9-11 , conductive material 48 is etched (e.g., isotropically) from the lowest first layer 22z. This may be performed selectively relative to at least the uppermost portion of conductor material 17 of conductor layer 16 and relative to materials 21, 27, and 60, as shown. In addition, such etching may remove all remaining conductive material 48 that has been located in trench 40 by previous processing (as shown). In addition, some lateral recessing of material 48 may be performed relative to the sidewalls of trench 40 defined by material 24 (not shown). In one embodiment in which lower material 27 is present, as shown, etching of conductive material 48 from the lowest first layer 22z is performed selectively relative to lower material 27 in the next higher second layer 20x to leave lower material 27 under intermediate material 23 in the next higher second layer 20x. Practitioners are able to select a suitable isotropic etching chemistry to selectively etch conductive material 48 relative to material 24. As an example, W conductive material 48 may be selectively etched relative to SiO using a mixture of ammonia and hydrogen peroxide or a mixture of sulfuric acid and hydrogen peroxide. 2 Materials 24 and 60 are etched isotropically.

[0030] In one embodiment, the sidewalls of the channel material of the string of channel materials in the lowest first layer and the second layer immediately above the lowest first layer are exposed. In one such embodiment, this is performed by etching the sacrificial material in the lowest first layer and etching the sacrificial material in the second layer immediately above the lowest first layer to form a cavity laterally between the channel material of the string of channel materials and the lower second material in the second layer immediately above the lowest first layer. Fig.12 and 13An example such subsequent processing is shown, where in one embodiment, material 30 (e.g., silicon dioxide), material 32 (e.g., silicon nitride), and material 34 (e.g., silicon dioxide or a combination of silicon dioxide and silicon nitride) are etched in each of layers 20z and 20x to expose sidewalls 41 of channel material 36 of channel material string 53 in each of layers 20z and 20x. Any of materials 30, 32, and 34 in layer 20z may be considered a sacrificial material therein. In addition, sacrificial material 60 (not shown) in second layer 20x is etched to form a cavity 75 laterally between channel material 36 of channel material string 53 and lower second material 23 in second layer 20x. In one embodiment, as shown, cavity 75 is formed to extend upward into upper first insulating material 21 above lower second material 23.

[0031] As an example, consider an embodiment in which material 23 is polysilicon, materials 21, 24, and 60 are silicon dioxide, and memory cell materials 30, 32, and 34 are each one or more of a silicon dioxide and silicon nitride layer. In such an example, the depicted construction can be produced by using modified or different chemistries to selectively etch silicon dioxide and silicon nitride sequentially relative to each other. As an example, a 100:1 (by volume) solution of water to HF will selectively etch silicon dioxide relative to silicon nitride, while a 1000:1 (by volume) solution of water to HF will selectively etch silicon nitride relative to silicon dioxide. Thus, in such an example, such etching chemistries can be used in an alternating manner, with the intent to achieve the desired etching behavior resulting from the use of modified or different chemistries to selectively etch silicon dioxide and silicon nitride sequentially relative to each other. Fig.12 and 13 The example configuration shown. Practitioners can select other chemistries to etch other different materials where desired. Fig.12 and 13 The construction shown in .

[0032] refer to Fig.14 and 15, and in one embodiment, the conductive / conductive material 42 has been deposited into the void spaces 35 of the lowest first layer 22z and into the cavities 75 in the next higher second layer 20x, directly against the exposed sidewalls 41 of the channel material 36 of the channel material strings 53 in the lowest first layer 22z and the next higher second layer 20x and directly against the uppermost surface 43 of the conductor material 17 of the conductor layer 16. For example, if none of the conductor material 17 is subsequently etched, the uppermost surface 43 may be the same as the top 19. This is merely an example whereby the conductive material 42 is deposited to electrically couple the channel material 36 of the individual channel material strings 53 and the conductor material 17 of the conductor layer 16 directly together (e.g., through the channel material sidewalls 41). In one embodiment, at least the uppermost portion of the conductor material 17 of the conductor layer 16 has the same composition as the conductive material 42 composition (e.g., both are conductively doped polysilicon). Alternatively, conductive material 42 has a composition that is different from the composition of at least the uppermost portion of conductor material 17 of conductor layer 16 .

[0033] refer to Fig.16 and 17 In one embodiment, the conductive material 48 includes a metal (i.e., at least one of a metal in elemental form or a metal in alloy form) along the sides 62 of the memory block regions 58 (i.e., at least along the sides 62). Silicon (e.g., conductively doped or non-conductively doped polysilicon) is formed between the memory block regions 58 over the metal of the first / conductive layer 22. As but only as one example, as shown, such silicon may be conductively doped polysilicon of the conductive material 42. Regardless, in one embodiment, such silicon and metal react to form therefrom a metal silicide 65 directly against and longitudinally along the metal of the respective first / conductive layer 22. In one such embodiment, such reaction includes heating to cause such reaction (e.g., a self-aligned silicide reaction). In one such embodiment, the conductive material 42 includes a conductively doped semiconductive material (e.g., conductively doped polysilicon) against (in one embodiment, directly against) the sidewalls 41 of the channel material 36 of the channel material strings 53. In such embodiments, such heating diffuses conductivity increasing dopants (e.g., n-type and / or p-type) in the conductively-doped semiconductive material into the channel material 36 of the channel material string 53, wherein such heating activates such conductivity increasing dopants in the conductively-doped semiconductive material and in the channel material 36 of the channel material string 53.

[0034] In one embodiment, the metal silicide 65 in the first / conductive layer 22 extends upward into the next higher insulating layer 20 laterally between the memory block regions 58. In one embodiment, the metal silicide 65 in the first / conductive layer 22 extends downward into the next lower insulating layer 20 laterally between the memory block regions 58. In one embodiment, as shown, the metal of the first / conductive layer 22 extends laterally in a direction 70 away from the channel material strings 53 into the space (e.g., trench 40) laterally between the memory block regions 58, wherein the reaction forms the metal silicide 65 into a vertical cross-section (e.g., Fig.17 has a C-shape in a cross-section (e.g., facing left or right).

[0035] refer to Fig.18 and 19 , conductive material 42 (unreacted silicon) has been removed from trench 40, for example, by a timed isotropic etch that may be selective relative to materials 21, 23, 24, 48, and 17. This may cause conductive material 42 to be laterally recessed in direction 39 toward string of channel material 53, as shown. This may cause conductor material 17 to undergo some etching when exposed (not shown). An example etching chemistry where material 42 is conductively doped polysilicon, materials 21 and 24 are silicon dioxide, material 23 is silicon nitride, and material 48 is W is tetramethylammonium hydroxide. If material 23 has the same composition as conductive material 24, material 23 may also be laterally etched thereby (not shown).

[0036] refer to Figure 20-26 , intervening material 57 is formed to be laterally between and longitudinally along laterally adjacent memory blocks 58. Intervening material 57 can provide lateral electrical isolation (insulation) between laterally adjacent memory blocks. This can include one or more of insulating, semiconducting, and conductive materials, and in any case can facilitate shorting of conductive layers 22* to each other in the finished circuit system construction. An example insulating material is SiO 2 、Si 3 N 4 、Al 2 O 3and undoped polysilicon. Intermediate material 57 may include through array vias (TAVs) and are not shown. By way of example only, intermediary material 57 is shown as a composite including insulating material 67 (e.g., silicon nitride), insulating material 68 (e.g., silicon dioxide), and insulating material 69 (e.g., undoped polysilicon). In one embodiment, as shown, intermediary material 57 includes insulating material (e.g., 67) directly against conductor material 17 of conductor layer 16, and in one embodiment, the insulating material (e.g., 67) of intermediary material 57 extends laterally in direction 39 toward channel material string 53 to be directly below what is now the lowest second layer 20x, which will eventually become the finished circuit system structure. Additionally and regardless, in one embodiment, as shown, in the finished circuit system structure, conductive material 48 of first layer 22* above lowest first layer 22z extends laterally into insulating material (e.g., 67) of intermediary material 57 in direction 70 away from channel material string 53.

[0037] In one embodiment, as shown, the lowest surface 71 ( Fig. 22 and 25 ) never directly abuts against any of the conductor materials 17 in the conductor layer 16 .

[0038] Conductive material 48 forms vertically extending strings 49 of individual conductive lines 29 (eg, word lines) and individual transistors and / or memory cells 56. The transistors and / or memory cells 56 are generally located at Fig.26 Indicated by brackets, and some Fig.21 , 23 , 24 and 25 are indicated by dashed outlines, where the transistors and / or memory cells 56 are substantially annular or ring-shaped in the depicted example. Alternatively, the transistors and / or memory cells 56 may not completely surround the individual channel openings 25, so that each channel opening 25 may have two or more vertically extending strings 49 (e.g., multiple transistors and / or memory cells surround the individual channel openings in individual conductive layers, where there may be multiple word lines per channel opening in the individual conductive layers and are not shown). The conductive material 48 can be viewed as having ends 50 ( Fig.26 ). In the depicted embodiment, control gate region 52 includes individual portions of individual conductive lines 29. Materials 30, 32, and 34 may be viewed as a memory structure 65 laterally located between control gate region 52 and channel material 36. In one embodiment, as shown with respect to the example "gate last" processing, conductive material 48 of conductive layer 22 is formed after forming channel opening 25 and / or trench 40. As mentioned above, the lowest first layer 22z may be a select gate layer (e.g., without any operational memory cells formed therein).

[0039] The charge blocking region (e.g., charge blocking material 30) is between the storage material 32 and the individual control gate regions 52. The charge blocking member may have the following functions in the memory cell: in the programming mode, the charge blocking member may prevent charge carriers from leaving the storage material (e.g., floating gate material, charge trapping material, etc.) toward the control gate, and in the erase mode, the charge blocking member may prevent charge carriers from flowing from the control gate into the charge storage material. Thus, the charge blocking member may be used to block charge migration between the control gate region and the storage material of each memory cell. The example charge blocking region as shown includes an insulator material 30. By way of further example, the charge blocking region may include a lateral (e.g., radially) outer portion of the storage material (e.g., material 32) where such storage material is insulating (e.g., in the absence of any different composition material between the insulating storage material 32 and the conductive material 48). Regardless, as an additional example, the intersection of the storage material and the conductive material of the control gate may be sufficient to act as a charge blocking region in the absence of any separate composition insulator material 30. Furthermore, the intersection of conductive material 48 and material 30 (if present) in conjunction with insulator material 30 may together act as a charge blocking region and alternatively or additionally may act as a lateral outer region of insulating storage material such as silicon nitride material 32. Example material 30 is one or more of hafnium silicon oxide and silicon dioxide.

[0040] Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used in the embodiments shown and described with reference to the above embodiments.

[0041] In some embodiments, a method for forming a memory array (e.g., 12) including strings (e.g., 49) of memory cells (e.g., 56) includes forming laterally spaced memory blocks (e.g., 58) each including a vertical stack (e.g., 18) comprising alternating insulating layers (e.g., 20) and conductive layers (e.g., 22). The string of channel materials (e.g., 53) of the memory cells extends through the insulating layers and the conductive layers. The conductive layers include metal (i.e., at least one of the metal in elemental form or the metal in alloy form) along the sides (e.g., 62) of the memory blocks. Silicon (e.g., 42) is formed between the memory blocks over the metal of the conductive layers. The silicon and the metal react to form metal silicides (e.g., 65) therefrom directly against and longitudinally along the metal of the individual ones of the conductive layers. After such reaction, silicon that has not yet reacted (i.e., unreacted silicon) is removed from between the memory blocks, and intervening materials (e.g., 57) are formed between and longitudinally along the memory blocks.

[0042] In one embodiment, a conductor layer (e.g., 16) comprising a conductor material (e.g., 17) is beneath the memory blocks, wherein the intervening material comprises an insulating material (e.g., 67) directly against the conductor material of the conductor layer. In one embodiment, the strings of channel material are formed prior to forming the laterally spaced memory blocks.

[0043] Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0044] Alternative embodiment configurations may result from the method embodiments described above or in other ways. Regardless, embodiments of the present invention encompass memory arrays that are independent of the method of manufacture. However, such memory arrays may have any of the properties described herein in the method embodiments. Likewise, the method embodiments described above may incorporate, form, and / or have any of the properties described with respect to the device embodiments.

[0045] In one embodiment, a memory array (e.g., 12) including strings (e.g., 49) of memory cells (e.g., 56) includes laterally spaced memory blocks (e.g., 58) each including a vertical stack (e.g., 18) comprising alternating insulating layers (e.g., 20) and conductive layers (e.g., 22). The string of channel materials (e.g., 53) of the memory cells extends through the insulating layers and the conductive layers. The conductive layers include a metal (i.e., at least one of a metal in elemental form or a metal in alloy form). Metal silicides (e.g., 65) are directly against and longitudinally along the metal of individual ones of the conductive layers and longitudinally along opposite sides (e.g., 62) of individual ones of the memory blocks. Intermediate materials (e.g., 57) are laterally between and longitudinally along laterally adjacent memory blocks. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0046] The above-described processing or construction may be considered relative to an array of components that are formed as a single stack or a single stack of such components or within a single stack or a single stack, the stack or stack being above or as part of the underlying base substrate (but a single stack / stack may have multiple layers). Control and / or other peripheral circuits for operating or accessing such components within the array may also be formed anywhere as part of the finished construction, and in some embodiments may be below the array (e.g., CMOS below the array). In any case, one or more additional such stacks / stacks may be provided or manufactured above and / or below the stacks / stacks shown on the way or described above. In addition, the arrays of components may be the same or different in different stacks / stacks relative to each other, and different stacks / stacks may have the same thickness or different thickness relative to each other. Intervening structures may be provided between stacks / stacks that are adjacent vertically (e.g., additional circuits and / or dielectric layers). Furthermore, different stacks / stacks may be electrically coupled relative to each other. Multiple stacks / stacks may be manufactured individually and sequentially (e.g., one on top of another), or two or more stacks / stacks may be manufactured substantially simultaneously.

[0047] The assemblies and structures discussed above can be used in integrated circuits / circuitry systems and can be incorporated into electronic systems. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multi-layer, multi-chip modules. The electronic system can be any of a wide range of systems, such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lamps, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0048] In this document, unless otherwise indicated, "vertical", "higher", "upper", "lower", "top", "top", "bottom", "above", "below", "below", "under", "upward", and "downward" generally refer to the vertical direction. "Horizontal" refers to the general direction along the surface of the main substrate (i.e., within 10 degrees) and can be relative to the direction in which the substrate is processed during manufacturing, and vertical is a direction generally orthogonal thereto. Reference to "just horizontal" is to the direction along the surface of the main substrate (i.e., without a degree of deviation therefrom) and can be relative to the direction in which the substrate is processed during manufacturing. In addition, "vertical" and "horizontal" as used herein are generally perpendicular directions relative to each other and have nothing to do with the orientation of the substrate in three-dimensional space. In addition, "vertically extending" and "vertically extending" refer to a direction inclined at least 45° from just horizontal. In addition, "vertically extending", "vertically extending", "horizontally extending", "horizontally extending" and similar terms relative to a field effect transistor are reference to the orientation of the channel length of the transistor, and in operation the current flows between the source / drain regions along the orientation. For bipolar junction transistors, "vertically extending", "vertically extending", "horizontally extending", "horizontally extending", etc. refer to the orientation of the substrate length along which current flows between the emitter and the collector in operation. In some embodiments, any component, feature and / or region extending vertically extends vertically or within 10° of vertical.

[0049] Furthermore, "directly above," "directly below," and "directly below" require at least some lateral overlap (i.e., horizontally) of the two stated regions / materials / components relative to each other. And, the use of "above" without a preceding "directly" requires only that some portion of the stated region / material / component that is above another stated region / material / component is vertically outside of the other stated region / material / component (i.e., regardless of whether there is any lateral overlap of the two stated regions / materials / components). Similarly, the use of "below" and "beneath" without a preceding "directly" requires only that some portion of the discussed region / material / component that is below / below another discussed region / material / component is vertically inside of the other discussed region / material / component (i.e., regardless of whether there is any lateral overlap of the two discussed regions / materials / components).

[0050] Any of the materials, regions, and structures described herein may be uniform or non-uniform, and in any case may be continuous or discontinuous over any material overlying it. When one or more example compositions are provided for any material, the material may comprise, consist essentially of, or consist of the one or more compositions. Furthermore, unless otherwise indicated, each material may be formed using any suitable existing or future developed technology, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0051] In addition, "thickness" (without a directional adjective in front) used alone is defined as the average straight-line distance perpendicularly passing through a given material or region from the closest surface of an adjacent material or adjacent region with different compositions. In addition, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If there is a variable thickness, unless otherwise indicated, the thickness refers to the average thickness, and such materials or regions will have a certain minimum thickness and a certain maximum thickness due to the variable thickness. As used herein, "different compositions" only require that those parts of the two discussed materials or regions that can directly abut against each other are chemically and / or physically different, such as in the case of the material or region being non-homogeneous. If the two stated materials or regions are not directly against each other, then in the case of such materials or regions being non-uniform, "different compositions" only require that those parts of the two stated materials or regions that are closest to each other are chemically and / or physically different. Herein, when the stated materials, regions or structures are in at least some physical contact relative to each other, the material, region or structure "directly abuts" another material, region or structure. In contrast, "over," "on," "adjacent," "along," and "against" without being preceded by "directly" encompasses "directly against" as well as configurations in which intervening materials, regions, or structures result in no physical touching contact of the stated materials, regions, or structures relative to each other.

[0052] As used herein, region-material-components are "electrically coupled" relative to one another if, in normal operation, electrical current is able to flow continuously from one region-material-component to another region-material-component, and the flow occurs primarily through the movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated. Another electronic component may be between the region-material-components and electrically coupled to the region-material-components. In contrast, when region-material-components are referred to as "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region-material-components.

[0053] Any use of "rows" and "columns" herein is for convenience in distinguishing one series or orientation of features from another series or orientation of features, and components have been or may be formed along such "rows" and "columns". "Rows" and "columns" are used synonymously with respect to any series of regions, components and / or features, regardless of function. Regardless, rows may be straight and / or curved and / or parallel and / or non-parallel relative to each other, as may columns. Furthermore, rows and columns may intersect at 90° relative to each other, or at one or more other angles (i.e., other than straight angles).

[0054] The components of any of the conductive / conductor / conductive materials herein may be metallic materials and / or conductively doped semiconductive / semiconductive / semiconductive materials. "Metallic material" is any or a combination of elemental metals, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compounds.

[0055] As used herein, "selectivity" with respect to etching / etching, removing / removal, deposition, and / or forming / formation is such that a stated material is acted upon relative to another stated material at a ratio of at least 2: 1 by volume. Additionally, any use of selectively depositing, selectively growing, or selectively forming is a deposition, growth, or formation where one material is deposited, grown, or formed relative to another stated material or materials at a ratio of at least 2: 1 by volume for at least the first 75 angstroms.

[0056] Unless otherwise indicated, the use of "or" herein includes either or both.

[0057] in conclusion

[0058] In some embodiments, a method for forming a memory array including a string of memory cells includes forming laterally spaced memory blocks each including a vertical stack, the vertical stack including alternating insulating layers and conductive layers. The channel material strings of the memory cells extend through the insulating layers and the conductive layers. The conductive layers include metal along the sides of the memory blocks. Silicon is formed between the memory blocks above the metal of the conductive layers. The silicon and the metal react to form a metal silicide therefrom directly against and longitudinally along the metal of individual ones of the conductive layers. After the reaction, unreacted portions of the silicon are removed from between the memory blocks, and an intervening material is formed between and longitudinally along the memory blocks.

[0059] In some embodiments, a method for forming a memory array including a string of memory cells includes forming a conductor layer including a conductor material on a substrate. A stack including vertically alternating first and second layers is formed above the conductor layer. The stack includes laterally spaced memory blocks with horizontally elongated trenches therebetween. A string of channel material extends through the first layer and the second layer. The material of the first layer has a composition different from that of the second layer. The lowest of the first layers is thicker than the first layer above it. The second layer material of the second layer immediately above the lowest first layer includes an upper first insulating material and a lower second material below the upper first insulating material. The lower second material has a composition different from that of the upper first insulating material. A sacrificial material is laterally between the channel material of the string of channel material and the lower second material in the second layer immediately above the lowest first layer. The sacrificial material is located in the lowest first layer laterally outward from the channel material of the string of channel material. The sacrificial material has a composition different from that of the lower second material. The first layer material is selectively isotropically etched relative to the second layer material to form a void space in the first layer. Conductive material is deposited into the trench and into the void space in the first layer. The conductive material fills the void space in the first layer above the lowest first layer. The conductive material does not completely fill the void space in the lowest first layer. The conductive material is etched from the lowest first layer. The sidewalls of the channel material of the string of channel materials are exposed in the lowest first layer and in the second layer immediately above the lowest first layer. The exposing includes etching the sacrificial material in the lowest first layer. The sacrificial material in the second layer immediately above the lowest first layer is etched to form a cavity laterally between the channel material of the string of channel materials and the lower second material in the second layer immediately above the lowest first layer. Conductive material is deposited into the void space of the lowest first layer and into the cavity in the second layer immediately above the lowest first layer, directly against the exposed sidewalls of the channel material of the string of channel materials in the lowest first layer and the second layer immediately above the lowest first layer and directly against the uppermost surface of the conductor material of the conductor layer.

[0060] In some embodiments, a memory array including strings of memory cells includes laterally spaced memory blocks each including a vertical stack including alternating insulating layers and conductive layers. A string of channel material of a memory cell extends through the insulating layers and the conductive layers. The conductive layers include metal. Metal silicide is directly against and longitudinally along the metal of individual ones of the conductive layers and longitudinally along opposite sides of individual ones of the memory blocks. Intermediate material is laterally between and longitudinally along the laterally adjacent memory blocks.

[0061] As specified, the subject matter disclosed herein has been described in language that is more or less specific with respect to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include example embodiments. Therefore, the claims have the full scope as written and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. A method for forming a memory array including a string of memory cells, comprising: forming laterally spaced apart memory blocks each comprising a vertical stack including alternating insulating layers and conductive layers through which strings of channel material of memory cells extend, the conductive layers comprising metal along sides of the memory blocks; forming silicon below an uppermost portion of the insulating layer and laterally between the memory blocks on the metal of the conductive layer therebelow; reacting the silicon and the metal to form therefrom metal silicides of the metal directly against and longitudinally along individual ones of the conductive layers beneath the uppermost insulating layer; as well as After the reaction, unreacted portions of the silicon are removed from between the memory blocks, and intervening material is formed between and longitudinally along the memory blocks.

2. The method of claim 1, wherein the reacting comprises heating to cause the reacting; and the method further comprises: forming a conductively doped semiconductive material against sidewalls of the channel material of the string of channel material; and The heating diffuses the conductivity-increasing dopant in the conductive-doped semiconductive material into the channel material of the string of channel materials, and the heating activates the conductivity-increasing dopant in the conductive-doped semiconductive material and in the channel material of the string of channel materials.

3. The method of claim 1, comprising a conductor layer beneath the memory block, the conductor layer comprising a conductor material, the intervening material comprising an insulating material directly against the conductor material of the conductor layer.

4. The method of claim 1 including forming the strings of channel material prior to forming the laterally spaced apart memory blocks.

5. A method for forming a memory array including a string of memory cells, comprising: forming laterally spaced apart memory blocks each comprising a vertical stack including alternating insulating layers and conductive layers through which strings of channel material of memory cells extend, the conductive layers comprising metal along sides of the memory blocks; forming silicon over the metal of the conductive layer and between the memory blocks; reacting the silicon and the metal to form therefrom a metal silicide of the metal directly against and longitudinally along individual ones of the conductive layers; as well as After the reaction, removing unreacted silicon from between the memory blocks and forming intervening material between and longitudinally along the memory blocks; and The metal silicide in the conductive layer protrudes upward into the next higher insulating layer laterally between the memory blocks.

6. A method for forming a memory array including a string of memory cells, comprising: forming laterally spaced apart memory blocks each comprising a vertical stack including alternating insulating layers and conductive layers through which strings of channel material of memory cells extend, the conductive layers comprising metal along sides of the memory blocks; forming silicon over the metal of the conductive layer and between the memory blocks; reacting the silicon and the metal to form therefrom a metal silicide of the metal directly against and longitudinally along individual ones of the conductive layers; as well as After the reaction, removing unreacted silicon from between the memory blocks and forming intervening material between and longitudinally along the memory blocks; and The metal silicide in the conductive layer extends downwardly into an immediately lower insulating layer laterally between the memory blocks.

7. The method according to claim 6, wherein: The metal silicide in the conductive layer protrudes upward into the next higher insulating layer laterally between the memory blocks.

8. A method for forming a memory array comprising a string of memory cells, comprising: forming laterally spaced apart memory blocks each comprising a vertical stack including alternating insulating layers and conductive layers through which strings of channel material of memory cells extend, the conductive layers comprising metal along sides of the memory blocks; forming silicon over the metal of the conductive layer and between the memory blocks; reacting the silicon and the metal to form therefrom a metal silicide of the metal directly against and longitudinally along individual ones of the conductive layers; as well as After the reaction, removing unreacted silicon from between the memory blocks and forming intervening material between and longitudinally along the memory blocks; and The metal of the conductive layer laterally protrudes in a direction away from the channel material string into a space laterally between the memory blocks, and the reaction forms the metal silicide to have a C-like shape in a vertical cross section.

9. A method for forming a memory array comprising a string of memory cells, comprising: forming a conductor layer including a conductor material on a substrate; forming a stack comprising vertically alternating first and second layers over the conductor layer, the stack comprising laterally spaced apart memory blocks with horizontally elongated trenches therebetween, a string of channel material extending through the first and second layers, the material of the first layers having a composition different from that of the second layers, the lowest of the first layers being thicker than the first layer above it, the second layer of material of the second layer immediately above the lowest first layer comprising an upper first insulating material and a lower second material below the upper first insulating material, the lower second material having a composition different from that of the upper first insulating material, a sacrificial material laterally between the channel material of the string of channel material and the lower second material in the second layer immediately above the lowest first layer, the sacrificial material being located in the lowest first layer laterally outward from the channel material of the string of channel material, the sacrificial material having a composition different from that of the lower second material; selectively isotropically etching the first layer of material relative to the second layer of material to form void spaces in the first layer; depositing a conductive material into the trench and into the void space in the first layer, the conductive material filling the void space in the first layer above the lowest first layer, the conductive material not completely filling the void space in the lowest first layer; etching said conductive material from said lowermost first layer; exposing sidewalls of the string of channel materials in the lowermost first layer and the second layer immediately above the lowermost first layer, the exposing comprising: etching the sacrificial material in the lowermost first layer; and etching the sacrificial material in the second layer immediately above the lowest first layer to form a cavity laterally between the channel material of the string of channel materials and the lower second material in the second layer immediately above the lowest first layer; and Conductive material is deposited into the void space of the lowest first layer and into the cavity in the second layer immediately above the lowest first layer, directly against the exposed sidewalls of the channel material of the string of channel materials in the lowest first layer and the second layer immediately above the lowest first layer and directly against the uppermost surface of the conductor material of the conductor layer.

10. The method of claim 9, comprising forming the cavity to extend upwardly into the upper first insulating material above the lower second material. 11 . The method of claim 9 , wherein the sacrificial material and the upper first insulating material have the same composition as each other.

12. The method of claim 11, comprising forming the cavity to extend upwardly into the upper first insulating material above the lower second material.

13. The method of claim 9, comprising forming the sacrificial material longitudinally along the lower second material of the second layer immediately above the lowermost first layer and longitudinally along opposite sides of individual ones of the memory block regions.

14. The method of claim 9, wherein the conductive material comprises metal along sides of the memory block region; and The method further comprises: forming silicon over the metal of the first layer and between the memory block regions; reacting the silicon and the metal to form therefrom a metal silicide directly against and longitudinally along the metal of individual ones of the first layer; as well as After the reaction, unreacted silicon is removed from between the memory block regions, and an intervening material is formed between and longitudinally along the memory block regions.

15. The method of claim 14, wherein the reacting comprises heating to cause the reacting; and the method further comprises: forming a conductively doped semiconductive material against sidewalls of the channel material of the string of channel material; and The heating diffuses the conductivity-increasing dopant in the conductive-doped semiconductive material into the channel material of the string of channel materials, and the heating activates the conductivity-increasing dopant in the conductive-doped semiconductive material and in the channel material of the string of channel materials.

16. The method of claim 9, wherein the lowermost first layer does not directly abut the conductor material of the conductor layer during the isotropic etching.

17. The method of claim 16, wherein a lowermost of the second layers is vertically located between the conductor material of the conductor layer and the lowermost first layer during the isotropic etching.

18. The method of claim 17, wherein the lowermost second layer is thinner than the second layer thereover during the isotropic etching.

19. The method of claim 18, wherein the second layer immediately above the lowermost first layer is thicker than the second layer thereabove during the isotropic etching.

20. The method of claim 9, wherein a lowermost surface of the channel material of the string of channel materials never directly abuts any of the conductor materials in the conductor layer.

21. The method of claim 9, wherein the lower second material comprises at least one of: conductively doped polysilicon, conductively non-doped polysilicon, carbon-doped polysilicon, silicon nitride, undoped silicon nitride, carbon-doped silicon nitride, and a metal material.

22. The method of claim 9, wherein the lower second material is thinner than the upper first insulating material.

23. A memory array comprising a string of memory cells, comprising: each comprising a vertical stack of laterally spaced-apart memory blocks, the vertical stack comprising alternating insulating layers and conductive layers through which strings of channel material of memory cells extend, the conductive layers comprising metal along sides of the memory blocks; metal silicide beneath an uppermost one of the insulating layers and directly against and longitudinally along the metal of individual ones of the conductive layers and longitudinally along opposing sides of individual ones of the memory blocks; as well as An intermediate material is laterally located between the laterally adjacent memory blocks and longitudinally along the laterally adjacent memory blocks.

24. A memory array comprising a string of memory cells, comprising: each comprising laterally spaced-apart memory blocks in a vertical stack, the vertical stack comprising alternating insulating and conductive layers through which strings of channel material of memory cells extend, the conductive layers comprising metal; metal silicide directly against and longitudinally along the metal of individual ones of the conductive layers and longitudinally along opposing sides of individual ones of the memory blocks; as well as an intervening material laterally between the laterally adjacent memory blocks and longitudinally along the laterally adjacent memory blocks; and The metal silicide in the conductive layer protrudes upward into the next higher insulating layer laterally between the memory blocks.

25. A memory array comprising a string of memory cells, comprising: each comprising laterally spaced-apart memory blocks in a vertical stack, the vertical stack comprising alternating insulating and conductive layers through which strings of channel material of memory cells extend, the conductive layers comprising metal; metal silicide directly against and longitudinally along the metal of individual ones of the conductive layers and longitudinally along opposing sides of individual ones of the memory blocks; as well as an intervening material laterally between the laterally adjacent memory blocks and longitudinally along the laterally adjacent memory blocks; and The metal silicide in the conductive layer extends downwardly into an immediately lower insulating layer laterally between the memory blocks.

26. The memory array of claim 25, wherein: The metal silicide in the conductive layer protrudes upward into the next higher insulating layer laterally between the memory blocks.

27. A memory array comprising a string of memory cells, comprising: each comprising laterally spaced-apart memory blocks in a vertical stack, the vertical stack comprising alternating insulating and conductive layers through which strings of channel material of memory cells extend, the conductive layers comprising metal; metal silicide directly against and longitudinally along the metal of individual ones of the conductive layers and longitudinally along opposing sides of individual ones of the memory blocks; as well as an intervening material laterally between the laterally adjacent memory blocks and longitudinally along the laterally adjacent memory blocks; and The metal of the conductive layer laterally protrudes in a direction away from the channel material string into a space laterally between the memory blocks, and the metal silicide has a C-like shape in a vertical cross section.

28. A memory array comprising a string of memory cells, comprising: each comprising laterally spaced-apart memory blocks in a vertical stack, the vertical stack comprising alternating insulating and conductive layers through which strings of channel material of memory cells extend, the conductive layers comprising metal; metal silicide directly against and longitudinally along the metal of individual ones of the conductive layers and longitudinally along opposing sides of individual ones of the memory blocks; an intervening material laterally disposed between the laterally adjacent memory blocks and longitudinally along the laterally adjacent memory blocks; as well as a conductor layer comprising a conductor material beneath the memory block; the conductive material of a lowermost of the conductive layer directly against the conductor material of the conductor layer and directly against the channel material of individual ones of the strings of channel material; and The insulating layer immediately above the lowest conductive layer includes an upper first insulating material and a lower second insulating material below the upper first insulating material, the lower second insulating material having a composition different from that of the upper first insulating material.

29. The memory array of claim 28 wherein the intervening material comprises an insulating material directly against the conductor material of the conductor layer.

30. The memory array of claim 28 wherein the upper first insulating material comprises silicon dioxide and the lower second insulating material comprises undoped polysilicon.

31. The memory array of claim 28 wherein the upper first insulating material comprises silicon dioxide and the lower second insulating material comprises silicon nitride.

32. The memory array of claim 28 wherein the lower second insulating material is thinner than the upper first insulating material.

33. The memory array of claim 28 wherein the conductive material is directly against sidewalls of the channel material of the individual ones of the strings of channel material.

34. A memory array comprising a string of memory cells, comprising: each comprising laterally spaced-apart memory blocks in a vertical stack, the vertical stack comprising alternating insulating and conductive layers through which strings of channel material of memory cells extend, the conductive layers comprising metal; metal silicide directly against and longitudinally along the metal of individual ones of the conductive layers and longitudinally along opposing sides of individual ones of the memory blocks; an intervening material laterally disposed between the laterally adjacent memory blocks and longitudinally along the laterally adjacent memory blocks; as well as a conductor layer comprising a conductor material under the memory block; and The conductive material of the lowermost of the conductive layers rests directly against the conductor material of the conductor layer and directly against the channel material of individual ones of the strings of channel material.

35. The memory array of claim 34 wherein the conductive material is directly against sidewalls of the channel material of the individual ones of the strings of channel material.

36. The memory array of claim 34 wherein the conductive material comprises conductively doped polysilicon and a metallic material.

37. The memory array of claim 34 wherein the lowermost of the conductive layers is thicker than the conductive layers above it.

38. The memory array of claim 34 wherein the intervening material comprises an insulating material directly against the conductor material of the conductor layer.

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