A Phase-Locked Loop Circuit Based on Double-Degree-of-Freedom PID Compensation

Abstract

The present invention discloses a phase-locked loop circuit based on double-degree-of-freedom PID compensation, which includes a Clarke transformation part, a Park transformation part, a moving average filter, a per-unit conversion part, a double-degree-of-freedom PID compensator, and a VCO link; the output of the Clarke transformation part is the input of the Park transformation part, and the q-axis component V output by the Park transformation part q is converted by the #imgabs0# per-unit conversion part into the input of the moving average filter; the double-degree-of-freedom PID compensator is divided into a PID1 compensator and a PID2 compensator; the output of the moving average filter is connected to the forward-channel PID1 compensator, and the output of the PID1 compensator, the output of the feedback-channel PID2 compensator, and the sum of the initial angular frequencies are connected to the VCO link, and its output is fed back to the Park transformation part and the input of the feedback-channel PID2 compensator. It can achieve fast phase locking when there are a large number of harmonics or even phase jumps in the distribution network during faults.

Description

Technical Field

[0001] The present invention relates to a phase-locked loop circuit based on double-degree-of-freedom PID compensation, belonging to the technical field of distributed energy converters. Background Art

[0002] In recent years, with the continuous access of grid-connected converters, the situation of the distribution network voltage has become extremely complex. However, grid-connected converters mainly rely on the phase-locked loop to accurately obtain the amplitude and phase information of the grid voltage to achieve stable operating characteristics. Therefore, when a fault or large harmonic fluctuation occurs, it may cause errors in phase locking.

[0003] Methods such as the phase-locked loop based on the double synchronous reference coordinate system and the decouple double synchronous reference frame PLL (DDSRF-PLL) have achieved certain effects, overcome the shortcomings of the traditional single-coordinate system phase-locked loop, and solved the phase-locking problem under harmonic conditions. However, the structure is too complex, and the dynamic performance of such phase-locked loops has a certain relationship with the PI parameters or low-pass filter parameters of the phase-locked loop. However, the traditional one-degree-of-freedom PI control has certain limitations and can only better meet any one of the tracking and anti-disturbance characteristics. For example, when the controller parameters are tuned according to the following characteristics to obtain the optimized value, since the only control degree of freedom of the system has been determined and cannot be adjusted further, the anti-disturbance performance of the system cannot be further optimized; similarly, when the parameters are tuned according to the anti-disturbance characteristics, the following performance of the system will not be able to be further optimized. Therefore, the above PI parameters or low-pass filter can only achieve a compromise between the following and anti-disturbance performances, and it is difficult to tune the parameters for suppressing large disturbances under the premise of traditional tracking priority in a complex environment. In fact, with the increase in grid-connected devices and the continuous development of active distribution networks, the phase-locked grid connection of converters in complex situations is also a new direction that the phase-locked loop technology needs to solve in recent years. Summary of the Invention

[0004] In order to solve the above technical problems, the present invention provides a phase-locked loop circuit based on double-degree-of-freedom PID compensation, which can effectively overcome the influence of low-order harmonics and DC components on the phase-locked loop and can also accurately track the ramp change of the grid frequency.

[0005] In order to achieve the above object, the technical solution adopted by the present invention is:

[0006] A phase-locked loop circuit based on double-degree-of-freedom PID compensation, characterized in that it includes a Clarke transformation part, a Park transformation part, a moving average filter, a per-unit conversion part, a double-degree-of-freedom PID compensator, and a VCO link;

[0007] The Clarke transformation part is used to sample the three-phase distribution network voltage Va , V b , V c Converted to the voltage V in the two-phase stationary coordinate system α , V β ; The output of the Clarke transformation part is the input of the Park transformation part, and the q-axis component V output by the Park transformation part q After The per-unit conversion part is converted into the input of the moving average filter;

[0008] The two-degree-of-freedom PID compensator is divided into a PID1 compensator and a PID2 compensator. The PID1 compensator is used to track and lock the phase of the actual phase θ of the distribution network voltage, while the PID2 compensator is used to resist disturbances caused by changes in the system voltage amplitude and frequency;

[0009] The output of the moving average filter is connected to the forward-channel PID1 compensator. The sum of the output of the forward-channel PID1 compensator and the output of the feedback-channel PID2 compensator, together with the sum of the initial angular frequencies, is connected to the VCO link. The output of the VCO link is the locked-phase angle, and this locked-phase angle is fed back to the input of the Park transformation part and the feedback-channel PID2 compensator; The phase-locked loop is used to track the frequency and phase of the distribution network and output the angular frequency and phase.

[0010] The transfer function PID 1 (s) of the PID1 compensator is as follows:

[0011]

[0012] Among them, S is a variable, K p is the proportionality coefficient, K i is the integral coefficient, K d is the differential coefficient; T f is the filtering coefficient, generally 1 / 10 of the differential coefficient; b is the proportionality ratio coefficient, and c is the differential ratio coefficient.

[0013] The transfer function PID 2 (s) of the PID2 compensator is as follows:

[0014]

[0015] Its coefficients are defined as in PID 1 (s), S is a variable, K p is the proportionality coefficient, K i is the integral coefficient, K d is the differential coefficient; T f is the filtering coefficient, generally 1 / 10 of the differential coefficient; b is the proportionality ratio coefficient, and c is the differential ratio coefficient.

[0016] The moving average filter is used to filter out the harmonic components and DC components in the distribution network voltage, and reduce the distortion degree of the harmonic on the phase of the phase-locked loop; the transfer function MAF(s) of the moving average filter is as follows:

[0017]

[0018] where S is a variable, ω c is the bandwidth, ω 0 is the power frequency angular frequency, T ω is the power frequency period of 20 ms, and e is the natural number.

[0019] The phase-locked loop includes Park transformation, per-unit conversion, and two-degree-of-freedom PID compensator;

[0020] The Park transformation is used to convert the two-phase stationary coordinate voltage into a synchronous coordinate signal with the same frequency as the distribution network voltage. By keeping the value of the q-axis component in the synchronous coordinate system as 0, the frequency and phase of the distribution network can be tracked;

[0021] The per-unit conversion divides the filtered output value of the q-axis component of the Park transformation by the filtered output value of the d-axis component to overcome the instability problem of the phase-locked loop due to insufficient PID gain during deep voltage dips.

[0022] The Park transformation is calculated as follows:

[0023]

[0024] where V d and V q are the d and q components of the distribution network voltage in the two-phase synchronous coordinate system respectively, is the estimated angular frequency; V α , V β are the two-phase stationary coordinate system voltages;

[0025] The is obtained by integrating the system angular frequency obtained by summing the output of the PID compensator and the initial angular frequency.

[0026] The beneficial effects achieved by the present invention are as follows:

[0027] 1. The present invention can overcome the influence of low-order harmonics and DC components on the phase-locked loop and improve the phase-locking accuracy;

[0028] 2. The phase-locked loop of the present invention adopts two-degree-of-freedom PID compensation to realize the separate stabilization of tracking and anti-interference performance and improve the stability of the phase-locked loop;

[0029] 3. The present invention provides PID compensation to accelerate the process of the software phase-locked loop by adding a differential link;

[0030] 4. The phase-locked loop technology of the present invention does not increase the hardware cost of the grid-connected inverter controller, but only increases the computational burden of a small amount of MCU. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The present invention will be further described below in conjunction with the drawings:

[0032] Figure 1 is the schematic diagram of the phase-locked loop of the present invention;

[0033] Figure 2 is the Bode plot of the MAF filter of the present invention;

[0034] Figure 3 is the two-degree-of-freedom PID design method based on MATLAB;

[0035] Figure 4 is the phase-locked simulation effect diagram of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0036] The following will be further described in conjunction with the attached Figures 1 to 4 The present invention will be further described. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present invention.

[0037] As Figure 1 shown, the present invention proposes a phase-locked loop circuit based on two-degree-of-freedom PID compensation, which is characterized in that it includes a Clarke transformation part, a Park transformation part, a moving average filter, a per-unit conversion part, a two-degree-of-freedom PID compensator, and a VCO link.

[0038] The working process of this circuit includes:

[0039] 1) The Clarke transformation part converts the three-phase distribution network voltage V a , V b , V c into the two-phase stationary coordinate system voltage V α , V β , and the specific calculation formula is as follows:

[0040]

[0041] 2) The Park transformation part converts the stationary coordinate voltage in step (1) into a synchronous coordinate signal with the same frequency as the distribution network voltage, and the calculation formula is as follows:

[0042]

[0043] Among them, V d and V q are the d and q components of the distribution network voltage in the two-phase synchronous coordinate system, respectively. is the estimated angular frequency. By keeping the value of the q-axis component V in the synchronous coordinate system as 0, the frequency and phase of the distribution network can be tracked. q

[0044] 3) The moving average filter adopts a moving average DC filter, which is a filter with the power frequency period of the distribution network voltage. The transfer function of the moving average filter is:

[0045]

[0046] where T ω is 20 ms.

[0047] From Figure 2 it can be seen that the moving average filter is equivalent to a low-pass filter with a cut-off frequency lower than the power frequency. Therefore, the selection of the DC component can be better realized. After the original DC component in the distribution network voltage undergoes Clarke and Park transformations, its signal becomes a -50 Hz signal. From Figure 2 it can be seen that the DC signal in the original voltage value can be well filtered out; for other harmonics, after Clarke and Park transformations, their signals become 50*(n - 1) Hz (n = 2, 3, 4, etc., integers) signals. From Figure 2 it can be seen that through the moving average filter, the harmonics can be simply filtered out; thus, other DC and its harmonic signals can be completely canceled within a complete cycle.

[0048] 4) The PID compensator is divided into a PID1 compensator and a PID2 compensator to form a two-degree-of-freedom PID compensation. The PID1 compensator is used for tracking and phase-locking the actual phase θ of the distribution network voltage, while the PID2 compensator is used for anti-disturbance against changes in the system voltage amplitude and frequency.

[0049] The transfer function PID 1 (s) of the PID1 compensator is:

[0050]

[0051] where K p is the proportional coefficient, K i is the integral coefficient, K d is the differential coefficient, T f is the filtering coefficient, generally 1 / 10 of the differential coefficient, b is the proportional ratio coefficient, and c is the differential ratio coefficient.

[0052] The transfer function PID 2 (s) of the PID2 compensator is:

[0053] ​

[0054] Its coefficients are defined as in PID 1 (s). The selection of parameters b and c is mainly set according to the requirements of tracking and anti-disturbance performance. Changing the values of b and c can adjust the following performance and anti-disturbance performance of the system for the given signal.

[0055] Such as Figure 1 As shown, the controlled object consists of a cascaded moving average filter and a VCO link, and its model is:

[0056]

[0057] To effectively design the parameters of the compensation link, the corresponding bandwidth and phase margin can be selected first according to the requirements of the system for anti-disturbance performance, and then use Figure 3 As shown, set the corresponding compensator type using the MATLAB-based PID software, import the above object model, and set the bandwidth and phase margin compensation requirements. The PID software will automatically generate the parameters of the above PID1 compensator and PID2 compensator according to the set parameters, and the parameters of the two are complementary.

[0058] Such as Figure 4 As shown, the first subfigure shows the actual voltage waveform, including harmonics, voltage dips, sudden changes in the feedforward quantity, and frequency jumps; the second subfigure uses atan phase locking. Obviously, although this method has a fast response speed, its anti-disturbance ability to harmonics is poor and the phase fluctuates; the third subfigure uses the phase-locked loop technology with a MAF filter with PI compensation. After the sudden change in the feedforward quantity, the phase locking becomes unstable and cannot work properly; the fifth subfigure is the single SRF phase-locked loop technology. Although it can work effectively, its anti-disturbance ability to harmonics is poor and the phase fluctuates; the sixth subfigure is the double SRF phase-locked loop technology. Although the anti-disturbance ability to harmonics has been improved, it becomes unstable after voltage dips and frequency jumps and cannot operate normally; the sixth subfigure uses the two-degree-of-freedom PID phase-locked loop technology proposed by the present invention. Even in a complex power grid environment, accurate phase can be obtained to ensure the performance of the grid-connected inverter; at the same time, when the voltage and frequency suddenly change, the phase information of the distribution network voltage can be quickly tracked to ensure the normal operation of the grid-connected inverter and guarantee the reliability and stability of the distribution network operation.

[0059] The circuit structure of the present invention can eliminate low-order harmonics and DC components through a moving average DC filter, improve the phase-locking adaptability of the phase-locked loop, and the filter parameters have little correlation with the parameters of the phase-locked loop control link. This not only improves the operating performance and tuning efficiency of the phase-locked loop, but also only increases a small amount of computational burden. In addition, it overcomes the mutual coupling limitations existing in the following performance and anti-disturbance performance of the traditional single-degree-of-freedom PI control. Through the two-degree-of-freedom setting, it can better meet the tracking and anti-disturbance characteristics at the same time. The phase-locking technology of the present invention realizes precise phase-locking in a complex environment and is very suitable for the field of power electronic converters including AC-DC conversion.

[0060] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the technical principle of the present invention, several improvements and deformations can be made, and these improvements and deformations should also be regarded as the protection scope of the present invention.

Claims

1. A phase-locked loop circuit based on double-degree-of-freedom PID compensation, characterized in that, it includes a Clarke transformation part, a Park transformation part, a moving average filter, a per-unit conversion part, a double-degree-of-freedom PID compensator, and a VCO link; The Clarke transformation part is used to transform the sampled voltages V a , V b , V c of the three-phase distribution network into the voltages Vα and Vβ in the two-phase stationary coordinate system; the output of the Clarke transformation part is the input of the Park transformation part, and the q-axis component V q output by the Park transformation part is converted into the input of the moving average filter through the per-unit conversion part; the double-degree-of-freedom PID compensator is divided into a PID1 compensator and a PID2 compensator. The PID1 compensator is used for tracking and phase-locking the actual phase θ of the distribution network voltage, while the PID2 compensator is used for anti-disturbance against the changes in the system voltage amplitude and frequency; the output of the moving average filter is connected to the forward-channel PID1 compensator. The sum of the output of the forward-channel PID1 compensator and the output of the feedback-channel PID2 compensator, and then the sum with the initial angular frequency is connected to the VCO link. The output of the VCO link is the phase-locked phase, and this phase-locked phase is fed back to the input of the Park transformation part and the feedback-channel PID2 compensator; the phase-locked loop is used to track the frequency and phase of the distribution network and output the angular frequency and phase; The transfer function PID of the PID1 compensator 1 is as follows: Among them, S is a variable, and K p is a proportionality coefficient, and K i is an integral coefficient, and K d is a differential coefficient; T f is a filtering coefficient, generally 1 / 10 of the differential coefficient; b is a proportionality ratio coefficient, and c is a differential ratio coefficient; The transfer function PID of the PID2 compensator 2 (s) is as follows: Its coefficients are defined as PID 1 (s), where S is a variable, K p is the proportional coefficient, K i is the integral coefficient, K d is the differential coefficient; T f is the filtering coefficient, generally 1 / 10 of the differential coefficient; b is the proportional ratio coefficient, and c is the differential ratio coefficient; the said Park transformation is used to convert the two-phase stationary coordinate voltage into a synchronous coordinate signal with the same frequency as the distribution network voltage. By keeping the value of the q-axis component in the synchronous coordinate system as 0, the frequency and phase of the distribution network can be tracked; the per-unit conversion divides the filtered output value of the q-axis component of the Park transformation by the filtered output value of the d-axis component to overcome the instability problem of the phase-locked loop due to insufficient PID gain during deep voltage dips.

2. The phase-locked loop circuit based on double-degree-of-freedom PID compensation according to claim 1, characterized in that, the said moving average filter is used to filter out the harmonic components and DC components in the distribution network voltage and reduce the distortion degree of the phase-locked loop phase caused by harmonics; the transfer function MAF(s) of the moving average filter is: where S is a variable, ω c is the bandwidth, ω 0 is the power frequency angular frequency, Tω is the power frequency period of 20 ms, and e is the natural number.

3. The phase-locked loop circuit based on double-degree-of-freedom PID compensation according to claim 1, characterized in that, the said Park transformation is calculated as follows: Among them, V d and V q are respectively the d and q components of the distribution network voltage in two-phase synchronous coordinate systems, is the estimated angular frequency; Vα and Vβ are the voltages in the two-phase stationary coordinate system; The above-mentioned is obtained by integrating the system angular frequency obtained from the sum of the output of the PID compensator and the initial angular frequency.

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