Quantization Error Reduction Technique for Fractional-N Phase-Locked Loops Using Σ-Δ Modulation

Abstract

A method and apparatus for fractional-N frequency synthesis using a phase-locked loop (PLL) is provided. A phase detector (PD) of the PLL determines a phase difference between a clock and a feedback clock (CLKFB). A low-pass loop filter of the PLL detects a control voltage based on the phase difference. A voltage-controlled oscillator (VCO) of the PLL generates a periodic signal based on the control voltage. A Σ-Δ modulator (SDM) of the PLL generates a frequency division sequence ratio and a selection control signal based on a frequency command word. A multi-mode divider (MMDIV) generates a first CLKFB and a second CLKFB based on the frequency division sequence ratio and a differential input of the periodic signal. The MMDIV outputs one of the first CLKFB and the second CLKFB as a CLKFB to the PD based on the selection control signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims priority from U.S. Provisional Patent Application filed in the U.S. Patent and Trademark Office on March 3, 2020 and assigned Serial No. 62 / 984,427, the contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to phase-locked loops (PLLs), and more particularly, to a method and system for quantization error (QE) reduction for fractional-N PLLs. Background Art

[0004] Sigma-Delta Modulator (SDM or ΣΔM) is commonly used to control the Multi-Modulus Divider (MMDIV) in a PLL for fractional-N frequency synthesis. Figure 1 , the diagram shows a fractional-N PLL. The MMDIV 102 driven by the SDM 104 is used in the feedback path of the fractional-N frequency synthesis. The SDM 104 receives a frequency command word (Frequency Command Word, FCM) and outputs a frequency division ratio sequence (NDIV) to drive the MMDIV 102. The output clock of the MMDIV 102 (also referred to as the feedback clock (CLKFB)) is fed to the phase detector (Phase Detector, PD), which is embodied as a phase frequency detector (Phase Frequency Detector, PFD) 106 and a charge pump 108. The PFD 106 receives CLKFB and a reference clock (CLKREF). The PFD 106 provides a signal proportional to the phase difference between the received clock signals, and the charge pump 108 is used to sink and source current to the low-pass loop filter 110 based on the output from the PFD 106. The low-pass loop filter 110 filters the received signal and outputs a control voltage V for controlling the frequency of a voltage-controlled oscillator (VCO) 112. ctrl , wherein the voltage controlled oscillator 112 outputs a periodic signal CLKVCO to the MMDIV 102 .

[0005] SDM 104 introduces QE in CLKFB of MMDIV 102. This QE degrades PLL performance in several ways. First, QE causes PLL in-band phase noise (PN). Second, QE increases the required linear operating range of the PD after locking, making PD design difficult.

[0006] Various techniques have been proposed to reduce QE. One such technique employs a high performance PD that can handle large QE. The PD can be embodied as a PFD 106 and a charge pump 108 in an analog PLL, or as a Time-to-Digital Converter (TDC) in a digital PLL. The charge pump and TDC are challenging submodules in a fractional-N PLL.

[0007] Another technique for reducing QE is to add a Digital-to-Time Converter (DTC) in the CLKREF path to offset the QE in CLKFB. Figure 2 is a diagram showing a fractional-N PLL using DTC to compensate for QE. Figure 2 The PLL includes MMDIV 202, SDM 204, PD 206, low-pass loop filter 210 and VCO 212, which are similar to those described above. Figure 1 SDM 204 provides QE (or φ) to multiplier 214. E (n) to be combined with the DTC gain. The DTC control word is output from multiplier 214 and provided to DTC 216, which uses the DTC control word to adjust CLKREF to CLKDTC. CLKDTC is fed to PD 206 along with CLKFB from MMDIV 202 so that QE can be offset from CLKFB.

[0008] This technique attempts to prevent the PD from seeing the QE. The DTC range is required to be large enough to cover the entire range of QE. For a given SDM order, the QE in CLKFB is proportional to the MMDIV input clock period, where the MMDIV input clock period is the VCO period (T VCO ). QE also increases rapidly with the order of SDM. For a 1st-order SDM, QE is VCO For a 2nd order SDM, QE doubles to 2*T VCO , and for a 3rd order SDM, QE becomes 4*T VCOGenerally speaking, a 2nd or 3rd order SDM is required in a fractional-N PLL to randomize the sequence, which results in lower fractional spurs to meet the requirements of communication systems.

[0009] Therefore, the QE canceller circuit (such as, for example, DTC 216) needs to cover more than 4*T for 3rd order SDM VCO Delay range. For example, if the VCO frequency is 4 GHz, the required DTC range is 1 nanosecond (ns). It is challenging to design a DTC with a larger delay range (DR) while achieving low integral nonlinearity (INL), which is critical for lower fractional spurious levels. In addition, DTC thermal noise increases in proportion to the square of the delay, which results in additional in-band PN in the PLL. Summary of the invention

[0010] According to one embodiment, a PLL for fractional-N frequency synthesis is provided. The PLL includes a PD configured to receive a clock and a CLKFB, and to generate and output a generated phase difference between the clock and the CLKFB. The PLL also includes a low-pass loop filter configured to receive the generated phase difference, and to generate and output a control voltage. The PLL additionally includes: a VCO configured to receive a control voltage, and to generate and output a periodic signal based on the voltage; and an SDM configured to receive a frequency command word, and to generate and output a frequency division sequence ratio and a selection control signal. The PLL also includes an MMDIV configured to receive a differential input of a periodic signal from the VCO, and to receive a frequency division sequence ratio and a selection control signal from the SDM. The MMDIV is configured to generate a first CLKFB and a second CLKFB based on the differential input and the frequency division sequence ratio, and to output one of the first CLKFB and the second CLKFB as a CLKFB to the PD based on the selection control signal.

[0011] According to one embodiment, a method for fractional-N frequency synthesis using a PLL is provided. The PD of the PLL determines the phase difference between the clock and the CLKFB. The low-pass loop filter of the PLL detects a control voltage based on the phase difference. The VCO of the PLL generates a periodic signal based on the control voltage. The SDM of the PLL generates a frequency division sequence ratio and a selection control signal based on a frequency command word. The MMDIV generates a first CLKFB and a second CLKFB based on the frequency division sequence ratio and a differential input of the periodic signal. The MMDIV outputs one of the first CLKFB and the second CLKFB as the CLKFB to the PD based on the selection control signal.

[0012] According to one embodiment, an MMDIV for a PLL for fractional-N frequency synthesis is provided. The MMDIV includes a frequency divider configured to receive a differential input of a periodic signal from a VCO of the PLL, receive a frequency division sequence ratio from a Σ-Δ modulator (SDM) of the PLL, and generate and output a clock signal. The MMDIV also includes a first flip-flop configured to receive a first differential input of a clock signal and a periodic signal, and generate and output a first CLKFB. The MMDIV additionally includes a second flip-flop configured to receive a second differential input of a clock signal and a periodic signal, and generate and output a second CLKFB. The MMDIV also includes a multiplexer configured to receive a first CLKFB, a second CLKFB, and a selection control signal from the SDM, and output one of the first CLKFB and the second CLKFB as a CLKFB to a PD of the PLL based on the selection control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1 is a diagram illustrating a fractional-N PLL;

[0015] Figure 2 is a diagram showing a fractional-N PLL using DTC to compensate for QE;

[0016] Figure 3A is a diagram showing a conventional MMDIV and SDM for a fractional-N PLL;

[0017] Figure 3B is a diagram illustrating MMDIV and SDM of a fractional-N PLL according to an embodiment of the present disclosure;

[0018] Figure 4A and Figure 4B is a diagram illustrating a retimed MMDIV output clock of a fractional-N PLL according to an embodiment of the present disclosure;

[0019] Figure 5 is a diagram illustrating an SDM of a fractional-N PLL according to an embodiment of the present disclosure;

[0020] Figure 6 is a diagram illustrating an SDM of a fractional-N PLL according to an embodiment of the present disclosure;

[0021] Figure 7 is a diagram illustrating a fractional-N PLL using DTC and VCO duty cycle correction according to an embodiment of the present disclosure;

[0022] Figure 8 is a flow chart illustrating a method for fractional-N frequency synthesis using a PLL according to an embodiment of the present disclosure;

[0023] Fig. 9 is a flow chart illustrating a method for fractional-N frequency synthesis using a DTC PLL according to an embodiment of the present disclosure; and

[0024] Fig.10 is a block diagram of an electronic device in a network environment according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same elements will be designated by the same reference numerals, although they are shown in different drawings. In the following description, only specific details such as detailed configuration and components are provided to help fully understand the embodiments of the present disclosure. Therefore, it should be apparent to those skilled in the art that various changes and modifications to the embodiments described herein may be made without departing from the scope of the present disclosure. In addition, for the sake of clarity and simplicity, descriptions of well-known functions and structures are omitted. The terms described below are defined in consideration of the functions in the present disclosure, and may be different according to the user, the user's intention, or custom. Therefore, the definition of the terms should be determined according to the content of the entire specification.

[0026] The present disclosure may have various modifications and various embodiments, wherein the embodiments are described in detail below with reference to the accompanying drawings. However, it should be understood that the present disclosure is not limited to the embodiments, but includes all modifications, equivalents and substitutes within the scope of the present disclosure.

[0027] Although the term including ordinal numbers (such as first, second, etc.) can be used to describe various elements, structural elements are not limited by the term. The term is only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, the first structural element can be referred to as the second structural element. Similarly, the second structural element can also be referred to as the first structural element. As used herein, the term "and / or" includes any and all combinations of one or more associated items.

[0028] The terms used in this article are only used to describe various embodiments of the present disclosure and are not intended to limit the present disclosure. The singular form is intended to include the plural form unless the context clearly indicates otherwise. In the present disclosure, it should be understood that the term "including" or "having" indicates the presence of a feature, number, step, operation, structural element, component or a combination thereof, and does not exclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, structural elements, components or a combination thereof.

[0029] Unless defined differently, all terms used herein have the same meaning as understood by those skilled in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having the same meaning as the contextual meaning in the relevant art, and are not to be interpreted as having an ideal or overly formal meaning unless explicitly defined in the present disclosure.

[0030] The electronic device according to one embodiment may be one of various types of electronic devices. The electronic device may include, for example, a portable communication device (e.g., a smart phone), a computer, a portable multimedia device, a portable medical device, a camera, a wearable device, or a household appliance. According to one embodiment of the present disclosure, the electronic device is not limited to those electronic devices mentioned above.

[0031] The terms used in the present disclosure are not intended to limit the present disclosure, but are intended to include various changes, equivalents or replacements of corresponding embodiments. Regarding the description of the accompanying drawings, similar reference numerals may be used to refer to similar or related elements. The singular form of the noun corresponding to the item may include one or more of the things, unless the relevant context clearly indicates otherwise. As used herein, each of the phrases such as "A or B", "at least one of A and B", "at least one of A or B", "A, B or C", "at least one of A, B and C" and "at least one of A, B or C" may include all possible combinations of the items listed together in the corresponding one in the phrase. As used herein, terms such as "the 1st", "the 2nd", "the first" and "the second" may be used to distinguish a corresponding component from another component, but are not intended to limit the component in other aspects (e.g., importance or order). It is expected that if an element (e.g., a first element) is referred to as being “coupled with another element (e.g., a second element)”, “coupled to another element”, “connected with another element” or “connected to another element” with or without the term “operably” or “communicatively”, it indicates that the element can be coupled with the other element directly (e.g., by wire), wirelessly, or via a third element.

[0032] As used herein, the term "module" may include units implemented in hardware, software, or firmware, and may be used interchangeably with other terms such as, for example, "logic," "logic block," "component," and "circuit." A module may be a single integral component, or a minimum unit or portion thereof, suitable for performing one or more functions. For example, according to one embodiment, a module may be implemented in the form of an application specific integrated circuit (ASIC).

[0033] The present system and method provides a technique to reduce the QE by half for any given SDM order. Therefore, the required linear operating range of the PD (i.e., TDC, or PFD and charge pump) can be halved. This results in lower noise, less power consumption, and low fractional spurs.

[0034] In a DTC-based PLL where DTC is used to eliminate QE before PD, the system and method can also help reduce the required DTC range by half. This results in less DTC thermal noise, better linearity, and lower power consumption of the DTC design.

[0035] Digital logic is added before and after the SDM to generate a new NDIV for MMDIV, a clock selection control signal for MMDIV, and a halved QE for QE cancellation used in a DTC or other canceller circuit.

[0036] The changes in the digital domain of the PLL can be synthesized, placed and routed via the digital flow with negligible impact on area and power. The analog domain requires the addition of two digital flip-flops to re-time the MMDIV output clock with the inverted version of CLKVCO (VCO_P) and CLKVCO (VCO_N), respectively, and thus use a multiplexer to select between the two. The selection control signal is generated from the modified SDM.

[0037] Since the QE is reduced by half, the required DTC range is halved. The simulated DTC PN is 4dB lower, and the INL is also reduced to half of the original INL. The system and method can also be applied to other fractional-N PLL topologies to improve PD performance and reduce the impact of QE on PLL PN.

[0038] refer to Figure 3A , the diagram shows the conventional MMDIV and SDM of a fractional-N PLL. SDM 304-1 receives FCW and outputs QE and NDIV. NDIV is related to CKVCO from VCO (with frequency f VCO ) are provided to MMDIV 302-1 and output CLKFB (F VCO / FCW).

[0039] Figure 3B 304-2 receives FCW and outputs QE / 2. Additionally, SDM 304-2 provides NDIV and SEL_CLKFB to MMDIV 302-2. SEL_CLKFB is used to select between CLKFB generated in MMDIV 302-2, as described below with reference to Figure 4ADescribed in more detail.

[0040] By Figure 3B With the changes described in , MMDIV can support NDIV of (N+0.5). Figure 3A Compared to the conventional embodiment, the QE introduced in CLKFB due to the fractional-N division is reduced by half.

[0041] Reference now Figure 4A and Figure 4B , the diagram shows the retimed MMDIV output clock of the fractional-N PLL according to an embodiment of the present disclosure. MMDIV 402 receives differential input clocks VCO_P and VCO_N from the VCO and NDIV from the SDM. MMDIV 402 outputs CLKFB_int to a first delay flip-flop (Delay Flip-Flop, DFF) 404 and a second DFF 406. By convention, CLKFB_int is the CLKFB provided to the PD and includes the QE.

[0042] The first DFF 404 also receives VCO_P and then outputs a first feedback clock CLKFB1. The second DFF 406 also receives VCO_N and then outputs a second feedback clock CLKFB2. The multiplexer (MUX) 408 receives CLKFB1 from the first DFF 404, CLKFB2 from the second DFF 406, and SEL_CLKFB from the SDM. According to SEL_CLKFB, the multiplexer 408 selects one of CLKFB1 and CLKFB2 as the output CLKFB. If the QE in CLKFB_int is greater than T VCO / 2, then CLKFB2 is selected because it is delayed by T compared to CLKFB1. VCO / 2. Accordingly, QE in CLKFB is reduced to T VCO / 2, which is equivalent to dividing by (N+0.5).

[0043] Figure 4B shows that due to the differential input clocks VCO_P and VCO_N, the rising edge of CLKFB2 is delayed by T compared to the rising edge of CLKFB1 VCO / 2

[0044] Figure 5 5 is a diagram illustrating an SDM for a fractional-N PLL according to an embodiment of the present disclosure. The FCW is received at multiplier 502 and multiplied by 2 (left shifted). The output from multiplier 502 is divided into an integer portion of the FCW and a fractional portion of the FCW and provided to a conventional SDM 504, which outputs the integer portion of QE (QE_int(n) or φ e,int(n)) and the integer portion of NDIV (NDIV_int). To obtain the correct division ratio, both QE_int(n) and NDIV_int must be divided by 2 (right shift). QE_int(n) is divided by 2 at the first divider 506 to produce QE(n) (or φ e (n)). NDIV_int is divided by 2 (right shifted) at the second divider 508. The NDIV_int is divided to produce a fractional bit (0 or 0.5), which is transmitted to the modulo 2 adder (mod2 adder) 510. The mod2 adder 510 outputs a carry output bit, which is added to the integer portion of NDIV_int / 2 at the adder 512 to produce NDIV. The produced NDIV is provided to MMDIV. Accordingly, the average NDIV is equal to the NDIV obtained by conventional methods.

[0045] The mod2 adder 510 also provides a delay block Z -2 514 (which implements a two clock cycle delay) outputs the sum s and provides the resulting SEL_CLKFB to MMDIV. Delay Block Z -1 516 also receives the sum s, implements a delay of one clock cycle, and provides the resulting output back to the mod2 adder 510.

[0046] Reference now Figure 6 , the diagram shows the SDM of a fractional-N PLL according to an embodiment. Specifically, Figure 6 The SDM corresponds to Figure 5 The fractional portion of the FCW is provided to the first adder 602, and the output from the first adder 602 is provided to the first delay block Z -1 604, which implements a delay of one clock cycle. From the first delay block Z -1 The delayed output of 604 is provided to a quantizer 606, and the quantized output along with the integer portion of the FCW is provided to a second adder 608. The output of the second adder 608 is the integer portion of the NDIV (or NDIV_int).

[0047] The quantized output from the quantizer 606 is also compared with the quantized output from the first delay block Z -1 The delayed outputs of 604 are provided together to a third adder 610. The output e2 from the third adder 610 is provided to the first adder 602 together with the fractional portion of the FCW.

[0048] The fractional part of FCW is also provided to the second delay block Z -1 612, which implements a delay of one clock cycle. From the second delay block Z -1The delayed output of 612 is provided to a fourth adder 614 together with the quantized output from the quantizer 606. The output e1 from the fourth adder 614 is the integer part of QE(n) (QE_int(n) or φ e,int (n)).

[0049] To implement the system and method robustly when the VCO clock is not a perfect 50% duty cycle (eg, with analog circuit imperfections), an LMS-based background calibration loop may be added to correct the duty cycle of the VCO clock.

[0050] Specifically, if VCO_P and VCO_N have duty cycle errors (i.e., they are not fully differential), then the CLKFB1 and CLKFB2 timings will not differ by exactly T VCO / 2, which introduces errors. These errors slow down the DTC gain calibration, resulting in convergence at incorrect values. Accordingly, a VCO duty cycle calibration (DCC) least-mean square (LMS) loop can be added by associating the phase error polarity with SEL_CLKFB. Specifically, the DTC gain converges quickly without error, and the calibration result is applied to the DTC to compensate for the error. Since the VCO duty cycle error is small, a simple and small extension can be added to the required DTC range.

[0051] Reference now Figure 7 , the diagram shows a fractional-N PLL using DTC and VCO duty cycle correction according to an embodiment. Specifically, Figure 7 Provided Figure 2 A more detailed diagram of the PLL, combined with Figure 4A MMDIV and Figure 5 Additionally, Figure 7 VCO duty cycle correction is provided.

[0052] Figure 7 The PLL includes MMDIV 702, SDM 704, PD 706, low-pass loop filter 710 and VCO 712. MMDIV 702 is as described above with respect to Figure 4A and SDM 704 operates as described above with respect to Figure 5 and Figure 6 SDM 704 provides QE(n) (or φ) to adder 718. E (n)), where the adder 718 also receives the converged value VCO_dcc_cmp from the VCO duty cycle correction block 720. The result from the adder 718 is provided to the first multiplier 714 to be combined with the DTC gain (K) from the DTC gain calibration block 722.DTC ). The DTC control word is output from the first multiplier 714 and provided to the DTC 716, which uses the DTC control word to adjust CLKREF to CLKDTC. CLKDTC is fed to the PD 706 along with the CLKFB from the MMDIV 702 so that QE can be eliminated from the CLKFB.

[0053] PHE_Sign is the sign information of the phase error between CLKDTC and CLKFB. If CLKDTC leads CLKFB, PHE_Sign is +1. If CLKDTC does not lead CLKFB, PHE_Sign is -1.

[0054] The VCO duty cycle error causes a phase shift in the CLKFB edge and is ultimately reflected in PHE_Sign. Therefore, PHE_Sign has a strong correlation with SEL_CLKFB because SEL_CLKFB is used to select CLKFB1 or CLKFB2 as CLKFB. Accordingly, a least mean square (LMS) adaptive loop based on sign-sign regression is added to extract the VCO duty cycle error.

[0055] The VCO duty cycle correction block 720 receives SEL_CLKFB and PHE_Sign from the SDM 704 at a second multiplier 724. The output from the second multiplier 724 is provided to an accumulator 726 with a gain factor. The accumulated output from the accumulator 726 is provided to a third multiplier 728 along with SEL_CLKFB from the SDM 704 to apply the correction. The output from the third multiplier 728 is a converged value VCO_dcc_cmp, which is added to QE(n) (or φ E (n)) are provided together to adder 718 to control the DTC delay.

[0056] Since the same phase shift on CLKFB caused by the VCO duty cycle error is applied to CLKDTC via the DTC delay code, the phase detector will no longer detect the phase error. The proposed VCO duty cycle correction does not require additional analog circuitry, but uses the pre-existing PHE_Sign signal for DTC gain calibration.

[0057] The DTC gain calibration block 722 receives the result of the adder 718 as an input and provides an output to a digital to analog converter (DAC) 730. The reference voltage Vref_adj output from the DAC 730 is provided to a voltage comparator 732 together with the output from the PD 706. The voltage comparator 732 provides PHE_Sign to the VCO duty cycle correction block 720. The DTC gain calibration block includes components such as, for example, an SDM, a multiplier, a delay block, and an accumulator, as well as functions well known in the art. Similarly, the PD 706 includes components such as, for example, a slope generator, and also includes functions well known in the art.

[0058] refer to Figure 8 , a flow chart illustrates a method for fractional-N frequency synthesis using a PLL according to an embodiment of the present disclosure. At 802, the PFD of the PLL generates a signal proportional to the phase difference between the clock and CLKFB. At 804, the charge pump of the PLL provides a sink current and a source current based on the signal. At 806, the low-pass loop filter of the PLL generates a control voltage based on the sink current and the source current. At 808, the VCO of the PLL generates a periodic signal based on the control voltage. At 810, the SDM of the PLL generates NDIV and SEL_CLKFB based on the frequency command word.

[0059] The NDIV is generated by doubling the frequency command word, performing sigma-delta modulation on the doubled frequency command word to generate a first NDIV, and halving the first NDIV to output a final NDIV.

[0060] At 812, MMDIV of the PLL generates a first CLKFB based on a first differential input (VCO_P) of a periodic signal and a clock signal, which is generated using first and second differential inputs (VCO_P and VCO_N) and NDIV. At 814, MMDIV generates a second CLKFB based on a second differential input (VCO_N) of a periodic signal and a clock signal. At 816, MMDIV selects one of the first CLKFB and the second CLKFB as the CLKFB output to the PFD based on SEL_CLKFB.

[0061] refer to Fig. 9, a flow chart illustrating a method for fractional-N frequency synthesis using a DTC PLL according to an embodiment of the present disclosure. At 902, the PD receives a clock and CLKFB, and outputs a generated phase difference between the clock and CLKFB. At 904, a low-pass loop filter of the PLL generates a control voltage based on the phase difference. At 906, a VCO of the PLL generates a periodic signal based on the control voltage. At 908, an SDM of the PLL generates NDIV, SEL_CLKFB, and QE based on a frequency command word.

[0062] The NDIV and QE are generated by doubling a frequency command word, performing sigma-delta modulation on the doubled frequency command word to generate a first NDIV and a first QE, halving the first NDIV to output a final NDIV, and halving the first QE to output a final QE.

[0063] At 910, QE and DTC gain are combined to generate a DTC control word. At 912, the DTC generates CLKDTC as a clock input to the PD based on CLKREF and the DTC control word.

[0064] At 914, MMDIV of the PLL generates a first CLKFB based on the first differential input (VCO_P) of the periodic signal and the clock signal, which is generated using the first and second differential inputs (VCO_P and VCO_N) and NDIV. At 916, MMDIV generates a second CLKFB based on the second differential input (VCO_N) of the periodic signal and the clock signal. At 918, MMDIV selects one of the first CLKFB and the second CLKFB as the CLKFB output to the PD based on SEL_CLKFB.

[0065] The disclosed systems and methods can support high-order SDM operations, support lower VCO oscillation frequencies for a given DTC range, provide little analog circuit changes or overhead, and digital background calibration ensures the robustness of the proposed systems and methods in the presence of VCO duty cycle errors.

[0066] The system and method can also be used to process 1 / 4T using a quadrature VCO (QVCO) or a ring oscillator. VCO Delayed example.

[0067] Fig.10 is a block diagram of an electronic device in a network environment according to an embodiment. Fig.10, the electronic device 1001 in the network environment 1000 may communicate with the electronic device 1002 via the first network 1098 (e.g., a short-range wireless communication network), or communicate with the electronic device 1004 or the server 1008 via the second network 1099 (e.g., a long-range wireless communication network). The electronic device 1001 may communicate with the electronic device 1004 via the server 1008. The electronic device 1001 may include a processor 1020, a memory 1030, an input device 1050, a sound output device 1055, a display device 1060, an audio module 1070, a sensor module 1076, an interface 1077, a haptic module 1079, a camera module 1080, a power management module 1088, a battery 1089, a communication module 1090, a subscriber identification module (Subscriber Identification Module, SIM) 1096 or an antenna module 1097. In one embodiment, at least one of the components (e.g., display device 1060 or camera module 1080) may be omitted from electronic device 1001, or one or more other components may be added to electronic device 1001. Some of the components may be implemented as a single integrated circuit (IC). For example, sensor module 1076 (e.g., fingerprint sensor, iris sensor, or illumination sensor) may be embedded in display device 1060 (e.g., display).

[0068] The processor 1020 may execute, for example, software (e.g., program 1040) to control at least one other component (e.g., hardware or software component) of the electronic device 1001 coupled to the processor 1020, and may perform various data processing or calculations. As at least part of the data processing or calculation, the processor 1020 may load a command or data received from another component (e.g., sensor module 1076 or communication module 1090) in the volatile memory 1032, process the command or data stored in the volatile memory 1032, and store the generated data in the non-volatile memory 1034. The processor 1020 may include a main processor 1021 (e.g., a central processing unit (CPU) or an application processor (AP)) and an auxiliary processor 1023 (e.g., a graphics processing unit (GPU), an image signal processor (ISP), a sensor hub processor, or a communication processor (CP)), wherein the auxiliary processor 1023 may operate independently of the main processor 1021 or in conjunction with the main processor 1021. Additionally or alternatively, the auxiliary processor 1023 may be adapted to consume less power than the main processor 1021, or to perform a specific function. The auxiliary processor 1023 may be implemented as a separate part from the main processor 1021 or as a part of the main processor 1021.

[0069] The auxiliary processor 1023 may control at least some of the functions or states related to at least one component (e.g., display device 1060, sensor module 1076, or communication module 1090) among the components of the electronic device 1001 instead of the main processor 1021 when the main processor 1021 is in an inactive (e.g., sleep) state, or control at least some of the functions or states together with the main processor 1021 when the main processor 1021 is in an active state (e.g., executing an application). The auxiliary processor 1023 (e.g., an image signal processor or a communication processor) may be implemented as a part of another component (e.g., a camera module 1080 or a communication module 1090) that is functionally related to the auxiliary processor 1023.

[0070] The memory 1030 may store various data used by at least one component of the electronic device 1001 (e.g., the processor 1020 or the sensor module 1076). The various data may include, for example, input data or output data of software (e.g., the program 1040) and commands related thereto. The memory 1030 may include a volatile memory 1032 or a non-volatile memory 1034.

[0071] The program 1040 may be stored in the memory 1030 as software, and may include, for example, an operating system (OS) 1042 , middleware 1044 , or an application 1046 .

[0072] The input device 1050 may receive commands or data to be used by other components (eg, the processor 1020) of the electronic device 1001 from outside the electronic device 1001 (eg, a user). The input device 1050 may include, for example, a microphone, a mouse, or a keyboard.

[0073] The sound output device 1055 can output sound signals to the outside of the electronic device 1001. The sound output device 1055 can include, for example, a speaker or a receiver. The speaker can be used for general purposes, such as playing multimedia or recording, and the receiver can be used to receive incoming calls. The receiver can be implemented as a part of the speaker or as a part of the speaker.

[0074] The display device 1060 can visually provide information to the outside of the electronic device 1001 (e.g., a user). The display device 1060 may include, for example, a display, a holographic device or a projector, and a control circuit, wherein the control circuit is used to control a corresponding one of the display, the holographic device, and the projector. The display device 1060 may include a touch circuit suitable for detecting a touch, or a sensor circuit (e.g., a pressure sensor) suitable for measuring the strength of the force caused by the touch.

[0075] The audio module 1070 can convert sound into an electrical signal and vice versa. The audio module 1070 can obtain sound via the input device 1050, or output sound via the sound output device 1055 or the earphone of the external electronic device 1002 directly (eg, wired) or wirelessly coupled to the electronic device 1001.

[0076] The sensor module 1076 can detect an operating state (e.g., power or temperature) of the electronic device 1001 or an environmental state (e.g., a user's state) outside the electronic device 1001, and then generate an electrical signal or data value corresponding to the detected state. The sensor module 1076 may include, for example, a gesture sensor, a gyroscope sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biosensor, a temperature sensor, a humidity sensor, or an illumination sensor.

[0077] The interface 1077 may support one or more specific protocols of the electronic device 1001 to be used for coupling directly (e.g., wired) or wirelessly with the external electronic device 1002. The interface 1077 may include, for example, a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, a Secure Digital (SD) card interface, or an audio interface.

[0078] The connection terminal 1078 may include a connector via which the electronic device 1001 may be physically connected to the external electronic device 1002. The connection terminal 1078 may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (eg, a headphone connector).

[0079] The haptic module 1079 may convert an electrical signal into a mechanical stimulus (eg, vibration or movement) or an electrical stimulus, which may be recognized by a user via a sense of touch or a sense of motion. The haptic module 1079 may include, for example, a motor, a piezoelectric element, or an electrical stimulator.

[0080] The camera module 1080 may capture still images or moving images. The camera module 1080 may include one or more lenses, image sensors, image signal processors, or flashes.

[0081] The power management module 1088 may manage power supplied to the electronic device 1001. The power management module 1088 may be implemented as, for example, at least a portion of a power management integrated circuit (PMIC).

[0082] The battery 1089 may supply power to at least one component of the electronic device 1001. The battery 1089 may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0083] The communication module 1090 can support the establishment of a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device 1001 and an external electronic device (e.g., electronic device 1002, electronic device 1004, or server 1008), and perform communication via the established communication channel. The communication module 1090 may include one or more communication processors that can operate independently of the processor 1020 (e.g., AP) and support direct (e.g., wired) communication or wireless communication. The communication module 1090 may include a wireless communication module 1092 (e.g., a cellular communication module, a short-range wireless communication module, or a Global Navigation Satellite System (GNSS) communication module) or a wired communication module 1094 (e.g., a Local Area Network (LAN) communication module or a Power Line Communication (PLC) module). A corresponding one of these communication modules can communicate via a first network 1098 (e.g., a short-range communication network such as Bluetooth TM , Wireless Fidelity (Wi-Fi) Direct, or Infrared Data Association (IrDA) standards) or a second network 1099 (e.g., a remote communication network such as a cellular network, the Internet, or a computer network (e.g., a LAN or a Wide Area Network (WAN)))) to communicate with an external electronic device. These various types of communication modules can be implemented as a single component (e.g., a single IC), or can be implemented as multiple components separated from each other (e.g., multiple ICs). The wireless communication module 1092 can use user information (e.g., International Mobile Subscriber Identity (IMSI)) stored in the user identification module 1096 to identify and authenticate the electronic device 1001 in a communication network (such as the first network 1098 or the second network 1099).

[0084] The antenna module 1097 may send or receive a signal or power to or from the outside (e.g., an external electronic device) of the electronic device 1001. The antenna module 1097 may include one or more antennas, and at least one antenna suitable for a communication scheme used in a communication network (such as the first network 1098 or the second network 1099) may be selected therefrom by, for example, the communication module 1090 (e.g., the wireless communication module 1092). Then, a signal or power may be sent or received between the communication module 1090 and the external electronic device via the selected at least one antenna.

[0085] At least some of the above components can be coupled to each other and communicate signals (e.g., commands or data) therebetween via an inter-peripheral communication scheme (e.g., a bus, a general purpose input and output (GPIO), a serial peripheral interface (SPI), or a mobile industry processor interface (MIPI)).

[0086] Commands or data may be sent or received between the electronic device 1001 and the external electronic device 1004 via a server 1008 coupled to the second network 1099. Each of the electronic devices 1002 and 1004 may be a device of the same type or a different type as the electronic device 1001. All or some of the operations to be performed at the electronic device 1001 may be performed at one or more of the external electronic devices 1002, 1004, or 1008. For example, if the electronic device 1001 should automatically perform a function or service, or in response to a request from a user or another device, instead of performing a function or service or in addition to performing a function or service, the electronic device 1001 may also request one or more external electronic devices to perform at least a portion of the function or service. The one or more external electronic devices receiving the request may perform at least a portion of the requested function or service, or additional functions or additional services related to the request, and pass the result of the execution to the electronic device 1001. The electronic device 1001 may provide the result as at least a part of the reply to the request with or without further processing the result. To this end, for example, cloud computing, distributed computing, or client-server computing technology may be used.

[0087] One embodiment may be implemented as software (e.g., program 1040), including one or more instructions stored in a storage medium (e.g., internal memory 1036 or external memory 1038) that can be read by a machine (e.g., electronic device 1001). For example, the processor of the electronic device 1001 may call at least one of the one or more instructions stored in the storage medium, and execute the at least one instruction with or without one or more other components under the control of the processor. Thus, the machine may be operated to perform at least one function according to the at least one instruction called. The one or more instructions may include code generated by a compiler or code executable by an interpreter. The machine-readable storage medium may be provided in the form of a non-transitory storage medium. The term "non-transitory" indicates that the storage medium is a tangible device and does not include signals (e.g., electromagnetic waves), but the term does not distinguish between data being semi-permanently stored in the storage medium and data being temporarily stored in the storage medium.

[0088] According to one embodiment, the method of the present disclosure may be included and provided in a computer program product. The computer program product may be traded as a product between a seller and a buyer. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., a Compact Disc Read Only Memory (CD-ROM)), or via an application store (e.g., Play Store TM ) online distribution (e.g., download or upload), or directly between two user devices (e.g., smart phones). If distributed online, at least a portion of the computer program product may be temporarily generated or at least temporarily stored in a machine-readable storage medium (such as a memory of a manufacturer's server, a server of an application store, or a relay server).

[0089] According to one embodiment, each of the above-mentioned components (e.g., a module or a program) may include a single entity or multiple entities. One or more of the above-mentioned components may be omitted, or one or more other components may be added. Alternatively or additionally, multiple components (e.g., modules or programs) may be integrated into a single component. In this case, the integrated component may still perform one or more functions of each of the multiple components in the same or similar manner as they were performed by a corresponding one of the multiple components before integration. The operations performed by a module, a program or another component may be performed sequentially, in parallel, repeatedly or heuristically, or one or more of the operations may be performed in a different order or omitted, or one or more other operations may be added.

[0090] Although certain embodiments of the present disclosure have been described in the detailed description of the present disclosure, the present disclosure may be modified in various forms without departing from the scope of the present disclosure. Therefore, the scope of the present disclosure should not be determined based solely on the described embodiments, but rather on the appended claims and their equivalents.

Claims

1. A phase-locked loop (PLL) for fractional-N frequency synthesis, the PLL comprising: a phase detector PD configured to receive a clock and a feedback clock CLKFB, and to generate and output a generated phase difference between the clock and the CLKFB; a low-pass loop filter configured to receive the generated phase difference and generate and output a control voltage; a voltage controlled oscillator VCO configured to receive the control voltage and generate and output a periodic signal based on the voltage; a sigma-delta modulator SDM configured to receive a frequency command word and to generate and output a frequency division sequence ratio and a selection control signal; as well as A multi-mode divider MMDIV is configured to receive a differential input of the periodic signal from the VCO, and to receive the division sequence ratio and the selection control signal from the SDM, wherein the MMDIV is configured to generate a first CLKFB and a second CLKFB based on the differential input and the division sequence ratio, and to output one of the first CLKFB and the second CLKFB as the CLKFB to the PD based on the selection control signal.

2. The PLL according to claim 1, wherein: The clock is a reference clock CLKREF.

3. The PLL according to claim 1, wherein: A rising edge of the second CLKFB is delayed from a rising edge of the first CLKFB by a half cycle of the VCO.

4. The PLL of claim 1, wherein: The PD includes: a phase frequency detector PFD configured to receive the clock and CLKFB, and to generate and output a signal proportional to the phase difference between the clock and the CLKFB; and A charge pump is configured to receive the signal from the PFD, generate a sink current and a source current based on the received signal, and output the sink current and the source current to the low-pass loop filter.

5. The PLL of claim 1, wherein: The MMDIV includes: a first flip-flop configured to receive a first differential input of the periodic signal and a clock signal, the clock signal being generated using the differential input and the frequency division sequence ratio, and the first flip-flop being configured to generate and output the first CLKFB; a second flip-flop configured to receive a second differential input of the periodic signal and the clock signal, and configured to generate and output the second CLKFB; and The multiplexer is configured to receive the first CLKFB, the second CLKFB, and the selection control signal, and output one of the first CLKFB and the second CLKFB as the CLKFB based on the selection control signal.

6. The PLL of claim 1, wherein: The SDM is configured to double the frequency command word, perform sigma-delta modulation on the doubled frequency command word to generate a first frequency division sequence ratio, and halve the first frequency division sequence ratio to output the frequency division sequence ratio to the MMDIV.

7. The PLL of claim 6, wherein: The carry-out bit is added to the halved first division sequence ratio to generate the division sequence ratio.

8. The PLL of claim 1, wherein: The SDM is further configured to generate a quantization error, and the PLL further comprises: a multiplier configured to receive the quantization error and a digital-to-time converter DTC gain, and to generate and output a DTC control word; and The DTC is configured to receive CLKREF and the DTC control word, and to generate and output a DTC clock CLKDTC as the clock input to the PD.

9. The PLL of claim 8, wherein: The SDM is configured to double the frequency command word, perform sigma-delta modulation on the doubled frequency command word to generate a first quantization error, and halve the first quantization error to output the quantization error to the multiplier.

10. The PLL of claim 9, wherein: Prior to the multiplier, a VCO clock duty cycle error correction is performed on the quantization error.

11. A method for fractional-N frequency synthesis using a phase-locked loop (PLL), the method comprising: The phase difference between the clock and the feedback clock CLKFB is detected by the phase detector PD of the PLL; determining, by a low pass loop filter of the PLL, a control voltage based on the phase difference; A voltage controlled oscillator (VCO) of the PLL generates a periodic signal based on the control voltage; A sigma-delta modulator SDM of the PLL generates a frequency division sequence ratio and a selection control signal based on a frequency command word; as well as Generate a first CLKFB and a second CLKFB by a multi-mode frequency divider MMDIV based on the frequency division sequence ratio and a differential input of the periodic signal; as well as One of the first CLKFB and the second CLKFB is output from the MMDIV to the PD as the CLKFB based on the selection control signal.

12. The method according to claim 11, wherein: The clock is a reference clock CLKREF.

13. The method according to claim 11, wherein: A rising edge of the second CLKFB is delayed from a rising edge of the first CLKFB by a half cycle of the VCO.

14. The method according to claim 11, wherein: Detecting the phase difference comprises: generating, by a phase frequency detector PFD, a signal proportional to the phase difference between the clock and the CLKFB; and A charge pump provides sinking current and sourcing current to the low-pass loop filter based on the signal.

15. The method according to claim 11, wherein: Generating the first CLKFB and the second CLKFB includes: generating the first CLKFB by a first trigger of the MMDIV based on a first differential input of the periodic signal and a clock signal, the clock signal being generated using the differential input and the frequency division sequence ratio; and The second CLKFB is generated by the second trigger of the MMDIV based on the second differential input of the periodic signal and the clock signal.

16. The method according to claim 11, wherein: Outputting one of the first CLKFB and the second CLKFB as the CLKFB includes: One of the first CLKFB and the second CLKFB is selected as the CLKFB by the multiplexer of the MMDIV based on the selection control signal.

17. The method according to claim 11, wherein: Generating the frequency division sequence ratio comprises: doubling the frequency command word; performing sigma-delta modulation on the doubled frequency command word to generate a first frequency division sequence ratio; and The first frequency division sequence ratio is halved to output the frequency division sequence ratio to the MMDIV.

18. The method of claim 17, further comprising adding a carry-out bit to a halved first division sequence ratio to generate the division sequence ratio.

19. The method according to claim 11, further comprising: The quantization error generated by the SDM, Combining the quantization error with a digital-to-time converter (DTC) gain to generate a DTC control word; as well as A DTC clock CLKDTC is generated by the DTC based on CLKREF and the DTC control word as the clock input to the PD.

20. The method according to claim 19, wherein: Generating the quantization error comprises: doubling the frequency command word; performing sigma-delta modulation on the doubled frequency command word to generate a first quantization error; and The first quantization error is halved to output the quantization error.

21. The method of claim 20, further comprising performing VCO clock duty cycle error correction on the quantization error before combining with the DTC gain.

22. A multi-mode frequency divider MMDIV for a phase-locked loop (PLL) for fractional-N frequency synthesis, the multi-mode frequency divider comprising: A frequency divider configured to receive a differential input of a periodic signal from a voltage controlled oscillator VCO of the PLL, receive a frequency division sequence ratio from a sigma-delta modulator SDM of the PLL, and generate and output a clock signal; A first flip-flop, configured to receive the clock signal and a first differential input of the periodic signal, and to generate and output a first feedback clock CLKFB; a second flip-flop configured to receive the clock signal and a second differential input of the periodic signal, and to generate and output a second CLKFB; as well as A multiplexer is configured to receive the first CLKFB, the second CLKFB, and a selection control signal from the SDM, and output one of the first CLKFB and the second CLKFB as the CLKFB to the phase detector PD of the PLL based on the selection control signal.

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