Semiconductor device and method of forming the same

Abstract

The method includes: forming a seed layer over a first conductive component of a wafer, forming a patterned plating mask over the seed layer, and plating a second conductive component in an opening in the patterned plating mask. The plating includes performing multiple plating cycles, each plating cycle including a first plating process performed using a first plating current density and a second plating process performed using a second plating current density that is less than the first plating current density. Then, the patterned plating mask is removed and the seed layer is etched. Embodiments of the present application also relate to semiconductor devices and methods of forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] In the formation of integrated circuits, integrated circuit devices such as transistors are formed on the surface of a semiconductor substrate on a wafer. Then, an interconnect structure is formed above the integrated circuit device. A metal pad electrically coupled to the interconnect structure is formed above the interconnect structure. A passivation layer and a first polymer layer are formed above the metal pad, and the metal pad is exposed through an opening in the passivation layer and the first polymer layer.

[0003] Then, redistribution lines are formed to connect to the top surface of the metal pad, and then a second polymer layer is formed above the redistribution lines. A under-bump metal (UBM) layer is formed in an opening extending into the second polymer layer, where the UBM is electrically connected to the redistribution lines. Solder balls can be placed above the UBM and reflowed. Summary of the Invention

[0004] Some embodiments of the present application provide a method of forming a semiconductor device, including: forming a seed layer above a first conductive component of a wafer; forming a patterned plating mask above the seed layer; plating a second conductive component in an opening in the patterned plating mask, where the plating includes performing a plurality of plating cycles, and each of the plurality of plating cycles includes: a first plating process performed using a first plating current density; and a second plating process performed using a second plating current density less than the first plating current density; removing the patterned plating mask; and etching the seed layer.

[0005] Some other embodiments of the present application provide a semiconductor device, including: a first dielectric layer; redistribution lines including a portion located above the first dielectric layer, where the portion of the redistribution lines includes: a plurality of nanocolumns extending in a direction perpendicular to a main top surface of the first dielectric layer, and each of the plurality of nanocolumns further includes a plurality of nanoplatelets; and a second dielectric layer extending on sidewalls and a second top surface of the redistribution lines.

[0006] Some further embodiments of the present application provide a semiconductor device, including: a first passivation layer; redistribution lines including a seed layer and a conductive component located above the seed layer, where the conductive component includes: a via portion extending into the first passivation layer, where the via portion has a polycrystalline structure; a line portion, where the line portion includes a plurality of nanocolumns located above the via portion and the first passivation layer; and a second passivation layer extending on sidewalls and a top surface of the plurality of nanocolumns. Brief Description of the Drawings

[0007] When combined with the attached Figure 1As the reading begins, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for the sake of clear discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0008] Figures 1 to 15 A cross-sectional view showing an intermediate stage of device formation according to some embodiments is presented.

[0009] Figure 16 A schematic cross-sectional view showing a nanocolumn in a redistribution line according to some embodiments is presented.

[0010] Figure 17 A schematic cross-sectional view showing a nanocolumn and a corresponding nanoplate in the nanocolumn according to some embodiments is presented.

[0011] Figure 18 A cross-sectional view showing a nanoplate according to some embodiments is presented.

[0012] Figure 19A 、 Figure 19B 、 Figure 19C and Figure 19D A cross-sectional view showing an intermediate stage of nanoplate formation in a nanocolumn according to some embodiments is presented.

[0013] Figure 20 A top view showing a nanocolumn and a nanoplate in a redistribution line according to some embodiments is presented.

[0014] Figure 21 A top view showing two redistribution lines according to some embodiments is presented.

[0015] Figure 22 A process flow for forming a device according to some embodiments is presented. Detailed Description

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of the present invention. Specific examples of components and arrangements are described below to briefly illustrate the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first component and the second component are formed in direct contact, and may also include embodiments where additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. Additionally, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] Moreover, for ease of description, spatial relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientation shown in the figures, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0018] According to some embodiments, a device and a method of forming the same are provided. The device includes redistribution lines that include conductive components having a nanocolumn structure. The formation process of the conductive components may include a plating process, in which a high plating current and a low plating current are alternated in multiple plating cycles to form nanosheets. According to some embodiments, an intermediate stage of the formation process of a package is shown. Some variations of some embodiments are discussed. In the various views and illustrative embodiments, the same reference numerals are used to designate the same elements.

[0019] Figures 1 to 15 A cross-sectional view showing an intermediate stage of device formation according to some embodiments of the present invention is shown. The corresponding process is also schematically reflected in Process Flow 200 as shown in Figure 22 Although device wafers and device dies are used as examples, embodiments of the present invention may also be applied to the formation of conductive components in other devices (package components), including but not limited to package substrates, interposers, packages, etc.

[0020] Figure 1 A cross-sectional view of an integrated circuit device 20 is shown. According to some embodiments of the present invention, device 20 is a device wafer or includes a device wafer that includes active devices and possibly passive devices, represented as integrated circuit device 26. Device 20 may include a plurality of chips / dies 22, and one chip 22 is shown. According to some alternative embodiments of the present invention, device 20 is an interposer wafer that does not have active devices and may or may not include passive devices. According to some other alternative embodiments of the present invention, device 20 is a package substrate strip or includes a package substrate strip that includes a coreless package substrate or a core package substrate with a core. In the following discussion, a device wafer is used as an example of device 20, and device 20 may also be referred to as wafer 20. Embodiments of the present invention may also be applied to interposer wafers, package substrates, packages, etc.

[0021] According to some embodiments of the present invention, the wafer 20 includes a semiconductor substrate 24 and components formed on the top surface of the semiconductor substrate 24. The semiconductor substrate 24 may be formed of or contain the following materials: crystalline silicon, crystalline germanium, silicon germanium, carbon-doped silicon, or group III-V compound semiconductors such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, etc. The semiconductor substrate 24 may also be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. A shallow trench isolation (STI) region (not shown) may be formed in the semiconductor substrate 24 to isolate active regions in the semiconductor substrate 24. Although not shown, vias extending into the semiconductor substrate 24 may or may not be formed, and the vias are used to electrically couple components located on opposite sides of the wafer 20 to each other.

[0022] According to some embodiments of the present invention, the wafer 20 includes an integrated circuit device 26 formed on the top surface of the semiconductor substrate 24. According to some embodiments, the integrated circuit device 26 may include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. Details of the integrated circuit device 26 are not shown herein. According to some alternative embodiments, the wafer 20 is used to form an interposer (without active devices), and the substrate 24 may be a semiconductor substrate or a dielectric substrate.

[0023] An interlayer dielectric (ILD) 28 is formed above the semiconductor substrate 24 and fills the space between gate stacks of transistors (not shown) in the integrated circuit device 26. According to some embodiments of the present invention, the ILD 28 is formed of phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), silicon oxide, etc. The ILD 28 may be formed using spin coating, flowable chemical vapor deposition (FCVD), etc. According to some embodiments of the present invention, the ILD 28 is formed using a deposition method such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), etc.

[0024] Contact plugs 30 are formed in the ILD 28 and are used to electrically connect to the integrated circuit device 26 to cover metal lines and vias. According to some embodiments of the present invention, the contact plugs 30 contain or are formed of the following conductive materials: conductive materials selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, their alloys, and / or their multilayers. The formation of the contact plugs 30 may include forming contact openings in the ILD 28, filling the contact openings with a conductive material, and performing a planarization process (such as a chemical mechanical polishing (CMP) process or a mechanical grinding process) to make the top surface of the contact plugs 30 flush with the top surface of the ILD 28.

[0025] There is an interconnect structure 32 above the ILD 28 and the contact plug 30. The interconnect structure 32 includes metal lines 34 and vias 36 formed in a dielectric layer 38 (also referred to as an intermetal dielectric layer (IMD)). Metal lines at the same level are collectively referred to as metal layers hereinafter. According to some embodiments of the present invention, the interconnect structure 32 includes a plurality of metal layers, which include metal lines 34 interconnected by vias 36. The metal lines 34 and the vias 36 can be formed of copper or a copper alloy, or can be formed of other metals. According to some embodiments of the present invention, the dielectric layer 38 is formed of a low-k dielectric material. For example, the dielectric constant (k value) of the low-k dielectric material can be lower than about 3.0. The dielectric layer 38 can include a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. According to some embodiments of the present invention, the formation of the dielectric layer 38 includes depositing a pore-forming agent-containing dielectric material in the dielectric layer 38, and then performing a curing process to expel the pore-forming agent, and thus the remaining dielectric layer 38 is porous.

[0026] The formation of the metal lines 34 and the vias 36 in the dielectric layer 38 can include a single damascene process and / or a dual damascene process. In the single damascene process for forming a metal line or a via, first, a trench or a via opening is formed in one of the dielectric layers 38, and then the trench or the via opening is filled with a conductive material. Then, a planarization process such as a CMP process is performed to remove the excess conductive material above the top surface of the dielectric layer, leaving a metal line or a via in the corresponding trench or via opening. In the dual damascene process, trenches and via openings are formed in the dielectric layer, where the via openings are located below the trenches and connected to the trenches. Then, the conductive material is filled into the trenches and the via openings respectively to form metal lines and vias. The conductive material can include a diffusion barrier layer and a copper-containing metal material located above the diffusion barrier layer. The diffusion barrier layer can include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0027] The metal line 34 includes a top conductive (metal) component, such as a metal line, a metal pad, or a via (denoted as 34A) in the top dielectric layer (i.e., the top layer of the dielectric layer 38) (denoted as the dielectric layer 38A). According to some embodiments, the dielectric layer 38A is formed of a low-k dielectric material similar to the material of the underlying dielectric layer 38. According to other embodiments, the dielectric layer 38A is formed of a non-low-k dielectric material, which may include silicon nitride, undoped silicate glass (USG), silicon oxide, etc. The dielectric layer 38A may also have a multi-layer structure, for example, including two USG layers and a silicon nitride layer sandwiched therebetween. The top metal component 34A may also be formed of copper or a copper alloy and may have a dual-damascene structure or a single-damascene structure. According to some embodiments, the top metal component 34A has a polycrystalline structure. The dielectric layer 38A is sometimes referred to as the top dielectric layer. The top dielectric layer 38A and the dielectric layer 38 immediately below the top dielectric layer 38A may form a single continuous dielectric layer, or may be formed as different dielectric layers using different processes, and / or formed of materials different from each other.

[0028] A passivation layer 40 (referred to as passivation-1 or pass-1 in some cases) is formed over the interconnect structure 32. The corresponding process is shown as process 202 in process flow 200 as Figure 22 shown. According to some embodiments, the passivation layer 40 is formed of a non-low-k dielectric material having a dielectric constant greater than that of silicon oxide. The passivation layer 40 may contain or be formed of an inorganic dielectric material, which may include but is not limited to silicon nitride (SiN x ), silicon oxide (SiO2), silicon oxynitride (SiON x ), silicon oxycarbide (SiOC x ), silicon carbide (SiC), etc. and combinations or multi-layers thereof. "x" represents the relative atomic ratio. According to some embodiments, the top surface of the top dielectric layer 38A and the metal line 34A are coplanar. Accordingly, the passivation layer 40 may be a planar layer. According to some alternative embodiments, the top conductive component protrudes above the top surface of the top dielectric layer 38A, and the passivation layer 40 is uneven.

[0029] Refer to Figure 2 , the passivation layer 40 is patterned in an etching process to form an opening 42. The corresponding process is shown as process 204 in process flow 200 as Figure 22 shown. The etching process may include a dry etching process, which includes forming a patterned etching mask (not shown), such as a patterned photoresist, and then etching the passivation layer 40. Then the patterned etching mask is removed. The metal line 34A is exposed through the opening 42.

[0030] Figure 3 The deposition process of the metal seed layer 44 is shown. The corresponding process is shown as Figure 22Process 206 in the process flow 200 shown. According to some embodiments, the metal seed layer 44 includes a titanium layer and a copper layer above the titanium layer. According to some alternative embodiments, the metal seed layer 44 includes a copper layer in contact with the passivation layer 40. The deposition process can be performed using physical vapor deposition (PVD), chemical vapor deposition (CVD), metalorganic chemical vapor deposition (MOCVD), etc.

[0031] Figure 4 Shows the formation of the patterned plating mask 46. The corresponding process is shown as Figure 22 Process 208 in the process flow 200 shown. According to some embodiments, the plating mask 46 is formed of photoresist and can thus also be referred to as photoresist 46. Openings 48 are formed in the patterned plating mask 46 to expose the metal seed layer 44.

[0032] Figure 5 Shows the plating of the polycrystalline transition layer 50. The corresponding process is shown as Figure 22 Process 210 in the process flow 200 shown. According to some embodiments of the present invention, the formation of the polycrystalline transition layer 50 includes a plating process, which can include an electroless plating process. The plating is performed using a plating chemical solution, which can include a CuSO4 solution. Accordingly, the resulting polycrystalline transition layer 50 can contain or be formed of copper. The transition layer has multiple functions. First, the transition layer can be used as a seed layer for subsequent formation of the conductive component 52. Second, it can prepare a relatively flat top surface (compared to the opening 42) for subsequent plating processes.

[0033] According to some embodiments, the polycrystalline transition layer 50 has a polycrystalline structure including a plurality of grains. A relatively small plating current density J1 (e.g., in the range of about 0.1 amperes per square decimeter (ASD) to about 4 ASD) can be used to perform the formation of the polycrystalline transition layer 50. The duration for plating the polycrystalline transition layer 50 can range between about 2.5 seconds and about 80 seconds. According to some embodiments, the polycrystalline transition layer 50 completely fills the opening 42 and can have a relatively flat top surface as shown by the top surface 50TA. According to some embodiments, for example, when the opening 42 is relatively deep, the polycrystalline transition layer 50 can completely fill the opening 42 and there is substantially no deposition on the top layer of the high portion of the metal seed layer 44, which is above the top surface of the passivation layer 40. According to these embodiments, the top surface of the polycrystalline transition layer 50 is substantially at the position marked 50TB. According to some other alternative embodiments, the polycrystalline transition layer 50 has a non-flat top surface, which can be conformal or non-conformal, and the formation of the polycrystalline transition layer 50 stops before the opening 42 is completely filled. The corresponding top surface of the polycrystalline transition layer 50 can be represented as 50TC.

[0034] Figure 6Shows the plating of the conductive material (component) 52 in the opening 48 and on top of the polycrystalline transition layer 50. The corresponding process is shown as the process 212 in the process flow 200 as Figure 22 shown. The relevant detailed structure and formation process are in Figure 16 , Figure 17 , Figure 18 and Figures 19A to 19D wherein various views and processes are shown.

[0035] Figure 16 Shows Figure 6 a part of the structure shown. The part shown includes the conductive component 52, which further includes a plurality of nanocolumns 54. The nanocolumns 54 may have a lateral dimension LD1 (width or length) in the range of between about 200 nm and about 2,000 nm. The nanocolumns 54 are elongated in the vertical direction and form columns on the nanoscale, and thus are called nanocolumns 54. The nanocolumns 54 have clearly distinguishable edges, for example, observable through an X-ray diffraction (XRD) image or an electron backscatter diffraction (EBSD) image. The nanocolumns 54 may extend from the top surface of the polycrystalline transition layer 50 to the top surface of the conductive component 52, or in other ways (which will be discussed in detail in the subsequent paragraphs). The edges of the nanocolumns 54 are substantially vertical and may or may not be slightly curved or tilted, and the overall trend is upward.

[0036] Figure 17 Shows more details of some of the nanocolumns 54. Details of the middle section of the part shown are shown. For other parts, although the details are not shown, other parts may have a structure similar to the part shown. According to some embodiments, each nanocolumn 54 includes a plurality of nanoplates 56, which are stacked upward to form the nanocolumn. The nanoplates 56 have clearly distinguishable edges, for example, when observed with an XRD image or an EBSD image. In a cross-sectional view, the nanoplates 56 are elongated, and the lateral dimension LD1 is significantly larger than the corresponding thickness T1. For example, the ratio LD1 / T1 of the nanoplate 56 may be greater than 5 and may be in the range of between about 5 and 40, wherein the lateral dimension LD1 of the nanoplate 56 is also the lateral dimension of the nanocolumn 54 ( Figure 16)。According to some embodiments, the thickness T1 of the nanoplate 56 ranges between about 5 nm and about 400 nm, and the lateral dimension LD1 ranges between about 200 nm and about 2,000 nm. The thicknesses T1 of different nanoplates 56 can be the same or different from each other. For example, the ratio T1A / T1B (the thickness ratio between two adjacent nanoplates 56) can range between about 0.25 and about 80, and can also range between about 0.8 and about 8. The ratio T1A / T1B can also be equal to 1.0. In addition, in any nanowire 54, the ratio between the thickest nanoplate 56 and the thinnest nanoplate 56 can be less than about 80. Figure 17 Schematically shows that the top and bottom surfaces of the nanoplate 56 in a nanowire 54 can be flush with, higher than, or lower than (in a random manner) their top and bottom surfaces in adjacent nanowires 54 that are in contact with the nanoplate 56.

[0037] According to some embodiments, all nanowires 54 have a clearly distinguishable edge that contacts the edge of an adjacent nanowire (e.g., in an XRD image or an EBSD image). This edge is also substantially vertical. In other embodiments, most nanowires have a clearly distinguishable edge (the edge is substantially vertical) to separate them from adjacent nanowires, while a few (e.g., less than 5% or 1%) nanoplates 56 can extend into adjacent nanowires 54. For example, some nanoplates 56 located in two adjacent nanowires 54 can merge with each other, where there is no distinguishable edge separating them from each other.

[0038] Figure 18 Shows a cross-sectional view of an exemplary nanoplate 56 that is a larger grain than the grain 58. According to some embodiments, the nanoplate 56 has a polycrystalline structure that includes a plurality of grains 58. Each grain 58 has a crystal structure that is different from and / or misaligned with the crystal structures of its adjacent grains to form boundaries. The grains 58 within the nanoplate 56 can have different shapes and different sizes from each other. The boundaries of the grains 58 within the nanoplate 56 are irregular (random non-repeating patterns) and are not aligned with each other. However, the top surfaces of the top grains 58 within the nanoplate 56 are aligned with each other (coplanar) to form a flat surface and form a flat interface with the nanoplate 56 above it. For example, the height variation of the top surfaces of the top grains 58 is less than about 5% of the thickness T1 or less than about 2%. The bottom surfaces of the top grains 58 within the nanoplate 56 are also aligned with each other to form a flat surface. The bottom surfaces of the bottom grains 58 can also be coplanar, for example, their height variation is also less than about 5% of the thickness T1 or less than about 2%. The edges of the grains 50 on the sidewalls of the nanoplate 56 are also substantially aligned to form a substantially vertical edge, for example, the offset is less than about 10% of the thickness T1. Accordingly, in the cross-sectional view, the nanoplate 56 can have a rectangular shape and a clearly distinguishable boundary.

[0039] Most of the grains 58 may have the same lattice orientation, which may be the (111) crystal plane. According to some embodiments, more than 85 volume % of the grains 58 are (111)-oriented, while the remaining volume % of the grains 58 have other lattice orientations.

[0040] Figure 20 A top view of a partial conductive member 52 is shown, in which a plurality of nanocolumns 54 are adjacent to each other and joined to each other. The nanoplatelets 56 in the same nanocolumn 54 may have the same (or similar) top view shape and the same (or similar) top view size, which are also the top view shape and top view size of the corresponding nanocolumn 54 formed by the nanoplatelets 56, respectively.

[0041] As Figure 18 、 Figure 17 and Figure 16 shown, a plurality of grains 58 together form a polycrystalline nanoplatelet 56, which has a clear top surface, bottom surface, and edges formed by the alignment of the outer surfaces of the outer grains 58. A plurality of nanoplatelets 56 are stacked to form nanocolumns 54. A plurality of nanocolumns 54 are further arranged to form a conductive member 52. According to some embodiments, nanoplatelets are included in all of the nanocolumns 54. According to some alternative embodiments, nanoplatelets 56 are included in some of the nanocolumns 54 (e.g., more than 80% or 90%). These nanocolumns 54 are hereinafter referred to as stacked nanocolumns. Nanocolumns 54 that do not have stacked nanoplatelets 56 may or may not be present, and the corresponding nanocolumns 54 are hereinafter referred to as non-stacked nanocolumns 54. The non-stacked nanocolumns 54 also have a polycrystalline structure that includes a plurality of grains 58 (refer to Figure 18 ). However, the non-stacked nanocolumns 54 do not have a clear interface that divides the non-stacked nanocolumns 54 into stacked nanoplatelets. Instead, an irregular pattern of grains 58 is distributed throughout the non-stacked nanocolumns 54.

[0042] According to some embodiments, the non-stacked nanocolumns 54 extend from the top surface of the conductive member 52 all the way to the top surface of the polycrystalline transition layer 50, which has substantially the same structure as the non-stacked nanocolumns 54, so that these non-stacked nanocolumns 54 and the polycrystalline transition layer 50 merge without forming a clearly distinguishable interface. According to some alternative embodiments, some of the nanocolumns 54 are divided into upper and lower portions, and the upper portion may be a non-stacked nanocolumn 54, while the corresponding lower portion is a stacked nanocolumn, and vice versa.

[0043] According to some embodiments, Figure 19A 、 Figure 19B 、 Figure 19C and Figure 19DA cross-sectional view showing an intermediate stage of forming the nanoplate 56 and the corresponding nanocolumn 54 is shown. It should be understood that when forming the shown nanoplate 56 and nanocolumn 54, more nanoplates 56 and nanocolumns 54 are formed simultaneously, thereby forming the conductive component 52.

[0044] Reference Figure 19A , a polycrystalline transition layer 50 is formed, and the process thereof has been discussed with reference to Figure 5 . It should be understood that the polycrystalline transition layer 50 is shown as having an extension portion that extends beyond the shown nanoplate 56 and the corresponding nanocolumn 54. Other nanoplates 56 and nanocolumns 54 are also formed on the extension portion of the polycrystalline transition layer 50 (although not shown). As described above, the polycrystalline transition layer 50 is plated using a current density J1, which can range between approximately 0.1 ASD and approximately 4 ASD. Depending on the plating current density, when the plating current density is small, for example, close to approximately 0.1 ASD, the top surface of the polycrystalline transition layer 50 can be a flat top surface, where the top surfaces of the grains are coplanar and aligned with the same plane. When plating the polycrystalline transition layer 50 using a higher (e.g., higher than approximately 0.2 ASD) current density, the top surfaces of the grains in the polycrystalline transition layer 50 can have a rough (non-coplanar) surface. According to some embodiments, when the top surfaces of the grains in the polycrystalline transition layer 50 are non-coplanar, a smaller plating current density J2 can be applied to form the top surface of the polycrystalline transition layer 50 into a plane. According to some embodiments, the plating current J2 ranges between approximately 0.05 ASD and approximately 0.2 ASD. The plating time can range between approximately 5 seconds and approximately 15 seconds. The plating current J2 serves to form and planarize the top surface of the polycrystalline transition layer 50 through low-plating.

[0045] Next, multiple plating cycles are performed, and each plating cycle forms a nanoplate 56 (and other nanoplates 56 at the same level). The plating can be performed using the same (or different) plating solution as that used for plating the polycrystalline transition layer 50. According to some embodiments, an electroless plating process is used. Each plating cycle includes a high-current plating process and a subsequent low-current plating process. Figure 19A and Figure 19B shows one cycle. Referring to Figure 19A , a high-current plating process is performed on the nanoplate 56. The current density J3 of the high-current plating process can be higher than, equal to, or slightly less than the current density J1 used for plating the polycrystalline transition layer 50, and higher than the current density J2 used for planarizing the top surface of the polycrystalline transition layer 50. According to some embodiments, the current density J3 ranges between approximately 2.0 ASD and approximately 6.0 ASD. The high-current plating process can be performed for a duration of time TP1 that ranges between approximately 1 second and approximately 5 seconds.

[0046] As Figure 19AAs shown, the top surface of the nanoplate 56 is rough. Accordingly, the plating cycle further includes a small-current plating process for planarizing the top surface of the nanoplate 56. The small-current plating process is performed using a current density J4 that is less than the current density J3. The resulting nanoplate 56 is as Figure 19B shown. The current density J4 can also be less than the current density J1 used for plating the polycrystalline transition layer 50, and can be in the same range or equal to the current density J2 used for shaping and planarizing the top surface of the polycrystalline transition layer 50. According to some embodiments, the current density J4 is in the range of between about 0.05 ASD and about 0.2 ASD. The duration TP2 of the low-current plating can be in the range of between about 5 seconds and about 20 seconds. In the small-current plating process, although the thickness of the nanoplate 56 may increase, its main function is to cause more growth on the lower concave surface than on the convex top surface, such that the top surface of the resulting nanoplate 56 is planar.

[0047] According to some embodiments, the ratio of the currents J3 / J4 (which is also the ratio of the corresponding plating currents) can be in the range of between about 10 and about 40. The ratio TP2 / TP1 can be in the range of between about 2 seconds and about 10 seconds. Accordingly, the high-current plating process can be a high-current short-duration plating process, and the low-current plating process can be a low-current long-duration plating process. Thus, the plating process of the conductive member 52 includes an optional high-current short-duration plating process and a low-current long-duration plating process.

[0048] Figure 19C A second plating cycle is shown, whereby a second nanoplate 56 is formed on the first nanoplate 56. When performing this second plating cycle, substantially the same process conditions as those used for plating the first nanoplate 56 can be used. When plating the second nanoplate 56, the top surface of the first nanoplate 56 serves as the nucleus for growing the second nanoplate 56. Thus, the edges of the upper nanoplate 56 will grow along the edges of the corresponding lower nanoplate 56, such that the nanocolumns grow vertically. Since the top and bottom surfaces of the nanoplate 56 are aligned and planar, the interfaces between the nanoplates 56 are clearly distinguishable.

[0049] Referring to Figure 19D , multiple plating cycles are performed using the process conditions discussed in Figure 19A and Figure 19B , and thereby more nanosheets 56 are formed and stacked, thus forming the nanocolumns 54. As Figure 20 shown, Figure 20 is a top view of the nanocolumns 54, and all the nanocolumns 54 combined form the conductive member 52.

[0050] Next, the photoresist (plating mask) 46 shown in Figure 6 is removed, and the result is as shown in Figure 7The structure shown. In a subsequent process, an etching process is performed to remove portions of the metal seed layer 44 that are not protected by the overlying conductive component 52. The corresponding process is shown as the process 214 in the process flow 200 as shown in Figure 22 The resulting structure is as shown in Figure 8 Throughout the description, the conductive component 52, the polycrystalline transition layer 50, and the corresponding underlying metal seed layer 44 are collectively referred to as the redistribution line (RDL) 60, where the redistribution line (RDL) 60 includes RDL 60A and RDL 60B. Each RDL 60 may include a via portion 60V extending into the passivation layer 40 and a trace / line portion 60T located above the passivation layer 40.

[0051] Referring to Figure 9 , a passivation layer 62 is formed. The corresponding process is shown as the process 216 in the process flow 200 as shown in Figure 22 The passivation layer 62 (referred to as passivation-2 or pass-2 in some cases) is formed as a blanket layer. According to some embodiments, the passivation layer 62 may include or be formed of an inorganic dielectric material, which may include but is not limited to silicon nitride, silicon oxide, silicon oxynitride, silicon carbon oxide, silicon carbide, etc. and combinations or multiple layers thereof. The material of the passivation layer 62 may be the same as or different from the material of the passivation layer 40. The deposition may be performed by a conformal deposition process, such as atomic layer deposition (ALD), CVD, etc. Accordingly, the vertical and horizontal portions of the passivation layer 62 have the same thickness or substantially the same thickness, for example, the variation in thickness is less than about 20% or less than about 10%. It should be understood that regardless of whether the material forming the passivation layer 62 is the same as the passivation layer 40, a distinguishable interface may exist, which may be visible, for example, in a transmission electron microscope (TEM) image, an XRD image, or an EBSD image of the structure.

[0052] Figure 10 The formation of the planarization layer 64 is shown. The corresponding process is shown as the process 218 in the process flow 200 as shown in Figure 22 According to some embodiments of the present invention, the planarization layer 64 is formed of a polymer (which may be a photosensitive material) such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy resin, etc. According to some embodiments, forming the planarization layer 64 includes coating the planarization layer in a flowable form and then hardening the planarization layer 64 by baking. A planarization process such as a mechanical polishing process may be performed (or not performed) to make the top surface of the planarization layer 64 flush.

[0053] Referring to Figure 11 , the planarization layer 64 is patterned, for example, by an exposure process and a subsequent development process. The corresponding process is shown as the process in Figure 22Process 220 in the process flow 200 shown. Thus, an opening 66 is formed in the planarization layer 64, and the passivation layer 62 is exposed.

[0054] Figure 12 The patterning of the passivation layer 62 is shown to extend downward the opening 66. The corresponding process is shown as in Figure 22 Process 222 in the process flow 200 shown. According to some embodiments, the patterning process of the passivation layer 62 is performed using the patterned planarization layer 64 as an etch mask. According to some alternative embodiments, the patterning of the passivation layer 62 includes forming an etch mask such as photoresist (not shown), patterning the etch mask, and using the etch mask to etch the passivation layer 62 to define a pattern.

[0055] Figure 13 The deposition of the metal seed layer 68 is shown. The corresponding process is shown as in Figure 22 Process 224 in the process flow 200 shown. According to some embodiments, the metal seed layer 68 includes a titanium layer and a copper layer located above the titanium layer. According to some alternative embodiments, the metal seed layer 68 includes a copper layer in contact with the top surface of the planarization layer 64, the passivation layer 62, and the conductive component 52.

[0056] Next, the conductive region 70 is plated. The corresponding process is shown as in Figure 22 Process 226 in the process flow 200 shown. The process for plating the conductive region 70 may include forming a patterned plating mask (e.g., photoresist, not shown), and plating the conductive region 70 at the opening of the plating mask. Then the plating mask is removed, leaving a structure as in Figure 13 shown. The conductive region 70 may contain copper, nickel, palladium, aluminum, gold, their alloys, and / or their multilayers. The conductive region 70 may include a copper region covered with solder, and the copper region may be formed of materials such as SnAg.

[0057] Then the metal seed layer 68 is etched to remove the portion of the metal seed layer 68 that is exposed after the removal of the plating mask, thus leaving the portion of the metal seed layer 68 directly below the conductive region 70. The corresponding process is shown as in Figure 22 Process 228 in the process flow 200 shown. The resulting structure is as in Figure 14 shown. The remaining portion of the metal seed layer 68 is the under bump metallization layer (UBM) 68'. The UBM 68' and the conductive region 70 combine to form a via 74 and an electrical connection 72 (also referred to as a bump).

[0058] According to some embodiments, the combination of the via 74 and the electrical connector 72 includes a polycrystalline transition layer 71 and a conductive component 73 located above the polycrystalline transition layer 71. The structure and formation method of the polycrystalline transition layer 71 can be substantially the same as those of the polycrystalline transition layer 50, and will not be described repeatedly here. The conductive component 73 may include nanocolumns 75, which may further include nanoplatelets 77 therein, where the nanoplatelets 77 are schematically drawn as one of the nanocolumns 75, while they can still be formed in other nanocolumns 75, although not shown. The structure and formation method of the conductive component 73 can be substantially the same as those of the conductive component 52, and will not be described repeatedly here. The details of the structures and formation processes of the nanocolumns 75 and the nanoplatelets 77 can be substantially the same as those of the nanocolumns 54 and the nanoplatelets 56 respectively, which are referred to Figure 17 , Figure 18 , Figure 19A , Figure 19B , Figure 19C , Figure 19D and Figure 20 for discussion.

[0059] According to some embodiments, as described above, the via 74 and the electrical connector 72 include nanocolumns and nanoplatelets. Accordingly, the via 74 and the electrical connector 72 also have the function of redistributing stress, thereby further reducing delamination between components such as the underlying passivation layer and RDL. According to some alternative embodiments, when the RDL 60 (with nanocolumns and nanoplatelets) is sufficient to redistribute stress and the risk of delamination is low, the via 74 and the electrical connector 72 can be formed, for example, by applying a uniform plating current density, to reduce manufacturing costs and increase production. The resulting via 74 and electrical connector 72 may not have nanocolumns and nanoplatelets. According to corresponding embodiments, the electrical connector 72 and the via 74 can have an amorphous structure. According to yet another alternative embodiment, the electrical connector 72 and the via 74 can have a polycrystalline structure. The polycrystalline structure can have a random pattern that does not form nanoplatelets and nanocolumns.

[0060] In subsequent processes, the wafer 20 is diced, for example, sawed along the cutting line 76, to form individual device dies 22. The corresponding process is shown as process 230 in the process flow 200 as shown in Figure 22 . The device die 22 is also referred to as the device 22 or the package component 22, because the device 22 can be used to engage with other package components to form a package. As described above, the device 22 can be a device die, an interposer, a package substrate, a package, etc.

[0061] Referring to Figure 15 , the device 22 is engaged with the package component 78 to form the package 84. The corresponding process is shown as in Figure 22Process 232 in the process flow 200 shown. According to some embodiments, the encapsulation component 78 is or includes an interposer, an encapsulation substrate, a printed circuit board, or a package, etc. The electrical connector 72 in the encapsulation component 78 can be joined to the encapsulation component 78 through the solder region 80. Underfill 82 is dispensed between the device 22 and the encapsulation component 78.

[0062] Figure 15 Two RDLs 60 are shown, also denoted as RDL 60A and 60B. According to some embodiments, RDL 60A is used to electrically connect the electrical connector 72 to the underlying integrated circuit device 26. On the other hand, RDL 60B is not connected to any upper electrical connector, but is used for internal electrical redistribution so as to make electrical connections to components within the device 22. For example, the opposite ends of RDL 60B can be connected to two metal lines 34A( Figure 15 and Figure 21 ). In other words, RDL 60B is entirely covered by the passivation layer 62, and all sidewalls of RDL 60B can be in contact with the passivation layer 62.

[0063] According to some embodiments, Figure 21 A top view of exemplary RDL 60A and 60B is shown. Each of RDL 60A and 60B includes a conductive component 52. As Figure 20 shown, the top view can be Figure 21 a view of the region 86 in Figure 15 . The via 74 (also refer to Figure 15 ) is located above the top surface of RDL 60A and is joined to the top surface. The opposite ends of RDL 60B can be connected to two underlying metal lines 34A through vias 60V. Accordingly, RDL 60B serves as an internal redistribution line.

[0064] Embodiments of the present invention have some advantageous features. By forming nanocolumns (the nanocolumns include nanoplates having a horizontal interface), the stress transferred from other encapsulation components is more likely to be distributed laterally along the horizontal interface and less likely to be transferred downward through grain boundaries that can extend in random directions. Accordingly, delamination between the RDL and its adjacent components (such as the passivation layer) is reduced. In addition, the nanoplate in the nanocolumn has the effect of confining copper atoms on the nanoplate and preventing electromigration.

[0065] According to some embodiments of the present invention, the method includes: forming a seed layer over a first conductive component of a wafer; forming a patterned plating mask over the seed layer; plating a second conductive component in an opening in the patterned plating mask, wherein the plating includes performing a plurality of plating cycles, each of the plurality of plating cycles including: performing a first plating process using a first plating current density; and performing a second plating process using a second plating current density less than the first plating current density; removing the patterned plating mask; and etching the seed layer. In an embodiment, the first plating process and the second plating process are configured to form a plurality of nanocolumns, each of the plurality of nanocolumns including a plurality of stacked nanoplatelets. In an embodiment, each of the plurality of stacked nanoplatelets includes a plurality of grains. In an embodiment, the first plating process is performed for a first time period, and the second plating process is performed for a second time period longer than the first time period. In an embodiment, the ratio of the first plating current density to the second plating current density ranges between about 10 and about 40. According to some embodiments of the present invention, the method further includes depositing a passivation layer over the second conductive component; forming a planarization layer over the passivation layer; etching through the planarization layer and the passivation layer; and forming a third conductive component extending into the planarization layer and the passivation layer to electrically connect to the second conductive component. In an embodiment, the method further includes plating a polycrystalline transition layer over the seed layer before plating the second conductive component, wherein there are no nanocolumns in the polycrystalline transition layer. In an embodiment, the polycrystalline transition layer is plated using a third plating current density higher than the second plating current density.

[0066] According to some embodiments of the present invention, the device includes: a first dielectric layer; a redistribution line including a portion located over the first dielectric layer, wherein the portion of the redistribution line includes: a plurality of nanocolumns extending in a direction perpendicular to a main top surface of the first dielectric layer, wherein each of the plurality of nanocolumns further includes a plurality of nanoplatelets; and a second dielectric layer extending over sidewalls and a second top surface of the redistribution line. In an embodiment, the plurality of nanocolumns are separated from each other by vertical boundaries. In an embodiment, the plurality of nanoplatelets are separated from each other by horizontal interfaces. In an embodiment, each of the plurality of nanoplatelets includes a plurality of grains. In an embodiment, more than 85 volume % of the grains in the portion of the redistribution line have a (111) crystal orientation. In an embodiment, the plurality of nanocolumns include copper. In an embodiment, the redistribution line further includes non-stacked nanocolumns, and there are no nanoplatelets in the non-stacked nanocolumns. In an embodiment, the redistribution line further includes: a seed layer; and a polycrystalline transition layer located above the seed layer and below the plurality of nanocolumns, wherein there are no nanocolumns in the polycrystalline transition layer. In an embodiment, both the plurality of nanocolumns and the polycrystalline transition layer include copper.

[0067] According to some embodiments of the present invention, a device includes: a first passivation layer; a redistribution line including a seed layer and a conductive component located above the seed layer, wherein the conductive component includes: a via portion extending into the first passivation layer, wherein the via portion has a polycrystalline structure; a line portion, wherein the line portion includes a plurality of nanocolumns located above the via portion and the first passivation layer; and a second dielectric layer extending on sidewalls and top surfaces of the plurality of nanocolumns. In an embodiment, bottoms of the plurality of nanocolumns are higher than all top surfaces of the seed layer and higher than additional top surfaces of the first passivation layer. In an embodiment, each of the plurality of nanocolumns further includes stacked nanoplates.

[0068] Some embodiments of the present application provide a method, including: forming a seed layer above a first conductive component of a wafer; forming a patterned plating mask above the seed layer; plating a second conductive component in an opening in the patterned plating mask, wherein the plating includes performing a plurality of plating cycles, and each of the plurality of plating cycles includes: a first plating process performed using a first plating current density; and a second plating process performed using a second plating current density less than the first plating current density; removing the patterned plating mask; and etching the seed layer. In some embodiments, the first plating process and the second plating process are configured to form a plurality of nanocolumns, and each of the plurality of nanocolumns includes a plurality of stacked nanoplates. In some embodiments, each of the plurality of stacked nanoplates includes a plurality of grains, and each of the plurality of stacked nanoplates is a grain larger than the corresponding plurality of grains therein, and each of the plurality of stacked nanoplates includes distinct grain boundaries. In some embodiments, the first plating process is performed for a first time period, the second plating process is performed for a second time period longer than the first time period, and a ratio of the first plating current density to the second plating current density is in a range between about 10 and about 40. In some embodiments, the first plating process performed using the first plating current density and the second plating process performed using the second plating current density are alternating. In some embodiments, the method further includes: depositing a passivation layer above the second conductive component; depositing a planarization layer above the passivation layer; etching through the planarization layer and the passivation layer; and forming a third conductive component extending into the planarization layer and the passivation layer to make electrical connection with the second conductive component. In some embodiments, the method further includes, before plating the second conductive component, plating a polycrystalline transition layer on the seed layer, wherein there are no nanocolumns in the polycrystalline transition layer. In some embodiments, a third plating current density higher than the second plating current density is used to plate the polycrystalline transition layer.

[0069] Some other embodiments of the present application provide a device, comprising: a first dielectric layer; a redistribution line, including a portion located above the first dielectric layer, wherein the portion of the redistribution line includes: a plurality of nanocolumns, extending in a direction perpendicular to the main top surface of the first dielectric layer, wherein each of the plurality of nanocolumns further includes a plurality of nanoplates; and a second dielectric layer, extending on the sidewalls and the second top surface of the redistribution line. In some embodiments, the plurality of nanocolumns are separated from each other by vertical boundaries. In some embodiments, the plurality of nanoplates are separated from each other by horizontal interfaces. In some embodiments, each of the plurality of nanoplates includes a plurality of grains, and each of the plurality of nanoplates is a grain larger than the corresponding plurality of grains therein, and each of the plurality of nanoplates includes distinct grain boundaries. In some embodiments, more than 85% by volume of the grains in the portion of the redistribution line have a (111) crystal orientation. In some embodiments, the plurality of nanocolumns include copper. In some embodiments, the redistribution line further includes non-stacked nanocolumns, and there are no nanoplates in the non-stacked nanocolumns. In some embodiments, the redistribution line further includes: a seed layer; and a polycrystalline transition layer, located above the seed layer and below the plurality of nanocolumns, wherein there are no nanocolumns in the polycrystalline transition layer. In some embodiments, both the plurality of nanocolumns and the polycrystalline transition layer include copper.

[0070] Some further embodiments of the present application provide a device, comprising: a first passivation layer; a redistribution line, including a seed layer and a conductive component located above the seed layer, wherein the conductive component includes: a via portion, extending into the first passivation layer, wherein the via portion has a polycrystalline structure; a line portion, wherein the line portion includes a plurality of nanocolumns located above the via portion and the first passivation layer; and a second passivation layer, extending on the sidewalls and the top surface of the plurality of nanocolumns. In some embodiments, the bottom surfaces of the plurality of nanocolumns are higher than all the top surfaces of the seed layer and higher than the additional top surface of the first passivation layer. In some embodiments, each of the plurality of nanocolumns further includes stacked nanoplates.

[0071] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes or structures so as to achieve the same purposes and / or realize the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations can be made thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming a semiconductor device, comprising: forming a seed layer over a first conductive component of a wafer; forming a patterned plating mask over the seed layer; plating a second conductive component in an opening in the patterned plating mask, wherein the plating includes performing a plurality of plating cycles, each of the plurality of plating cycles including: a first plating process performed using a first plating current density; and a second plating process performed using a second plating current density less than the first plating current density; removing the patterned plating mask; and etching the seed layer.

2. The method according to claim 1, wherein The first plating process and the second plating process are configured to form a plurality of nanocolumns, each of the plurality of nanocolumns including a plurality of stacked nanoplatelets.

3. The method according to claim 2, wherein, Each of the plurality of stacked nanoplatelets includes a plurality of grains, and each of the plurality of stacked nanoplatelets is a grain larger than the corresponding plurality of grains therein, and each of the plurality of stacked nanoplatelets includes distinct grain boundaries.

4. The method according to claim 1, wherein, The first plating process is performed for a first period of time, the second plating process is performed for a second period of time longer than the first period of time, and wherein the ratio of the first plating current density to the second plating current density ranges between 10 and 40.

5. The method according to claim 1, wherein, The first plating process performed using the first plating current density and the second plating process performed using the second plating current density are alternating.

6. The method according to claim 1, further comprising: depositing a passivation layer over the second conductive component; depositing a planarization layer over the passivation layer; etching through the planarization layer and the passivation layer; and forming a third conductive component extending into the planarization layer and the passivation layer to make electrical connection with the second conductive component.

7. The method according to claim 1 further includes, before plating the second conductive component, plating a polycrystalline transition layer on the seed layer, wherein, There are no nanocolumns in the polycrystalline transition layer.

8. The method according to claim 7, wherein The polycrystalline transition layer is plated using a third plating current density higher than the second plating current density.

9. A semiconductor device, comprising: a first dielectric layer; a redistribution line including a portion located over the first dielectric layer, wherein the portion of the redistribution line includes: a plurality of nanocolumns extending in a direction perpendicular to a main top surface of the first dielectric layer, wherein each of the plurality of nanocolumns further includes a plurality of nanoplatelets; and a second dielectric layer extending over sidewalls and a second top surface of the redistribution line; Each of the plurality of nanoplatelets includes a plurality of grains, and each of the plurality of nanoplatelets is a grain larger than the corresponding plurality of grains therein, and each of the plurality of nanoplatelets includes distinct grain boundaries.

10. The semiconductor device according to claim 9, wherein, The plurality of nanocolumns are separated from each other by vertical boundaries.

11. The semiconductor device according to claim 9, wherein, The plurality of nanoplatelets are separated from each other by horizontal interfaces.

12. The semiconductor device according to claim 9, wherein, The plurality of grains within the nanoplatelets have different shapes and different sizes from each other.

13. The semiconductor device according to claim 9, wherein, More than 85 volume % of the grains in the portion of the redistribution line have a (111) crystal orientation.

14. The semiconductor device according to claim 9, wherein, The plurality of nanocolumns include copper.

15. The semiconductor device according to claim 9, wherein, The redistribution line further includes non-stacked nanocolumns, and there are no nanoplatelets in the non-stacked nanocolumns.

16. The semiconductor device according to claim 9, wherein, The redistribution line further includes: a seed layer; and A polycrystalline transition layer, located above the seed layer and below the plurality of nanocolumns, wherein there are no nanocolumns in the polycrystalline transition layer.

17. The semiconductor device according to claim 16, wherein, Both the plurality of nanocolumns and the polycrystalline transition layer include copper.

18. A semiconductor device, comprising: A first passivation layer; A redistribution line, comprising a seed layer and a conductive component located above the seed layer, wherein the conductive component comprises: A via portion extending into the first passivation layer, wherein the via portion has a polycrystalline structure; A line portion, wherein the line portion comprises a plurality of nanocolumns located above the via portion and the first passivation layer; and A second passivation layer extending on sidewalls and top surfaces of the plurality of nanocolumns.

19. The semiconductor device according to claim 18, wherein, Bottom surfaces of the plurality of nanocolumns are higher than all top surfaces of the seed layer and higher than additional top surfaces of the first passivation layer.

20. The semiconductor device according to claim 18, wherein, Each of the plurality of nanocolumns further comprises stacked nanoplatelets.

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