Method of manufacturing a semiconductor device and semiconductor device

Abstract

In a method of manufacturing a semiconductor device, a sacrificial pattern is formed over a hard mask layer disposed over a substrate, a sidewall pattern is formed on sidewalls of the sacrificial pattern, the sacrificial pattern is removed, thereby leaving the sidewall pattern as a first hard mask pattern, the hard mask layer is patterned by using the first hard mask pattern as an etch mask, thereby forming a second hard mask pattern, and the substrate is patterned by using the second hard mask pattern as an etch mask, thereby forming a fin structure. Each of the first sacrificial patterns has a tapered shape with a top smaller than a bottom. Embodiments of the present application also relate to a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to a method of manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] As the semiconductor industry enters nanotechnology process nodes in pursuit of higher device density, higher performance, lower power consumption, and lower cost, challenges from manufacturing and design issues have led to the development of three-dimensional designs such as fin field-effect transistors (Fin FETs). In Fin FET devices, additional sidewalls can be utilized and short-channel effects can be suppressed. Summary of the Invention

[0003] Some embodiments of the present application provide a method of manufacturing a semiconductor device, including: forming a sacrificial pattern over a hard mask layer disposed over a substrate; forming a sidewall pattern on sidewalls of the sacrificial pattern; removing the sacrificial pattern, thereby leaving the sidewall pattern as a first hard mask pattern; patterning the hard mask layer by using the first hard mask pattern as an etching mask, thereby forming a second hard mask pattern; and patterning the substrate by using the second hard mask pattern as an etching mask, thereby forming a fin structure, wherein each of the first sacrificial patterns has a tapered shape, and a top of the tapered shape is smaller than a bottom.

[0004] Some other embodiments of the present application provide a method of manufacturing a semiconductor device, including: forming a first hard mask layer over a substrate; forming a sacrificial layer over the hard mask layer; forming a second hard mask layer over the sacrificial layer; forming a first hard mask pattern by patterning the second hard mask layer; forming a sacrificial pattern by patterning the sacrificial layer by using the first hard mask pattern as an etching mask, each of the sacrificial patterns having a tapered shape; forming a sidewall pattern on sidewalls of the sacrificial pattern; removing the sacrificial pattern, thereby retaining the sidewall pattern as a second hard mask pattern; removing a part of the second hard mask pattern; after removing the part of the second hard mask pattern, patterning the hard mask layer by using a remaining part of the second hard mask pattern as an etching mask, thereby forming a third hard mask pattern; and patterning the substrate by using the third hard mask pattern as an etching mask, thereby forming a fin structure.

[0005] Some other embodiments of the present application provide a semiconductor device, including: a first fin field-effect transistor including a first pair of fin structures and a first gate electrode; and a second fin field-effect transistor including a second pair of fin structures and a second gate electrode, wherein a difference between a width of the first pair of fin structures and a width of the second pair of fin structures is 0.01 - 0.1 nm. Brief Description of the Drawings

[0006] As will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, for the sake of clear discussion, the dimensions of the various components can be increased or decreased arbitrarily.

[0007] Figure 1 、 Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 and Figure 18 illustrate cross-sectional views of the various stages of a sequential manufacturing operation for a semiconductor device in accordance with an embodiment of the present invention.

[0008] Figure 19 、 Figure 20 、 Figure 21 、 Figure 22 and Figure 23 illustrate cross-sectional views of the various stages of a sequential manufacturing operation for a semiconductor device in accordance with an embodiment of the present invention.

[0009] Figure 24A 、 Figure 24B 、 Figure 24C 、 Figure 24D and Figure 24E illustrate cross-sectional views of the various stages of a sequential manufacturing operation of a semiconductor device in accordance with an embodiment of the present invention.

[0010] Figure 25 illustrates a cross-sectional view of one of the various stages of a sequential manufacturing operation for a semiconductor device in accordance with an embodiment of the present invention.

[0011] Figure 26 illustrates a cross-sectional view of one of the various stages of a sequential manufacturing operation for a semiconductor device in accordance with an embodiment of the present invention.

[0012] Figure 27A and Figure 27B illustrates a cross-sectional view of one of the various stages of a sequential manufacturing operation for a semiconductor device in accordance with an embodiment of the present invention.

[0013] Figure 28 、 Figure 29 and Figure 30A cross-sectional view showing one of the various stages of a sequential manufacturing operation for a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, the dimensions of the elements are not limited to the disclosed ranges or values, but may depend on process conditions and / or the desired properties of the device. In addition, in the following description, forming a first component above or on a second component may include embodiments where the first component and the second component are formed in direct contact, and may also include embodiments where additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. In addition, for simplicity and clarity, the various components may be arbitrarily drawn in different proportions.

[0015] Moreover, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientation shown in the figures, the spatially relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Additionally, the term "made of" may mean "comprising" or "consisting of".

[0016] The fin structures for FinFETs are fabricated by various patterning methods. For example, when the critical dimension (CD) of the fin structure is reduced to less than 20 nm, it is generally difficult to directly form a pattern with such a small size by a single optical lithography process, and some fine patterning processes have been developed. For example, double patterning or multiple patterning processes can be used to pattern the fin structures. Generally, the double patterning or multiple patterning processes combine lithography and self-alignment processes, thereby allowing the creation of patterns having, for example, a pitch smaller than the pitch obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer, typically referred to as a mandrel pattern, is formed over the substrate and patterned using a lithography process. A spacer is formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacer can then be used to pattern the fin structure. This operation can be repeated to fabricate the desired fin pattern.

[0017] Figures 1 to 18 Stages of a sequential manufacturing process of a semiconductor FinFET device according to an embodiment of the present invention are shown. It should be understood that it can be in Figure 1 and Figure 18Provide additional operations before, during, and after the process shown, and some of the operations described below may be replaced or eliminated in additional embodiments of the method. In some embodiments, the order of the operations may be changed.

[0018] As Figure 1 shown, a plurality of layers for a hard mask are formed over a substrate 10 to pattern the substrate 10 into fin structures. In some embodiments, the substrate 10 is a silicon substrate. Optionally, the substrate 10 may include another elemental semiconductor, such as germanium; compound semiconductors, including: group IV-IV compound semiconductors such as SiC and SiGe, group III-V compound semiconductors such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0019] In some embodiments, a first layer 11 is formed over the substrate 10. In some embodiments, the first layer 11 is a pad oxide layer formed by, for example, a thermal oxidation process or a chemical vapor deposition (CVD) process. In some embodiments, the thickness of the first layer 11 is in the range of about 1 nm to about 5 nm. Additionally, in some embodiments, a second layer 12 made of a material different from the first layer 11 is formed over the first layer 11. In some embodiments, the second layer 12 is a second liner layer or a hard mask layer, including, for example, silicon nitride formed by, for example, a CVD or atomic layer deposition (ALD) process. In some embodiments, the thickness of the second layer 12 is in the range of about 2 nm to about 20 nm.

[0020] Furthermore, in some embodiments, a third layer 13 made of a material different from the second layer 12 is formed over the second layer 12. In some embodiments, the third layer 13 is a hard mask layer formed by, for example, a CVD process. In some embodiments, the third layer 13 includes silicon oxide, SiON, SiOC, SiOCN, aluminum oxide, or any other suitable material. In some embodiments, the thickness of the third layer 13 is in the range of about 5 nm to about 30 nm. In some embodiments, the third layer 13 is made of the same or different material as the first layer 11.

[0021] Then, in some embodiments, a fourth layer 14 made of a material different from the third layer 13 is formed over the third layer 13. In some embodiments, the fourth layer 14 is a sacrificial layer for a mandrel pattern formed, for example, by a CVD process. In some embodiments, the fourth layer 14 includes amorphous or polycrystalline Si, SiGe or Ge, silicon oxide, SiOC, SiON, SiOCN, or any other suitable material. In certain embodiments, undoped polysilicon is used as the fourth layer 14. In some embodiments, the thickness of the fourth layer 14 ranges from about 5 nm to about 30 nm. Further, in some embodiments, a fifth layer 15 made of a material different from the fourth layer 14 is formed over the fourth layer 14. In some embodiments, the fifth layer 15 is a hard mask layer formed, for example, by a CVD process. In some embodiments, the fifth layer 15 includes silicon oxide, silicon nitride, SiON, SiOC, SiOCN, or any other suitable material. In certain embodiments, silicon nitride is used as the fifth layer 15. In some embodiments, the thickness of the fifth layer 15 ranges from about 4 nm to about 20 nm.

[0022] Then, in some embodiments, an organic bottom anti-reflective coating (BARC) layer 16 is formed over the fifth layer 15, and a photoresist layer is formed over the BARC layer 16. Then, the photoresist layer is patterned by using a lithography operation to form a photoresist pattern 17, as Figure 1 shown. In some embodiments, according to the design requirements, the width W1 of the photoresist pattern 17 ranges from about 20 nm to about 100 nm, and the pitch S1 ranges from about 30 nm to about 200 nm. In some embodiments, the pitch S1 is greater than the width W1.

[0023] Then, the BARC layer 16 is patterned by using the photoresist pattern 17 as an etch mask, and the fifth layer 15 is patterned by using the patterned BARC layer 16 (and the photoresist pattern 17) as an etch mask to form a first hard mask pattern 15A. Then, by using the first hard mask pattern 15A, the fourth (sacrificial) layer 14 is patterned by using one or more plasma dry etch operations to form a mandrel pattern 14A, as Figure 3 shown. Then, as Figure 2 shown, the first hard mask pattern 15A is removed by wet and / or dry etching, as Figure 3 shown.

[0024] In some embodiments, the etching of the fourth layer 14 is a tapered etch operation that forms a trapezoidal cross-sectional shape with a top smaller than the bottom, as Figure 2 and Figure 3 shown. The effect of the trapezoidal shape will be described later.

[0025] Then, asFigure 4 As shown, a sixth layer 18 for sidewall spacers is conformally formed on the mandrel pattern 14A and the exposed third layer 13. In some embodiments, the sixth layer 18 is made of a material different from the mandrel pattern 14A and the third layer 13, and includes silicon nitride, SiON, SiCN, or any other suitable material. In certain embodiments, the silicon nitride layer serves as the sixth layer 18. In some embodiments, the thickness of the sixth layer 18 ranges from about 5 nm to about 15 nm, and in other embodiments from about 7 nm to about 12 nm, depending on design requirements and / or process requirements. In some embodiments, the sixth layer 18 is formed by an ALD process.

[0026] Next, as Figure 5 shown, an anisotropic etch is performed on the sixth layer 18 to remove the horizontal portions of the sixth layer 18 deposited on top of the mandrel pattern 14A and on the third layer 13 between adjacent mandrel patterns 14A. Due to the anisotropic etch, as Figure 5 shown, the sixth layer 18 remains as sidewall spacers 18A disposed on opposite sides of the mandrel pattern 14A.

[0027] Then, as Figure 6 shown, the mandrel pattern 14A is removed by one or more dry and / or wet etch operations, leaving the sidewall spacers 18A as the second hard mask pattern. As Figure 6 shown, due to the trapezoidal shape of the mandrel pattern 14A, the second hard mask pattern 18A extends substantially vertically. The effect of the trapezoidal shape will be described later. As Figure 6 shown, the mandrel spacer MS is the spacer from which the mandrel pattern 14A has been removed and is formed by the left sidewall 18A-L and the right sidewall 18A-R, while the spacer spacer SS is the spacer in which no mandrel pattern 14A is present and is formed by the right sidewall 18A-R and the left sidewall 18A-L. In some embodiments, the width and / or spacing of the mandrel pattern 14A and / or the thickness of the sixth layer 18 are adjusted or set such that the second hard mask pattern 18A has a substantially constant pitch. In some embodiments, the variation in pitch is greater than zero and less than about 0.5 nm. In some embodiments, the spacing between the second hard mask patterns 18A at the mandrel spacer MS is greater than the spacing between the second hard mask patterns 18A at the spacer spacer SS, and in other embodiments, the spacing between the second hard mask patterns 18A at the mandrel spacer MS is less than the spacing between the second hard mask patterns 18A at the spacer spacer SS.

[0028] Next, as Figure 7As shown, a mask pattern such as a photoresist pattern 19 is formed over the second hard mask pattern 18A, and portions of the second hard mask pattern are removed and the second hard mask pattern is sliced into pieces through one or more etching operations. As will be described later, the sliced second hard mask pattern 18A corresponds to a fin structure used in a FinFET. After the etching operation, as Figure 8 shown, the mask pattern 19 is removed. In some embodiments, the remaining hard mask pattern 18A constitutes a core spacer MS, as Figure 8 shown. Further, in some embodiments, an isolated second hard mask pattern 18A ( Figure 8 the rightmost pattern in

[0029] ) is included, and the spacing between the second hard mask pattern and an adjacent hard mask pattern is greater than the spacing of the core spacer MS and / or the spacer spacing SS.

[0029] Then, as Figure 9 shown, an optional additional hard mask layer 18B is conformally formed over the second hard mask layer 18A to adjust the thickness (width) of the second hard mask layer 18A. In some embodiments, the additional hard mask layer 18B is made of the same or a similar material as the second hard mask layer 18A and includes silicon nitride, SiON, SiCN, or any other suitable material formed by an ALD process. In some embodiments, silicon nitride is used as the additional hard mask layer 18B. In some embodiments, the thickness of the additional hard mask layer 18B ranges from about 1 nm to about 2 nm. In some embodiments, after forming the additional hard mask layer 18B, anisotropic etching is performed to remove the horizontal portions of the deposited additional hard mask layer 18B.

[0030] In Figure 10 , the combination of the second hard mask pattern 18A and the additional hard mask layer 18B is shown as a hard mask pattern 18C. Then, as Figure 11 shown, the third layer 13 is patterned through one or more plasma dry etches by using the hard mask pattern 18C as an etch mask, thereby forming a third hard mask pattern 13A. Then, the hard mask pattern 18C is removed through one or more dry and / or wet etching operations.

[0031] In addition, by using the third hard mask pattern 13A as an etch mask, the second layer 12 is patterned by one or more plasma dry etches to form a fourth hard mask pattern 12A. In some embodiments, after the patterning operation, an additional hard mask layer 13B is conformally formed over the third hard mask pattern 13A and the fourth hard mask pattern 12A to adjust the thickness (width) of the hard mask pattern. In some embodiments, the additional hard mask layer 13B is made of the same or a similar material as the third hard mask layer 13A and includes silicon oxide, SiON, SiOC, or any other suitable material formed by an ALD process. In certain embodiments, silicon oxide is used as the additional hard mask layer 13B. In some embodiments, the thickness of the additional hard mask layer 13B is in the range of about 0.5 nm to about 2 nm. In some embodiments, after forming the additional hard mask layer 13B, anisotropic etching is performed to remove the horizontal portions of the deposited additional hard mask layer 13B.

[0032] Then, using the hard mask pattern 13A and / or 12A as an etch mask, the first layer 12 and the substrate 10 are patterned by one or more plasma dry etches to form a fin structure 20 as Figure 13 shown. In some embodiments, after the patterning etch, the hard mask pattern 12A and the patterned first layer 11A remain on top of each fin structure 20. In some embodiments, the hard mask pattern 13A is removed during and / or after the patterning of the substrate 10.

[0033] Then, an insulating layer 30L for the isolation insulating layer is formed to completely cover the fin structure, as Figure 14As shown. The insulating layer 30L includes one or more insulating material layers, such as insulating materials formed by LPCVD (low-pressure chemical vapor deposition), plasma CVD, or flowable CVD, such as silicon oxide, silicon oxynitride, or silicon nitride. In flowable CVD, a flowable dielectric material is deposited instead of silicon oxide. As the name implies, the flowable dielectric material can "flow" during deposition to fill gaps or spaces with a high aspect ratio. Generally, various chemicals are added to the silicon-containing precursor to allow the deposited film to flow. In some embodiments, nitrogen-hydrogen bonds are added. Examples of flowable dielectric precursors (particularly, flowable silicon oxide precursors) include silicates, siloxanes, methylsilsesquioxane (MSQ), hydrogen silsesquioxane (HSQ), mixtures of MSQ and HSQ, perhydrosilazane (TCPS), perhydro-polysilazane (PSZ), tetraethyl orthosilicate (TEOS), or silylamines (such as trimethylsilylamine (TSA)). These flowable silicon oxide materials are formed in multiple processing steps. After depositing the flowable film, the flowable film is cured and then annealed to remove undesirable elements to form silicon oxide. The flowable film can be doped with boron and / or phosphorus. In some embodiments, the insulating layer 30L can be formed of one or more layers of spin-on glass (SOG), SiO, SiON, SiOCN, and / or fluorine-doped silicate glass (FSG).

[0034] In some embodiments, one or more fin liner layers (not shown) are conformally formed on the fin structure 20 before forming the insulating layer 30L. In some embodiments, the fin liner layer includes a first layer and a second layer made of a material different from the first layer. In some embodiments, the fin liner layer is formed of silicon nitride or a silicon nitride-based material (e.g., silicon oxynitride, silicon carbonitride, or silicon carbon oxynitride) and a silicon oxide-based material (e.g., silicon oxide or silicon carbon oxide). In some embodiments, the thickness of each of the first fin liner layer and the second fin liner layer is in the range of about 1 nm to about 5 nm.

[0035] Then, as Figure 15 shown, one or more planarization operations, such as an etch-back operation or a chemical mechanical polishing (CMP) operation, are performed to expose the hard mask pattern 12A. Subsequently, as Figure 16 shown, the hard mask pattern 12A is removed by one or more wet and / or dry etching operations.

[0036] Furthermore, as Figure 17 shown, the insulating layer 30L is recessed to form an isolation insulating layer 30 as a shallow trench isolation (STI). As Figure 17As shown, the upper portion 20U of the fin structure protrudes from the isolation insulating layer 30, and the lower portion 20B of the fin structure is embedded in the isolation insulating layer 30. In some embodiments, the patterned first layer 11A is removed during or after the recess etching. When forming the fin liner layer, the fin liner layer is also recessed during and / or after the recessing of the insulating layer 30L.

[0037] After forming the fin structure 20, a sacrificial gate structure is formed over the channel region of the fin structure, a source / drain epitaxial layer is formed at the source / drain regions of the fin structure, and one or more dielectric layers 60 are formed over the sacrificial gate structure and the source / drain epitaxial layer. Further, as Figure 18 shown, the sacrificial gate structure is replaced with a metal gate structure. In some embodiments, the metal gate structure 80 includes a gate dielectric layer 82 and one or more conductive layers 84. In some embodiments, the gate dielectric layer 82 includes one or more dielectric material layers, such as silicon oxide, silicon nitride, or a high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconia, alumina, titanium oxide, hafnium oxide-aluminum oxide (HfO2-Al2O3) alloy, La2O3, HfO2-La2O3, Y2O3, Dy2O3, Sc2O3, MgO, or other suitable high-k dielectric materials and / or combinations thereof.

[0038] In some embodiments, the conductive layer 84 includes a barrier layer, one or more work function adjustment layers, a glue layer, and a bulk metal layer. In some embodiments, the barrier layer includes a metal nitride, such as WN, TaN, TiN, and TiSiN. In some embodiments, the work function adjustment layer includes WN, WCN, TiAlN, AlN, TaN, TiN, TiSiN, Ru, W, TaAlC, TiC, TaAl, TaC, Co, Al, TiAl, or TiAlC, or a multi-layer of two or more of these materials. In some embodiments, the glue layer is made of one or more of TiN, Ti, and Co. In some embodiments, the bulk metal layer includes one or more conductive material layers, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, WCN, Ru, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloy, other suitable materials, and / or combinations thereof.

[0039] Figures 19 to 23 Stages of a sequential manufacturing process of a semiconductor FinFET device according to an embodiment of the present invention are shown. It should be understood that it is possible to Figures 19 to 23Additional operations are provided before, during, and after the process shown, and in additional embodiments of the method, some of the operations described below may be replaced or eliminated. The order of operations may be changed. The materials, configurations, processes, and / or dimensions described with reference to the above embodiments may be applied to the following embodiments, and their detailed descriptions may be omitted.

[0040] Figure 19 and Figure 20 with Figure 5 and Figure 6 are the same. In some embodiments, in the fin cutting operation described with reference to Figure 7 the remaining second hard mask pattern 18A forms one or more mandrel spacer patterns MS and one or more spacer spacer patterns SS, as Figure 21 shown. Subsequently, the operations described with reference to Figures 9 to 13 are performed to form a fin structure 20 as Figure 22 shown. In addition, the operations described with reference to Figures 14 to 18 are performed to form an isolation insulating layer 30 and a metal gate structure, as Figure 23 shown.

[0041] Figures 24A to 24E Shows the various stages of a sequential manufacturing process of a semiconductor FinFET device according to another embodiment of the present invention. It should be understood that additional operations may be provided before, during, and after the process shown, and in additional embodiments of the method, some of the operations described below may be replaced or eliminated. The order of operations may be changed. The materials, configurations, processes, and / or dimensions described with reference to the above embodiments may be applied to the following embodiments, and their detailed descriptions may be omitted. Figures 24A to 24E shown.

[0042] In another embodiment, as Figure 24A shown, the mandrel pattern 14A' has a substantially rectangular cross-section with substantially vertical sides. Then, similar to Figure 4 , the sixth layer 18 is conformally formed on the mandrel pattern 14A' and the exposed third layer 13. Next, similar to Figure 5 , anisotropic etching is performed on the sixth layer 18' to remove the horizontal portions of the sixth layer 18 deposited on the top of the mandrel pattern 14A' and on the third layer 13 between adjacent mandrel patterns. Then, similar to Figure 6 , the mandrel pattern 14A' is removed by one or more dry and / or wet etching operations, leaving the sidewall spacer 18A as the second hard mask pattern, as Figure 24C shown. Figure 24D Shows a cross-sectional view after a fin cutting process as described with reference to Figure 7 and Figure 8 shown.

[0043] Here, due to the intrinsic stress of the material of the sixth layer 18 (sidewall spacer 18A) and / or the stress difference between the sixth layer 18 and the mandrel pattern 14A', after removing the mandrel pattern 14A', the sidewall spacer 18A tilts in different (opposite) directions, as Figure 24C shown. For example, when viewed from left to right, the even-numbered sidewall spacers tilt to the right, and the odd-numbered sidewall spacers tilt to the left, thereby forming a narrower top spacing in the spacer spacing SS and a wider top spacing in the mandrel spacing MS. When the top spacing is wider, more of the additional hard mask layer 18B is deposited in the mandrel spacing MS, which results in a thicker sidewall spacer.

[0044] In some embodiments, when the sidewall spacer 18A (second hard mask pattern) tilts, when patterning the third layer 13 into a hard mask layer, the etching rates between the mandrel spacing MS and the spacer spacing SS can be different from each other, such that the sizes (widths) of the patterned hard mask layers are different. In other embodiments, the deposition amounts of the additional hard mask layer 18A (see Figure 9 ) can be different from each other on the second hard mask pattern 18A in the mandrel spacing MS and the spacer spacing SS, thereby making the sizes (widths) of the patterned hard mask layers different, in some embodiments. For example, the deposition amount on the second hard mask pattern 18A on the side facing the mandrel spacing MS with a wider top spacing is greater than the deposition amount on the second hard mask pattern 18A on the side facing the spacer spacing SS with a narrower top spacing. This makes the pattern width of the second hard mask pattern 18A constituting the mandrel spacing MS wider than that of the second hard mask pattern 18A constituting the spacer spacing SS. Therefore, the fin structures 20 formed by the operations described with reference to Figures 9 to 13 have different widths W11 and W12, where W11 > W12.

[0045] In some embodiments, the width of the fin structure formed by the sidewall spacer 18A constituting the mandrel spacing MS is greater than the width of the fin structure formed by the sidewall spacer 18A constituting the spacer spacing SS. In some embodiments, the width variation between the fin structure formed by the mandrel spacing MS and the fin structure formed by the spacer spacing SS is about 0.3 - 0.5 nm. In addition, the width variation within the fin structure formed by the mandrel spacing MS or the fin structure formed by the spacer spacing SS is about 7 - 10% of the average width, respectively.

[0046] In an embodiment, as described with reference to Figures 1 to 23 , the mandrel pattern 14A has a trapezoidal cross-section with inclined sides, as Figure 2 and Figure 3 shown, and the trapezoidal shape compensates for the tilt of the sidewall spacer 18A caused by the intrinsic stress. Thus, as Figure 6 andFigure 20 As shown, when the mandrel pattern is removed, the second hard mask pattern 18A extends substantially perpendicular to the third layer (in the vertical direction), thereby suppressing the width variation of the fin structure 20. In some embodiments, in Figures 18 to 23 the case of, the width variation between the fin structures formed by the mandrel spacer MS and the fin structures formed by the spacer spacer SS is about 0.01 - 0.1 nm in some embodiments and about 0.04 - 0.07 nm in other embodiments. In addition, the width variation within the fin structures formed by the mandrel spacer MS or the fin structures formed by the spacer spacer SS is about 0.5% to 3% of the average width. In some embodiments, the average width ranges from about 8 nm to 10 nm. In some embodiments, the width of the fin structure is measured at the level of the upper surface of the isolation insulating layer 30.

[0047] Figure 25 is a line graph of a TEM (transmission electron microscope) image of the mandrel pattern 14A. In some embodiments, the sidewall of the mandrel pattern 14A is defined between 10% and 90% of the total height H1 of the mandrel pattern and is linearly fitted within this height range. In some embodiments, the sidewall tilt angle θ1 between the fitted line of the sidewall and the vertical line ranges from about 5 degrees to about 15 degrees and from about 6 degrees to about 10 degrees in other embodiments. When the sidewall tilt angle θ1 is outside this range, the sidewall spacer 18A may undesirably tilt, which may cause fin width variation.

[0048] In some embodiments, the width ratio of 10% of H1 to 90% of H1 ranges from about 1.3 to about 1.5, and the width ratio of 50% of H1 to 90% of H1 ranges from about 1.1 to about 1.3. When the ratio of the widths is outside this range, the sidewall spacer 18A may undesirably tilt, which may cause fin width variation.

[0049] Figure 26is a line graph of a TEM image of the second hard mask pattern 18A. In some embodiments, the sidewall of the second hard mask pattern 18A is defined between 10% (starting from the bottom most) and 90% of the total height H2 of the second hard mask pattern and is fitted by a straight line within this height range. In some embodiments, the sidewall tilt angle θ2 between the fitted line of the sidewall and the vertical line is in the range of about -10 degrees (tilted left (towards the core axis spacing MS)) to about 5 degrees (tilted right (towards the spacer spacing SS)), and in other embodiments in the range of about -7 degrees to about -1 degree. In other embodiments, the tilt angle θ2 is in the range of about 1 degree to 7 degrees (e.g., 4 - 6 degrees) towards the spacer spacing. In some embodiments, the sidewall tilt angle θ2 is not zero. When the sidewall tilt angle θ2 is outside this range, the sidewall spacer 18A may undesirably tilt, which may cause fin width variations. As Figure 26 shown, in some embodiments, the third layer 13 is etched more in the spacer spacing 22 than in the core axis spacing MS. In some embodiments, the third layer 13 can be etched during the removal etch of the core pattern 14A. In some embodiments, as Figure 26 shown, depending on the tilt angle θ2, the amount of etching of the third layer 13 in the core axis spacing MS is less than the amount of etching of the third layer 13 in the spacer spacing SS. In other embodiments, the amount of etching of the third layer 13 in the core axis spacing MS is greater than the amount of etching of the third layer 13 in the spacer spacing SS.

[0050] Figure 27A and Figure 27B are line graphs of TEM images of the fin structure 20 corresponding to Figure 13 and Figure 22 respectively.

[0051] As described above, the width of the fin structure formed by the core axis spacing MS is substantially the same as the width of the fin structure formed by the spacer spacing SS. Due to the use of the trapezoidal core pattern 14A, the difference in width is in the range of about 0.2% to about 1.2%.

[0052] In some embodiments, the depth of the spacing between adjacent fin structures can vary depending on whether the spacing is the core axis spacing MS or the spacer spacing SS. In some embodiments, the depth D1 of the core axis spacing MS is less than the depth D2 of the spacer spacing SS, as Figure 27B shown. In some embodiments, D2 / D1 is in the range of about 1.03 to about 1.05. In other embodiments, the depth D1 is greater than the depth D2. In some embodiments, the depth difference can depend on the tilt angle θ2.

[0053] In addition, in the present embodiment, the second hard mask pattern 18A is designed to have a pitch P0 at the mandrel pitch MS and the spacer pitch SS (i.e., in the layout design). In some embodiments, the depth D0 between second hard mask patterns (pitches other than the mandrel pitch MS and the spacer pitch) having a pitch greater than P0 (e.g., 2P0, 3P0, …) is greater than the depths D1 and D2. In some embodiments, D0 / D1 or D0 / D2 is in the range of about 1.05 to about 1.15.

[0054] Figures 28 to 30 Shows the various stages of a sequential manufacturing process of a semiconductor FinFET device according to an embodiment of the present invention. It should be understood that additional operations may be provided before, during, and after the Figures 28 to 30 process shown, and in additional embodiments of the method, some of the operations described below may be replaced or eliminated. The order of operations may be changed. The materials, configurations, processes, and / or dimensions described with reference to the above embodiments may be applied to the following embodiments, and their detailed descriptions may be omitted.

[0055] In some embodiments, depending on the material of the sixth layer 18 and / or the mandrel pattern 14A, after removing the mandrel pattern, due to the internal stress difference, the sidewall spacers 18A are inclined in a direction opposite to the Figure 22 direction shown. For example, when viewed from left to right, an even number of sidewall spacers are inclined to the left, and an odd number of sidewall spacers are inclined to the right, thereby forming a narrower top pitch in the mandrel pitch MS and a wider top pitch in the spacer pitch SS.

[0056] Therefore, in the Figures 28 to 30 embodiment, in order to compensate for the subsequent pattern tilt, the mandrel pattern 14A” has an inverted conical shape with a wider top and a smaller bottom, as Figure 28 shown. Then, as Figure 29 shown, the sixth layer 18 is conformally formed on a mandrel pattern 14A” similar to the Figure 4 one. By referring to the Figures 5 - 6 operations described, a second hard mask pattern 18A that extends substantially vertically can be obtained.

[0057] In some embodiments, the tilt angle θ3 is in the range of about 5 degrees to about 15 degrees in some embodiments, and in the range of about 6 degrees to about 10 degrees in other embodiments. The definition of the tilt angle θ3 is the same as that of the tilt angle θ1 except for the angle measurement direction.

[0058] In some embodiments, after removing the mandrel pattern 14A, the taper angle is adjusted by a feedback operation based on the measurement of the tilt angle of the second hard mask pattern 18A. When the second hard mask pattern 18A tilts beyond the target tilt (standard) such that the top spacing in the mandrel spacing MS is wider than the top spacing in the spacer spacing, the taper angle (tilt angle) θ1 increases, and when the second hard mask pattern 18A tilts beyond the target tilt such that the top spacing in the mandrel spacing MS is less than the top spacing in the spacer spacing, the taper angle (tilt angle) θ1 decreases. The taper angle of the mandrel pattern 14A can be controlled by controlling one or more of the etching gas species, the flow rate of the etching gas, the process pressure, the process temperature, and / or the etching power (e.g., high-frequency power and / or DC bias power).

[0059] The various embodiments or examples described herein provide several advantages over the prior art. For example, in the present invention, the mandrel pattern has a tapered shape to compensate for the tilt of the sidewall spacer (second hard mask pattern) after removing the mandrel pattern, and thus the variation in the width of the fin structure patterned using the hard mask pattern formed by the sidewall spacer can be reduced.

[0060] It should be understood that not all advantages need to be discussed herein, that no particular advantage is required for all embodiments or examples, and that other embodiments or examples may provide different advantages.

[0061] According to one aspect of the present invention, in a method of manufacturing a semiconductor device, a sacrificial pattern is formed over a hard mask layer disposed over a substrate, a sidewall pattern is formed on sidewalls of the sacrificial pattern, the sacrificial pattern is removed, thereby leaving the sidewall pattern as a first hard mask pattern, the hard mask layer is patterned by using the first hard mask pattern as an etch mask, thereby forming a second hard mask pattern, and the substrate is patterned by using the second hard mask pattern as an etch mask, thereby forming a fin structure. Each of the first sacrificial patterns has a tapered shape with a top smaller than a bottom. In one or more of the foregoing and following embodiments, the sacrificial pattern is made of polysilicon. In one or more of the foregoing and following embodiments, the first hard mask pattern is made of silicon nitride. In one or more of the foregoing and following embodiments, the first hard mask pattern is inclined. In one or more of the foregoing and following embodiments, an inclination angle of the first hard mask pattern with respect to a spacer from which a corresponding one of the sacrificial patterns is removed is 1 to 7 degrees. In one or more of the foregoing and following embodiments, an inclination angle of the first hard mask pattern with respect to a spacer where no sacrificial pattern is formed is 1 to 7 degrees. In one or more of the foregoing and following embodiments, a taper angle of the sacrificial pattern is in a range of 5 degrees to 15 degrees. In one or more of the foregoing and following embodiments, the hard mask layer includes a plurality of dielectric material layers. In one or more of the foregoing and the following embodiments, a blanket layer is conformally formed by atomic layer deposition, and anisotropic etching is performed to remove a horizontal portion of the blanket layer, thereby forming the sidewall pattern.

[0062] According to another aspect of the present invention, in a method of manufacturing a semiconductor device, a first hard mask layer is formed over a substrate, a sacrificial layer is formed over the first hard mask layer, a second hard mask layer is formed over the sacrificial layer, a first hard mask pattern is formed by patterning the second hard mask layer, a sacrificial pattern is formed by patterning the sacrificial layer using the first hard mask pattern as an etching mask pattern, a sidewall pattern is formed on sidewalls of the sacrificial pattern, the sacrificial pattern is removed so that the sidewall pattern remains as a second hard mask pattern, a part of the second hard mask pattern is removed, after removing the part of the second hard mask pattern, the hard mask layer is patterned by using the second hard mask pattern as an etching mask so as to form a third hard mask pattern, and the substrate is patterned by using the third hard mask pattern as an etching mask so as to form a fin structure. Each first sacrificial pattern has a tapered shape. In one or more of the foregoing and following embodiments, an additional hard mask layer is further formed over the second hard mask layer. In one or more of the foregoing and following embodiments, an additional hard mask layer is further formed over the third hard mask layer. In one or more of the foregoing and following embodiments, the first hard mask layer includes a first layer formed on the substrate, a second layer formed on the first layer and made of a material different from that of the first layer, and a third layer formed on the second layer and made of a material different from that of the second layer. In one or more of the foregoing and following embodiments, the first layer and the third layer are made of the same material. In one or more of the foregoing embodiments and following embodiments, the second hard mask pattern includes a first pair and a second pair, a corresponding one of the sacrificial patterns is removed from the first pair, and there is no sacrificial pattern between the second pair. A width of a fin structure corresponding to the first pair is different from a width of a fin structure corresponding to the second pair. In one or more of the foregoing and following embodiments, a depth of a space between adjacent fin structures corresponding to the first pair is different from a depth of a space between adjacent fin structures corresponding to the second pair.

[0063] According to another aspect of the present invention, in a method of manufacturing a semiconductor device, a sacrificial pattern is formed over a hard mask layer disposed over a substrate, a sidewall pattern is formed on sidewalls of the sacrificial pattern, the sacrificial pattern is removed, thereby leaving the sidewall pattern as a first hard mask pattern, the hard mask layer is patterned by using the first hard mask pattern as an etch mask, thereby forming a second hard mask pattern, and the substrate is patterned by using the second hard mask pattern as an etch mask, thereby forming a fin structure. Each first sacrificial pattern has a tapered shape, and a taper angle is adjusted such that an inclination angle of the first hard mask pattern is within a standard. In one or more of the foregoing and following embodiments, each first sacrificial pattern has a tapered shape, and a top of the tapered shape is smaller than a bottom. In one or more of the foregoing embodiments and following embodiments, an inclination angle of the first hard mask pattern with respect to a spacer from which a corresponding one of the sacrificial patterns is removed is 1 to 7 degrees. In one or more of the foregoing embodiments and following embodiments, an inclination angle of the first hard mask pattern with respect to a spacer where no sacrificial pattern is formed is 1 to 7 degrees.

[0064] According to another aspect of the present invention, a semiconductor device includes a first fin field effect transistor and a second fin field effect transistor. The first fin field effect transistor includes a first pair of fin structures and a first gate electrode disposed over the first pair of fin structures. The second fin field effect transistor includes a second pair of fin structures and a second gate electrode disposed over the second pair of fin structures. A difference between a width of the first pair of fin structures and a width of the second pair of fin structures is 0.01 to 0.1 nm. In one or more of the foregoing and following embodiments, a depth D1 of a spacer between the first pair of fin structures starting from a top of the first pair of fin structures is different from a depth D2 of a spacer between the second pair of fin structures starting from a top of the second pair of fin structures. In one or more of the foregoing and following embodiments, a ratio D2 / D1 is in a range of 1.03 to 1.05. In one or more of the foregoing and following embodiments, a distance by which the first pair of fin structures and the second pair of fin structures are separated is greater than a spacer between the first pair of fin structures.

[0065] Features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructs do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present invention.

Claims

1. A method of manufacturing a semiconductor device, comprising: forming a sacrificial pattern over a hard mask layer disposed over a substrate; forming sidewall patterns on sidewalls of the sacrificial pattern, wherein a spacer gap is defined between the sidewall patterns on opposite sidewalls of adjacent sacrificial patterns; removing the sacrificial pattern, thereby leaving the sidewall patterns as a first hard mask pattern and the gap formed by removing the sacrificial pattern as a mandrel gap; removing a portion of the first hard mask pattern such that the remaining spacer gaps and mandrel gaps are spaced apart, and a space formed by removing one of the first hard mask patterns exists between adjacent spacer gaps and mandrel gaps; patterning the hard mask layer by using the first hard mask pattern as an etch mask, thereby forming a second hard mask pattern; and patterning the substrate by using the second hard mask pattern as an etch mask, thereby forming a fin structure, wherein each sacrificial pattern has an inverted conical shape with a top larger than a bottom.

2. The method according to claim 1, wherein The sacrificial pattern is made of polysilicon.

3. The method according to claim 2, wherein, The first hard mask pattern is made of silicon nitride.

4. The method according to claim 3, wherein, The first hard mask pattern is inclined with respect to a direction perpendicular to an upper surface of the substrate.

5. The method according to claim 4, wherein, The first hard mask pattern has an inclination angle of 1 - 7 degrees with respect to a gap from which a corresponding sacrificial pattern is removed.

6. The method according to claim 4, wherein, The first hard mask pattern has an inclination angle of 1 - 7 degrees with respect to a gap where no sacrificial pattern is formed.

7. The method according to claim 1, wherein The cone angle of the sacrificial pattern is in a range of 5 degrees to 15 degrees.

8. The method according to claim 1, wherein The hard mask layer includes a plurality of dielectric material layers.

9. The method according to claim 1, wherein The sidewall patterns are formed by conformally forming a blanket layer by atomic layer deposition and performing anisotropic etching to remove a horizontal portion of the blanket layer.

10. A method of manufacturing a semiconductor device, comprising: forming a first hard mask layer over a substrate; forming a sacrificial layer over the first hard mask layer; forming a second hard mask layer over the sacrificial layer; forming a first hard mask pattern by patterning the second hard mask layer; forming sacrificial patterns by patterning the sacrificial layer by using the first hard mask pattern as an etch mask pattern, each sacrificial pattern having an inverted conical shape; forming sidewall patterns on sidewalls of the sacrificial patterns, wherein a spacer gap is defined between the sidewall patterns on opposite sidewalls of adjacent sacrificial patterns; removing the sacrificial patterns, thereby leaving the sidewall patterns as a second hard mask pattern and the gaps formed by removing the sacrificial patterns as mandrel gaps; removing a portion of the second hard mask pattern such that the remaining spacer gaps and mandrel gaps are spaced apart, and a space formed by removing one of the second hard mask patterns exists between adjacent spacer gaps and mandrel gaps; after removing a portion of the second hard mask pattern, patterning the hard mask layer by using a remaining portion of the second hard mask pattern as an etch mask, thereby forming a third hard mask pattern; and patterning the substrate by using the third hard mask pattern as an etch mask, thereby forming a fin structure.

11. The method according to claim 10, wherein, An additional hard mask layer is formed over the second hard mask layer.

12. The method according to claim 10, wherein, An additional hard mask layer is formed over the third hard mask pattern.

13. The method according to claim 10, wherein The first hard mask layer includes a first layer formed on the substrate, a second layer formed on the first layer and made of a material different from that of the first layer, and a third layer formed on the second layer and made of a material different from that of the second layer.

14. The method according to claim 13, wherein, The first layer and the third layer are made of the same material.

15. The method according to claim 10, wherein: The second hard mask pattern includes a first pair of pattern structures and a second pair of pattern structures, with a corresponding one of the sacrificial patterns removed from the first pair of pattern structures, no sacrificial pattern existing between the second pair of pattern structures, and The width of the fin structure corresponding to the first pair of pattern structures is different from the width of the fin structure corresponding to the second pair of pattern structures.

16. The method according to claim 15, wherein, The depth of the space between adjacent fin structures corresponding to the first pair of pattern structures is different from the depth of the space between adjacent fin structures corresponding to the second pair of pattern structures.

17. A semiconductor device includes: A first fin field effect transistor including a first pair of fin structures and a first gate electrode; A second fin field effect transistor including a second pair of fin structures and a second gate electrode, wherein the difference between the width of each fin structure in the first pair of fin structures and the width of each fin structure in the second pair of fin structures is 0.01 - 0.1 nm, and the depth D1 of the space between the first pair of fin structures starting from the top of the first pair of fin structures is different from the depth D2 of the space between the second pair of fin structures starting from the top of the second pair of fin structures.

18. The semiconductor device according to claim 17 further comprises: A first metal gate structure located above the first pair of fin structures and a second metal gate structure located above the second pair of fin structures.

19. The semiconductor device according to claim 17, wherein, The ratio D2 / D1 is in the range of 1.03 to 1.

05.

20. The semiconductor device according to claim 17, wherein, The distance by which the first pair of fin structures and the second pair of fin structures are separated is greater than the space between the first pair of fin structures.

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