Display device and method for driving display device

Abstract

This disclosure relates to a display device and a method for driving the display device. The display device includes: a display unit including a first display area and a second display area; a scan driver configured to provide a scan signal to each scan line connected to a plurality of first pixels and a plurality of second pixels; and an emission controller configured to provide an emission control signal to each emission control line connected to the plurality of first pixels and a plurality of second pixels, wherein the plurality of first pixels have a first density in the first display area, the plurality of second pixels have a second density in the second display area that is less than the first density, and the plurality of second pixels include at least one sub-pixel, the sub-pixel including a boost capacitor.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2020-0029685, filed on March 10, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Some exemplary embodiments of this disclosure relate to a display device and a method of driving the display device. Background Technology

[0003] Display devices, such as those in general-purpose smartphones, may include at least one display area. The display area may be a data output device, and input data may be displayed on the display area. Furthermore, the display area may be equipped with a touch sensor and can operate as a touchscreen. Such a display area may be used on the front surface of the display device to display various information.

[0004] Recently, in display devices such as mobile terminals, since the display area occupies most of the front surface, camera devices, proximity sensors, fingerprint recognition sensors, lighting sensors, near-infrared sensors, etc., can overlap with at least one area of ​​the display area.

[0005] In recent years, flat panel display devices, such as liquid crystal displays (LCDs), plasma display panels (PDPs), or organic light-emitting diode (OLEDs), have been most commonly used as image display devices.

[0006] The information disclosed in this background section is only intended to enhance understanding of the background, and therefore the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0007] Some aspects of example embodiments of this disclosure include a display device and a method of driving the display device, which can easily adjust the brightness of pixels in a display area where sensors and the like overlap.

[0008] Some exemplary embodiments of this disclosure are not limited to the features described above, and other technical features not described will be more clearly understood by those skilled in the art through the following description.

[0009] A display device according to some example embodiments of the present disclosure for achieving the above-described objectives includes: a display unit including a first display area having a plurality of first pixels and a second display area having a plurality of second pixels; a data driver configured to provide a data signal to each data line connected to the plurality of first pixels and the plurality of second pixels; a scan driver configured to provide a scan signal to each scan line connected to the plurality of first pixels and the plurality of second pixels; and an emission controller configured to provide an emission control signal to each emission control line connected to the plurality of first pixels and the plurality of second pixels. The plurality of first pixels have a first density in the first display area, the plurality of second pixels have a second density in the second display area that is less than the first density, and the plurality of second pixels includes at least one sub-pixel, the sub-pixel of the plurality of second pixels including a boost capacitor connected between a node electrically connected to the gate electrode of each driving transistor and the emission control line.

[0010] According to some example implementations, a plurality of first pixels may include at least one sub-pixel, the sub-pixel of the plurality of first pixels including a first boost capacitor connected between the node to which the gate electrode of each driving transistor is connected and the scan line, and at least one sub-pixel of a plurality of second pixels including a first boost capacitor and a second boost capacitor as a boost capacitor.

[0011] According to some example implementations, in the sub-pixels of a plurality of second pixels, the capacitance of the second boost capacitor may be greater than the capacitance of the first boost capacitor.

[0012] According to some example implementations, a boost capacitor may include a first electrode formed on a component electrically connected to a transmit control line and a second electrode formed on a component electrically connected to the gate electrode of a drive transistor.

[0013] According to some example implementations, at least one sub-pixel may also include another boost capacitor, which includes a third electrode formed on a component electrically connected to the scan line and a fourth electrode formed on a component electrically connected to the gate electrode of the driving transistor.

[0014] According to some example implementations, a first electrode may be formed on a first gate electrode layer, a second electrode may be formed on a first source-drain electrode layer, and the first source-drain electrode layer may be located on the first gate electrode layer.

[0015] According to some example implementations, the first gate electrode layer may include an emitter control line, and the first source-drain electrode layer may include an electrode pattern electrically connected to the node, and define an overlapping region in the electrode pattern that overlaps with the emitter control line.

[0016] According to some example implementations, the gate electrode and the emitter control line can be physically separated from each other.

[0017] According to some example implementations, a plurality of first pixels may not include a boost capacitor.

[0018] The display device may further include a second gate electrode layer on the first gate electrode layer and a second source-drain electrode layer on the first source-drain electrode layer, and the first source-drain electrode layer may be located on the second gate electrode layer.

[0019] According to some example implementations, the driving transistor may be a P-type transistor.

[0020] According to some example implementations, the display device may also include a sensor that overlaps with the second display area.

[0021] According to some example implementations, the first density can be 4 to 16 times greater than the second density.

[0022] A method for driving a display device according to some example embodiments of the present disclosure for achieving the above-described objectives, the display device including a first display area having a plurality of first pixels with a first density and a second display area having a plurality of second pixels with a second density less than the first density, includes: during a frame initialization period, initializing the gate electrode of a driving transistor or the anode of a light-emitting element of one of the plurality of first pixels or the plurality of second pixels; during a data writing period following the initialization period, writing a data signal to the first electrode of the driving transistor; and during a transmission period following a delay period and the data writing period, emitting light by the light-emitting elements of the plurality of first pixels and the plurality of second pixels. The voltage level of the gate electrodes of the plurality of first pixels decreases to a first level during the transmission period, and the voltage level of the gate electrodes of the plurality of second pixels decreases to a second level greater than the first level during the transmission period.

[0023] According to some example implementations, the voltage level of the gate electrodes of a plurality of first pixels may be increased by a third level during a delay period, and the voltage level of the gate electrodes of a plurality of second pixels may be increased by a fourth level less than the third level during a delay period.

[0024] According to some example implementations, each of the plurality of first pixels and the plurality of second pixels may include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor as driving transistors. The first electrode of the first transistor may be connected to the fifth transistor, the second electrode of the first transistor may be connected to the sixth transistor, the gate electrode of the first transistor may be connected to a first node, the second transistor may be connected between a data line and the first electrode of the first transistor, the gate electrode of the second transistor may be connected to a first scan line, the third transistor may be connected between the first electrode of the first transistor and the first node, the gate electrode of the third transistor may be connected to the first scan line, the fourth transistor may be connected between the first node and an initialization power line to which power is applied, the gate electrode of the fourth transistor may be connected to a second scan line, and each gate electrode of the fifth and sixth transistors may be connected to a transmit control line to which transmit control signals are provided.

[0025] According to some example implementations, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor may be P-type transistors.

[0026] According to some example implementations, the plurality of second pixels may also include a first boost capacitor connected between the first node and the emission control line.

[0027] According to some example implementations, each of the plurality of first pixels and the plurality of second pixels may further include a second boost capacitor connected between the first node and the first scan line.

[0028] A display device according to some exemplary embodiments of the present disclosure for achieving the above-described objectives includes: a display unit including a first display area having a plurality of first pixels and a second display area having a plurality of second pixels; a data driver configured to provide a data signal to each data line connected to the plurality of first pixels and the plurality of second pixels; a scan driver configured to provide a plurality of scan signals to a first scan line, a second scan line, and a third scan line respectively connected to the plurality of first pixels and the plurality of second pixels; and an emission controller configured to provide an emission control signal to each emission control line connected to the plurality of first pixels and the plurality of second pixels. The plurality of first pixels have a first density in the first display area, the plurality of second pixels have a second density in the second display area that is less than the first density, and the plurality of second pixels include at least one sub-pixel, the sub-pixel including a first boost capacitor connected between a node electrically connected to the gate electrode of each driving transistor included in each second pixel and a first scan line, and a second boost capacitor connected between the node and the second scan line.

[0029] According to some example implementations, each of the plurality of first pixels and the plurality of second pixels may include a first transistor as a driving transistor, a second transistor having a gate electrode connected to a first scan line, and a third transistor having a gate electrode connected to a second scan line.

[0030] According to some example implementations, the first transistor and the second transistor may be P-type transistors, and the third transistor may be an N-type transistor.

[0031] According to some example embodiments, the display device may be driven per frame by including: an initialization period, which is a period in which the gate electrode of each driving transistor of a plurality of first pixels and a plurality of second pixels or the anode of the light-emitting element is initialized to an initialization voltage; a data writing period, which is a period after the initialization period in which a data signal is written to the first electrode of each driving transistor; a delay period, which is a period after the data writing period and before the light emission of the light-emitting element begins; and an emission period after the delay period, in which each light-emitting element of the plurality of first pixels and a plurality of second pixels emits light, the voltage level of the gate electrode of the plurality of first pixels may be increased by a first level in the delay period, and the voltage level of the gate electrode of the plurality of second pixels may be decreased by a second level less than the first level in the delay period.

[0032] According to some example implementations, at least one of the plurality of scan signals may be converted to a gate-on level at the beginning of the initialization period and to a gate-off level at the beginning of the delay period.

[0033] According to some example implementations, the display device may be a mobile terminal.

[0034] According to some example implementations, the capacitance of the second boost capacitor may be smaller than that of the first boost capacitor.

[0035] According to some exemplary embodiments of this disclosure, the display device can relatively easily adjust the brightness of pixels while including overlapping display areas such as sensors.

[0036] Furthermore, the display device can relatively easily adjust the brightness of pixels while providing the same voltage level data signal to pixels in overlapping display areas such as sensors and pixels in non-overlapping display areas such as sensors.

[0037] The features of embodiments based on this disclosure are not limited to those described above, and various other effects are included in this specification. Attached Figure Description

[0038] The above and other features of the invention will become more apparent from a more detailed description of aspects of some exemplary embodiments of the invention with reference to the accompanying drawings, in which:

[0039] Figure 1 This is a perspective view schematically showing the front surface of a display device according to some example embodiments;

[0040] Figure 2 It is shown schematically. Figure 1 A perspective view of the rear surface of the display device;

[0041] Figure 3 This is a schematic plan view of a display device according to some example embodiments of the present disclosure;

[0042] Figure 4 and Figure 5 yes Figure 3 Example of modification;

[0043] Figure 6 It is along Figure 3 A cross-sectional view taken by line I-I';

[0044] Figure 7 This is a block diagram schematically illustrating a display device according to some example embodiments of the present disclosure;

[0045] Figure 8 This is a schematic plan view illustrating a first display area according to some exemplary embodiments of the present disclosure;

[0046] Figure 9 This illustrates an embodiment. Figure 8 A circuit diagram showing the electrical connections between the components included in the first sub-pixel;

[0047] Figure 10 This is a schematic plan view illustrating a second display area according to some example embodiments of the present disclosure;

[0048] Figure 11 yes Figure 10 An enlarged schematic plan view of section EA;

[0049] Figures 12 to 14 yes Figure 11 Example of modification;

[0050] Figure 15 This illustrates some example implementations. Figure 10 A circuit diagram showing the electrical connections between the components included in the first sub-pixel;

[0051] Figure 16 It is a layout diagram of a sub-pixel of the second pixel according to some exemplary embodiments of the present disclosure;

[0052] Figure 17 yes Figure 16 Layout diagram of the semiconductor layer;

[0053] Figure 18 yes Figure 16 The layout diagram of the first gate electrode layer;

[0054] Figure 19 yes Figure 16 The layout diagram of the second gate electrode layer;

[0055] Figure 20 yes Figure 16 Layout diagram of the first source-drain electrode layer;

[0056] Figure 21 yes Figure 16 The layout diagram of the second source-drain electrode layer;

[0057] Figure 22 It is a layout diagram of a sub-pixel of the second pixel according to some exemplary embodiments of the present disclosure;

[0058] Figure 23 This is a timing diagram illustrating a method for driving a display device according to some example embodiments of the present disclosure;

[0059] Figure 24 This is a block diagram schematically illustrating a display device according to some example embodiments of the present disclosure;

[0060] Figure 25 This illustrates some example implementations. Figure 24 A circuit diagram showing the electrical connections between components included in the sub-pixels of the first pixel;

[0061] Figure 26 This illustrates some example implementations. Figure 24 The circuit diagram showing the electrical connections between components included in the sub-pixels of the second pixel;

[0062] Figure 27 It is shown Figure 24 A timing diagram of the method for driving the display device shown; and

[0063] Figure 28 It is based on Figure 27 The timing diagram for the modified example. Detailed Implementation

[0064] Together with Figure 1The characteristics of the embodiments according to this disclosure and the methods for implementing these characteristics will become apparent from the detailed description of the embodiments described below. However, the embodiments according to this disclosure are not limited to those disclosed below and can be implemented in various different forms. The exemplary embodiments herein are provided to make this disclosure more detailed and complete, and to enable those skilled in the art to fully understand the scope of this disclosure. The embodiments according to this disclosure are defined by the claims and their scope.

[0065] The reference numeral "on" another element or layer includes cases where the layer or element is disposed directly on the other element or between the other layers. Throughout the specification, the same reference numerals denote the same components.

[0066] Although terms such as "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, within the technical spirit of this disclosure, the "first component" mentioned below may refer to the "second component." Unless the context clearly indicates otherwise, singular expressions include plural expressions.

[0067] In the following description, an example embodiment will be provided, in which the display device is implemented as a mobile terminal such as a smartphone. However, embodiments according to this disclosure are not limited thereto, and the display device may be implemented as a variety of smart devices, including laptops, monitors, televisions, mobile phones, MP3 players, medical measuring devices, wearable devices, and HMDs, unless the spirit of this disclosure changes.

[0068] In the following description, aspects of some exemplary embodiments of this disclosure will be described in more detail with reference to the accompanying drawings. In the drawings, the same or similar reference numerals are used for the same components.

[0069] Figure 1 This is a perspective view schematically showing the front surface 100a of a display device 100 according to some example embodiments. Figure 2 It is shown schematically. Figure 1 A perspective view of the rear surface 100b of the display device 100.

[0070] Figure 1 For convenience, an example is shown in which the main desktop screen is displayed on the display panel DP of the display device 100.

[0071] Reference Figure 1 and Figure 2According to some exemplary embodiments of this disclosure, a display panel DP may be arranged on the front surface 100a of a display device 100. The front surface 100a of the display device 100 may include a display area DA in which various data is displayed and a non-display area NDA provided on at least one side of the display area DA.

[0072] The rear camera (CAM), flash (FLA), speaker (SPK), etc., may be located on the rear surface 100b of the display device 100. Furthermore, according to some exemplary embodiments of this disclosure, a power / reset button, volume buttons, a terrestrial DMB antenna for broadcast reception, one or more microphones (MIC), etc., may be located on the side surface 100c of the display device 100. Additionally, a connector (CN) may be formed on the lower side surface of the display device 100. A plurality of electrodes may be formed in the connector (CN), and can be wired to an external device. A headphone jack (EPJ) may be arranged on the upper side surface of the display device 100.

[0073] In the aforementioned display device 100, components such as sensors can be arranged inside the display panel DP. Therefore, the front surface 100a has an aesthetically pleasing appearance and ensures a wide display area DA. This component can be a light-related optical component. For example, it can be an optical component that allows external light to pass through it for incident or emitted light. For example, optical components may include, for example, fingerprint scanners, image capture devices, flashlights, optical sensors, proximity sensors, indicators, solar panels, etc.

[0074] The display panel DP can be formed as a large screen to occupy the entire front surface 100a of the display device 100. When the display panel DP is arranged entirely on the front surface 100a of the display device 100, the display device 100 can be essentially referred to as a "fully front-facing display". Here, in a "fully front-facing display", the entire front surface 100a of the display device 100 can be the display area DA.

[0075] For example, the aforementioned display panel DP may be an organic light-emitting display panel. In this case, the display device 100 employing the aforementioned display panel DP may be an organic light-emitting display device. According to some example embodiments, the display panel DP may be configured as a touch screen including touch electrodes.

[0076] like Figure 1 As shown, the display panel DP can display the main desktop screen, and when the display device 100 is powered on, the main desktop screen can be the first screen displayed on the display panel DP. At this time, the status of the display device 100, such as battery charging status, received signal strength, and current time, can be displayed at the top of the display panel DP. The display panel DP can display various content to the user (e.g., text, images, videos, icons, symbols, etc.).

[0077] Figure 3 This is a schematic plan view of a display device 100 according to some example embodiments of the present disclosure. Figure 4 and Figure 5 yes Figure 3 Example of modification. Figure 6 It is along Figure 3 A cross-sectional view taken by line I-I'.

[0078] Reference Figures 1 to 6 The display device 100 may be flexible in all or at least in part. For example, the display device 100 may be flexible throughout the entire area, or it may be flexible in an area corresponding to the flexible area. When the entire display device 100 is flexible, the display device 100 may be a rollable display device, and when a part of the display device 100 is flexible, the display device 100 may be a foldable display device. However, this disclosure is not limited thereto.

[0079] According to some example embodiments of this disclosure, the display device 100 may include a display panel DP, a touch sensor TS, a window WD, and at least one sensor SR.

[0080] The display panel DP can be arranged on the front surface of the display device 100.

[0081] Display panel DP displays arbitrary visual information, such as text, video, photographs, two-dimensional or three-dimensional images, on its front surface (e.g., an image display surface). The display panel DP displays images, and there are no particular limitations on the type of display panel DP. As a display panel DP, a self-emissive display panel, such as an organic light-emitting display panel (OLED panel), can be used. Alternatively, a non-emissive display panel, such as a liquid crystal display panel (LCD panel), an electrophoretic display panel (EPD panel), or an electro-wetting display panel (EWD panel), can be used as a display panel DP. When a non-emissive display panel is used as the display panel DP of a display device 100 according to some example embodiments of this disclosure, the display device 100 may include a backlight unit that provides light to the display panel DP. Descriptions of some example embodiments of this disclosure will be based on examples where the display panel DP is an organic light-emitting display panel. However, the type of display panel DP is not limited thereto, and another display panel may be used within the scope (or limitation) consistent with the concept of this disclosure. According to some example embodiments of this disclosure, the configuration of the display panel DP may be... Figure 1The display panel DP used in the display device 100 shown is the same.

[0082] The display panel DP may include a display area DA and a non-display area NDA surrounding at least one side of the display area DA.

[0083] Multiple pixels PXL1 and PXL2 may be arranged in the display area DA. According to some example embodiments, each of the multiple pixels PXL1 and PXL2 may include at least one light-emitting element. According to some example embodiments, the light-emitting element may be an organic light-emitting diode or a light-emitting unit including an ultra-small inorganic light-emitting diode with a scale ranging from micrometers to nanometers, but this disclosure is not limited thereto. The display panel DP can display an image in the display area DA by driving the multiple pixels PXL1 and PXL2 in correspondence with input image data. The display area DA may be formed as a large screen to occupy most of the front surface of the display device 100.

[0084] The non-display area NDA may be a region surrounding at least one side of the display area DA, and may also be the remaining region other than the display area DA. According to some example implementations, the non-display area NDA may include line areas, pad areas, various dummy areas, etc.

[0085] According to some exemplary implementations of this disclosure, such as Figures 3 to 5 As shown, the display area DA can be formed to cover the entire (or almost the entire) front surface of the display device 100. Because the display area DA is formed on the entire front surface of the display device 100, according to some example embodiments, the non-display area NDA may not be formed or may be formed in a very narrow (or minimal) area on the front surface. For example, the display area DA may be formed to contact the edge of the side surface of the display device 100 or spaced apart from the edge of the side surface of the display device 100 by a certain distance (e.g., a set or predetermined distance). Figures 3 to 5 In this embodiment, the display area DA is formed only on the front surface of the display device 100, but the implementation of this disclosure is not limited thereto. According to some example embodiments, the display area DA may be formed at at least one region on the edge of a side surface of the display device 100 or at least one region on the rear surface. The display areas DA formed on multiple surfaces of the display device 100 may be at least partially connected to or separated from each other.

[0086] According to some exemplary embodiments of this disclosure, the display device 100 may include at least one sensor SR formed to overlap with at least a portion of the display area DA. The sensor SR may be formed beneath a plurality of pixels PXL1 and PXL2 and / or lines formed in the display area DA, and may be hidden relative to the front surface of the display device 100. When such a sensor SR is formed beneath the display area DA to overlap with at least a portion of the display area DA, the appearance of the display device 100, such as the appearance of the front surface corresponding to the display area DA, becomes aesthetically pleasing, and a wider display area DA is ensured.

[0087] According to some exemplary embodiments of this disclosure, the display area DA can be divided into a first display area A1 and a second display area A2. The first display area A1 may be an area that does not overlap with the sensor SR, while the second display area A2 may be an area that overlaps with the sensor SR. In various embodiments, the first display area A1 may be configured to have a larger size (or area) than the second display area A2.

[0088] like Figure 3 and Figure 5 As shown, the second display area A2 may be located inside the display area DA and may be surrounded by the first display area A1. Figure 3 In this embodiment, the second display area A2 has a substantially circular shape, but this disclosure is not limited thereto. According to some exemplary embodiments, such as... Figure 5 As shown, the second display area A2 may have a polygonal shape including quadrilaterals, and may have various shapes such as ellipses. Furthermore, multiple second display areas A2 may be arranged within the display area DA.

[0089] like Figure 4 As shown, the display area DA may include a first display area A1 and a second display area A2 divided along one direction, such as a second direction DR2. The first display area A1 and the second display area A2 may be adjacent to each other. According to some example embodiments, the second display area A2 may be provided (or configured) to have a wider area than the area overlapping with the sensor SR. For example, as Figure 4 As shown, the second display area A2 may be formed as wide at one end (e.g., the upper portion) of the display device 100. Figure 4In this embodiment, at least one second display area A2 is disposed only on the upper portion of the front surface of the display device 100, but the present disclosure is not limited thereto. According to some exemplary embodiments, one or more second display areas A2 may be provided, and they may be arranged adjacent to or distributed at any location within the display area DA. For example, according to some exemplary embodiments, wherein the display area DA is formed on the side surface edge, rear surface, etc., of the display device 100, a portion of the second display area A2 may be formed within the display area DA on the side surface edge and / or rear surface of the display device 100.

[0090] The sensor SR, arranged to overlap with the second display area A2, may be an optical component. That is, the sensor SR may be a component that receives or emits light. The sensor SR may include, for example, a fingerprint sensor, an image sensor, a camera device, a flash, an optical sensor, a lighting sensor, a proximity sensor, an RGB sensor, an infrared sensor, an indicator, a solar panel, etc. However, the sensor SR is not limited to optical components and may include various components such as ultrasonic sensors, microphones, environmental sensors (e.g., barometers, hygrometers, thermometers, radiation detection sensors, thermal detection sensors, etc.), and chemical sensors (gas detection sensors, dust sensors, odor detection sensors, etc.). According to some exemplary embodiments of this disclosure, the sensor SR may include multiple sensors overlapping the second display area A2. Here, the multiple sensors may include a camera device, a proximity sensor, and a lighting sensor arranged side-by-side.

[0091] On a separate base substrate BS (such as a bracket or housing) formed of plastic or metal material, the aforementioned sensor SR can be arranged to face (or correspond to) at least one area of ​​the display area DA, such as the second display area A2, using a surface mount device (SMD) method.

[0092] The second display area A2 can transmit signals (e.g., rays or light) input to the sensor SR. To improve signal transmittance, the transmittance of the second display area A2 can be greater than that of the first display area A1. Here, each of the transmittance of the second display area A2 and the transmittance of the first display area A1 can be the degree of light transmission per unit area (a preset area or the same area). For example, transmittance can be the ratio of light transmitted through the display panel DP to light incident on a unit area of ​​the display panel DP. Therefore, the second display area A2, with relatively high transmittance, can transmit signals (e.g., rays or light) better than the first display area A1.

[0093] In the following text, the pixel arranged in the first display area A1 is defined as the first pixel PXL1, and the pixel arranged in the second display area A2 is defined as the second pixel PXL2.

[0094] For example, the second pixel PXL2 in the second display area A2 can be formed at a density lower than that of the first pixel PXL1 in the first display area A1. By forming physical and / or optical apertures, such as transmission windows, the gaps of the second pixel PXL2 formed at a low density can better transmit signals (e.g., rays or light).

[0095] Each of the plurality of pixels PXL1 and PXL2 may include a light-emitting element that emits light. The light-emitting element may be, for example, an organic light-emitting diode, but this disclosure is not limited thereto. According to some example embodiments, the light-emitting element may be an inorganic light-emitting element comprising an inorganic light-emitting material or a light-emitting element that emits light by using quantum dots to change the wavelength of the emitted light (quantum dot display element).

[0096] The touch sensor TS and the window WD can be arranged on the display panel DP, which includes the aforementioned components.

[0097] The touch sensor TS may include touch electrodes. The touch sensor TS may be disposed on the image display surface of the display panel DP to receive touch input and / or hover input from a user. The touch sensor TS can sense touch capacitance through contact and / or proximity by an independent input method (such as a user's hand or a similar conductor) to identify touch input and / or hover input of the display device 100. Here, touch input may mean that the display device 100 is directly touched (or contacted) by a user's hand or another independent input method, while hover input may mean that a user's hand or another independent input method is close to the display device 100 including the touch sensor TS but does not touch the display device 100.

[0098] Furthermore, the touch sensor TS can sense a user's touch operation and, in response to the touch operation, move an object displayed on the display device 100 from its original display position to another position. Here, the touch operation can include at least one of single-point touch, multi-point touch, and touch gesture. For example, various touch operations may exist, including specific gestures, such as zooming in or out of text or images by moving the user's finger a specific distance while the user's finger is touching the touch surface of the touch sensor TS.

[0099] A window WD is a component or assembly formed or arranged on the uppermost part of a display device 100 including a display panel DP, and may be a transparent (or substantially transparent or translucent) light-transmitting substrate. The window WD transmits images from the display panel DP and mitigates external impacts, thereby preventing or reducing damage to the display panel DP caused by external impacts. For example, an external impact may be an external force, which can be represented by pressure, stress, etc., and an external impact may refer to a force that can cause defects in the display panel DP. The window WD may include a rigid or flexible substrate, and there are no particular limitations on the constituent materials of the window WD.

[0100] Figure 7 This is a block diagram schematically illustrating a display device 100 according to some example embodiments of the present disclosure.

[0101] Reference Figure 7 According to some embodiments of the present disclosure, the display device 100 may include a timing controller 11, a data driver 12, a scan driver 13, a display unit 15, a power supply 16, and a transmission controller 17.

[0102] The timing controller 11 can provide the data driver 12 with grayscale values, control signals, etc. for each frame. In addition, the timing controller 11 can provide the scan driver 13 with clock signals, control signals, etc.

[0103] The data driver 12 can generate data voltages to be supplied to multiple data lines D1 to Dm using grayscale values, control signals, etc., received from the timing controller 11. For example, the data driver 12 can sample grayscale values ​​using a clock signal and can apply data voltages corresponding to grayscale values ​​to the multiple data lines D1 to Dm in units of pixel rows (e.g., pixels connected to the same scan line). m can be a natural number.

[0104] The scan driver 13 can receive clock signals, scan start signals, etc. from the timing controller 11, and generate scan signals to be provided to multiple scan lines G11 to Gn1, G12 to Gn2, and G13 to Gn3. Here, n can be a natural number.

[0105] According to some example implementations, scan driver 13 may include multiple sub-scan drivers. For example, a first sub-scan driver may provide scan signals for multiple first scan lines G11 to Gn1, a second sub-scan driver may provide scan signals for multiple second scan lines G12 to Gn2, and a third sub-scan driver may provide scan signals for multiple third scan lines G13 to Gn3. Each sub-scan driver may include multiple scan stage circuits connected in the form of shift registers. For example, the scan signal may be generated by sequentially transmitting pulses of the on-level of a scan start signal provided to the scan start line to the next scan stage circuit.

[0106] The transmit controller 17 can receive clock signals, transmit stop signals, etc., from the timing controller 11, and generate transmit control signals to be provided to multiple transmit control lines E1 to En. For example, the transmit controller 17 can sequentially provide transmit control signals with pulses having a gate-off level to the multiple transmit control lines E1 to En. For example, the transmit controller 17 can be configured as a shift register and generate transmit control signals in such a way that, under the control of the clock signal, pulses with a gate-off level of the transmit stop signal are sequentially transmitted to the next stage circuit.

[0107] The display unit 15 includes a plurality of pixels PXL1 and PXL2. As described above, the display unit 15 may include a first display area A1 defined as an area in which the first pixel PXL1 is disposed and a second display area A2 defined as an area in which the second pixel PXL2 is disposed.

[0108] According to some example implementations, each first pixel PXL1 can be connected to a corresponding data line Dj (see...). Figure 9 ), multiple scan lines Gi1, Gi2 and Gi3 (see Figure 9 ) and transmit control line Ei (see Figure 9 Each second pixel PXL2 can be connected to the corresponding data line Dq (see...). Figure 15 ), multiple scan lines Gp1, Gp2 and Gp3 (see Figure 15 ) and the launch control line Ep (see Figure 15 ).

[0109] Power supply 16 can receive an external input voltage and convert the external input voltage to provide a power voltage to the output terminal. For example, power supply 16 generates a first power voltage (high-level power voltage) for a first power ELVDD and a second power voltage (low-level power voltage) for a second power ELVSS based on the external input voltage. In this specification, the first power ELVDD and the second power ELVSS may have different voltage levels. Power supply 16 can provide an initialization power Vint voltage for each of a plurality of pixels PXL1 and PXL2, the initialization power Vint voltage being used to initialize the gate electrode of the driving transistor or initialize the light-emitting element OLED (see [link to documentation]). Figure 9 The anode of ).

[0110] Power supply 16 can receive an external input voltage from a battery or the like and boost the external input voltage to generate a power voltage greater than the external input voltage. For example, power supply 16 can be configured with a power management integrated chip (PMIC). For example, power supply 16 can be configured with an external DC / DC IC.

[0111] Figure 8 This is a schematic plan view of the first display area A1 according to some example embodiments of the present disclosure. Figure 9 This illustrates some example implementations. Figure 8 A circuit diagram showing the electrical connections between the components included in the first sub-pixel SP1.

[0112] exist Figure 9 The diagram illustrates multiple i-th scan lines Gi1, Gi2, and Gi3 connected to the i-th horizontal pixel row arranged in the first display area A1, the i-th emission control line Ei, and the j-th data line Dj arranged in the j-th vertical pixel column, and includes effective sub-pixels with seven transistors, for example, Figure 9 The first sub-pixel SP1.

[0113] Reference Figure 8 and Figure 9 The first display area A1 is the area of ​​the display area DA, and can be arranged with multiple first pixels PXL1.

[0114] Each first pixel PXL1 may include at least one sub-pixel. For example, the first pixel PXL1 may include four sub-pixels SP1, SP2, SP3, and SP4. Each of the first sub-pixel SP1 and the third sub-pixel SP3 may be a red pixel R that emits red light or a blue pixel B that emits blue light, and the second sub-pixel SP2 and the fourth sub-pixel SP4 may be a green pixel G that emits green light. However, this disclosure is not limited thereto, and according to some example embodiments, two of the plurality of sub-pixels SP1, SP2, SP3, and SP4 may be green pixels G that emit green light, and each of the other two sub-pixels may be a red pixel R that emits red light or a blue pixel B that emits blue light.

[0115] According to some exemplary embodiments, a first sub-pixel SP1 formed by a red pixel R and a third sub-pixel SP3 formed by a blue pixel B can be alternately arranged in a first direction DR1 (e.g., a horizontal or row direction) to form a first pixel row. A second sub-pixel SP2 and a fourth sub-pixel SP4 formed by a green pixel G can be arranged in the first direction DR1 to form a second pixel row. According to some exemplary embodiments, the pixel arrangement order of the first pixel row can be different from each other.

[0116] Multiple first pixel rows and second pixel rows can be provided, and they can be arranged alternately in a second direction DR2 (e.g., vertical or column direction).

[0117] In the first display area A1, two first sub-pixels SP1 formed by the red pixel R and two third sub-pixels SP3 formed by the blue pixel B can be located diagonally with the second sub-pixel SP2 formed by the green pixel G as the center. For example, the third sub-pixel SP3 formed by the blue pixel B can be arranged in a third direction DR3 (e.g., inclined to the first direction DR1) with the second sub-pixel SP2 as the center, and the first sub-pixel SP1 formed by the red pixel R can be arranged in a fourth direction DR4 (e.g., inclined to the second direction DR2).

[0118] A first sub-pixel SP1 formed by a red pixel R and a third sub-pixel SP3 formed by a blue pixel B can face each other centered on a second sub-pixel SP2 formed by a green pixel G. Each of the plurality of sub-pixels SP1, SP2, SP3, and SP4 can have a rhomboid structure and be formed to have the same or similar area. However, this disclosure is not limited thereto, and the plurality of sub-pixels SP1, SP2, SP3, and SP4 can have different structures from each other, and the emission area (or size) of some of the plurality of sub-pixels SP1, SP2, SP3, and SP4 can be smaller or larger than the emission area (or size) of the remaining sub-pixels. Figure 8 In the image, the area (or size) of the first sub-pixel SP1 and the third sub-pixel SP3 is different from the area (or size) of the second sub-pixel SP2 and the fourth sub-pixel SP4.

[0119] According to some exemplary embodiments of this disclosure, a first display area A1 may include a first pixel region PXA1 in which one of a plurality of first pixels PXL1 is arranged. That is, a plurality of first pixel regions PXA1 may be arranged in the first display area A1. The first pixel regions PXA1 may be arranged in a specific number (e.g., a set or predetermined number) along a first direction DR1 and a second direction DR2 according to the resolution of the display panel DP. Colored light and / or white light may be achieved by a combination of subpixels included in each first pixel region PXA1.

[0120] In the first display area A1, a plurality of first pixels PXL1, each including a first sub-pixel SP1 and a second sub-pixel SP2, can be arranged at a first density. For example, the first density may be the density of the plurality of first pixels PXL1 densely arranged in the first display area A1, and therefore the total area of ​​the first display area A1 is the same as or substantially the same as the area where the first pixels PXL1 are arranged. Here, the first density may be defined as the total number of first pixels PXL1 per unit area of ​​the first display area A1 (pixels per inch, PPI).

[0121] Each of the plurality of sub-pixels SP1, SP2, SP3, and SP4 may include pixel circuitry, the pixel circuitry comprising a light-emitting element and at least one transistor for driving the light-emitting element. The pixel circuitry of each of the plurality of sub-pixels SP1, SP2, SP3, and SP4 may have substantially similar or identical structures. Therefore, for ease of description, the description of the pixel circuitry of each of the plurality of sub-pixels SP1, SP2, SP3, and SP4 may be replaced with a description specific to a reference. Figure 9 Description of the pixel circuit PXC of the first sub-pixel SP1.

[0122] like Figure 9 As shown, the first sub-pixel SP1 of the first pixel PXL1 may include a light-emitting element OLED and a pixel circuit PXC connected to the light-emitting element OLED to drive the light-emitting element OLED. Here, the pixel circuit PXC may include a first transistor T1 to a seventh transistor T7, a storage capacitor Cst, and a first boost capacitor Cb1. However, in this disclosure, the configuration included in the pixel circuit PXC of the first sub-pixel SP1 is not limited to the above-described embodiment.

[0123] The first electrode of the first transistor T1 (driving transistor) can be connected to the first power ELVDD via the fifth transistor T5, and the second electrode can be connected to the anode of the light-emitting element OLED via the sixth transistor T6. The first electrode corresponds to either the source electrode or the drain electrode, and the second electrode corresponds to the other of the source electrode and the drain electrode. The gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 can control the amount of current flowing from the first power ELVDD through the light-emitting element OLED to the second power ELVSS in accordance with the voltage of the first node N1.

[0124] A second transistor T2 (a switching transistor) can be connected between the j-th data line Dj and the first electrode of the first transistor T1. Furthermore, the gate electrode of the second transistor T2 can be connected to the second scan line Gi2. When a scan signal is provided to the second scan line Gi2, the second transistor T2 can be turned on to electrically connect the j-th data line Dj and the first electrode of the first transistor T1 to each other.

[0125] A third transistor T3 (diode-connected transistor) can be connected between the second electrode of the first transistor T1 and the first node N1. Furthermore, the gate electrode of the third transistor T3 can be connected to the second scan line Gi2. When a scan signal with a gate on-state voltage is provided to the second scan line Gi2, the third transistor T3 can be turned on to electrically connect the second electrode of the first transistor T1 and the first node N1 to each other. Therefore, when the third transistor T3 is turned on, the first transistor T1 can be connected in the form of a diode.

[0126] A fourth transistor T4 (gate initialization transistor) can be connected between the first node N1 and the initialization power line IPL to which the initialization power Vint is applied. Furthermore, the gate electrode of the fourth transistor T4 can be connected to the first scan line Gi1. When a scan signal is provided to the first scan line Gi1, the fourth transistor T4 can be turned on to provide the initialization power Vint voltage to the first node N1.

[0127] The fifth transistor T5 (the first emitter transistor) can be connected between the first transistor T1 and the power line PL to which the first power ELVDD is applied. Furthermore, the gate electrode of the fifth transistor T5 can be connected to the i-th emitter control line Ei. The fifth transistor T5 can be turned off when the emitter control signal EM, representing the gate turn-off voltage, is provided to the i-th emitter control line Ei, and can be turned on under other conditions.

[0128] A sixth transistor T6 (the second emitter transistor) can be connected between the first transistor T1 and the light-emitting element OLED. Furthermore, the gate electrode of the sixth transistor T6 can be connected to the i-th emitter control line Ei. The sixth transistor T6 can be turned off when an emitter control signal EM with a gate turn-off voltage (e.g., a high-level voltage) is provided to the i-th emitter control line Ei, and can be turned on under other conditions.

[0129] A seventh transistor T7 (anode initialization transistor) can be connected between the initialization power line IPL, to which initialization power Vint is applied, and the first electrode (e.g., anode) of the light-emitting element OLED. Furthermore, the gate electrode of the seventh transistor T7 can be connected to the third scan line Gi3. When a scan signal with a gate on-state voltage (e.g., a low-level voltage) is provided to the third scan line Gi3, the seventh transistor T7 can be turned on to provide the voltage of the initialization power Vint to the anode of the light-emitting element OLED. Here, the voltage of the initialization power Vint can be set to be less than the voltage of the data signal. That is, the voltage of the initialization power Vint can be set to be equal to or less than the minimum voltage of the data signal.

[0130] The storage capacitor Cst can be connected between the power line PL, to which the first power ELVDD is applied, and the first node N1. The storage capacitor Cst can store the voltage corresponding to the data signal and the threshold voltage of the first transistor T1.

[0131] A first boost capacitor Cb1 may be connected between the first node N1 and the second scan line Gi2. The first boost capacitor Cb1 can refer to a capacitor generated due to coupling phenomena in the overlapping area of ​​the electrode electrically connected to the first node N1 and the second scan line Gi2 in the plane, and interference stripe phenomena in the non-overlapping area of ​​the electrode electrically connected to the first node N1 and the second scan line Gi2 in the plane. The first boost capacitor Cb1 may be formed between the gate electrode of the first transistor T1 electrically connected to the first node N1 and the gate electrode of the second transistor T2 electrically connected to the second scan line Gi2. Furthermore, the first boost capacitor Cb1 may be formed between the gate electrode of the first transistor T1 electrically connected to the first node N1 and the gate electrode of the third transistor T3 electrically connected to the second scan line Gi2.

[0132] According to some example implementations, each of the plurality of transistors T1 to T7 may be a P-type (PMOS) transistor. The channel of the plurality of transistors T1 to T7 may be made of polysilicon. The polysilicon transistor may be a low-temperature polysilicon (LTPS) transistor. Polysilicon transistors have high electron mobility and therefore fast drive characteristics.

[0133] According to some example implementations, the plurality of transistors T1 to T7 may be N-type (NMOS) transistors. In this case, the channels of the plurality of transistors T1 to T7 may be made of oxide semiconductor. Oxide semiconductor transistors can be fabricated at low temperatures and have a lower charge mobility than polysilicon. Therefore, the leakage current generated by oxide semiconductor transistors in the off state is less than the leakage current of polysilicon transistors.

[0134] According to some example implementations, some transistors (e.g., T1, T2, T5, T6, and T7) may be P-type transistors, and the remaining transistors (e.g., T3 and T4) may be N-type transistors (see [link to implementation details]). Figure 25 ).

[0135] The anode of the OLED is connected to the first transistor T1 via a sixth transistor T6, and the cathode is connected to the second power source ELVSS. The OLED generates light with a brightness (e.g., a set or predetermined brightness) corresponding to the amount of current supplied from the first transistor T1. The voltage value of the first power source ELVDD can be set to be greater than the voltage value of the second power source ELVSS so that current flows through the OLED.

[0136] For example, an OLED can be an organic light-emitting diode. An OLED can emit light in one of the following colors: red, green, and blue. However, this disclosure is not limited thereto.

[0137] Meanwhile, the structure of the first sub-pixel SP1 in the first pixel PXL1 is not limited to that relative to Figure 9 The illustrated implementation is shown. For example, various known pixel circuit PXC structures can be applied to the first sub-pixel SP1 in the first pixel PXL1.

[0138] Figure 10 This is a schematic plan view of the second display area A2 according to some example embodiments of the present disclosure. Figure 11 yes Figure 10 An enlarged schematic plan view of section EA. Figures 12 to 14 yes Figure 11 Example of modification. Figure 15 This illustrates some example implementations. Figure 10 A circuit diagram showing the electrical connections between the components included in the first sub-pixel SP1.

[0139] The second pixel PXL2 can be arranged in the second display area A2 at a second density. The second density can be set to be less than the first density. Here, the second density can be defined as the total number of second pixels PXL2 per unit area of ​​the second display area A2 (pixels per inch (PPI)). In the following description, the first pixel PXL1 and the second pixel PXL2 are collectively referred to as a plurality of pixels PXL1 and PXL2.

[0140] Because the second pixel PXL2 in the second display area A2 is arranged at a relatively low density compared to the first pixel PXL1 in the first display area A1, the transmittance, such as light transmittance, of the second display area A2 can be greater than that of the first display area A1. According to some example embodiments, the first density of the first pixel PXL1 can be approximately 4 to 16 times greater than the second density of the second pixel PXL2.

[0141] According to some exemplary embodiments, each first pixel PXL1 in the first display area A1 can emit light with the same brightness, and each second pixel PXL2 in the second display area A2 can emit light with the same brightness. However, since the first pixel PXL1 and the second pixel PXL2 are arranged at different densities in the first display area A1 and the second display area A2, the first pixel PXL1 and the second pixel PXL2 can emit light with different brightness depending on the area. For example, the first pixel PXL1 in the first display area A1 can emit light with a first brightness, and the second pixel PXL2 in the second display area A2 can emit light with a second brightness.

[0142] Because the second pixel PXL2 is arranged at a density lower than that of the first pixel PXL1, the second pixel PXL2 can be set to emit light at a brightness greater than that of the first pixel PXL1, so that the user will not easily identify the boundary between the first display area A1 and the second display area A2.

[0143] According to some exemplary implementations, the relationship between the first brightness of the first pixel PXL1 and the second brightness of the second pixel PXL2 can be inversely proportional to the density relationship. For example, the second brightness of the second pixel PXL2 can be approximately 4 to 16 times greater than the first brightness of the first pixel PXL1.

[0144] The second display area A2 may include multiple pixel rows and multiple pixel columns. According to some example implementations, each pixel row includes pixels (or subpixels) arranged in a first direction DR1. Each pixel column includes pixels (or subpixels) arranged in a second direction DR2. Pixels (or subpixels) in a pixel row may be connected to different data lines. Pixels (or subpixels) included in each pixel column may be connected to the same data line for each pixel column.

[0145] The configuration of the first pixel PXL1 in the first display area A1 and the configuration of the second pixel PXL2 in the second display area A2 may be different from each other.

[0146] For example, the materials of the signal lines connected to the first pixel PXL1 in the first display area A1 and the materials of the signal lines connected to the second pixel PXL2 in the second display area A2 may be different from each other. For example, the material of the signal lines connected to the first pixel PXL1 in the first display area A1 may be formed of an opaque metal, and the material of the signal lines connected to the second pixel PXL2 in the second display area A2 may be formed of a transparent metal. According to some example embodiments, the signal lines connected to a plurality of pixels PXL1 and PXL2 in the first display area A1 and the second display area A2 may be composed of one of an opaque metal and a transparent metal, and the ratio of signal lines formed of transparent metal in the second display area A2 may be greater than the ratio of signal lines formed of transparent metal in the first display area A1. According to some example embodiments of this disclosure, the light transmittance of the transparent metal may be greater than the light transmittance of the opaque metal (e.g., a reflective metal).

[0147] As another example, the materials of the anode of the OLED light-emitting element included in the first pixel PXL1 of the first display area A1 and the materials of the anode of the OLED light-emitting element included in the second pixel PXL2 of the second display area A2 may be different from each other. For example, the material of the anode of the OLED light-emitting element included in the first pixel PXL1 of the first display area A1 may be made of opaque metal, and the material of the anode of the OLED light-emitting element included in the second pixel PXL2 of the second display area A2 may be made of transparent metal.

[0148] As a further example, the ratio of the cathode CE of the OLED included in the first pixel PXL1 of the first display area A1 may be different from the ratio of the cathode CE of the OLED included in the second pixel PXL2 of the second display area A2. For example, the ratio of the cathode CE of the OLED included in the second pixel PXL2 of the second display area A2 may be less than the ratio of the cathode CE of the OLED included in the first pixel PXL1 of the first display area A1.

[0149] As a further example, the layout of the first pixel PXL1 (e.g., the arrangement of components included in the pixel circuit PXC) and the layout of the second pixel PXL2 can differ from each other. For example, the signal lines connected to the second pixel PXL2 can be designed to be narrower than the signal lines connected to the first pixel PXL1, or the signal lines connected to the second pixel PXL2 can be arranged to overlap with the insulating layer placed between them. Therefore, when the distance between the signal lines in the second display area A2 is fixed, the area occupied by the signal lines can be reduced, and thus the light transmittance of the second display area A2 can be improved.

[0150] Each second pixel PXL2 may include four sub-pixels SP1, SP2, SP3, and SP4. Each of the first sub-pixel SP1 and the third sub-pixel SP3 may be a red pixel R emitting red light or a blue pixel B emitting blue light, and the second sub-pixel SP2 and the fourth sub-pixel SP4 may be a green pixel G emitting green light. Each second pixel PXL2 may be arranged in the second pixel region PXA2, and colored light or white light may be achieved by combining the light emitted from the multiple sub-pixels SP1, SP2, SP3, and SP4. As described above, four sub-pixels SP1, SP2, SP3, and SP4 constitute a second pixel PXL2, but embodiments according to this disclosure are not limited thereto.

[0151] According to some example implementations, such as Figure 12As shown, each second pixel PXL2 may include a first sub-pixel SP1 to a third sub-pixel SP3 arranged in the same pixel row along a first direction DR1. The first sub-pixels SP1 to SP3 may be arranged in a strip-shaped arrangement in each second pixel region PXA2. The first sub-pixel SP1 may be a red pixel R emitting red light, the second sub-pixel SP2 may be a green pixel G emitting green light, and the third sub-pixel SP3 may be a blue pixel B emitting blue light. In this case, the first sub-pixels SP1 to SP3 may each have a rectangular structure and may be formed to have the same or similar area (or size) as each other.

[0152] According to some example implementations, such as Figure 13 As shown, the second pixel PXL2 may include four sub-pixels SP1, SP2, SP3, and SP4. The first sub-pixel SP1 may be a red pixel R emitting red light, the second sub-pixel SP2 may be a green pixel G emitting green light, the third sub-pixel SP3 may be a blue pixel B emitting blue light, and the fourth sub-pixel SP4 may be a white pixel W emitting white light. The first sub-pixel SP1 and the third sub-pixel SP3 may be repeatedly arranged along the second direction DR2 to form a first pixel column. The second sub-pixel SP2 and the fourth sub-pixel SP4 may be repeatedly arranged along the second direction DR2 to form a second pixel column.

[0153] According to some example implementations, such as Figure 14As shown, a second pixel PXL2 may include four sub-pixels SP1, SP2, SP3, and SP4. The first sub-pixel SP1 may be a red pixel R emitting red light, the second sub-pixels SP2 and the fourth sub-pixel SP4 may be green pixels G emitting green light, and the third sub-pixel SP3 may be a blue pixel B emitting blue light. According to some exemplary embodiments, the first sub-pixel SP1 and the third sub-pixel SP3 may have a shape in which the length of the second direction DR2 is longer than the length of the first direction DR1, and the second sub-pixel SP2 and the fourth sub-pixel SP4 may have a shape in which the length of the first direction DR1 is longer than the length of the second direction DR2; however, embodiments according to this disclosure are not limited to the above shapes. The first sub-pixel SP1 and the third sub-pixel SP3 may be repeatedly arranged along the second direction DR2 to form a first pixel column. A plurality of second sub-pixels SP2 and fourth sub-pixels SP4 may be arranged along the second direction DR2 to form a second pixel column. The first sub-pixel SP1, the second sub-pixels SP2 and fourth sub-pixels SP4 overlapping in the second direction DR2, and the third sub-pixel SP3 may be repeatedly arranged along the first direction DR1 to form a first pixel row. According to some exemplary embodiments, the emission region defined by the second sub-pixel SP2 and the fourth sub-pixel SP4 may overlap with a first sub-pixel SP1 and a third sub-pixel SP3 in the first direction DR1. The first sub-pixel SP1 and the third sub-pixel SP3 overlapping in the first direction DR1, and the second sub-pixel SP2 and the fourth sub-pixel SP4 overlapping in the second direction DR2, may be connected to the same scan lines Gp1, Gp2, and Gp3 (see [link to documentation]). Figure 15 ).

[0154] Reference Figure 15 The first sub-pixel SP1 of the second pixel PXL2 may include a light-emitting element (OLED) and a pixel circuit PXC connected to the OLED to drive it. Here, the pixel circuit PXC may include a first transistor T1 to a seventh transistor T7, a storage capacitor Cst, a first boost capacitor Cb1, and a second boost capacitor Cb2. In the following text, the pixel circuit PXC in the second pixel PXL2 may have the same or similar connection relationships as the pixel circuit PXC in the first pixel PXL1, the difference being that the pixel circuit PXC in the second pixel PXL2 also includes the second boost capacitor Cb2, and therefore, repeated descriptions will be omitted.

[0155] The second boost capacitor Cb2 can be connected between the first node N1 and the transmit control line Ep. The second boost capacitor Cb2 can refer to the capacitor generated by the coupling phenomenon generated in the area where the electrode electrically connected to the first node N1 and the transmit control line Ep overlap in the plane, and the interference stripe phenomenon in the area where the electrode electrically connected to the first node N1 and the transmit control line Ep do not overlap in the plane.

[0156] According to some example implementations, the capacitance of the second boost capacitor Cb2 in the second pixel PXL2 may be greater than the capacitance of the first boost capacitor Cb1.

[0157] Figure 16 This is a layout diagram of a subpixel of the second pixel PXL2 according to some exemplary embodiments of the present disclosure. Figure 17 yes Figure 16 The layout diagram of the semiconductor layer ACT. Figure 18 yes Figure 16 The layout diagram of the first gate electrode layer GAT1. Figure 19 yes Figure 16 The layout diagram of the second gate electrode layer GAT2. Figure 20 yes Figure 16 The layout diagram of the first source-drain electrode layer SD1. Figure 21 yes Figure 16 The layout diagram of the second source-drain electrode layer SD2.

[0158] The layout shown is merely an example, and the implementation is not limited to the layout shape shown. In this layout diagram, the location of each of the plurality of transistors T1 to T7 is indicated.

[0159] Reference Figures 16 to 20 The display device 100 includes a first gate electrode layer GAT1 and a second gate electrode layer GAT2 forming electrodes for a plurality of transistors T1 to T7, a first source-drain electrode layer SD1 and a second source-drain electrode layer SD2, a semiconductor layer ACT forming a channel, and an insulating layer. According to some exemplary embodiments, a top-gate transistor with a gate electrode disposed above the semiconductor layer ACT can be applied to the plurality of transistors T1 to T7 as P-type transistors.

[0160] According to some exemplary embodiments, in order to form each of the plurality of transistors T1 to T7, the display device 100 may include a semiconductor layer ACT, a first gate electrode layer GAT1, a second gate electrode layer GAT2, a first source-drain electrode layer SD1, and a second source-drain electrode layer SD2 stacked sequentially. Each insulating layer may be disposed between the semiconductor layer ACT, the first gate electrode layer GAT1, the second gate electrode layer GAT2, the first source-drain electrode layer SD1, and the second source-drain electrode layer SD2. Furthermore, according to some exemplary embodiments, a passivation layer and a light-emitting element OLED may be sequentially disposed on the second source-drain electrode layer SD2.

[0161] To form each of the plurality of transistors T1 to T7, the display device 100 may include a contact hole CNT through an inserted insulating layer such that the semiconductor layer ACT, the first gate electrode layer GAT1, the second gate electrode layer GAT2, the first source-drain electrode layer SD1, and the second source-drain electrode layer SD2 are physically connected to each other in some regions where the semiconductor layer ACT, the first gate electrode layer GAT1, the second gate electrode layer GAT2, the first source-drain electrode layer SD1, and the second source-drain electrode layer SD2 overlap in a plane.

[0162] The display device 100 may include a via VIA through a passivation layer to electrically connect some electrodes of a plurality of transistors T1 to T7 to a light-emitting element OLED.

[0163] First, the first sub-pixel SP1 based on the second pixel PXL2 will be described.

[0164] For each of the multiple sub-pixels SP1 and SP2, the semiconductor layer ACT can be separated from each other. The semiconductor layer ACT can have a specific pattern on a plane.

[0165] The semiconductor layer ACT may include polycrystalline silicon. Polycrystalline silicon can be formed by crystallizing amorphous silicon. Examples of crystallization methods include, but are not limited to, rapid thermal annealing (RTA), solid-phase crystallization (SPC), excimer laser annealing (ELA), metal-induced crystallization (MIC), metal-induced lateral crystallization (MILC), and sequential lateral solidification (SLS). As another example, the semiconductor layer ACT may include monocrystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, etc.

[0166] The first gate electrode layer GAT1 may be disposed on the semiconductor layer ACT. According to some example embodiments, an insulating layer may be disposed between the semiconductor layer ACT and the first gate electrode layer GAT1. The first gate electrode layer GAT1 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first gate electrode layer GAT1 may be a single-layer film or a multilayer film.

[0167] The second gate electrode layer GAT2 may be disposed on the first gate electrode layer GAT1. According to some exemplary embodiments, an insulating layer may be disposed between the first gate electrode layer GAT1 and the second gate electrode layer GAT2. The second gate electrode layer GAT2 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The second gate electrode layer GAT2 may be a single-layer film or a multilayer film.

[0168] The first gate electrode layer GAT1 and the second gate electrode layer GAT2 may include a first scan line Gp1, a second scan line Gp2, a third scan line Gp3, the gate electrode of each of the plurality of transistors T1 to T7, an emitter control line Ep, and an initialization power line IPL. That is, the first gate electrode layer GAT1 and the second gate electrode layer GAT2 may include the first scan line Gp1, the second scan line Gp2, the third scan line Gp3, the gate electrode of each of the plurality of transistors T1 to T7, the emitter control line Ep, and the initialization power line IPL, which may be arranged in at least one of the first gate electrode layer GAT1 and the second gate electrode layer GAT2.

[0169] According to some example embodiments, the first gate electrode layer GAT1 may include a first scan line Gp1, a second scan line Gp2, a third scan line Gp3, the gate electrode of each of a plurality of transistors T1 to T7, and an emitter control line Ep, and the second gate electrode layer GAT2 may include an initialization power line IPL. In this case, the first scan line Gp1, the second scan line Gp2, the third scan line Gp3, and the emitter control line Ep may be formed to be physically separated from each other in the first gate electrode layer GAT1.

[0170] The first source-drain electrode layer SD1 may be disposed on the second gate electrode layer GAT2. According to some exemplary embodiments, an insulating layer may be disposed between the second gate electrode layer GAT2 and the first source-drain electrode layer SD1. The first source-drain electrode layer SD1 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first source-drain electrode layer SD1 may be a single-layer film or a multilayer film.

[0171] The second source-drain electrode layer SD2 may be disposed on the first source-drain electrode layer SD1. According to some exemplary embodiments, an insulating layer may be disposed between the first source-drain electrode layer SD1 and the second source-drain electrode layer SD2. The second source-drain electrode layer SD2 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The second source-drain electrode layer SD2 may be a single-layer film or a multilayer film.

[0172] The first source-drain electrode layer SD1 and the second source-drain electrode layer SD2 may include a first electrode and a second electrode of each of a plurality of transistors T1 to T7, and at least some electrodes of a first boost capacitor Cb1 and a second boost capacitor Cb2. That is, the first electrode and the second electrode of each of the plurality of transistors T1 to T7, and at least some electrodes of the first boost capacitor Cb1 and the second boost capacitor Cb2 may be formed in any one of the first source-drain electrode layer SD1 and the second source-drain electrode layer SD2.

[0173] According to some example embodiments, the first source-drain electrode layer SD1 may include a first electrode and a second electrode of each of a plurality of transistors T1 to T7 and a data line Dq, and the second source-drain electrode layer SD2 may include a power line PL. However, the layer in which the first electrode and second electrode of each of the plurality of transistors T1 to T7, the power line PL and the data line Dq are arranged is not limited thereto. That is, each of the first electrode and second electrode of each of the plurality of transistors T1 to T7, the power line PL and the data line Dq may be arranged in either the first source-drain electrode layer SD1 and the second source-drain electrode layer SD2.

[0174] For example, according to some exemplary embodiments, the first source-drain electrode layer SD1 may include a first electrode and a second electrode of each of a plurality of transistors T1 to T7 and a power line PL, and the second source-drain electrode layer SD2 may include a data line Dq.

[0175] According to some example implementations, the first source-drain electrode layer SD1 may include a first electrode and a second electrode of each of a plurality of transistors T1 to T7, and the second source-drain electrode layer SD2 may include a power line PL and a data line Dq.

[0176] According to some example implementations, the first source-drain electrode layer SD1 may include a first electrode and a second electrode of each of a plurality of transistors T1 to T7, a power line PL, and a data line Dq.

[0177] According to some example implementations, the second source-drain electrode layer SD2 may include a first electrode and a second electrode of each of a plurality of transistors T1 to T7, a power line PL, and a data line Dq.

[0178] Meanwhile, according to some exemplary embodiments, the first source-drain electrode layer SD1 may include an electrode pattern electrically connected to a first node N1 and defining a first overlapping region OA1 that at least partially overlaps with the second scan line Gp2. Furthermore, the first source-drain electrode layer SD1 may include an electrode pattern electrically connected to the first node N1 and defining a second overlapping region OA2 that at least partially overlaps with the emission control line Ep. In this specification, unless otherwise specified, the term "overlap" means two structures overlapping in the thickness direction of the display device 100.

[0179] According to some example implementations, the first boost capacitor Cb1 may be formed by a first overlapping region OA1, and the second boost capacitor Cb2 may be formed by a second overlapping region OA2.

[0180] According to some example embodiments, the electrode pattern defining the first overlapping region OA1 and the second overlapping region OA2 is shown as the same electrode pattern in the first source-drain electrode layer SD1, but is not limited thereto.

[0181] According to some example embodiments, the first boost capacitor Cb1 may include a first electrode included in the first gate electrode layer GAT1 (e.g., Figure 18 The components electrically connected to the second scan line Gp2 in the first source-drain electrode layer SD1 and the second electrode included in the first source-drain electrode layer SD1 (e.g., Figure 20 The components electrically connected to the gate electrode of the first transistor T1; the components electrically connected to the first node N1; and the electrodes including the first overlapping region OA1.

[0182] According to some example implementations, the second boost capacitor Cb2 may include a first electrode included in the first gate electrode layer GAT1 (e.g., Figure 18 The components electrically connected to the transmit control line Ep in the first source-drain electrode layer SD1 and the second electrode included in the first source-drain electrode layer SD1 (e.g., Figure 20 The components electrically connected to the gate electrode of the first transistor T1; the components electrically connected to the first node N1; and the electrodes including the second overlapping region OA2.

[0183] Next, the first sub-pixel SP1 of the first pixel PXL1 will be described.

[0184] Figure 22 It is a layout diagram of a subpixel in the first pixel according to some exemplary embodiments of the present disclosure.

[0185] Reference Figure 16 and Figure 22 The first sub-pixel SP1 of the first pixel PXL1 may not include the second overlapping region OA2. The shape of the first sub-pixel SP1 of the first pixel PXL1 is similar to that of the first sub-pixel SP1 of the second pixel PXL2, except that it does not include the second overlapping region OA2.

[0186] Therefore, each of the plurality of sub-pixels SP1 and SP2 of the second pixel PXL2 may include a first boost capacitor Cb1 and a second boost capacitor Cb2, and each of the sub-pixels SP1 and SP2 of the first pixel PXL1 may include a first boost capacitor Cb1. However, due to the interference stripe phenomenon, a coupling phenomenon similar to that of the second boost capacitor Cb2 may occur in each of the plurality of sub-pixels SP1 and SP2 of the first pixel PXL1.

[0187] In other words, in each of the multiple sub-pixels SP1 and SP2 of the first pixel PXL1, the electrode electrically connected to the first node N1 and the emission control line Ep are formed to not overlap in the plane, but coupling phenomena caused by interference stripes may occur between the electrode electrically connected to the first node N1 and the emission control line Ep.

[0188] At this time, the capacitance of the first boost capacitor Cb1 can be greater than the capacitance between the electrode of the first node N1 and the emission control line Ep in the first pixel PXL1.

[0189] According to some exemplary embodiments, the area of ​​each of the plurality of pixels PXL1 and PXL2 may be different. The area of ​​each of the plurality of pixels PXL1 and PXL2 may refer to the area including the pixel circuit PXC, the plurality of signal lines connected to the pixel circuit PXC, and the area of ​​the light-emitting element OLED. According to some exemplary embodiments, the area of ​​each of the plurality of pixels PXL1 and PXL2 may refer to the area of ​​the light-emitting surface of the light-emitting element OLED, for example, the size of the light-emitting region. According to some exemplary embodiments, the area of ​​each sub-pixel of the second pixel PXL2 may be smaller than the area of ​​each sub-pixel of the first pixel PXL1. Therefore, compared to the first pixel PXL1, the transmissive portion TA of the second pixel PXL2, which is an element disposed below the pixel circuit PXC, may be increased.

[0190] Figure 23 This is a timing diagram illustrating a method for driving a display device 100 according to some example embodiments of the present disclosure.

[0191] exist Figure 23In this circuit, since the fifth transistor T5 and the sixth transistor T6 are P-type transistors, when the transmit control signal EM is at the first voltage level (low level), the fifth transistor T5 and the sixth transistor T6 can have gate turn-on signals, and when the transmit control signal EM is at the second voltage level (high level), the fifth transistor T5 and the sixth transistor T6 can have gate turn-off signals.

[0192] exist Figure 23 In this text, for ease of description, each frame is divided into four time periods, but the implementation method is not limited to this.

[0193] A frame may include an initialization period TP1, a data writing period TP2, a delay period TP3, and a transmission period TP4. Before the initialization period TP1 of a frame, there is a transmission period TP4_pre of the previous frame.

[0194] The initialization period TP1 corresponds to the period during which the fourth transistor T4 and the seventh transistor T7 are turned on, and therefore the gate electrode of the first transistor T1 and / or the anode of the light-emitting element OLED are initialized to the initialization voltage.

[0195] During the initialization period TP1, the voltage level V at the gate electrode of the first transistor T1 is... T1G_PXL1 and voltage level V T1G_PXL2 The voltage level becomes the initialization voltage, and the initialization voltage level can be maintained during the initialization period TP1. According to some example embodiments, the voltage level V of the gate electrode of each of the first transistor T1 in each of the plurality of sub-pixels SP1 and SP2 of the first pixel PXL1 and the second pixel PXL2 is... T1G_PXL1 and voltage level V T1G_PXL2 Both of these can have voltage levels similar to the initial voltage level.

[0196] The data writing period TP2 corresponds to the period during which the second transistor T2 is turned on, and thus the data signal is written to the first electrode of the first transistor T1.

[0197] During the data writing period TP2, the data signal is gradually charged into the storage capacitor Cst, and therefore the voltage level V at the gate electrode of the first transistor T1 is increased. T1G_PXL1 and voltage level V T1G_PXL2 This can be gradually changed. According to some example implementations, a data signal can be injected, and therefore the voltage level V of the gate electrode of each first transistor T1 in each sub-pixel of the first pixel PXL1 and the second pixel PXL2 can be adjusted. T1G_PXL1 and voltage level V T1G_PXL2 It can be increased gradually.

[0198] The delay period TP3 is the period during which the second transistor T2 is turned off and the fifth transistor T5 and the sixth transistor T6 are turned off, and corresponds to the period after the data signal writing is completed and before the light-emitting element OLED starts to emit light.

[0199] During the delay period TP3, when the second transistor T2 in each of the plurality of sub-pixels SP1 and SP2 of the first pixel PXL1 is turned off, the voltage level V at the gate electrode of the first transistor T1 is... T1G_PXL1 The first voltage level V1 can be increased due to the effect of the first boost capacitor Cb1.

[0200] Simultaneously, during the delay period TP3, when the second transistor T2 in each of the multiple sub-pixels SP1 and SP2 of the second pixel PXL2 is turned off, the voltage level V at the gate electrode of the first transistor T1... T1G_PXL2 The second voltage level V2, which is less than the first voltage level V1, can be increased due to the influence of the second boost capacitor Cb2.

[0201] The emission period TP4 corresponds to the period during which the fifth transistor T5 and the sixth transistor T6 are turned on, and thus the light-emitting element OLED emits light.

[0202] During the transmission period TP4, when the fifth transistor T5 and the sixth transistor T6 in each of the multiple sub-pixels SP1 and SP2 of the first pixel PXL1 are turned on, the voltage level V at the gate electrode of the first transistor T1 is... T1G_PXL1 The third level V3 may be reduced due to the influence of the first boost capacitor Cb1.

[0203] Simultaneously, during the transmission period TP4, when the fifth transistor T5 and the sixth transistor T6 in each of the multiple sub-pixels SP1 and SP2 of the second pixel PXL2 are turned on, the voltage level V at the gate electrode of the first transistor T1... T1G_PXL2 The fourth level V4, which is greater than the third level V3, can be reduced due to the influence of the first boost capacitor Cb1 and the second boost capacitor Cb2.

[0204] According to some exemplary embodiments, the first pixel PXL1 can be configured such that the capacitance of the first boost capacitor Cb1 is relatively large. Therefore, as shown in the figures, the voltage level V at the gate electrode of the first transistor T1... T1G_PXL1 It can maintain a relatively high voltage.

[0205] According to some example implementations, the second pixel PXL2 is configured such that the capacitance of the first boost capacitor Cb1 decreases and the capacitance of the second boost capacitor Cb2 increases. Therefore, as shown in the figures, the voltage level V at the gate electrode of the first transistor T1... T1G_PXL2 It can maintain a relatively low voltage.

[0206] In this method, the voltage level V of the gate electrode of each first transistor T1 of the first pixel PXL1 and the second pixel PXL2 is... T1G_PXL1 and voltage level V T1G_PXL2 They can be adjusted to be different. Therefore, even if the same voltage level data signal is provided to the first pixel PXL1 and the second pixel PXL2, a current difference is still generated for each light-emitting element OLED of the first pixel PXL1 and the second pixel PXL2, and thus the brightness can be adjusted.

[0207] Next, the display device and the method of driving the display device according to some example embodiments will be described in more detail below. In the following, the same or similar reference numerals are used to denote... Figures 1 to 23 The components in the accompanying drawings are the same as those in the accompanying drawings, and their descriptions are omitted.

[0208] Figure 24 This is a block diagram schematically illustrating a display device 100 according to some example embodiments of the present disclosure. Figure 25 This illustrates some example implementations. Figure 24 The circuit diagram shown illustrates the electrical connections between components included in the sub-pixels of the first pixel PXL1. Figure 26 This illustrates some example implementations. Figure 24 The circuit diagram shown illustrates the electrical connections between components included in the sub-pixels of the second pixel PXL2. Figure 27 It is shown Figure 24 The timing diagram shows the method of driving the display device 100. Figure 28 It is based on Figure 27 The timing diagram for the modified example.

[0209] Reference Figures 24 to 27 The display device 100 according to some example embodiments and for... Figure 7 , Figure 9 , Figure 15 and Figure 23 The difference in the described implementation is that some transistors in each sub-pixel SP1 of the first pixel PXL1 and the second pixel PXL2 are N-type transistors.

[0210] Power supply 16 can provide a first initialization voltage Vint1 for initializing the gate electrode of the driving transistor of each of the plurality of pixels PXL1 and PXL2 and a second initialization voltage Vint2 for initializing the anode of the light-emitting element OLED.

[0211] First, the electrical connection relationship is described based on the first sub-pixel SP1 of the first pixel PXL1.

[0212] The first electrode of the first transistor T1 (driving transistor) can be connected to the first power ELVDD via the fifth transistor T5, and the second electrode can be connected to the anode of the light-emitting element OLED via the sixth transistor T6. The first electrode corresponds to either the source electrode or the drain electrode, and the second electrode corresponds to the other of the source electrode and the drain electrode. The gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 can control the amount of current flowing from the first power ELVDD through the light-emitting element OLED to the second power ELVSS in accordance with the voltage of the first node N1.

[0213] A second transistor T2 (a switching transistor) can be connected between the j-th data line Dj and the first electrode of the first transistor T1. Furthermore, the gate electrode of the second transistor T2 can be connected to the second scan line Gi2. When a scan signal is provided to the second scan line Gi2, the second transistor T2 can be turned on to electrically connect the j-th data line Dj and the first electrode of the first transistor T1 to each other.

[0214] A third transistor T3 (diode-connected transistor) can be connected between the second electrode of the first transistor T1 and the first node N1. Furthermore, the gate electrode of the third transistor T3 can be connected to the third scan line Gi3. When a scan signal with a gate on-state voltage is provided to the third scan line Gi3, the third transistor T3 can be turned on to electrically connect the second electrode of the first transistor T1 and the first node N1 to each other. Therefore, when the third transistor T3 is turned on, the first transistor T1 can be connected in the form of a diode.

[0215] A fourth transistor T4 (gate initialization transistor) can be connected between the first node N1 and the initialization power line to which the first initialization power Vint1 is applied. Furthermore, the gate electrode of the fourth transistor T4 can be connected to the first scan line Gi1. When a scan signal is provided to the first scan line Gi1, the fourth transistor T4 can be turned on to provide the voltage of the first initialization power Vint1 to the first node N1.

[0216] The fifth transistor T5 (the first emitter transistor) can be connected between the first transistor T1 and the power line to which the first power ELVDD is applied. Furthermore, the gate electrode of the fifth transistor T5 can be connected to the i-th emitter control line Ei. The fifth transistor T5 can be turned off when the emitter control signal with the gate turn-off voltage is provided to the i-th emitter control line Ei, and can be turned on under other conditions.

[0217] A sixth transistor T6 (the second emitter transistor) can be connected between the first transistor T1 and the light-emitting element OLED. Furthermore, the gate electrode of the sixth transistor T6 can be connected to the i-th emitter control line Ei. The sixth transistor T6 can be turned off when an emitter control signal with a gate turn-off voltage (e.g., a high-level voltage) is provided to the i-th emitter control line Ei, and can be turned on under other conditions.

[0218] A seventh transistor T7 (anode initialization transistor) can be connected between the initialization power line to which the second initialization power Vint2 is applied and the first electrode (e.g., anode) of the light-emitting element OLED. Furthermore, the gate electrode of the seventh transistor T7 can be connected to the second scan line G(i-1)2. When a scan signal with a gate on-state voltage (e.g., a low-level voltage) is provided to the second scan line G(i-1)2, the seventh transistor T7 can be turned on to provide the voltage of the second initialization power Vint2 to the anode of the light-emitting element OLED. Here, the voltage of the second initialization power Vint2 can be set to be less than the voltage of the data signal. That is, the voltage of the second initialization power Vint2 can be set to be equal to or less than the minimum voltage of the data signal.

[0219] The storage capacitor Cst can be connected between the power line to which the first power ELVDD is applied and the first node N1. The storage capacitor Cst can store the voltage corresponding to the data signal and the threshold voltage of the first transistor T1.

[0220] A first boost capacitor Cb1 may be connected between the first node N1 and the third scan line Gi3. The first boost capacitor Cb1 can refer to a capacitor formed due to coupling phenomena generated when the first node N1 and the third scan line Gi3 overlap in a plane, or due to coupling phenomena generated by interference stripes even when the first node N1 and the third scan line Gi3 do not overlap in a plane. The first boost capacitor Cb1 may be formed between the gate electrode of the first transistor T1 electrically connected to the first node N1 and the third scan line Gi3. Furthermore, the first boost capacitor Cb1 may be formed between the gate electrode of the first transistor T1 electrically connected to the first node N1 and the gate electrode of the third transistor T3 electrically connected to the third scan line Gi3.

[0221] According to some exemplary embodiments, some transistors (e.g., T1, T2, T5, T6, and T7) may be P-type transistors, and the remaining transistors (e.g., T3 and T4) may be N-type transistors. According to some exemplary embodiments, a bottom-gate transistor in which the gate electrode is disposed below the semiconductor layer may be used as an N-type transistor, specifically the third transistor T3 and the fourth transistor T4.

[0222] Next, the electrical connections will be described based on the first sub-pixel SP1 of the second pixel PXL2. Since the pixel circuit PXC in the second pixel PXL2 has the same or similar connections as the pixel circuit PXC in the first pixel PXL1, the difference being that the pixel circuit PXC also includes a second boost capacitor Cb2, a repetitive description will be omitted.

[0223] The second boost capacitor Cb2 can be connected between the first node N1 and the second scan line Gp2. The second boost capacitor Cb2 can refer to the capacitor generated by the coupling phenomenon generated in the area where the electrode electrically connected to the first node N1 and the second scan line Gp2 overlap in the plane, and by the coupling phenomenon generated in the area where the electrode electrically connected to the first node N1 and the second scan line Gp2 do not overlap in the plane due to the interference stripe phenomenon.

[0224] According to some exemplary embodiments, the capacitance of the first boost capacitor Cb1 in the first pixel PXL1 can be smaller than the capacitance between the electrode electrically connected to the first node N1 and the second scan line Gi2. The capacitance of the second boost capacitor Cb2 in the second pixel PXL2 can be smaller than the capacitance of the first boost capacitor Cb1. Based on the capacitance of the second boost capacitor Cb2, the current difference supplied to each light-emitting element OLED of the first pixel PXL1 and the second pixel PXL2 can be significantly increased. Specifically, the smaller the capacitance of the second boost capacitor Cb2, the greater the emitted brightness, and the effect of reducing the area of ​​the pixel circuit PXC can be achieved. Therefore, compared to the first pixel PXL1, the aperture ratio of the elements arranged below the pixel circuit PXC of the second pixel PXL2 can be increased.

[0225] According to some example implementations, the scan signal GC provided to the multiple third scan lines Gi3 and Gp3 can be maintained at a first voltage level (low level) as a gate turn-off signal during the transmission period TP4_pre of the previous frame, can be changed to a second voltage level (high level) as a gate turn-on signal at the beginning of the initialization period TP1, and can be changed to a first voltage level (low level) as a gate turn-off signal at the beginning of the delay period TP3 (see...). Figure 27 ).

[0226] According to some example implementations, the scan signal GC provided to the multiple third scan lines Gi3 and Gp3 can be maintained at a first voltage level (low level) as a gate turn-off signal during the transmit period TP4_pre of the previous frame, can be changed to a second voltage level (high level) as a gate turn-on signal at the beginning of the data write period TP2, and can be changed to a first voltage level (low level) as a gate turn-off signal at the beginning of the delay period TP3 (see...). Figure 28 ).

[0227] During the delay period TP3, when the second transistor T2 in each of the plurality of sub-pixels SP1 and SP2 of the first pixel PXL1 is turned off, the voltage level V at the gate electrode of the first transistor T1 is... T1G_PXL1 The fifth level V5 can be increased due to the effect of the first boost capacitor Cb1.

[0228] Simultaneously, during the delay period TP3, when the second transistor T2 in each of the multiple sub-pixels SP1 and SP2 of the second pixel PXL2 is turned off, the voltage level V at the gate electrode of the first transistor T1... T1G_PXL2 However, due to the influence of the first boost capacitor Cb1 and the second boost capacitor Cb2, the voltage level V6 is reduced to less than the fifth level V5.

[0229] During the transmission period TP4, the voltage level V of the gate electrode of each first transistor T1 of the first pixel PXL1 and the second pixel PXL2 is... T1G_PXL1 and voltage level V T1G_PXL2 It can maintain a voltage level similar to that in the delay period TP3.

[0230] In this method, the voltage level V of the gate electrode of each first transistor T1 of the first pixel PXL1 and the second pixel PXL2 is... T1G_PXL1 and voltage level V T1G_PXL2 They can be adjusted to be different. Therefore, even if the same voltage level data signal is provided to the first pixel PXL1 and the second pixel PXL2, a current difference is still generated for each light-emitting element OLED of the first pixel PXL1 and the second pixel PXL2, and thus the brightness can be adjusted.

[0231] Although various aspects of some exemplary embodiments according to this disclosure have been described with reference to the accompanying drawings, those skilled in the art will understand that embodiments may be implemented in other specific forms without altering the technical spirit and essential characteristics of this disclosure. Therefore, it should be understood that the above embodiments are illustrative and non-limiting in all respects.

Claims

1. A display device, comprising: The display unit includes a first display area having a plurality of first pixels and a second display area having a plurality of second pixels, wherein the second display area is surrounded by the first display area; A data driver is configured to provide a data signal to each data line connected to the plurality of first pixels and the plurality of second pixels; A scan driver is configured to provide a scan signal to each scan line connected to the plurality of first pixels and the plurality of second pixels; as well as The emission controller is configured to provide emission control signals to each emission control line connected to the plurality of first pixels and the plurality of second pixels. Wherein, the plurality of first pixels have a first density in the first display area. The plurality of second pixels have a second density in the second display area that is lower than the first density. The plurality of first pixels includes at least one sub-pixel, and the sub-pixel of the plurality of first pixels includes a first boost capacitor connected between a node electrically connected to the gate electrode of each driving transistor and the scan line, and The plurality of second pixels includes at least one sub-pixel, and the at least one sub-pixel of the plurality of second pixels includes the first boost capacitor and a second boost capacitor connected between the node and the emission control line.

2. The display device according to claim 1, wherein, In the sub-pixels of the plurality of second pixels, the capacitance of the second boost capacitor is greater than the capacitance of the first boost capacitor.

3. The display device according to claim 1, wherein, The second boost capacitor includes a first electrode formed on a component electrically connected to the emitter control line and a second electrode formed on a component electrically connected to the gate electrode of the drive transistor.

4. The display device according to claim 3, wherein, The first boost capacitor includes a third electrode formed on a component electrically connected to the scan line and a fourth electrode formed on a component electrically connected to the gate electrode of the drive transistor.

5. The display device according to claim 3, wherein, The first electrode is formed on the first gate electrode layer. The second electrode is formed on the first source-drain electrode layer, and The first source-drain electrode layer is located on the first gate electrode layer.

6. The display device according to claim 5, wherein, The first gate electrode layer includes the emitter control line, and The first source-drain electrode layer includes an electrode pattern electrically connected to the node, and defines an overlapping region in the electrode pattern that overlaps with the emission control line.

7. The display device according to claim 6, wherein, The gate electrode and the emitter control line are physically separated from each other.

8. The display device according to claim 6, wherein, The plurality of first pixels do not include the second boost capacitor.

9. The display device according to claim 5, further comprising: The second gate electrode layer on the first gate electrode layer; as well as The second source-drain electrode layer on the first source-drain electrode layer, The first source-drain electrode layer is located on the second gate electrode layer.

10. The display device according to claim 1, wherein, The driving transistor is a P-type transistor.

11. The display device according to claim 1, further comprising: The sensor that overlaps with the second display area.

12. The display device according to claim 1, wherein, The first density is 4 to 16 times greater than the second density.

13. A method for driving a display device, the display device comprising a first display area having a plurality of first pixels having a first density and a second display area having a plurality of second pixels having a second density less than the first density, the method comprising: During the frame initialization period, the gate electrode of the driving transistor or the anode of the light-emitting element of one of the plurality of first pixels or the plurality of second pixels is initialized; During the data write period following the initialization period, a data signal is written to the first electrode of the driving transistor; as well as During the emission period following the delay period and the data writing period, the light-emitting elements of the plurality of first pixels and the light-emitting elements of the plurality of second pixels emit light. Specifically, the voltage level of the gate electrode of the plurality of first pixels decreases by a first level during the emission period. The voltage level of the gate electrode of the plurality of second pixels decreases to a second level greater than the first level during the emission period, and The second display area is surrounded by the first display area.

14. The method according to claim 13, wherein, The voltage level of the gate electrode of the plurality of first pixels is increased by a third level during the delay period, and The voltage level of the gate electrode of the plurality of second pixels increases to a fourth level less than the third level during the delay period.

15. The method according to claim 13, wherein, Each of the plurality of first pixels and the plurality of second pixels includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor as driving transistors. The first electrode of the first transistor is connected to the fifth transistor, the second electrode of the first transistor is connected to the sixth transistor, and the gate electrode of the first transistor is connected to the first node. The second transistor is connected between the data line and the first electrode of the first transistor, and the gate electrode of the second transistor is connected to the first scan line. The third transistor is connected between the first electrode of the first transistor and the first node, and the gate electrode of the third transistor is connected to the first scan line. The fourth transistor is connected between the first node and the initialization power line to which initialization power is applied, and the gate electrode of the fourth transistor is connected to the second scan line. Each gate electrode of the fifth and sixth transistors is connected to a transmit control line that provides transmit control signals.

16. The method according to claim 15, wherein, The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are P-type transistors.

17. The method according to claim 15, wherein, The plurality of second pixels also include a first boost capacitor connected between the first node and the emission control line.

18. The method according to claim 17, wherein, Each of the plurality of first pixels and the plurality of second pixels further includes a second boost capacitor connected between the first node and the first scan line.

19. A display device, comprising: The display unit includes a first display area having a plurality of first pixels and a second display area having a plurality of second pixels, wherein the second display area is surrounded by the first display area; A data driver is configured to provide a data signal to each data line connected to the plurality of first pixels and the plurality of second pixels; A scan driver is configured to provide a plurality of scan signals to a first scan line, a second scan line, and a third scan line, each connected to the plurality of first pixels and the plurality of second pixels; as well as The emission controller is configured to provide emission control signals to each emission control line connected to the plurality of first pixels and the plurality of second pixels. Wherein, the plurality of first pixels have a first density in the first display area. The plurality of second pixels have a second density in the second display area that is less than the first density, and The plurality of second pixels include at least one sub-pixel, the at least one sub-pixel including a first boost capacitor connected between a node electrically connected to the gate electrode of each driving transistor included in each second pixel and the first scan line, and a second boost capacitor connected between the node and the second scan line.

20. The display device according to claim 19, wherein, Each of the plurality of first pixels and the plurality of second pixels includes a first transistor as the driving transistor, a second transistor having a gate electrode connected to the first scan line, and a third transistor having a gate electrode connected to the second scan line.

21. The display device according to claim 20, wherein, The first transistor and the second transistor are P-type transistors, and The third transistor is an N-type transistor.

22. The display device according to claim 19, wherein, The display device is driven per frame by a time period including the following: The initialization period is the period during which the gate electrode of each driving transistor of the plurality of first pixels and the plurality of second pixels or the anode of the light-emitting element is initialized to the initialization voltage; The data writing period is the period after the initialization period during which the data signal is written to the first electrode of each of the driving transistors; The delay period is the period after the data writing period and before the light-emitting element begins to emit light; as well as During the emission period following the delay period, each of the light-emitting elements of the plurality of first pixels and the plurality of second pixels emits light during the emission period. The voltage level of the gate electrode of the plurality of first pixels increases by a first level during the delay period, and The voltage level of the gate electrode of the plurality of second pixels decreases to a second level less than the first level during the delay period.

23. The display device according to claim 22, wherein, At least one of the plurality of scan signals is converted to a gate-on level at the beginning of the initialization period and to a gate-off level at the beginning of the delay period.

24. The display device according to claim 19, wherein, The display device is a mobile terminal.

25. The display device according to claim 19, wherein, The capacitance of the second boost capacitor is smaller than that of the first boost capacitor.

Images