Circuit assembly with electrical isolation

Abstract

Embodiments in accordance with the present disclosure relate to a circuit assembly with electrical isolation. According to one embodiment, the circuit assembly has a primary coil and a secondary coil that are inductively coupled but electrically isolated from each other, a first voltage divider connected between first and second terminals of the secondary coil and having a center tap connected to a ground node, a second voltage divider connected between the first and second terminals of the secondary coil, and an active circuit connected to the first and second terminals of the secondary coil, the center tap of the second voltage divider, and the ground node. The active circuit is designed to provide current paths between the first terminal of the secondary coil and the ground node and between the second terminal of the secondary coil and the ground node in dependence on a voltage at the center tap of the second voltage divider.

Description

TECHNICAL FIELD

[0001] The present specification relates to the field of integrated circuits with integrated coreless transformers for galvanic isolation of electronic circuits. BACKGROUND

[0002] Galvanic isolation (also referred to as electrical isolation) is required in many applications. One example is a semiconductor switch (e.g. IGBT for an inverter) with integrated driver electronics containing one or more integrated coreless transformers to galvanically isolate the semiconductor switch from control logic contained in the driver electronics. Here, control signals are transmitted from the control logic to the driver circuit via the coreless transformer. The driver circuit switches the semiconductor switch on and off depending on the received control signals. Signal transmission via integrated coreless transformers is known per se and products using integrated coreless transformers for galvanic isolation are commercially available.

[0003] A parameter that can be relevant to the performance of such products is the so-called CTMI value (CTMI = Common Mode Transient Immunity). The CTMI value represents the maximum allowable rate of change of a common mode voltage (e.g. volts per nanosecond) between two galvanically isolated circuits. This common mode voltage can be observed, for example, between the ground nodes of two galvanically isolated circuits.

[0004] With the introduction of silicon carbide devices, for example in inverter applications, the switching frequency has become higher and thus the requirements on the driver electronics in terms of CTMI have increased. A known method for achieving a high CTMI value is to use a coreless transformer with full differential signal transmission. Since the coreless transformer is integrated in the metallization layer of a semiconductor chip, it is not easy to manufacture a coupling coil with a center tap (such a coupling coil is necessary for differential operation). In practice, a coil with a center tap is manufactured by arranging two sub-coils connected in series next to each other in the metallization layer. As a result, the coreless transformer requires four sub-coils, two series coils on the primary side of the coreless transformer and two corresponding series coils on the secondary side of the coreless transformer. This method can achieve a high CTMI, however, results in a very high chip area consumption, since the number of coils required for differential transmission is twice that of a "normal" coreless transformer with non-differential ("single-ended") transmission.

[0005] In view of the above, it can be seen as an object of the present invention to provide a circuit assembly with a coreless transformer that has a relatively high CTMI value and at the same time requires a relatively small chip area. SUMMARY

[0006] The above objects are achieved by a circuit assembly according to the present application and by a method according to the present application. Various embodiments and refinements are subject of the dependent claims.

[0007] In the following a circuit assembly with electrical isolation is described. According to one embodiment the circuit assembly has a primary coil and a secondary coil which are inductively coupled but electrically isolated from each other, a first voltage divider connected between a first terminal and a second terminal of the secondary coil and having a center tap connected to a ground node, a second voltage divider connected between the first terminal and the second terminal of the secondary coil, and an active circuit connected to the first terminal and the second terminal of the secondary coil, to the center tap of the second voltage divider, and to the ground node. The active circuit is designed to provide a current path between the first terminal of the secondary coil and the ground node and between the second terminal of the secondary coil and the ground node depending on a voltage at the center tap of the second voltage divider.

[0008] Further, a method for transmitting a differential signal by a coreless transformer having a primary coil and a secondary coil is described, wherein a voltage divider is connected between a first terminal and a second terminal of the secondary coil and a center tap of the voltage divider is connected to a ground node. According to one embodiment the method comprises generating a control voltage depending on a common mode voltage at the first terminal and the second terminal of the secondary coil, and activating a current path between the first terminal of the secondary coil and the ground node by driving a first transistor with the control voltage, wherein a load current path of the first transistor couples the first terminal of the secondary coil to the ground node. Further, the method comprises activating a current path between the second terminal of the secondary coil and the ground node by driving a second transistor with the control voltage, wherein a load current path of the second transistor couples the second terminal of the secondary coil to the ground node. BRIEF DESCRIPTION OF DRAWINGS

[0009] In the following embodiments will be explained in more detail with reference to the drawings. The drawings show in general schematic illustrations and the embodiments are not limited to the aspects shown. Rather, the focus is on illustrating the principles on which the embodiments are based. Among others:

[0010] Figure 1 An example of a circuit assembly with a coreless transformer suitable for differential signal transmission is shown. The primary coil and the secondary coil of the coreless transformer are two sub-coils in series, respectively.

[0011] Figure 2 An example of a circuit assembly with a coreless transformer is shown, which is composed of two coupled coils without a center tap. The secondary coil is connected with a voltage divider having a center tap.

[0012] Figure 3 Another example of a circuit assembly with a coreless transformer is shown, which is composed of two coupled coils without a center tap. The secondary coil is coupled with an active circuit, which leads out undesired displacement currents.

[0013] Figure 4 Another example is shown, which is a modification of the example in Figure 3

[0014] Figure 5 An alternative implementation of the example in Figure 4 is shown.

[0015] Figure 6 Another alternative of the example in Figure 4 is shown.

[0016] Figure 7 is a flow chart showing one example of a method that can be implemented by the active circuit in Figure 3 DETAILED DESCRIPTION

[0017] Figure 1 An example of a circuit assembly with a coreless transformer suitable for differential signal transmission is shown. The primary coil and the secondary coil of the coreless transformer are two series-connected sub-coils L P1 and L P2 (primary side) and L S1 and L S2 (secondary side), respectively. A circuit node between the two sub-coils L P1 and L P2 is connected with a first ground node GND1 and a circuit node between the two sub-coils L S1 and L S2 is connected with a second ground node GND2. The first ground node GND1 is electrically isolated from the second ground node GND2, i.e. the corresponding ground potentials can move relative to each other. The voltage between the first ground node GND1 and the second ground node GND2 is the above-mentioned common-mode voltage, which can change relatively fast (e.g. several hundred volts per nanosecond) depending on the application.

[0018] The transmitter circuit 11 is coupled with the primary coil (sub-coils L P1 and L P2 ) and the receiver circuit 21 is coupled with the secondary coil (sub-coils L S1 and L S2 ​​The transmitter circuit 11 is designed to transmit signals via a coreless transformer formed by a primary coil and a secondary coil, and the receiver circuit 21 is designed to receive the transmitted signals. The transmitter circuit 11 operates in a first voltage domain having a ground potential at a ground node GND1, and the receiver circuit 21 operates in a second voltage domain having a ground potential at a ground node GND2. In the example shown, the transmitter circuit 11 and the coreless transformer are integrated in a first semiconductor chip 1, while the receiver circuit 21 is integrated in a second semiconductor chip 2. The second semiconductor chip 2 is connected to the secondary coil of the coreless transformer, for example, by means of bonding wires. Center taps of the primary and secondary coils, connected to their respective ground nodes, allow for a symmetrical structure of the circuit components and fully differential signal transmission via the coreless transformer. The two semiconductor chips 1 and 2 can be housed in the same chip housing.

[0019] As mentioned above, Figure 1 Symmetrical design of circuit components in a chip can lead to high chip area consumption. Figure 2 The example shown is a circuit assembly with a coreless transformer, which consists of two coupled coils (primary coil L) without a center tap. P and secondary coil L S As in the previous example, a coreless transformer couples the transmitter circuit 11 and receiver circuit 21, which are integrated in different semiconductor chips. Refer to the description above for details. This is achieved by using two identical resistors R... sym The voltage divider and secondary coil L S The parallel connection ensures symmetry (balance) on the secondary side of the coreless transformer. The center tap of the voltage divider is connected to the ground node GND2 of the second voltage domain. Therefore, the receiver circuit "sees" the differential signal of the potential of the reference ground node GND2.

[0020] However, in practice, only when the resistance R of the voltage divider... sym When it is relatively small, Figure 2 The circuit only works when the resistor R is in the circuit. sym In cases where the voltage is too high, the following situation may occur: the maximum permissible input voltage range at the input terminal of receiver circuit 21 may be exceeded. The primary and secondary coils of the integrated coreless transformer are inductively coupled, but due to manufacturing technology, they also exhibit capacitive coupling. This capacitive coupling is caused by the parasitic capacitor C. P This indicates that the parasitic capacitor C P The primary and secondary coils are coupled. When the common-mode voltage between ground nodes GND1 and GND2 changes, it is through capacitor C... PThis generates a displacement current. On the secondary side, this displacement current flows through resistor R. sym The current flows to the ground node GND2, causing a corresponding voltage drop in the resistor. This voltage drop may be high, exceeding the allowable input voltage range of the receiver circuit 21. However, if the resistor R... sym Choosing a relatively small value will reduce the amplitude of the differential signal transmitted through the transformer, thereby reducing the reliability of the transmission.

[0021] therefore, Figure 2 The example in the example theoretically allows for differential signal transmission using a simple coreless transformer (without a center tap in the primary and secondary coils); however, the resistor R... sym The design of this type of resistor can cause serious problems in practice. The method described below enables the resistor R to be... sym The range of options is relatively large, and it still follows the allowable input voltage range of receiver circuit 21.

[0022] Figure 3 Another example of a circuit assembly with a coreless transformer is shown, which consists of two coupled coils without a center tap. Figure 3 Examples and Figure 2 The examples in the text are basically the same, but Figure 3 The example in the example has a secondary coil L S An additional active circuit is coupled in place. This active circuit actively responds to the aforementioned displacement current and drains the displacement current through a temporary low-resistance current path. Figure 2 Similarly, the transmitter circuit 11 and the coreless transformer can be integrated into the first chip 1, and the receiver circuit 21 can be integrated into the second chip 2. The two chips 1 and 2 can be arranged in the same chip housing P and connected by means of bonding wire B.

[0023] As described above, the voltage change dV between grounding nodes GND1 and GND2 CMT / dt will cause water to flow through the parasitic capacitor C. P displacement current i CTM As an illustrative example, suppose C P =0.1pF, and dV CMT / dt = 200V / ns. These values ​​can be used to obtain the displacement current i. CTM =20mA. It can be seen that at receiver circuit 21, even a relatively small resistance of a few hundred ohms will result in a relatively high input voltage, which receiver circuit 21 with a typical power supply voltage of 1.5V cannot handle.

[0024] With secondary coil LS The coupled active circuit solves the above problems by temporarily providing a current path between the first terminal of the secondary winding L S and the ground node GND2 and between the second terminal of the secondary winding L S and the ground node GND2 in order to derive the displacement current i CTM . The further voltage divider is symmetrically constructed with respect to its center tap; it consists of a series circuit of two identical resistors R1, R1 connected between the first terminal of the secondary winding L S and the second terminal of the secondary winding L S .

[0025] In the example shown in Fig. Figure 3 , the active circuit has a first transistor T N1 and a second transistor T N2 . The first transistor T N1 has a load current path connecting the first terminal of the secondary winding L S and the ground node GND2, and the second transistor T N2 has a load current path connecting the second terminal of the secondary winding L S and the ground node GND2. The control electrode of the first transistor T N1 and the control electrode of the second transistor T N2 are coupled to the center tap of the second voltage divider R1. In other words, the center tap of the further voltage divider R1, R1 provides a control voltage V0 for the transistors T N1 and T N2 , which depends on the common-mode voltage V1 = R S · i sym at the first and second terminals of the secondary winding L CTM . However, the differential signal transmitted by the coreless transformer does not change the control voltage V0.

[0026] The transistors T N1 and T N2 are activated in response to a potential drop of the ground node GND2 (relative to the potential of the ground node GND1). In this case, the rate of change dV CMT / dt and the resulting displacement current i CTM are positive, which results in a positive control voltage V0 that is suitable for switching on the transistors T N1 and T N2 . In the present example, the transistors T N1 and T N2 are implemented as n-channel MOS transistors. In order to achieve good performance, it is desirable that the two transistors T N1 and TN2 They should have the most similar characteristics (characteristic curves) and the same electrical performance.

[0027] In order to also handle negative rates of change dV CMT / dt responds, and the active circuit can also have a third transistor T. P1 and the fourth transistor T P2 The third transistor T P1 With connection to secondary coil L S The load current path between the first terminal and the ground node GND2, and the fourth transistor T P2 With connection to secondary coil L S The load current path between the second terminal and the ground node GND2. The third transistor T... P1 control electrode and fourth transistor T P2 The control electrode is also coupled to the center tap of the second voltage divider R1. The third transistor T... P1 and the fourth transistor T P2 It is related to the first transistor T N1 Second transistor T N2 The transistor types are complementary. In this example, transistor T P1 and T P2 It is implemented as a p-channel MOS transistor. Two transistors T P1 and T P2 They can have the same characteristics (characteristic curves) and the same electrical performance. At the rate of change dV CMT When / dt is negative, the control voltage V0 is also negative, and sufficient to activate transistor T. P1 and T P2 .

[0028] In the example illustrated here, the transistor T of the active circuit N1 T N2 T P1 and T P2 It is implemented as a MOS field-effect transistor (MOSFET). A MOSFET typically has an intrinsic body diode parallel to the MOS channel of the corresponding transistor (i.e., parallel to the load current path). For an n-channel transistor, the source electrode is the anode of the intrinsic body diode, and the drain electrode is the cathode of the intrinsic body diode (the opposite is true for a p-channel transistor). Figure 3 In the example shown, although the active circuit provides protection against transient common-mode current, transistor T N1 T N2 T P1 and T P2The intrinsic body diode limits the possible voltage swing of the differential signal transmitted through the coreless transformer to approximately ±0.7V (depending on temperature), which corresponds to the forward voltage of the body diode. To address this issue, the diode can be coupled with a transistor T. N1 T N2 T P1 and T P2 The load current path (i.e., the drain-source current path) is connected in series, where these diodes are connected in anti-series with the intrinsic body diode. Figure 4 This situation is illustrated.

[0029] Besides the transistor T N1 T N2 T P1 or T P2 In addition to the diodes D1, D2, D3, and D4 arranged in series for the load current path, Figure 4 The example shown is the same as Figure 3 The example is the same. When the transistor is off, diodes D1, D2, D3, and D4 are connected in anti-series connection with their respective body diodes. Figure 4 The transistor T is clearly shown in the text. N1 T N2 T P1 and T P2 The intrinsic body diodes. In the remaining figures, the intrinsic body diodes have been omitted for simplicity, but they are still present.

[0030] exist Figure 4 In the example shown, diodes D1, D2, D3, and D4 are implemented using pn junctions; that is, they are conventional silicon diodes (if silicon is used as the semiconductor substrate). Alternatively, the diodes can also be implemented as MOS diodes. This is the case in... Figure 5 As shown, the MOS transistors connected as "MOS diodes" are represented by D1', D2', D3', and D4'. Transistors D1' and D2', operating as diodes, are p-channel MOSFETs, and transistors D3' and D4' are n-channel MOSFETs. The gate electrodes of transistors D1', D2', D3', and D4' are connected to a constant potential, which in this example is connected to the ground node GND2. For simplicity, ... Figure 5 The intrinsic body diode of the transistor is not shown, but it is still present. In this example, the transistor T is connected in series. N1 and D1' (and T) N2 The intrinsic body diodes (such as D2', etc.) are not connected in anti-series. Therefore, Figure 5 The circuit in has the same Figure 3The same problem exists in the circuit, however, the possible voltage swing of the differential signal transmitted through the coreless transformer is not limited to about ±0.7V, but to twice that value of about ±1.4V, which is sufficient for many applications.

[0031] Figure 6 Another example is shown, which can be regarded as Figure 4 The example in the text is an alternative solution. To avoid the aforementioned limitations on the voltage swing of the differential signal, transistor T... N1 T N2 T P1 and T P2 The body terminal (also known as the bulk-anschluss terminal) can also be connected to a circuit node with a constant reference voltage. Figure 6 In the example, this constant reference voltage is for the n-channel transistor T N1 and T N2 V- represents the value of T for a p-channel transistor. P1 and T P2 Represented by V+. Unlike this, in Figure 4 In the example, the body terminal of the transistor is directly connected to the source electrode of the corresponding transistor. Figure 6 In the example, the reference voltage V- is negative relative to ground GND2, and the reference voltage V+ is positive and higher than the power supply voltage V of the receiver circuit 21. S For example, it is possible to use techniques known in themselves (such as charge pumps) based on the power supply voltage V. S To provide reference voltages V+ and V-.

[0032] The following will summarize Figures 3 to 6 The embodiments described herein are functional. It should be understood that the following description is not a complete enumeration of the functions provided by the embodiments, but only summarizes some important aspects by way of example. Figure 7 It can be made by Figures 3 to 6 The flowchart shows the method for implementing active circuits in the diagram.

[0033] Essentially, the embodiments described herein implement a method for using a primary coil (see, for example, see...) Figures 3 to 6 Primary coil L P ) and secondary coil L S (For example, see) Figures 3 to 6 Secondary coil L S A method of transmitting differential signals using a coreless transformer. A voltage divider is connected between the first and second terminals of the secondary coil (see, for example, see...). Figures 3 to 6 It has two resistors R sym The voltage divider), and the center tap of the voltage divider is connected to the grounding node (see, for example, the voltage divider). Figures 3 to 6GND2 represents the ground terminal of the secondary side electronic device). According to Figure 7 the method comprises generating a control voltage (see Figure 7 , step S1) which depends on the common mode voltage at the first terminal and the second terminal of the secondary coil (see Figure 3 , common mode voltage VI). The method further comprises activating a current path between the first terminal of the secondary coil and the mentioned ground node by driving the first transistor with the control voltage (see Figure 7 , step S2). For this purpose, the load current path of the first transistor couples the first terminal of the secondary coil with the ground node. The method further comprises activating a current path between the second terminal of the secondary coil and the ground node by driving the second transistor with the control voltage (see Figure 7 , step S3). For this purpose, the load current path of the second transistor couples the second terminal of the secondary coil with the ground node (see Figures 3 to 6 , transistors T N1 and T N2 ).

[0034] It should be understood that the functionality provided by the embodiments described herein can be implemented in many different manners. Accordingly, the specific circuitry shown in the drawings is merely provided as an example. The circuitry can also be constructed more complex and with additional components depending on the actual application. It should be understood that circuitry parts which are known per se and which are not necessary for the description of the functionality (e.g. charge pumps, conventional power supply circuitry, etc. as mentioned with reference to Figure 6 have been omitted in order not to unnecessarily complicate the description.

Claims

1. A circuit assembly having the following: a primary coil (L P ) and a secondary coil (L S ), which are inductively coupled but electrically isolated from each other; a first voltage divider (R SYM ) connected between the first terminal and the second terminal of the secondary winding (L S ) and having a center tap connected to a ground node (GND2); a second voltage divider (R1) connected between the first terminal and the second terminal of the secondary winding (L S ) an active circuit connected to the first terminal and to the second terminal of the secondary winding (L S ), to the center tap of the second voltage divider (R1), and to the ground node (GND2), wherein the active circuit comprises: a first transistor (T N1 ) having a load current path connecting the first terminal of the secondary coil (L S ) and the ground node (GND2), a second transistor (T N2 ) having a load current path connecting the second terminal of the secondary coil (L S ) and the ground node (GND2), a third transistor (T P1 ) having a load current path connecting the second terminal of the secondary coil (L S ) and the ground node (GND2), a fourth transistor (T P2 ) having a load current path connecting the first terminal of the secondary coil (L S ) and the ground node (GND2), wherein the control electrode of the first transistor (T N1 ), the control electrode of the second transistor (T N2 ), the control electrode of the third transistor (T P1 ) and the control electrode of the fourth transistor (T P2 ) are coupled to the center tap of the second voltage divider (R1).

2. The circuit assembly according to claim 1, wherein the active circuit is designed to provide a current path between the first terminal of the secondary coil (L S ) and the ground node (GND2), and between the second terminal of the secondary coil (L S ) and the ground node (GND2), depending on the voltage at the center tap of the second voltage divider (R1).

3. The circuit assembly according to claim 1, wherein the first voltage divider (R SYM ) is symmetrically configured with respect to a center tap of the first voltage divider.

4. The circuit assembly according to any one of claims 1 to 3, wherein the second voltage divider (R1) is symmetrically configured with respect to a center tap of the second voltage divider.

5. The circuit assembly according to any one of claims 1 to 3, wherein said first transistor (T N1 ) and said second transistor (T N2 ) have the same characteristics.

6. The circuit assembly according to any one of claims 1 to 3, wherein the third transistor (T P1 ) and the fourth transistor (T P2 ) have the same characteristics.

7. The circuit assembly according to any one of claims 1 to 3, wherein said first transistor (T N1 ) and said second transistor (T N2 ) are of a first transistor type, and said third transistor (T P1 ) and said fourth transistor (T P2 ) are of a second transistor type complementary to said first transistor type.

8. The circuit assembly according to any one of claims 1 to 3, wherein the load current path of the first transistor (T N1 ), the load current path of the second transistor (T N2 ), the load current path of the third transistor (T P1 ), and the load current path of the fourth transistor (T P2 ) are connected in series with a diode, respectively.

9. The circuit assembly according to claim 8, wherein the diode is implemented as a pn junction or a MOS diode.

10. The circuit assembly according to any one of claims 1 to 3, wherein the load current path of the first transistor (T N1 ), the load current path of the second transistor (T N2 ), the load current path of the third transistor (T P1 ), and the load current path of the fourth transistor (T P2 ) are connected in series with the load current path of a further transistor (D1’, D2’, D3’, D4’), respectively.

11. The circuit assembly according to claim 10, wherein the further transistor (D1’, D2’, D3’, D4’) is designed as a MOS transistor, the gate electrode of which is coupled to the ground node (GND2).

12. The circuit assembly according to any one of claims 1 to 3, wherein the first transistor (T N1 ) and the second transistor (T N2 ) have a body terminal connected to a constant first voltage (V-).

13. The circuit assembly according to any one of claims 1 to 3, wherein said third transistor (T P1 ) and said fourth transistor (T P2 ) have a body terminal connected to a constant second potential (V+), which is higher than the potential of said ground node (GND2).

14. The circuit assembly according to any one of claims 1 to 3, further having: a transmitter circuit (11) designed to drive the primary coil (L P ), wherein the transmitter circuit (11) is arranged in a first semiconductor chip (1), and wherein the active circuit is arranged in a second semiconductor chip (2), and wherein the two semiconductor chips are arranged in the same chip housing (P).

15. A semiconductor component having the following: a chip housing having a first semiconductor chip (1) and a second semiconductor chip (2); The circuit assembly according to any one of claims 1 to 14, wherein the primary coil (L P ) and the secondary coil (L S ) are integrated in a metallization layer of the first semiconductor chip (1), and wherein the first voltage divider (R SYM ), the second voltage divider (R1) and the active circuit are integrated in the second semiconductor chip (2).

16. The semiconductor component according to claim 15, wherein the first terminal of the secondary coil (L S ) and the second terminal of the secondary coil (L S ) are connected with the second semiconductor chip (2) by bond wires, respectively.

17. A method for transmitting a differential signal through a coreless transformer having a primary coil (Lp) and a secondary coil (Ls), wherein a voltage divider (Rv) is connected between a first terminal and a second terminal of the secondary coil (Ls), and a center tap of the voltage divider (Rv) is connected to a ground node (GND2); the method comprising: applying a first voltage (Vp) to the primary coil (Lp); applying a second voltage (Vp) to the primary coil (Lp); and connecting a first terminal of the secondary coil (Ls) to a first terminal of the voltage divider (Rv) and connecting a second terminal of the secondary coil (Ls) to a second terminal of the voltage divider (Rv). P ) and a secondary coil (L S ); wherein a voltage divider (R S ) is connected between a first terminal and a second terminal of the secondary coil (L SYM ), and a center tap of the voltage divider (R SYM ) is connected to a ground node ( - generating a control voltage dependent on a common mode voltage at the first and second terminals of the secondary winding (L S ) by driving the first transistor (T N1 ) and the fourth transistor (T P2 ) with the control voltage to activate a current path between the first terminal of the secondary coil (L S ) and the ground node (GND2), wherein a load current path of the first transistor (T N1 ) or a load current path of the fourth transistor (T P2 ) couples the first terminal of the secondary coil (L S ) with the ground node (GND2); and by driving the second transistor (T N2 ) and the third transistor (T P1 ) with the control voltage to activate a current path between the second terminal of the secondary coil (L S ) and the ground node (GND2), wherein a load current path of the second transistor (T N2 ) or a load current path of the third transistor (T P1 ) couples the second terminal of the secondary coil (L S ) with the ground node (GND2).

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