Metal gate and method for forming the same

Abstract

The present disclosure relates to metal gates and methods for forming the same. A method includes: depositing a first conductive layer on a gate dielectric layer; depositing a first work function adjustment layer on the first conductive layer; selectively removing the first work function adjustment layer from a first region of the first conductive layer; doping the first work function adjustment layer with a dopant; and after doping the first work function adjustment layer, performing a first treatment process to etch the first region of the first conductive layer and the second region of the first work function adjustment layer. The first treatment process etches the first conductive layer at a greater rate than etching the first work function adjustment layer.

Description

Technical Field

[0001] The present disclosure relates to metal gates and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of material over a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.) by continually reducing minimum feature sizes, which allows more components to be integrated into a given area. Summary of the invention

[0004] According to one embodiment of the present disclosure, a method for forming a gate electrode is provided, the method comprising: depositing a first conductive layer on a gate dielectric layer; depositing a first work function adjustment layer on the first conductive layer; selectively removing the first work function adjustment layer from a first region of the first conductive layer; doping the first work function adjustment layer with a dopant; and after doping the first work function adjustment layer, performing a first treatment process to etch the first region of the first conductive layer and a second region of the first work function adjustment layer, wherein the first treatment process etches the first conductive layer at a greater rate than etching the first work function adjustment layer.

[0005] According to another embodiment of the present disclosure, a transistor is provided, comprising: a first source / drain region; a second source / drain region; and a gate, between the first source / drain region and the second source / drain region, the gate comprising: a gate dielectric; and a gate electrode, above the gate dielectric, the gate electrode comprising: a first conductive material; a first p-type work function adjustment metal, above the first conductive material, the first p-type work function adjustment metal comprising silicon or aluminum; an n-type work function adjustment metal, above the first p-type work function adjustment metal; and a filling metal, above the n-type work function adjustment metal.

[0006] According to another embodiment of the present disclosure, a semiconductor device is provided, including: a first gate electrode, the first gate electrode including: a first conductive material, above a first gate dielectric; a first n-type work function adjustment metal, in contact with the first conductive material; and a first filling material, above the first n-type work function adjustment metal; and a second gate electrode, the second gate electrode including: a second conductive material, above the second gate dielectric, the first conductive material being thinner than the second conductive material; a first p-type work function adjustment metal, in contact with the second conductive material, the first p-type work function adjustment metal including silicon or aluminum; a second n-type work function adjustment metal, in contact with the first p-type work function adjustment metal; and a second filling material, above the second n-type work function adjustment metal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is an example of a fin field effect transistor (finFET) in a three-dimensional view according to some embodiments.

[0009] Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Figure 6C , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15A , Fig. 15B and Fig. 15C is a cross-sectional view of an intermediate stage in fabricating a finFET, according to some embodiments. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0011] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0012] Various embodiments provide a gate electrode having a doped work function adjustment layer (e.g., a titanium nitride layer). The work function adjustment layer may be doped with, for example, silicon, aluminum, etc., and the work function adjustment layer may further include oxygen (e.g., Si) bonded to the dopant. x O y 、Al x O y By adjusting the composition of the work function adjustment layer, the etch selectivity between the work function adjustment layer and the underlying layer (e.g., a tantalum nitride layer) can be increased during a chlorine-based process that reduces the thickness of the underlying layer for threshold voltage adjustment. In this way, a greater difference between the threshold voltages of different transistors in a device can be achieved.

[0013] Figure 1An example of a FinFET in a three-dimensional view according to some embodiments is shown. The FinFET includes a fin 72 on a substrate 70 (e.g., a semiconductor substrate). An isolation region 74 is disposed in the substrate 70, and the fin 72 protrudes from above and between adjacent isolation regions 74. Although the isolation region 74 is described / illustrated as being separated from the substrate 70, as used herein, the term "substrate" may be used to refer to only a semiconductor substrate or a semiconductor substrate including an isolation region. In addition, although the fin 72 is shown as a single continuous material that is the same as the substrate 70, the fin 72 and / or the substrate 70 may include a single material or multiple materials. In this context, the fin 72 refers to the portion extending between adjacent isolation regions 74.

[0014] Gate dielectric layer 92 is along the sidewalls of fin 72 and over the top surface of fin 72, and gate electrode 120 is over gate dielectric layer 92. Source / drain region 84 or 86 is disposed on the opposite side of fin 72 relative to gate dielectric layer 92 and gate electrode 120. Figure 1 Reference cross sections used in subsequent figures are further illustrated. Cross section AA is along the longitudinal axis of the gate electrode 120 and in a direction perpendicular to the direction of current flow, for example, between the source / drain regions 84 / 86 of the FinFET. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of the fin 72 and in a direction of current flow, for example, between the source / drain regions 84 / 86 of the FinFET. Cross section CC is parallel to cross section AA and extends through the source / drain regions of the FinFET. For clarity, subsequent figures refer to these reference cross sections.

[0015] Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In some embodiments, a gate-first process may be used. In addition, some embodiments contemplate aspects used in planar devices (e.g., planar field effect transistors), nanostructure (e.g., nanosheets, nanowires, gate-all-around, etc.) field effect transistors (NSFETs), and the like.

[0016] Figures 2 to 15C is a cross-sectional view of an intermediate stage in fabricating a finFET according to an exemplary embodiment. Figure 2 , Figure 3 , Figure 4A , Figure 5A and Fig.15A Shows Figure 1 Reference cross section AA shown, except with multiple fins. Figure 4B , Figure 5B , Fig. 6A , Figures 7 to 14 and Fig. 15B Shows Figure 1 Reference cross section BB is shown, except that there are multiple finFETs. Figure 6B , Figure 6C and Fig. 15C Shows Figure 1 Reference cross section CC is shown, except that there are multiple finFETs.

[0017] Figure 2 A substrate 70 is shown. The substrate 70 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor on insulator (SOI) substrate, a multilayer or gradient substrate, etc. The substrate 70 may include a semiconductor material, such as an elemental semiconductor including Si and Ge; a compound or alloy semiconductor including SiC, SiGe, GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb, and / or GaInAsP; or a combination thereof. The substrate 70 may be doped or undoped. In a specific example, the substrate 70 is a bulk silicon substrate.

[0018] Figure 3 The formation of fins 72 and isolation regions 74 between adjacent fins 72 is shown. Figure 3 In the embodiment of the present invention, fins 72 are formed in substrate 70. In some embodiments, fins 72 may be formed in substrate 70 by etching trenches in substrate 70. The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching may be anisotropic.

[0019] In addition, Figure 3 In the embodiment shown, an insulating material is formed between adjacent fins 72 to form an isolation region 74. The insulating material may be an oxide (e.g., silicon oxide), a nitride, etc., or a combination thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert the deposited material to another material, e.g., oxide), etc., or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the embodiment shown, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. In addition, in Figure 3 In the process, a planarization process such as chemical mechanical polishing (CMP) can remove any excess insulating material and form the top surface of the isolation region 74 and the top surface of the fin 72 to be coplanar.

[0020] Although not specifically shown, appropriate wells may be formed in the fin 72 and / or the substrate 70. For example, a first region 200 and a fourth region 500 (in the substrate 70) in which a p-type device such as a p-type finFET is to be formed may be formed. Figure 4B and subsequent figures), and a second region 300 and a third region 400 (in the substrate 70) in which an n-type device such as an n-type finFET is to be formed may be formed. Figure 4B and shown in subsequent figures) to form a p-well.

[0021] For example, in order to form an n-well in the first region 200 and the fourth region 500, a photoresist may be formed over the fins 72 and the isolation regions 74 in the second region 300 and the third region 400 of the substrate 70. The photoresist may be patterned to expose the first region 200 and the fourth region 500 of the substrate 70. The photoresist may be formed by using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, n-type impurity implantation may be performed in the first region 200 and the fourth region 500, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the second region 300 and the third region 400. The n-type impurity may be phosphorus, arsenic, etc., implanted into the first region 200 and the fourth region 500, and the concentration thereof may be equal to or less than 10 18 cm -3 , for example, at about 10 17 cm -3 and about 10 18 cm -3 After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0022] In addition, in order to form a p-well in the second region 300 and the third region 400, a photoresist may be formed over the fin 72 and the isolation region 74 in the first region 200 and the fourth region 500 of the substrate. The photoresist may be patterned to expose the second region 300 and the third region 400 of the substrate 70. The photoresist may be formed by using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation may be performed in the second region 300 and the third region 400, and the photoresist may act as a mask to substantially prevent the p-type impurity from being implanted into the first region 200 and the third region 400. The p-type impurity may be boron, BF2, etc., implanted into the second region 300 and the third region 400, and the concentration thereof is equal to or less than 10 18 cm -3 , for example, at about 10 17 cm -3 and about 10 18 cm-3 After the implantation, the photoresist may be removed, for example, by an acceptable ashing process. After the implantation, an anneal may be performed to activate the implanted p-type and n-type impurities. The implantation may form an n-well in the first region 200 and the fourth region 400, and may form a p-well in the second region 300 and the third region 400.

[0023] exist Figure 4A and Figure 4B In the embodiment, the isolation regions 74 are recessed, for example, to form shallow trench isolation (STI) regions. The isolation regions 74 are recessed so that the fins 72 protrude from between adjacent isolation regions 74. An acceptable etching process (e.g., an etching process that is selective to the material of the isolation regions 74) may be used to recess the isolation regions 74. Etch or apply material with SICONI tools or chemical oxide removal with dilute hydrofluoric (dHF) acid.

[0024] It will be readily understood by those skilled in the art that Figure 2 , Figure 3 , Figure 4A and Figure 4B The process described is only one example of how fins may be formed. In other embodiments, a dielectric layer may be formed over the top surface of substrate 70; trenches may be etched through the dielectric layer; epitaxial fins may be grown epitaxially in the trenches; and the dielectric layer may be recessed so that homoepitaxial and / or heteroepitaxial structures protrude from the dielectric layer to form epitaxial fins. It may be advantageous to epitaxially grow a different material or epitaxial fin structure for an n-type finFET than that for a p-type finFET.

[0025] exist Figure 5A and Figure 5B In the embodiment of the present invention, a dummy dielectric layer is formed on the fin 72. The dummy dielectric layer can be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to an acceptable technique (e.g., chemical vapor deposition (CVD), thermal oxidation, etc.). A dummy gate layer is formed on the dummy dielectric layer, and a mask layer is formed on the dummy gate layer. The dummy gate layer can be deposited on the dummy dielectric layer, for example, by using CVD, and then the dummy gate layer can be flattened, for example, by CMP. The mask layer can be deposited on the dummy gate layer, for example, by using CVD, etc. The dummy gate layer can include, for example, polysilicon, but other materials with high etching selectivity can also be used. The mask layer can include, for example, silicon nitride, silicon oxynitride, silicon carbonitride, etc.

[0026] In addition, Figure 5A and Figure 5BIn the embodiment of the present invention, the mask layer may be patterned using acceptable photolithography and etching techniques to form a mask 80. The pattern of the mask 80 may then be transferred to the dummy gate layer and the dummy dielectric layer by an acceptable etching technique to form a dummy gate 78 and a dummy gate dielectric 76 from the dummy gate layer and the dummy dielectric layer, respectively. The etching may include acceptable anisotropic etching, such as RIE, NBE, etc. The dummy gate 78 covers each channel region of the fin 72. The dummy gate 78 may also have a length direction substantially perpendicular to the length direction of each fin 72.

[0027] Although not specifically shown, an implantation for a lightly doped source / drain (LDD) region may be performed. Similar to the implantation discussed above, a mask (e.g., a photoresist) may be formed over the second region 300 and the third region 400 (e.g., for an n-type device) while exposing the first region 200 and the fourth region 500 (e.g., for a p-type device), and p-type impurities may be implanted into the exposed fins 72 in the first region 200 and the fourth region 500. The mask may then be removed. Subsequently, a mask (e.g., a photoresist) may be formed over the first region 200 and the fourth region 500 while exposing the second region 300 and the third region 400, and n-type impurities may be implanted into the exposed fins 72 in the second region 300 and the third region 400. The mask may then be removed. The n-type impurity may be any of the n-type impurities discussed previously, and the p-type impurity may be any of the p-type impurities discussed previously. The lightly doped source / drain region may have a thickness of approximately 10 15 cm -3 to about 10 16 cm -3 Annealing can be used to activate the implanted impurities.

[0028] In addition, Figure 5A and Figure 5B In the embodiment of the present invention, a gate spacer 82 is formed along the sidewalls of the dummy gate 78 and the dummy gate dielectric 76. The gate spacer 82 can be formed by conformally depositing (e.g., CVD, etc.) a material and then anisotropically etching (e.g., RIE, NBE, etc.) the material. The material of the gate spacer 82 can be silicon nitride, silicon carbonitride, a combination thereof, etc.

[0029] exist Fig. 6A , Figure 6B and Figure 6CIn the first region 200 and the fourth region 500, epitaxial source / drain regions 84 and 86 are formed in the source / drain regions of the fins 72. In the first region 200 and the fourth region 500, epitaxial source / drain regions 84 are formed in the source / drain regions of the fins 72, so that each dummy gate 78 is disposed between a corresponding pair of epitaxial source / drain regions 84 in each fin 72. In the second region 300 and the third region 400, epitaxial source / drain regions 86 are formed in the source / drain regions of the fins 72, so that each dummy gate 78 is disposed between a corresponding pair of epitaxial source / drain regions 86 in each fin 72.

[0030] The epitaxial source / drain regions 84 in the first region 200 and the fourth region 500 (e.g., for a p-type device) can be formed by, for example, masking the second region 300 and the third region 400 (e.g., for an n-type device) with a hard mask. Then, the source / drain regions of the fins 72 in the first region 200 and the fourth region 500 are etched to form recesses. The etching can be any suitable etching that is selective to the fins 72 and can be anisotropic. The epitaxial source / drain regions 84 in the first region 200 and the fourth region 500 are then epitaxially grown in the recesses. The epitaxial growth can be performed using metal organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), etc. or a combination thereof. The epitaxial source / drain regions 84 can include any acceptable material, such as suitable for p-type finFETs. For example, the epitaxial source / drain regions 84 can include SiGe, SiGeB, Ge, GeSn, etc. In some embodiments, the epitaxial source / drain regions 84 may impose compressive strain on the channel region of the fin 72, thereby improving p-type device performance. The epitaxial source / drain regions 84 may have surfaces that are raised from the corresponding outer surfaces of the fin 72 and may have facets. The mask may then be removed, for example, by using an etch that is selective to the material of the mask.

[0031] The epitaxial source / drain regions 86 in the second region 300 and the third region 400 may be formed by, for example, masking the first region 200 and the fourth region 500 with a hard mask. Then, the source / drain regions of the fins 72 in the second region 300 and the third region 400 are etched to form recesses. The etching may be any suitable etching that is selective to the fins 72 and may be anisotropic. The epitaxial source / drain regions 86 in the second region 300 and the third region 400 are then epitaxially grown in the recesses. The epitaxial growth may be performed using MOCVD, MBE, LPE, VPE, etc. or a combination thereof. The epitaxial source / drain regions 86 may include any acceptable material, such as suitable for n-type finFETs. For example, the epitaxial source / drain regions 86 may include silicon, SiC, SiCP, SiP, etc. In some embodiments, the epitaxial source / drain regions 86 may apply tensile strain on the channel region of the fin 72, thereby improving n-type device performance. The epitaxial source / drain regions 86 may have surfaces that are raised from the corresponding outer surfaces of the fins 72 and may be faceted.The mask may then be removed, for example, by using an etch that is selective to the material of the mask.

[0032] The epitaxial source / drain regions 84 and 86 and / or the source / drain regions of the fin 72 may be implanted with dopants similar to the process previously discussed for forming lightly doped source / drain regions and then annealing. The impurity concentration of the source / drain regions may be about 10 19 cm -3 and about 10 21 cm -3 The p-type impurities for the source / drain regions in the first region 200 and the fourth region 500 (e.g., for p-type devices) may be any of the p-type impurities discussed previously, and the n-type impurities for the source / drain regions in the second region 300 and the third region 400 (e.g., for n-type devices) may be any of the n-type impurities discussed previously. In other embodiments, the epitaxial source / drain regions 84 and 86 may be doped in situ during growth.

[0033] As a result of the epitaxial process used to form epitaxial source / drain regions 84 and 86, the upper surfaces of epitaxial source / drain regions 84 / 86 have facets that extend laterally outward beyond the sidewalls of fin 72. In some embodiments, these facets cause adjacent source / drain regions 84 / 86 of the same FinFET to merge, such as Figure 6B In other embodiments, after the epitaxial process is completed, the adjacent source / drain regions 84 / 86 remain separated, such as Figure 6C As shown. Figure 6B and Figure 6CIn the illustrated embodiment, gate spacers 82 are formed to cover a portion of the sidewalls of fins 72 extending over STI regions 74, thereby preventing epitaxial growth. In some other embodiments, the spacer etch used to form gate spacers 82 can be tuned to remove spacer material, thereby allowing the region of epitaxial growth to extend to the surface of STI regions 74.

[0034] In addition, Fig. 6A , Figure 6B and Figure 6C In the embodiment of the present invention, an etch stop layer (ESL) 88 is conformally formed on the epitaxial source / drain regions 84 and 86, the gate spacer 82, the mask 80, and the isolation region 74. In some embodiments, the ESL 88 may include silicon nitride, silicon carbonitride, etc. formed using ALD, CVD, etc., or a combination thereof. A bottom interlayer dielectric (ILD) 90 is deposited on the ESL 88. The ILD 90 may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc., and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), FCVD, etc., or a combination thereof.

[0035] exist Figure 7 In the embodiment of the present invention, a planarization process such as CMP is performed to make the top surface of the ILD 90 flush with the top surface of the dummy gate 78. The CMP can also remove the mask 80 and the ESL 88 from above the dummy gate 78. Accordingly, the top surface of the dummy gate 78 is exposed by the ILD 90. The dummy gate 78 and the dummy gate dielectric 76 are removed in (one or more) etching steps so that an opening through the ILD 90 and defined by the gate spacer 82 is formed to the fin 72. Each opening exposes a channel region of a corresponding fin 72. Each channel region is disposed between adjacent pairs of epitaxial source / drain regions 84 and 86. The (one or more) etching steps can be selective to the materials of the dummy gate 78 and the dummy gate dielectric 76, and the etching can be a dry etching or a wet etching. During etching, when etching the dummy gate 78, the dummy gate dielectric 76 can be used as an etching stop layer. Then, after removing the dummy gate 78, the dummy gate dielectric 76 can be etched. Although not specifically shown, depending on the similarity of materials used for ILD 90 and dummy gate dielectric 76 , ILD 90 may be recessed when dummy gate dielectric 76 is removed, and the recessing may cause portions of ESL 88 and / or gate spacers 82 to protrude above the top surface of ILD 90 .

[0036] An interface dielectric 92 is formed in each opening and on the fin 72. The interface dielectric 92 may be, for example, an oxide formed by thermal oxidation, chemical oxidation, ALD, etc. The thickness of the interface dielectric 92 may be in the range of about 0.7 nm to about 2 nm. In some embodiments, the dummy gate dielectric 76 is not completely removed from one or more openings, and a separate interface dielectric 92 need not be deposited in these openings. For example, the remaining portion of the dummy gate dielectric 76 may be the interface dielectric 92.

[0037] Then, a gate dielectric layer 94 is conformally formed on the top surface of the ILD 90, along the sidewalls of the gate spacer 82 in the opening, and on the interface dielectric layer 92. In some embodiments, the gate dielectric layer 94 includes a high-k dielectric material, and in these embodiments, the k value of the gate dielectric layer 94 can be greater than about 7.0, and can include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The formation method of the gate dielectric layer 94 can include ALD, CVD, molecular beam deposition (MBD), etc. or a combination thereof. The thickness of the gate dielectric layer 94 can be in the range of about 1.2 nm to about 3 nm. In other embodiments, the gate dielectric layer 94 can have different thicknesses.

[0038] A capping layer is then conformally formed on the gate dielectric layer 94. In the embodiment shown, the capping layer includes a first conductive layer 96 and a second conductive layer 98. In some embodiments, the capping layer may be a single layer, or may include additional conductive layers. The capping layer may be used as a barrier layer to prevent subsequently deposited metal-containing materials from diffusing into the gate dielectric layer 94. In addition, as shown, if the first conductive layer 96 is formed of the same material as the work function adjustment layer, the second conductive layer 98 may be used as an etch stop during the formation of the work function adjustment layer in the various regions 200, 300, 400, and 500, which will become clearer later. The first conductive layer 96 may include titanium nitride (TiN), titanium silicon nitride (ti-SiN), etc. deposited on the gate dielectric layer 94 by ALD, CVD, physical vapor deposition (PVD), etc. The second conductive layer 98 may include tantalum nitride (TaN), etc. deposited on the first conductive layer 96 by ALD, CVD, PVD, etc. The thickness of the capping layer may be in the range of about 0.7 nm to about 6 nm. In the illustrated embodiment, the thickness of the first conductive layer 96 may be in the range of about 0.7 nm to about 3 nm, and the thickness of the second conductive layer 98 may be in the range of about 1 nm to about 3 nm. In other embodiments, other thicknesses are possible.

[0039] A first work function adjustment layer 100 is then conformally formed on the cap layer (e.g., on the second conductive layer 98). The first work function adjustment layer 100 may be any acceptable material to adjust the work function of the device to a desired amount for the application of the device to be formed, and may be deposited using any acceptable deposition process. In some embodiments, the first work function adjustment layer 100 is a p-type work function metal, and may include titanium nitride (TiN) or the like deposited by ALD, CVD, PVD, or the like. The thickness of the first work function adjustment layer 100 may be in the range of about 0.7 nm to about 2.5 nm. In other embodiments, other thicknesses are also possible.

[0040] Then, a mask 102 is deposited over the first work function adjusting layer 100 and patterned. The mask layer 102 may cover the first work function adjusting layer 100 in the third region 400 and the fourth region 500 while exposing the first work function adjusting layer 100 in the first region 200 and the second region 300. In some embodiments, the mask 102 is a photoresist formed by using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the mask 102 is patterned, an etch having selectivity to the first work function adjusting layer 100 is performed to remove the first work function adjusting layer 100 from the first region 200 and the second region 300, as shown in FIG. Figure 8 The second conductive layer 98 in the first region 200 and the second region 300 may serve as an etch stop during this etching. If the mask 102 is a photoresist, the mask 102 is then removed, for example, by using an appropriate wet stripping and / or ashing process.

[0041] exist Figure 8 In the embodiment of the present invention, the second work function adjustment layer 104 is then conformally formed on the capping layer in the first region 200 and the second region 300 (for example, on the second conductive layer 98), and is conformally formed on the first work function adjustment layer 100 in the third region 400 and the fourth region 500. The second work function adjustment layer 104 can be any acceptable material to adjust the work function of the device to a desired amount for the application of the device to be formed, and can be deposited using any acceptable deposition process. In some embodiments, the second work function adjustment layer 104 is a p-type work function metal and can include titanium nitride (TiN) and the like deposited by ALD, CVD, PVD, etc. In some embodiments, the second work function adjustment layer 104 can have the same or different material composition as the first work function adjustment layer 100. In some embodiments, the bottom surface of the second work function adjustment layer 104 can form an interface with the top surface of the first work function adjustment layer 100. The thickness of the second work function adjustment layer 104 can be in the range of about 0.7 nm to about 2.5 nm. In other embodiments, other thicknesses are also possible.

[0042] In some embodiments, a vacuum break may occur between forming the first work function adjusting layer 100 and forming the second work function adjusting layer 104. As a result, the top surface of the first work function adjusting layer 100 may be oxidized. For example, due to the exposure of the top surface of the first work function adjusting layer 100 to the oxygen-containing environment, a titanium oxynitride region may be formed at the top surface of the first work function adjusting layer 100. In such an embodiment, the oxidized region (e.g., the titanium oxynitride region) may be deposited at the interface between the first work function adjusting layer 100 and the second work function adjusting layer 104.

[0043] Then, a mask 106 is deposited over the second work function adjusting layer 104 and patterned. The mask 106 may cover the second work function adjusting layer 104 in the fourth region 500 while exposing the second work function adjusting layer 104 in the first region 200, the second region 300, and the third region 400. In some embodiments, the mask 106 is a photoresist formed by using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the mask 106 is patterned, etching is performed to remove the second work function adjusting layer 104 from the first region 200, the second region 300, and the third region 400, as shown in FIG. Fig. 9 In some embodiments, a timed and / or selective etching process may be performed such that only the second work function adjusting layer 104 is substantially removed in the first region 200, the second region 300, and the third region 400 without significantly removing underlying layers (e.g., the second conductive layer 98 and the first work function adjusting layer 100) in these regions. If the mask 106 is a photoresist, the mask 106 is then removed, for example, by using an appropriate wet stripping and / or ashing process.

[0044] By using Figure 6 to Fig. 9 According to the process described in the drawings, one or more p-type work function adjustment layers can be formed in each of the regions 200, 300, 400 and 500 to a desired cumulative thickness (e.g., the thickness of the first work function adjustment layer 100 and / or the second work function adjustment layer 104 in each opening), and transistors with different threshold voltages can be formed in each of the regions 200, 300, 400 and 500.

[0045] like Fig. 9As further shown, a mask 108 is then deposited over the second conductive layer 98, the first work function adjusting layer 100, and the second work function adjusting layer 104, and the mask 108 is patterned. The mask 108 covers the second conductive layer 98 in the first region 200 and the second region 300, while exposing the first work function adjusting layer 100 in the third region 400 and exposing the second work function adjusting layer 104 in the fourth region 500. In some embodiments, the mask 108 is a photoresist, which can be formed by a spin coating technique and can be patterned using an acceptable photolithography technique.

[0046] Once the mask 108 is patterned, a doping process 110 is performed to dope the exposed portion of the first work function adjustment layer 100 (e.g., the portion of the first work function adjustment layer 100 in the third region 400) and the exposed portion of the second work function adjustment layer 104 (e.g., the portion of the second work function adjustment layer 104 in the fourth region 500). The doping process 110 may include doping the exposed portions of the first work function adjustment layer 100 and the second work function adjustment layer 104 with silicon. In an embodiment, the doping process 110 is an ALD process using SiH4 or the like as a doping gas. The silicon concentration of the doping gas used in the doping process 110 may be in a range of about 5% to about 25%. In some embodiments, the doping process 110 may be performed under the following conditions: at a temperature in a range of about 250° C. to about 475° C.; for about 1 second to about 10 minutes; at a pressure of about 0.5 Torr to about 50 Torr; and using a carrier gas such as Ar or the like. In other embodiments, the doping process 110 may be performed using one or more different process conditions as described above.

[0047] As a result of the doping process 110, the first work function adjustment layer 100 in the third region 400 and the second work function adjustment layer 104 in the fourth region 500 may both include silicon. For example, the first work function adjustment layer 100 in the third region 400 and the second work function adjustment layer 104 in the fourth region 500 may include titanium silicon nitride or the like. The silicon concentration in the first work function adjustment layer 100 in the third region 400 may be in the range of about 0.5% to about 10%, and the silicon concentration in the second work function adjustment layer 104 in the fourth region 500 may be in the range of about 0.5% to about 10%. It has been observed that by doping the first work function adjustment layer 100 and the second work function adjustment layer 104 to have silicon in the above range, a desired etching selectivity may be achieved. In addition, during the doping process 110, a portion of the first work function adjustment layer 100 in the fourth region 500 may be masked by the second work function adjustment layer 104, and the first work function adjustment layer 100 in the fourth region 500 may be substantially undoped and free of silicon. Alternatively, silicon may diffuse from the second work function adjusting layer 104 into the underlying first work function adjusting layer 100 in the fourth region 500, and thus, the first work function adjusting layer 100 in the fourth region 500 may also include silicon. In such an embodiment, the first work function adjusting layer 100 in the fourth region 500 may have a lower silicon concentration than the first work function adjusting layer 100 in the third region 400. Diffusion of silicon into the first work function adjusting layer 100 in the fourth region 500 may be enhanced by one or more annealing processes performed after the doping process 110. In such an embodiment, the second conductive layer 98 may act as a diffusion barrier that prevents silicon from substantially diffusing into underlying layers.

[0048] In another embodiment, a different doping process may be used to replace the doping process 110. For example, Fig.10An alternative embodiment of performing a doping process 111 (instead of the doping process 110) on the first work function adjustment layer 100 and the second work function adjustment layer 104 is shown. The doping process 111 may include doping the exposed portion of the first work function adjustment layer 100 (e.g., the portion of the first work function adjustment layer 100 in the third region 400) and the exposed portion of the second work function adjustment layer 104 (e.g., the portion of the second work function adjustment layer 104 in the fourth region 500) with aluminum. In an embodiment, the doping process 111 is an ALD process using AlCl3, trimethylaluminum (TMA), etc. as a doping gas. The aluminum concentration of the doping gas used in the doping process 111 may be in the range of about 5% to about 25%. In some embodiments, the doping process 111 may be performed under the following conditions: at a temperature in the range of about 250°C to about 475°C; for about 1 second to about 10 minutes; at a pressure of about 0.5 Torr to about 50 Torr; and using a carrier gas such as Ar, etc. In other embodiments, the doping process 111 may be performed using one or more different process conditions as described above.

[0049] As a result of the doping process 111, the first work function adjustment layer 100 in the third region 400 and the second work function adjustment layer 104 in the fourth region 500 may both include aluminum. For example, the first work function adjustment layer 100 in the third region 400 and the second work function adjustment layer 104 in the fourth region 500 may include titanium aluminum nitride or the like. The aluminum concentration in the first work function adjustment layer 100 in the third region 400 may be in the range of about 2.5% to about 40%, and the aluminum concentration in the second work function adjustment layer 104 in the fourth region 500 may be in the range of about 2.5% to about 40%. It has been observed that by doping the first work function adjustment layer 100 and the second work function adjustment layer 104 with aluminum in the above range, a desired etching selectivity may be achieved. In addition, during the doping process 111, a portion of the first work function adjustment layer 100 in the fourth region 500 may be masked by the second work function adjustment layer 104, and the first work function adjustment layer 100 in the fourth region 500 may be substantially undoped and free of aluminum. Alternatively, aluminum may diffuse from the second work function adjusting layer 104 into the underlying first work function adjusting layer 100 in the fourth region 500, and thus, the first work function adjusting layer 100 in the fourth region 500 may also include aluminum. In such an embodiment, the first work function adjusting layer 100 in the fourth region 500 may have a lower aluminum concentration than the first work function adjusting layer 100 in the third region 400. Diffusion of aluminum may be enhanced by one or more annealing processes performed after the doping process 111. In such an embodiment, the second conductive layer 98 may act as a diffusion barrier layer that prevents aluminum from substantially diffusing into underlying layers.

[0050] If the mask 108 is a photoresist, the mask 108 may be removed after the doping process 110 or 111 by using an appropriate wet stripping and / or ashing process. In some embodiments, as a result of the doping process 110 or 111, removal of the mask 108, and / or exposure to an oxygen-containing environment such as a natural environment, terminating species such as hydroxides and / or oxygen may terminate the surfaces of the second conductive layer 98, the first work function adjustment layer 100, and the second work function adjustment layer 104. When these species are hydroxides and / or oxygen, they may form oxides, such as native oxides, on these layers 98, 100, and 104. As a result, the exposed portions of the first work function adjustment layer 100 and the second work function adjustment layer 104 may be oxidized and include titanium silicon oxynitride, etc. Specifically, the oxidation may cause silicon-oxygen bonds (e.g., SiO2) to be formed in the first work function adjustment layer 100 in the third region 400 and the second work function adjustment layer 104 in the fourth region 500. x O y ) or aluminum-oxygen bond (Al x O y ). By including Si in the gate electrode x O y , which can improve the flat-band voltage (V FB ). In addition, as will be described in more detail below, by doping portions of the first work function adjustment layer 100 and the second work function adjustment layer 104 with silicon, aluminum, and / or oxygen, the etch selectivity between the second conductive layer 98 (e.g., comprising tantalum nitride) and the first and second work function adjustment layers 100 and 104 (e.g., comprising titanium, silicon, and nitrogen) can be increased, thereby improving process control and allowing different transistors with larger threshold voltage differences to be formed in different regions of the device.

[0051] Next, in Fig.11 In the embodiment of the present invention, a chlorine-based treatment 112 is performed on the top surfaces of the second conductive layer 98, the first work function adjustment layer 100, and the second work function adjustment layer 104. In some embodiments, the chlorine-based treatment 112 includes exposing the top surfaces of the second conductive layer 98, the first work function adjustment layer 100, and the second work function adjustment layer 104 to a chlorine-based fluid. The chlorine-based fluid may further be a metal-chlorine fluid, such as TiCl x 、TaCl x 、WCl xEtc. or a combination thereof. In some embodiments, the chlorine-based fluid (more specifically, a metal-chlorine fluid) is a gas. Chlorine-based gas or metal-chlorine gas can be used in the process without using plasma. In some embodiments, the top surfaces of the second conductive layer 98, the first work function adjustment layer 100, and the second work function adjustment layer 104 are exposed to a hot dip of a chlorine-based gas (e.g., WCL5), for example, at a temperature in the range of about 200° C. to about 600° C., with a flow rate of the chlorine-based gas in the range of about 100 sccm to about 10,000 sccm, and a duration in the range of about 10 seconds to about 300 seconds (e.g., about 30 seconds to about 120 seconds).

[0052] The chlorine-based treatment 112 may remove or strip the termination material from the top surfaces of the second conductive layer 98, the first work function adjustment layer 100, and the second work function adjustment layer 104, and the chlorine-based material such as chlorine (Cl) may re-terminate the top surfaces of the second conductive layer 98, the first work function adjustment layer 100, and the second work function adjustment layer 104. The chlorine-based treatment 112 may also etch the top surfaces of the exposed layers (e.g., the second conductive layer 98, the first work function adjustment layer 100, and the second work function adjustment layer 104). For example, the thickness of the second conductive layer 98 in the first region 200 and the second region 300 may be less than the thickness of the second conductive layer 98 in the third region 400 and the fourth region 500. In addition, the thickness of the first work function adjustment layer 100 in the third region 400 may be less than the thickness of the first work function adjustment layer 100 in the fourth region 500. By adjusting the thickness of the second conductive layer 98, the first work function adjusting layer 100, and the second work function adjusting layer 104, the threshold voltage of the transistor formed in each of the first region 200, the second region 300, the third region 400, and the fourth region 500 may be adjusted. For example, a smaller cumulative thickness of the conductive layer 98, the first work function adjusting layer 100, and / or the second work function adjusting layer 104 may correspond to a lower threshold voltage.

[0053] However, in some embodiments, due to the presence of oxygen-bound dopants (e.g., silicon or aluminum) in the treated first work function adjusting layer 100 and the second work function adjusting layer 104, the chlorine-based treatment 112 will not significantly etch the treated first work function adjusting layer 100 and the second work function adjusting layer 104. For example, due to the presence of Si x O y or Al x O y, the chlorine-based treatment 112 may not significantly etch the treated first work function adjusting layer 100 and the second work function adjusting layer 104. Therefore, the chlorine-based treatment 112 will etch the second conductive layer 98 more significantly and at a greater rate than the first work function adjusting layer 100 or the second work function adjusting layer 104. For example, the etched thickness of the first work function adjusting layer 100 and the second work function adjusting layer 104 (e.g., the respective thickness of the first work function adjusting layer 100 and the second work function adjusting layer 104 etched away by the chlorine-based treatment 112) is less than the etched thickness of the second conductive layer 98 (e.g., the thickness of the second conductive layer 98 etched away by the chlorine-based treatment 112). In some embodiments, the etched thickness of the first work function adjusting layer 100 and the second work function adjusting layer 104 may be about or less. In some embodiments, the etching thickness of the first work function adjustment layer 100 and the second work function adjustment layer 104 may be less than half of the etching thickness of a similar work function adjustment layer that is not doped according to the above-described doping process 110 / 111. Therefore, the doping processes 110 and 111 may increase the etching selectivity of the second conductive layer 98 compared to the treated first work function adjustment layer 100 and the second work function adjustment layer 104. For example, the ratio of the etching thickness of the second conductive layer 98 to the etching thickness of the first work function adjustment layer 100 and the second work function adjustment layer 104 may be increased. By increasing the etching selectivity of these layers, the increased threshold voltage spacing of different transistors in different regions 200, 300, 400, and 500 may be increased. Specifically, a lower threshold voltage may be achieved for transistors in the first region 200 and the second region 300, while a higher threshold voltage may be maintained for transistors in the third region 400 and the fourth region 500. Various embodiments allow for greater threshold voltage spacing flexibility during the replacement metal gate process.

[0054] exist Fig.12 In the embodiment of the present invention, after the chlorine-based treatment 112, a third work function adjustment layer 114 is conformally formed on the second conductive layer 98 in the first region 200 and the second region 300, on the first work function adjustment layer 100 in the third region 400, and on the second work function adjustment layer 104 in the fourth region 500. The third work function adjustment layer 114 can be any acceptable material to adjust the work function of the device to a desired amount for the application of the device to be formed, and can be deposited using any acceptable deposition process. In some embodiments, the third work function adjustment layer 114 is an n-type work function metal, and can include aluminum (Al), aluminum nitride (AlN), titanium aluminum (TiAl), tantalum aluminum (TaAl), etc., deposited by ALD, CVD, PVD, etc. The thickness of the third work function adjustment layer 114 can be in the range of about 1.5 nm to about 4 nm.

[0055] exist Fig.13 In the embodiment of the present invention, an adhesion layer or glue layer 116 is conformally formed on the third work function adjustment layer 114 in the first region 200, the second region 300, the third region 400, and the fourth region 500. The glue layer 116 may include titanium nitride (TiN) or the like deposited by ALD or the like. The thickness of the glue layer 116 may be in the range of about 2 nm to about 4 nm.

[0056] Also in Fig.13 , a conductive material 118 is deposited on the glue layer 116. The conductive material 118 may include a metal, such as tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), combinations thereof, etc. The conductive material 118 may be deposited using CVD, PVD, etc., or combinations thereof. The conductive material 118 fills at least the remaining portion of the opening, for example, the portion not filled by the first conductive layer 96, the second conductive layer 98, the first work function adjustment layer 100, the second work function adjustment layer 104, the third work function adjustment layer 114, and the glue layer 116.

[0057] Next, if Fig.14 As shown, a planarization process such as CMP may be performed to remove excess portions of the first conductive layer 96, the second conductive layer 98, the first work function adjustment layer 100, the second work function adjustment layer 104, the third work function adjustment layer 114, the glue layer 116, and the conductive material 118 (these excess portions are above the top surface of the ILD 90) to form gate dielectric materials 94A, 94B, 94C, and 94D (e.g., the remaining portions from the gate dielectric layer 94, see FIG. 1 ) in the first region 200, the second region 300, the third region 400, and the fourth region 500, respectively. Fig.13 ) and the gate electrodes 120A, 120B, 120C and 120D (including the first conductive layer 96, the second conductive layer 98, the first work function adjustment layer 100 in the third region 400 and the fourth region 500, the second work function adjustment layer 104 in the fourth region 500, the third work function adjustment layer 114, the glue layer 116 and the remaining portion of the conductive material 118, see Fig.13). Specifically, the first gate electrode 120A in the first region 200 includes a conductive material 96A, a conductive material 98A, a work function adjustment metal 114A, a glue material 116A, and a filling metal 118A. The second gate electrode 120B in the second region 300 includes a conductive material 96B, a conductive material 98B, a work function adjustment metal 114B, a glue material 116B, and a filling metal 118B. The third gate electrode 120C in the third region 400 includes a conductive material 96C, a conductive material 98C, a work function adjustment metal 100A, a work function adjustment metal 114C, a glue material 116C, and a filling metal 118C. The fourth gate electrode 120D in the fourth region 500 includes a conductive material 96D, a conductive material 98D, a work function adjustment metal 100B, a work function adjustment metal 104A, a work function adjustment metal 114D, a glue material 116D, and a filling metal 118D. Conductive materials 96A, 96B, 96C and 96D can be formed from the remaining portion of the first conductive layer 96; conductive materials 98A, 98B, 98C and 98D can be formed from the remaining portion of the second conductive layer 98; work function metals 100A and 100B can be formed from the remaining portion of the first work function adjustment layer 100; work function metal 104A can be formed from the remaining portion of the second work function adjustment layer 104; work function metals 114A, 114B, 114C and 114D can be formed from the remaining portion of the third work function adjustment layer 114; glue materials 116A, 116B, 116C and 116D can be formed from the remaining portion of the glue layer 116; and filling metals 118A, 118B, 118C and 118D can be formed from the remaining portion of the filling metal 118. As a result of the aforementioned processing steps, the conductive materials 98A and 98B can be thinner than the conductive materials 98C and 98D, and the work function adjustment metal 100B is thinner than the work function adjustment metal 100A. Therefore, the threshold voltage of the transistor including the first electrode 120A and the second electrode 120B can be less than the threshold voltage of the transistor including the third electrode 120C, and the threshold voltage of the transistor including the third electrode 120C can be less than the threshold voltage of the transistor including the fourth electrode 120D. For ease of reference, the gate electrodes 120A, 120B, 120C, and 120D are referred to as gate electrodes 120 below.

[0058] exist Fig.15A , Fig. 15B and Fig. 15CIn the embodiment of the present invention, a gate mask 128 is formed over the gate stack (including the gate dielectric layer 94 and the corresponding gate electrode 120), and the gate mask 128 may be disposed between opposite portions of the gate spacers 82. In some embodiments, forming the gate mask 128 includes recessing the gate stack so that a groove is formed directly above the gate stack and between opposite portions of the gate spacers 82. The gate mask 128 including one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled in the groove, and then a planarization process is performed to remove excess portions of the dielectric material extending over the first ILD 90.

[0059] Likewise Fig.15A , Fig. 15B and Fig. 15C As shown, the second ILD 124 is deposited on the ILD 90. In some embodiments, the second ILD 124 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 124 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD and PECVD.

[0060] According to some embodiments, a gate contact 132 and a source / drain contact 130 are formed through the second ILD 124 and the ILD 90. An opening for the source / drain contact 130 is formed through the ILD 90 and 124, and an opening for the gate contact 132 is formed through the ILD 124 and the gate mask 128. The opening can be formed using acceptable photolithography and etching techniques. A liner (not shown) such as a diffusion barrier layer, an adhesion layer, etc. and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the ILD 124. The remaining liner and conductive material form a source / drain contact 130 and a gate contact 132 in the opening. An annealing process may be performed to form a silicide 136 at the interface between the epitaxial source / drain regions 84 / 86 and the source / drain contact 130. The source / drain contact 130 is physically and electrically coupled to the epitaxial source / drain regions 84 / 86, and the gate contact 132 is physically and electrically coupled to the gate electrode 120. The source / drain contact 130 and the gate contact 132 may be formed using different processes, or may be formed using the same process. Although shown as being formed in the same cross-section, it should be understood that each of the source / drain contact 130 and the gate contact 132 may be formed in different cross-sections, which may avoid shorting of the contacts.

[0061] Although not explicitly shown, it will be readily understood by those skilled in the art that Fig.13 Further processing steps may be performed on the structures in the ILD 124. For example, various intermetal dielectrics (IMDs) and their corresponding metallizations may be formed over the ILD 124.

[0062] Various embodiments provide a gate electrode having a doped work function adjustment layer (e.g., a titanium nitride layer). The work function adjustment layer may be doped with, for example, silicon, aluminum, etc., and the work function adjustment layer may further include oxygen (e.g., Si) bonded to the dopant. x O y 、Al x O y By adjusting the composition of the work function adjustment layer, the etch selectivity between the work function adjustment layer and the underlying layer (e.g., a tantalum nitride layer) can be increased during a chlorine-based process that reduces the thickness of the underlying layer for threshold voltage adjustment. In this way, a greater difference between the threshold voltages of different transistors in a device can be achieved.

[0063] In some embodiments, a method includes: depositing a first conductive layer over a gate dielectric layer; depositing a first work function adjustment layer over the first conductive layer; selectively removing the first work function adjustment layer from over a first region of the first conductive layer; doping the first work function adjustment layer with a dopant; after doping the first work function adjustment layer, performing a first treatment process to etch the first region of the first conductive layer and the second region of the first work function adjustment layer. The first treatment process etches the first conductive layer at a greater rate than etching the first work function adjustment layer. Optionally, in some embodiments, the dopant is silicon or aluminum. Optionally, in some embodiments, doping the first work function adjustment layer with the dopant includes an atomic layer deposition process. Optionally, in some embodiments, the atomic layer deposition process includes using SiH4 as a doping gas. Optionally, in some embodiments, the atomic layer deposition process includes using AlCl3 or trimethylaluminum (TMA) as a doping gas. Optionally, in some embodiments, the method further comprises: depositing a second work function adjusting layer over the first work function adjusting layer; selectively removing the second work function adjusting layer from over the second region of the first work function adjusting layer; doping the second work function adjusting layer with a dopant while doping the first work function adjusting layer with a dopant; performing a first treatment process to etch a third region of the second work function adjusting layer, wherein the first treatment process etches the first conductive layer at a greater rate than etching the second work function adjusting layer. Optionally, in some embodiments, the first conductive layer comprises tantalum nitride and the first work function adjusting layer comprises titanium nitride. Optionally, in some embodiments, the method further comprises: diffusing oxygen into the first work function adjusting layer, wherein the oxygen is combined with the dopant. Optionally, in some embodiments, the first treatment process is a chlorine-based etching process. Optionally, in some embodiments, the chlorine-based etching process comprises a chlorine-based hot dip. Optionally, in some embodiments, the chlorine-based hot dip comprises using WCl5 as a process gas. Optionally, in some embodiments, the method further comprises: after the first treatment process, depositing a third work function adjusting layer on the first work function adjusting layer, wherein the first work function adjusting layer is a p-type layer, and the third work function adjusting layer is an n-type layer.

[0064] In some embodiments, a transistor includes: a first source / drain region; a second source / drain region; and a gate, between the first source / drain region and the second source / drain region, the gate including: a gate dielectric; and a gate electrode, on the gate dielectric, the gate electrode including: a first conductive material; a first p-type work function adjustment metal, on the first conductive material, the first p-type work function adjustment metal including silicon or aluminum; an n-type work function adjustment metal, on the first p-type work function adjustment metal; and a fill metal, on the n-type work function adjustment metal. Optionally, in some embodiments, the first p-type work function adjustment metal includes Si x Oy or Al x O y . Optionally, in some embodiments, the gate electrode further comprises: a second p-type work function adjustment metal below the first p-type work function adjustment metal, wherein the second p-type work function adjustment metal comprises a lower concentration of silicon or aluminum than the first p-type work function adjustment metal. Optionally, in some embodiments, the first conductive material comprises tantalum nitride, and wherein the first p-type work function adjustment metal comprises titanium nitride.

[0065] In some embodiments, a device includes: a first gate electrode, the first gate electrode including: a first conductive material, above a first gate dielectric; a first n-type work function adjustment metal, in contact with the first conductive material; and a first filling material, above the first n-type work function adjustment metal; and a second gate electrode, the second gate electrode including: a second conductive material, above the second gate dielectric, the first conductive material being thinner than the second conductive material; a first p-type work function adjustment metal, in contact with the second conductive material, the first p-type work function adjustment metal including silicon or aluminum; a second n-type work function adjustment metal, in contact with the first p-type work function adjustment metal; and a second filling material, above the second n-type work function adjustment metal. Optionally, in some embodiments, the device further comprises: a third gate electrode, the third gate electrode comprising: a third conductive material, on top of the third gate dielectric, the third conductive material having the same material composition as the first conductive material, the first conductive material being thinner than the third conductive material; a second p-type work function adjustment metal, in contact with the third conductive material, the first p-type work function adjustment metal being thinner than the second p-type work function adjustment metal; a third p-type work function adjustment metal, in contact with the second p-type work function adjustment metal, the third p-type work function adjustment metal comprising silicon or aluminum; a third n-type work function adjustment metal, in contact with the third p-type work function adjustment metal; and a third fill material, on top of the third n-type work function adjustment metal. Optionally, in some embodiments, the first p-type work function adjustment metal further comprises oxygen. Optionally, in some embodiments, both the first conductive material and the second conductive material comprise tantalum nitride, wherein the first p-type work function adjustment metal comprises titanium nitride.

[0066] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0067] Example 1. A method for forming a gate electrode, the method comprising: depositing a first conductive layer on a gate dielectric layer; depositing a first work function adjustment layer on the first conductive layer; selectively removing the first work function adjustment layer from a first region of the first conductive layer; doping the first work function adjustment layer with a dopant; and after doping the first work function adjustment layer, performing a first treatment process to etch the first region of the first conductive layer and a second region of the first work function adjustment layer, wherein the first treatment process etches the first conductive layer at a greater rate than etching the first work function adjustment layer.

[0068] Example 2. The method of Example 1, wherein the dopant is silicon or aluminum.

[0069] Example 3. The method of Example 1, wherein doping the first work function adjustment layer with the dopant comprises an atomic layer deposition process.

[0070] Example 4. The method of Example 3, wherein the atomic layer deposition process includes using SiH4 as a doping gas.

[0071] Example 5. A method according to Example 3, wherein the atomic layer deposition process includes using AlCl3 or trimethylaluminum as a doping gas.

[0072] Example 6. The method according to Example 1 also includes: depositing a second work function adjustment layer on top of the first work function adjustment layer; selectively removing the second work function adjustment layer from the second region of the first work function adjustment layer; doping the second work function adjustment layer with the dopant while doping the first work function adjustment layer with the dopant; and performing the first treatment process to etch a third region of the second work function adjustment layer, wherein the first treatment process etches the first conductive layer at a greater rate than etching the second work function adjustment layer.

[0073] Example 7. The method of Example 1, wherein the first conductive layer comprises tantalum nitride and the first work function adjustment layer comprises titanium nitride.

[0074] Example 8. The method of Example 1, further comprising: diffusing oxygen into the first work function adjustment layer, wherein the oxygen combines with the dopant.

[0075] Example 9. The method of Example 1, wherein the first treatment process is a chlorine-based etching process.

[0076] Example 10. The method of Example 9, wherein the chlorine-based etching process comprises a chlorine-based hot dip.

[0077] Example 11. The method of Example 10, wherein the chlorine-based hot soak includes using WCl5 as a process gas.

[0078] Example 12. The method according to Example 1 further includes: after the first processing process, depositing a third work function adjustment layer on the first work function adjustment layer, wherein the first work function adjustment layer is a p-type layer and the third work function adjustment layer is an n-type layer.

[0079] Example 13. A transistor comprising: a first source / drain region; a second source / drain region; and a gate, between the first source / drain region and the second source / drain region, the gate comprising: a gate dielectric; and a gate electrode, above the gate dielectric, the gate electrode comprising: a first conductive material; a first p-type work function adjustment metal, above the first conductive material, the first p-type work function adjustment metal comprising silicon or aluminum; an n-type work function adjustment metal, above the first p-type work function adjustment metal; and a filling metal, above the n-type work function adjustment metal.

[0080] Example 14. The transistor of Example 13, wherein the first p-type work function adjustment metal comprises Si x O y or Al x O y .

[0081] Example 15. A transistor according to Example 13, wherein the gate electrode further includes: a second p-type work function adjustment metal, below the first p-type work function adjustment metal, wherein the second p-type work function adjustment metal includes a lower concentration of silicon or aluminum than the first p-type work function adjustment metal.

[0082] Example 16. The transistor of Example 13, wherein the first conductive material comprises tantalum nitride, and wherein the first p-type work function adjusting metal comprises titanium nitride.

[0083] Example 17. A semiconductor device comprising: a first gate electrode, the first gate electrode comprising: a first conductive material, above a first gate dielectric; a first n-type work function adjustment metal, in contact with the first conductive material; and a first filling material, above the first n-type work function adjustment metal; and a second gate electrode, the second gate electrode comprising: a second conductive material, above a second gate dielectric, the first conductive material being thinner than the second conductive material; a first p-type work function adjustment metal, in contact with the second conductive material, the first p-type work function adjustment metal comprising silicon or aluminum; a second n-type work function adjustment metal, in contact with the first p-type work function adjustment metal; and a second filling material, above the second n-type work function adjustment metal.

[0084] Example 18. The semiconductor device according to Example 17 further includes a third gate electrode, the third gate electrode including: a third conductive material, above the third gate dielectric, the third conductive material having the same material composition as the first conductive material, the first conductive material being thinner than the third conductive material; a second p-type work function adjustment metal, in contact with the third conductive material, the first p-type work function adjustment metal being thinner than the second p-type work function adjustment metal; a third p-type work function adjustment metal, in contact with the second p-type work function adjustment metal, the third p-type work function adjustment metal including silicon or aluminum; a third n-type work function adjustment metal, in contact with the third p-type work function adjustment metal; and a third filling material, above the third n-type work function adjustment metal.

[0085] Example 19. The semiconductor device of Example 17, wherein the first p-type work function adjusting metal further comprises oxygen.

[0086] Example 20. The semiconductor device of Example 17, wherein the first conductive material and the second conductive material both comprise tantalum nitride, and wherein the first p-type work function adjusting metal comprises titanium nitride.

Claims

1. A method for forming a gate electrode, the method comprising: depositing a first conductive layer over the gate dielectric layer; depositing a first work function adjustment layer on the first conductive layer; selectively removing the first work function adjusting layer from above the first region of the first conductive layer; doping the first work function adjustment layer with a dopant; as well as After doping the first work function adjusting layer, a first treatment process is performed to etch the first region of the first conductive layer and a second region of the first work function adjusting layer, wherein the first treatment process etches the first conductive layer at a greater rate than etching the first work function adjusting layer.

2. The method according to claim 1, wherein: The dopant is silicon or aluminum.

3. The method according to claim 1, wherein: Doping the first work function adjusting layer with the dopant includes an atomic layer deposition process.

4. The method according to claim 3, wherein: The atomic layer deposition process includes using SiH4 as a doping gas.

5. The method according to claim 3, wherein: The atomic layer deposition process includes using AlCl3 or trimethylaluminum as a doping gas.

6. The method according to claim 1, further comprising: depositing a second work function adjusting layer on the first work function adjusting layer; selectively removing the second work function adjusting layer from above the second region of the first work function adjusting layer; doping the second work function adjusting layer with the dopant while doping the first work function adjusting layer with the dopant; as well as The first treatment process is performed to etch a third region of the second work function adjusting layer, wherein the first treatment process etches the first conductive layer at a greater rate than etching the second work function adjusting layer.

7. The method according to claim 1, wherein: The first conductive layer includes tantalum nitride, and the first work function adjusting layer includes titanium nitride.

8. The method according to claim 1, further comprising: Oxygen is diffused into the first work function adjusting layer, wherein the oxygen is combined with the dopant.

9. The method according to claim 1, wherein: The first treatment process is a chlorine based etching process.

10. The method according to claim 9, wherein: The chlorine-based etch process includes a chlorine-based hot dip.

11. The method according to claim 10, wherein: The chlorine-based hot soak involves using WCl5 as the process gas.

12. The method according to claim 1, further comprising: After the first treatment process, a third work function adjusting layer is deposited on the first work function adjusting layer, wherein the first work function adjusting layer is a p-type layer, and the third work function adjusting layer is an n-type layer.

13. A transistor comprising: a first source / drain region; a second source / drain region; as well as A gate, between the first source / drain region and the second source / drain region, the gate comprising: a gate dielectric; and A gate electrode, on the gate dielectric, the gate electrode comprising: a first conductive material; a first p-type work function adjustment metal, on the first conductive material, the first p-type work function adjustment metal comprising silicon or aluminum; a second p-type work function adjusting metal beneath the first p-type work function adjusting metal, wherein the second p-type work function adjusting metal comprises a lower concentration of silicon or aluminum than the first p-type work function adjusting metal; an n-type work function adjustment metal on the first p-type work function adjustment metal; and A filler metal is provided on top of the n-type work function adjusting metal.

14. The transistor according to claim 13, wherein: The first p-type work function adjustment metal comprises Si x O y or Al x O y .

15. The transistor according to claim 13, wherein: The first conductive material includes tantalum nitride, and wherein the first p-type work function adjusting metal includes titanium nitride.

16. A semiconductor device comprising: A first gate electrode, wherein the first gate electrode comprises: a first conductive material overlying the first gate dielectric; A first n-type work function adjustment metal in contact with the first conductive material; and a first filling material, on the first n-type work function adjusting metal; and A second gate electrode, the second gate electrode comprising: a second conductive material on the second gate dielectric, the first conductive material being thinner than the second conductive material; a first p-type work function adjustment metal, in contact with the second conductive material, wherein the first p-type work function adjustment metal comprises silicon or aluminum; a second n-type work function adjusting metal, in contact with the first p-type work function adjusting metal; and a second filling material, on the second n-type work function adjusting metal; A third gate electrode, the third gate electrode comprising: a third conductive material on the third gate dielectric, the third conductive material having the same material composition as the first conductive material, the first conductive material being thinner than the third conductive material; a second p-type work function adjustment metal, contacting the third conductive material, the first p-type work function adjustment metal being thinner than the second p-type work function adjustment metal; a third p-type work function adjusting metal in contact with the second p-type work function adjusting metal, the third p-type work function adjusting metal comprising silicon or aluminum, and the third p-type work function adjusting metal comprising a higher concentration of silicon or aluminum than the second p-type work function adjusting metal; a third n-type work function adjusting metal in contact with the third p-type work function adjusting metal; and A third filling material is on the third n-type work function adjusting metal.

17. The semiconductor device according to claim 16, wherein: The first p-type work function adjusting metal further includes oxygen.

18. The semiconductor device according to claim 16, wherein: The first conductive material and the second conductive material both include tantalum nitride, and wherein the first p-type work function adjusting metal includes titanium nitride.

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