Semiconductor device including parallel conductive layers

Abstract

A semiconductor device includes a semiconductor chip, and the semiconductor chip includes a first chip contact pad on a first chip main surface. The semiconductor device further includes a first conductive layer, which is disposed above the first chip main surface and electrically coupled to the first chip contact pad, wherein the first conductive layer extends in a direction parallel to the first chip main surface. The semiconductor device further includes a second conductive layer, which is disposed above the first conductive layer and electrically coupled to the first conductive layer, wherein the second conductive layer extends in a direction parallel to the first conductive layer. The semiconductor device further includes an electrical through-connection structure, which is electrically coupled to the first conductive layer and the second conductive layer, wherein the electrical through-connection structure extends in a direction perpendicular to the first chip main surface, and in a top view of the first chip main surface, the electrical through-connection structure and the semiconductor chip do not overlap.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor technology. More particularly, the present disclosure relates to semiconductor devices including parallel conductive layers. Additionally, the present disclosure relates to methods for manufacturing such semiconductor devices. Background Art

[0002] Semiconductor chips may be disposed in protective packages to allow for easy handling and assembly on a circuit board and to protect the semiconductor chips from damage. In a standard semiconductor package, the semiconductor chip is typically disposed on a lead frame and encapsulated by a molding compound. Manufacturers of semiconductor devices have been working to improve their products and their manufacturing methods. Compared to standard semiconductor devices, it may be desirable to develop semiconductor devices with improved electrical and thermal performance. Additionally, it may be desirable to provide a cost-effective method for manufacturing such semiconductor devices. Summary of the Invention

[0003] One aspect of the present disclosure relates to a semiconductor device. The semiconductor device includes a semiconductor chip including a first chip contact pad on a first chip major surface. The semiconductor device further includes a first conductive layer disposed over the first chip major surface and electrically coupled to the first chip contact pad, wherein the first conductive layer extends in a direction parallel to the first chip major surface. The semiconductor device further includes a second conductive layer disposed over the first conductive layer and electrically coupled to the first conductive layer, wherein the second conductive layer extends in a direction parallel to the first conductive layer. The semiconductor device further includes an electrical through-connection structure electrically coupled to the first conductive layer and the second conductive layer, wherein the electrical through-connection structure extends in a direction perpendicular to the first chip major surface and, in a top view of the first chip major surface, the electrical through-connection structure and the semiconductor chip do not overlap.

[0004] One aspect of the present disclosure relates to a method for manufacturing a semiconductor device. The method includes providing a semiconductor chip including a first chip contact pad on a first chip major surface. The method further includes forming a first conductive layer disposed over the first chip major surface and electrically coupled to the first chip contact pad, wherein the first conductive layer extends in a direction parallel to the first chip major surface. The method further includes forming a second conductive layer disposed over the first conductive layer and electrically coupled to the first conductive layer, wherein the second conductive layer extends in a direction parallel to the first conductive layer. The method further includes forming an electrical through-connection structure electrically coupled to the first conductive layer and the second conductive layer, wherein the electrical through-connection structure extends in a direction perpendicular to the first chip major surface and, in a top view of the first chip major surface, the electrical through-connection structure and the semiconductor chip do not overlap. Brief Description of the Drawings

[0005] The accompanying drawings included are used to provide a further understanding of various aspects. The drawings illustrate various aspects and, together with the detailed description, are used to explain the principles of the aspects. By referring to the following detailed description, other aspects and many of the intended advantages of the various aspects can be better understood. The elements of the drawings are not necessarily to scale relative to each other. The same reference numerals may indicate corresponding similar parts.

[0006] Figure 1 A side cross-sectional view of a semiconductor device 100 according to the present disclosure is schematically shown.

[0007] Figure 2 A side cross-sectional view of a semiconductor device 200 according to the present disclosure is schematically shown.

[0008] Figure 3 A feature of the semiconductor device 200 according to the present disclosure is schematically shown.

[0009] Figure 4 A feature of the semiconductor device 200 according to the present disclosure is schematically shown.

[0010] Figure 5 A feature of the semiconductor device 200 according to the present disclosure is schematically shown.

[0011] Figure 6 A feature of the semiconductor device 200 according to the present disclosure is schematically shown.

[0012] Figure 7 A side cross-sectional view of a semiconductor device 700 according to the present disclosure is schematically shown.

[0013] Figure 8 A bottom cross-sectional view of a semiconductor device 800 according to the present disclosure is schematically shown.

[0014] Figure 9 A bottom view of a semiconductor device 900 according to the present disclosure is schematically shown.

[0015] Figure 10 A top view of an assembly 1000 including a plurality of semiconductor devices according to the present disclosure is schematically shown.

[0016] Figure 11 A flowchart of a method for manufacturing a semiconductor device according to the present disclosure is shown. Detailed Description

[0017] In the following detailed description, reference is made to the accompanying drawings, which show, by way of illustration, specific aspects in which the present disclosure may be practiced. In this regard, directional terms such as "top", "bottom", "front", "rear", etc. may be used with reference to the orientation of the described drawings. Since the components of the described device may be positioned in many different orientations, the directional terms are for illustrative purposes only and are in no way limiting. Without departing from the concepts of the present disclosure, other aspects may be utilized and structural or logical changes may be made. Accordingly, the following detailed description should not be considered limiting.

[0018] Figure 1 A side cross-sectional view of a semiconductor device 100 according to the present disclosure is schematically shown. For the purpose of qualitatively illustrating aspects of the present disclosure, the semiconductor device 100 is shown in a schematic manner. It should be understood that the semiconductor device 100 may include other aspects not shown for simplicity. For example, the semiconductor device 100 may be extended by incorporating any aspect described in connection with other semiconductor devices and methods according to the present disclosure.

[0019] The semiconductor device 100 may include a semiconductor chip 2 having a first chip main surface 4 and a second chip main surface 6 disposed opposite to the first chip main surface 4. Chip contact pads 8 may be disposed on or at the first chip main surface 4. The semiconductor device 100 may further include a first conductive layer 10 disposed over the first chip main surface 4 and electrically coupled to the chip contact pads 8. The first conductive layer 10 may extend in a direction parallel to the first chip main surface 4, i.e., in the x direction. In Figure 1 the example, the electrical coupling between the chip contact pads 8 and the first conductive layer 10 is exemplarily shown by a single vertical connection element. In other examples, such electrical coupling may be provided differently.

[0020] The semiconductor device may further include a second conductive layer 12 disposed over the first conductive layer 10 and electrically coupled to the first conductive layer 10. The second conductive layer 12 may extend in a direction parallel to the first conductive layer 10, i.e., in the x direction. In Figure 1 the example, the electrical coupling between the first conductive layer 10 and the second conductive layer 12 is exemplarily shown by a single vertical connection element. In other examples, such electrical coupling may be provided differently.

[0021] The semiconductor device 100 may further include an electrical through connection structure 14 electrically coupled to the first conductive layer 10 and the second conductive layer 12. The electrical through connection structure 14 may extend in a direction perpendicular to the first chip main surface 4, i.e., in the y direction. In a top view of the first chip main surface 4, i.e., when viewed along the z direction, the electrical through connection structure 14 and the semiconductor chip 2 may not overlap.

[0022] Figure 2 A side cross-sectional view of a semiconductor device 200 according to the present disclosure is schematically shown. The semiconductor device 200 can be regarded as Figure 1 a more detailed version of the semiconductor device 100.

[0023] The semiconductor device 200 may include a semiconductor chip 2. In one example, the semiconductor chip 2 may be made of an elemental semiconductor material (e.g., Si). In another example, the semiconductor chip 2 may be made of a wide-bandgap semiconductor material or a compound semiconductor material (e.g., SiC, GaN, SiGe, GaAs). In particular, the semiconductor chip 2 may include a power semiconductor chip. The power semiconductor chip can be used in any kind of power application, such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a half-bridge circuit, a power module including a gate driver, etc. For example, the power semiconductor chip may include a power device such as a power MOSFET, an LV (low voltage) power MOSFET, a power IGBT (Insulated Gate Bipolar Transistor), a power diode, a superjunction power MOSFET, etc. or may be part of such a power device. The power semiconductor element may, for example, have a supply voltage greater than about 20V.

[0024] The semiconductor chip 2 may include two chip main surfaces, namely, a top chip surface 4 and a bottom chip surface 6. A first contact pad 8A and a second contact pad 8B may be disposed on the top chip surface 4 and the bottom chip surface 6, respectively. In Figure 2 an example, the semiconductor chip 2 may include or may correspond to a power transistor, such as a power MOSFET. In this case, the first contact pad 8A may be a drain contact pad of the power transistor, and the second contact pad 8B may be a source contact pad of the power transistor. For example, the drain contact pad 8A may cover more than about 80% of the top chip surface 4, or even more than about 90%. The semiconductor chip 2 may further include a gate contact pad, which may, for example, be disposed on the bottom chip surface 6 but is not visible in Figure 2 the selected view angle.

[0025] The semiconductor chip 2 can have a vertical structure, i.e., the semiconductor chip 2 can be fabricated such that current can flow substantially in a direction perpendicular to the main surface of the semiconductor chip 2, i.e., the z-direction. The semiconductor chip 2 having a vertical structure can have electrodes on its two main surfaces, i.e., on its top side and bottom side. In particular, a power semiconductor chip can have a vertical structure and can have load electrodes arranged on the two main surfaces. For example, the source electrode and the gate electrode of a power MOSFET can be arranged on one surface, while the drain electrode of the power MOSFET can be arranged on the other surface. In another example, a power HEMT can be configured as a vertical power semiconductor chip. Other examples of vertical power semiconductor chips are PMOS (P-Channel Metal Oxide semiconductor) or NMOS (N-Channel Metal Oxide semiconductor).

[0026] The semiconductor device 200 can include a first conductive layer 10, which is arranged on the top chip surface 4 of the semiconductor chip 2 and is electrically coupled to the first chip contact pad 8A. The first conductive layer 10 can continuously extend parallel to the top chip surface 4, and thus can be configured to continuously carry current in the x-direction. Generally, the first conductive layer 10 can be fabricated from at least one of metals and metal alloys. More particularly, the first conductive layer 10 can be fabricated from at least one of copper and copper alloys.

[0027] The first conductive layer 10 can have the shape of a conductor plane. In other words, the first conductive layer 10 does not have to be formed as a conductor line that extends substantially only in a single direction. Instead, the first conductive layer 10 can extend in the x-direction and the y-direction to a substantially similar extent. When viewed in the z-direction, the first conductive layer 10 can cover the top chip surface 4 of the semiconductor chip 2 by more than about 50%, or more than about 60%, or more than about 70%, or more than about 80%, or even more than about 90%. The thickness of the first conductive layer 10 in the z-direction can be in the range of about 15 micrometers to about 45 micrometers, more particularly in the range of about 20 micrometers to about 40 micrometers. In Figure 2 the example, the top surface and the bottom surface of the first conductive layer 10 can be substantially flat, such that the thickness of the first conductive layer 10 can be substantially constant over its entire size.

[0028] The semiconductor device 200 may include a second conductive layer 12 disposed on top of the first conductive layer 10 and electrically coupled to the first conductive layer 10. The second conductive layer 12 may be at least partially similar to the first conductive layer 10, such that the above statements regarding the first conductive layer 10 may also apply to the second conductive layer 12. In the z direction, the thickness of the first conductive layer 10 may be less than the thickness of the second conductive layer 12. The thickness of the second conductive layer 12 in the z direction may be in the range of about 30 microns to 90 microns, more particularly in the range of about 35 microns to about 65 microns.

[0029] The semiconductor device 200 may include a first via array 15 disposed between the first chip contact pad 8A and the first conductive layer 10 and electrically coupling them. In particular, the first via array 15 may include a plurality of via connection structures 16 electrically connecting the top surface of the first chip contact pad 8A and the bottom surface of the first conductive layer 10. Generally, the first via array 15 may be made of at least one of metals and metal alloys. More particularly, the first via array 15 may be made of at least one of copper and copper alloys. For example, the via connection structures 16 of the first via array 15 may include at least one of micro via connection structures or PTH (Plated through hole) via connection structures. The first via array 15 may cover the first chip contact pad 8A by more than about 5%, or more than about 10%, or more than about 20%, or more than about 30%, or more than about 40%, or more than about 50%, or even more than about 60%. The number of the via connection structures 16 of the first via array 15 may be related to the size of the via connection structures 16 and the size of the first contact pad 8A, and may be dozens or even hundreds. The via connection structures 16 may be distributed on the first contact pad 8A in a regular pattern.

[0030] The semiconductor device 200 may include a second via array 18 disposed between the first conductive layer 10 and the second conductive layer 12 and electrically coupling them. The second via array 18 may be at least partially similar to the first via array 15, such that the above description regarding the first via array 15 may also apply to the second via array 18. When observed in the z direction, the via connection structures 16 of the first via array 15 and the via connection structures 16 of the second via array 18 may be arranged consistently.

[0031] The semiconductor device 200 may include an electrical through-connection structure 14 electrically coupled to the first conductive layer 10 and the second conductive layer 12. The electrical through-connection structure 14 may continuously extend in a direction perpendicular to the top chip surface 4 of the semiconductor chip 2, and thus may be configured to continuously carry current in the z direction. In Figure 2In a side view, the electrical through-connection structure 14 and the semiconductor chip 2 can be arranged side by side. In other words, when viewed in the z direction, the electrical through-connection structure 14 and the semiconductor chip 2 may not overlap. In Figure 2 In an example, the electrical through-connection structure 14 can be formed by a stacked via connection structure, such as a micro via connection structure or a PTH via connection structure. The electrical through-connection structure 14 can be referred to as a through-packaging via connection structure. In Figure 2 In an example, due to the selected viewing angle, only one through-packaging connection structure is visible. However, the electrical through-connection structure 14 can also include more than one through-packaging via connection structure, as can be seen in Figure 8 the bottom cross-sectional view.

[0032] The semiconductor device 200 can include a third conductive layer 20 disposed on the bottom chip surface 6 of the semiconductor chip 2 and electrically coupled to the second chip contact pad 8B. The third conductive layer 20 can be at least partially similar to the first conductive layer 10, and thus, the above description regarding the first conductive layer 10 can also apply to the third conductive layer 20. In particular, in the z direction, the thickness of the third conductive layer 20 can be similar to the thickness of the first conductive layer 10.

[0033] The semiconductor device 200 can include a fourth conductive layer 22 disposed on the bottom surface of the third conductive layer 20. The fourth conductive layer 22 can be at least partially similar to the second conductive layer 12, and thus, the above description regarding the second conductive layer 12 can also apply to the fourth conductive layer 22. In particular, in the z direction, the thickness of the fourth conductive layer 22 can be similar to the thickness of the second conductive layer 12.

[0034] The semiconductor device 200 can include a third via array 24 disposed between the second chip contact pad 8B and the third conductive layer 20 and electrically coupling them. In addition, the semiconductor device 200 can include a fourth via array 26 disposed between the third conductive layer 20 and the fourth conductive layer 22 and electrically coupling them. When viewed in the z direction, the via connection structures 16 of the third via array 24 and the via connection structures 16 of the fourth via array 26 can be arranged consistently. Each of the third via array 24 and the fourth via array 26 can be at least partially similar to, for example, the first via array 15, and thus, the above description regarding the first via array 15 can also apply to the third via array 24 and the fourth via array 26.

[0035] The semiconductor device 200 can include a laminate 28, wherein one or more components of the semiconductor device 200 can be embedded in the laminate 28. Thus, the semiconductor device 200 can also be referred to as a semiconductor package. InFigure 2 In the example, all of the previously described components can be at least partially encapsulated by the material of the laminate 28. For example, the laminate 28 can include a glass-reinforced epoxy laminate material. In particular, the laminate can include an FR4 laminate. The more detailed structure and deployment of the exemplary laminate 28 are shown and described in Figure 7 . The laminate 28 and / or the first and second conductive layers 10, 12 can have mechanical robustness, which can provide sufficient mechanical support for the semiconductor device 200. Thus, additional support structures such as lead frames, etc. are not required.

[0036] The semiconductor device 200 can include a first device main surface 30 and a second device main surface 32 arranged opposite to the first device main surface 30. In Figure 2 the example, the upper surface of the second conductive layer 12 can form at least a part of the first device main surface 30. The upper surface of the second conductive layer 12 can not be covered by the laminate 28. In Figure 2 the example, the upper surface of the second conductive layer 12 can not be covered by any other (especially solid) material. In another example, a heat sink (not shown) can be arranged above the upper surface of the second conductive layer 12 for cooling purposes. In particular, the upper surface of the second conductive layer 12 can provide the entire top-side copper pad for good thermal connection. The heat generated during the operation of the semiconductor device 200 can be dissipated and guided to the heat sink.

[0037] The fourth conductive layer 22 can include a first device contact pad 34 and a second device contact pad 36. Each of the first device contact pad 34 and the second device contact pad 36 can be arranged at the bottom device surface 32. In Figure 2 the example, the bottom surfaces of the first device contact pad 34 and the second device contact pad 36 can not be covered by the laminate 28. In Figure 2 the example, the bottom surfaces of the first device contact pad 34 and the second device contact pad 36 can not be covered by any other (especially solid) material. In another example, a solder material (not shown) can be arranged above the first device contact pad 34 and the second device contact pad 36 to electrically and mechanically connect the semiconductor device 200 to a circuit board (not shown). The electrical redistribution structure formed by the conductive layer and the via array arranged above the bottom surface of the semiconductor chip 2 can easily optimize the footprint area of the semiconductor device 200.

[0038] The first chip contact pad 8A can be electrically coupled to the second device contact pad 36 via the first conductive layer 10, the second conductive layer 12, the first via array 15, the second via array 18, and the electrical through-connection structure 14. Thus, current can flow continuously from the first chip contact pad 8A to the second device contact pad 36, and / or vice versa. Here, the first conductive layer 10 and the second conductive layer 12 can be configured to carry current in parallel. Due to this electrical redistribution, the drain contact pad 8A of the power transistor can be made accessible at the second device contact pad 36. In a similar manner, the second chip contact pad 8B can be electrically coupled to the first device contact pad 34 via the third conductive layer 20, the third via array 24, and the fourth via array 26. Thus, the source contact pad 8B of the power transistor can be made accessible at the first device contact pad 34.

[0039] Figure 3 A feature of the semiconductor device 200 according to the present disclosure is schematically illustrated. In Figure 3 , the current flowing from the first chip contact pad 8A (e.g., drain contact pad) to the second device contact pad 36 is indicated by an arrow. The current can flow particularly in parallel through the first conductive layer 10 and the second conductive layer 12. Compared with conventional semiconductor devices in which the lateral path of the current is provided by only a single conductive layer, the ohmic loss and resistance can be reduced. As described above, the first conductive layer 10 can be thinner than the second conductive layer 12. That is, the first conductive layer 10 can provide better design rules and lower plating costs.

[0040] Figure 4 A feature of the semiconductor device 200 according to the present disclosure is schematically illustrated. In Figure 4 , the current flowing from the second chip contact pad 8B (e.g., source contact pad) to the first device contact pad 34 is indicated by the arrow on the left. When viewed in the z direction, the via connection structures 16 of the third via array 24 and the via connection structures 16 of the fourth via array 26 can be arranged consistently. Thus, the shown current can flow from the second chip contact pad 8B to the first device contact pad 34 along the shortest path. There will be no lateral current generated due to staggered via connection structures. In Figure 4 , the current flowing from the first conductive layer 10 and the second conductive layer 12 to the second device contact pad 36 is indicated by the arrow on the right. This current path of the semiconductor device 200 can provide a direct vertical electrical connection, thus providing good thermal and electrical performance.

[0041] Figure 5 A feature of the semiconductor device 200 according to the present disclosure is schematically illustrated. In Figure 5In [description], the current flowing between the first chip contact pad 8A, the second chip contact pad 8B and the first device contact pad 34, the second device contact pad 36 is indicated by arrows. The electrical redistribution provides a short and direct electrical connection between the first chip contact pad 8A, the second chip contact pad 8B and a circuit board (not shown), and the semiconductor device 200 can be mounted on the circuit board through the first device contact pad 34, the second device contact pad 36. Such optimized current can minimize parasitic effects and provide low inductance. It should be noted that the short and direct electrical connection is provided especially by the via connection structure 16 that uniformly arranges the first via array 15, the second via array 18 and / or by the via connection structure 16 that uniformly arranges the third via array 24, the fourth via array 26.

[0042] Each of the first via array 15 and the third via array 24 may include densely arranged via connection structures 16, such as micro-via connection structures. Due to this dense arrangement, the first contact pad 8A and the second contact pad 8B can be optimally contacted by the first via array 15 and the third via array 24. For example, the via connection structures 16 can be arranged especially close to the edge of the semiconductor chip 2, so that a small distance from the peripheral via connection structure to the chip edge can be achieved. In contrast, it may be problematic to achieve such a small distance by using a clip connection. The minimum distance "d" from the via connection structure of, for example, the first via array 15 to the edge of the semiconductor chip 2 can be in the range of about 50 microns to about 350 microns, more particularly in the range of about 75 microns to about 300 microns. The small distance from the peripheral via connection structure to the chip edge can improve the thermal performance and high-frequency performance of the semiconductor device 200. In addition, the via connection structures arranged close to the chip edge can be configured to carry most of the current flowing through the first via array 15 and the third via array 24.

[0043] Figure 6 One feature of the semiconductor device 200 according to the present disclosure is schematically shown. In Figure 6In [the figure], the semiconductor chip 2, the first device contact pad 34 (e.g., the device source pad) and the second device contact pad 36 (e.g., the device drain pad) are surrounded by a dashed rectangle. The first solid rectangle on the left shows the first overlapping region 38A between the semiconductor chip 2 and the first device contact pad 34. In a similar manner, the second solid rectangle on the right shows the second overlapping region 38B between the semiconductor chip 2 and the second device contact pad 36. When viewed in the z-direction, the semiconductor chip 2 can at least partially overlap with the first device contact pad 34 and / or the second device contact pad 36. The first overlapping region 38A and the second overlapping region 38B can provide the possibility of reducing the size of the semiconductor device 200 in the x-direction and the y-direction. Additionally, the occupied area of the semiconductor device 200 and the occupied areas of the first device contact pad 34 and the second device contact pad 36 can be optimized.

[0044] Figure 7 A side cross-sectional view of a semiconductor device 700 according to the present disclosure is schematically shown. The semiconductor device 700 can be at least partially similar to Figure 2 the semiconductor device 200. Figure 7 Shows the dimensions of the components forming the semiconductor device according to the present disclosure. The information provided by Figure 7 is also applicable to other semiconductor devices according to the present disclosure described herein.

[0045] Figure 7 Includes information about the materials of the components forming the semiconductor device 700. The semiconductor device 700 can include an intermediate FR4 layer that can embed the semiconductor chip 2. The intermediate FR4 layer can cover the side surface of the semiconductor chip 2. The semiconductor device 700 can further include a plurality of additional FR4 layers arranged above and below the intermediate FR4 layer. In particular, the FR4-based PCB material can include only a small amount of halogen content, e.g., a low chlorine content. For example, Figure 7 the intermediate FR4 layer and the additional FR4 layers can at least partially form Figure 2 the material of the laminate 28. The semiconductor device 700 can further include a plurality of copper layers or copper foils arranged above and below the intermediate FR4 layer and between the other FR4 layers. For example, the copper layers can at least partially form Figure 2 the first conductive layer 10, the second conductive layer 12, the third conductive layer 20, and the fourth conductive layer 22.

[0046] Figure 7 Includes a first table that provides exemplary values for the thicknesses of the shown material layers. Additionally, a second table provides a range of exemplary values for the thicknesses of the material layers. For example, the thickness of the intermediate FR4 layer can be in the range from about 60 microns to about 130 microns. In Figure 7In the example, the thickness of the middle FR4 layer can have an exemplary value of about 80 micrometers.

[0047] The expected total thickness or height of the semiconductor device 700 in the z - direction can be in the range of about 380 micrometers to about 600 micrometers, or about 410 micrometers to about 600 micrometers, or about 490 micrometers to about 600 micrometers. Thus, compared with traditional semiconductor devices, the semiconductor device according to the present disclosure can provide a reduced height in the z - direction. The reduced height can provide the possibility of arranging additional components, such as passive elements, above one or more main device surfaces.

[0048] In Figure 7 the dashed - rectangle indicates the area around the semiconductor chip 2. In Figure 7 the example, the indicated area may have no fiberglass. The layers arranged outside the rectangle may include fiberglass. The size (or depth) of the via - connection structure 16 arranged on the upper surface of the semiconductor chip 2 in the z - direction can be in the range from about 55 micrometers to about 60 micrometers. The size (or depth) of the via - connection structure 16 arranged on the lower surface of the semiconductor chip 2 in the z - direction can be in the range from about 60 micrometers to about 65 micrometers. The size of the semiconductor chip 2 in the z - direction can be in the range from about 40 micrometers to about 110 micrometers and can have an exemplary value of 60 micrometers.

[0049] Figure 8 A bottom cross - sectional view of a semiconductor device 800 according to the present disclosure is schematically shown. The semiconductor device 800 can be similar to the semiconductor device 200 discussed in the previous figures. In particular, Figure 8 the bottom cross - sectional view can be similar to the bottom view of the cross - section along the plane A - A' of the semiconductor device 200 in Figure 2 .

[0050] The semiconductor device 800 can include a semiconductor chip 2 represented by a dashed rectangle. Figure 8 The size of the semiconductor chip 2 in Figure 8 is exemplary and can be different in other examples. In Figure 8 the example, the semiconductor chip 2 can include transistors having gate pads, source pads, and drain pads. Figure 8In the example, the first part 20A can be formed in a T shape, and the third part 20C can be formed in a U shape. The second part 20B can be disposed between the first part 20A and the third part 20C, and thus can have a shape adapted to the shapes of the first part 20A and the third part 20C.

[0051] Figure 8 An array of vias is shown that provides electrical connections between a first part 20A of a conductive layer and source pads of semiconductor chip 2. Figure 8 The number of via connection structures 16 in is exemplary and can be different in other examples. Referring again to Figure 2 , the via connection structures 16 can correspond, for example, to a third via array 24. The via connection structures 16 can provide a large source pad coverage. For example, the via connection structures 16 can cover more than 5%, or more than about 10%, or more than about 20%, or more than about 30%, or more than about 40%, or more than about 50%, or even more than about 60% of the source contact pads of semiconductor chip 2. The via connection structures 16 can be evenly distributed over the source pads. In particular, the via connection structures 16 can be disposed on flat regions of the source pads. Uneven regions of the source pads (possibly caused by gate runners or (polyimide) passivation) can remain uncovered. It should be noted that this can also be the case for via connection structures that contact gate contact pads and drain contact pads of semiconductor chip 2. Placing the via connection structures 16 only on flat regions of the corresponding chip contact pads can minimize reflections that may cause non-ideal via shapes or deformations during laser drilling.

[0052] Figure 8 An array of electrical through-connection structures 14 is shown that provides at least a portion of the electrical coupling between the drain contact pads of semiconductor chip 2 and the footprint area of semiconductor device 800. Figure 8 The number of electrical through-connection structures 14 in is exemplary and can be different in other examples. The electrical through-connection structures 14 can correspond to Figure 2 similar components as shown in. In Figure 8 's example, the electrical through-connection structures 14 can be arranged in a U shape so as to at least partially surround semiconductor chip 2. As discussed with reference to the foregoing figures, the electrical through-connection structures 14 can help minimize resistance in semiconductor device 800.

[0053] Figure 8 A via connection structure 48 is shown that provides an electrical connection between a second part 20B of a conductive layer and a gate pad of semiconductor chip 2. In Figure 8In the example, only one via connection structure 48 is shown. In other examples, the number of via connection structures 48 may be different.

[0054] Figure 9 A bottom view of a semiconductor device 900 according to the present disclosure is schematically shown. For example, the semiconductor device 900 may be similar to any of the semiconductor devices discussed previously, and vice versa. The semiconductor device 900 may include a plurality of device contact pads disposed at the bottom surface of the semiconductor device 900. In Figure 9 the example, the semiconductor device 900 may include two source contact pads 40A, 40B, two gate contact pads 42A, 42B, and two drain contact pads 44A, 44B. The contact pads may be symmetrically arranged such that current can be directed in two different directions, e.g., in the positive x direction and the negative x direction (see arrows). Using a plurality of contact pads can support solder inspection (LTI, lead tip inspection). For example, compared to solder inspection based on only one gate contact pad disposed at the center of the bottom surface of the device, solder inspection based on Figure 9 the two gate contact pads 42A, 42B shown in the example may be easier to perform.

[0055] Figure 10 A top view of an assembly 1000 including a plurality of semiconductor devices according to the present disclosure is schematically shown. For example, each semiconductor device may be similar to Figure 9 the semiconductor device 900. The assembly 1000 may include a plurality of signal lines 46A, 46B, and 46C, which may be configured to electrically couple the contact pads of the semiconductor device 900. In particular, the first signal line 46A may be configured to electrically couple the source contact pads 40A, 40B of the semiconductor device 900, the second signal line 46B may be configured to electrically couple the gate contact pads 42A, 42B of the semiconductor device 900, and the third signal line 46B may be configured to electrically couple the drain contact pads 44A, 44B of the semiconductor device 900. As can be seen from Figure 10 the semiconductor device 900's footprint design allows multiple power MOSFETs to be easily arranged in parallel on the board.

[0056] Figure 11 A flowchart of a method for manufacturing a semiconductor device according to the present disclosure is shown. The method is described in a general manner to qualitatively specify various aspects of the present disclosure. Figure 11 The method may include other aspects. For example, Figure 11 the method may be extended by incorporating any aspect described in other examples according to the present disclosure.

[0057] At step 50, a semiconductor chip including first chip contact pads on a first chip main surface can be provided. At step 52, a first conductive layer disposed over the first chip main surface and electrically coupled to the first chip contact pads can be formed. The first conductive layer can extend in a direction parallel to the first chip main surface. At step 54, a second conductive layer disposed over the first conductive layer and electrically coupled to the first conductive layer can be formed. The second conductive layer can extend in a direction parallel to the first conductive layer. At step 56, an electrical through connection structure electrically coupled to the first conductive layer and the second conductive layer can be formed. The electrical through connection structure can extend in a direction perpendicular to the first chip main surface. In a top view of the first chip main surface, the electrical through connection structure and the semiconductor chip may not overlap.

[0058] Example

[0059] Hereinafter, a semiconductor device including parallel conductive layers and a method for manufacturing such a semiconductor device will be explained by way of examples.

[0060] Example 1 is a semiconductor device including: a semiconductor chip including first chip contact pads on a first chip main surface; a first conductive layer disposed over the first chip main surface and electrically coupled to the first chip contact pads, wherein the first conductive layer extends in a direction parallel to the first chip main surface; a second conductive layer disposed over the first conductive layer and electrically coupled to the first conductive layer, wherein the second conductive layer extends in a direction parallel to the first conductive layer; and an electrical through connection structure electrically coupled to the first conductive layer and the second conductive layer, wherein the electrical through connection structure extends in a direction perpendicular to the first chip main surface, and in a top view of the first chip main surface, the electrical through connection structure and the semiconductor chip do not overlap.

[0061] Example 2 is the semiconductor device according to Example 1, wherein the first conductive layer and the second conductive layer are configured to carry current in parallel between the first chip contact pads and the electrical through connection structure.

[0062] Example 3 is the semiconductor device according to Example 1 or 2, wherein the semiconductor chip includes a power transistor and the first chip contact pads include drain contact pads of the power transistor.

[0063] Example 4 is the semiconductor device according to any of the foregoing examples, the semiconductor device further including: a first device main surface, wherein the first chip main surface faces the first device main surface; and a second device main surface disposed opposite to the first device main surface, wherein the electrical through connection structure is electrically coupled to first device contact pads disposed at the second device main surface.

[0064] Example 5 is a semiconductor device according to any of the foregoing examples, the semiconductor device further comprising: a laminate in which at least a semiconductor chip, a first conductive layer, and an electrical through-connection structure are embedded.

[0065] Example 6 is a semiconductor device according to any of the foregoing examples, wherein a surface of the second conductive layer facing away from the main surface of the first chip is exposed.

[0066] Example 7 is a semiconductor device according to any of the foregoing examples, wherein in a top view of the main surface of the first chip, the first conductive layer covers more than 50% of the main surface of the first chip.

[0067] Example 8 is a semiconductor device according to any of the foregoing examples, wherein in a direction perpendicular to the main surface of the first chip, a thickness of the first conductive layer is less than a thickness of the second conductive layer.

[0068] Example 9 is a semiconductor device according to any of the foregoing examples, wherein in a direction perpendicular to the main surface of the first chip, the thickness of the first conductive layer is in a range from 15 micrometers to 45 micrometers.

[0069] Example 10 is a semiconductor device according to any of the foregoing examples, wherein in a direction perpendicular to the main surface of the first chip, the thickness of the second conductive layer is in a range from 30 micrometers to 90 micrometers.

[0070] Example 11 is a semiconductor device according to any of the foregoing examples, the semiconductor device further comprising: a first via array that electrically couples a first chip contact pad and the first conductive layer.

[0071] Example 12 is a semiconductor device according to Example 11, wherein the first via array covers more than 5% of the first chip contact pad.

[0072] Example 13 is a semiconductor device according to Example 11 or 12, wherein a minimum distance between the first via array and an edge of the semiconductor chip is in a range from about 50 micrometers to about 350 micrometers.

[0073] Example 14 is a semiconductor device according to any of the foregoing examples, the semiconductor device further comprising: a second via array that electrically couples the first conductive layer and the second conductive layer.

[0074] Example 15 is a semiconductor device according to Example 14, wherein in a top view of the main surface of the first chip, via connection structures of the first via array and via connection structures of the second via array are arranged in a consistent manner.

[0075] Example 16 is a semiconductor device according to any of the foregoing examples, the semiconductor device further comprising: a second chip contact pad disposed on a second chip main surface opposite to the first chip main surface; and a third conductive layer disposed over the second chip main surface and electrically coupled to the second chip contact pad, wherein the third conductive layer extends in a direction parallel to the second chip main surface.

[0076] Example 17 is the semiconductor device according to Example 16, the semiconductor device further comprising: a third via array that electrically couples the second chip contact pad and the third conductive layer.

[0077] Example 18 is the semiconductor device according to Example 16 or 17, the semiconductor device further comprising: a second device contact pad disposed at the second device main surface; and a fourth via array that electrically couples the third conductive layer and the second device contact pad.

[0078] Example 19 is the semiconductor device according to Example 18, wherein in a top view of the first chip main surface, via connection structures of the third via array and via connection structures of the fourth via array are arranged consistently.

[0079] Example 20 is the semiconductor device according to any of Examples 4 - 19, wherein in a top view of the first chip main surface, the semiconductor chip and the first device contact pad at least partially overlap.

[0080] Example 21 is a method for manufacturing a semiconductor device, wherein the method comprises: providing a semiconductor chip including a first chip contact pad on a first chip main surface; forming a first conductive layer disposed over the first chip main surface and electrically coupled to the first chip contact pad, wherein the first conductive layer extends in a direction parallel to the first chip main surface; forming a second conductive layer disposed over the first conductive layer and electrically coupled to the first conductive layer, wherein the second conductive layer extends in a direction parallel to the first conductive layer; and forming an electrical through - connection structure electrically coupled to the first conductive layer and the second conductive layer, wherein the electrical through - connection structure extends in a direction perpendicular to the first chip main surface, and in a top view of the first chip main surface, the electrical through - connection structure and the semiconductor chip do not overlap.

[0081] As used in this specification, the terms "connect", "couple", "electrically connect" and / or "electrically couple" may not necessarily mean that elements must be directly connected or coupled together. Intermediate elements may be provided between elements that are "connected", "coupled", "electrically connected" or "electrically coupled".

[0082] Further, the term "above" as used herein with respect to, for example, a material layer formed or positioned "above" the surface of an object can be used to mean that the material layer can be positioned "directly" (e.g., formed, deposited, etc.) on the corresponding surface, such as in direct contact with the corresponding surface. The term "above" as used herein with respect to, for example, a material layer formed or positioned "above" a surface can also be used to mean that the material layer can be positioned "indirectly" (e.g., formed, deposited, etc.) on the corresponding surface, where one or more additional layers are disposed between the corresponding surface and the material layer.

[0083] In addition, the terms "having", "means", "including", "with" or variants thereof used in the specification or claims are intended to be open-ended inclusions in a manner similar to the term "comprising". In other words, the terms "having", "containing", "including", "with", "comprising", etc. used herein are open-ended terms that indicate the presence of the stated element or feature, but do not exclude other elements or features. Unless the context clearly indicates otherwise, the articles "a", "an" and "the" are intended to include both the plural and the singular.

[0084] In addition, the term "exemplary" is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "exemplary" is not necessarily to be construed as superior to other aspects or designs. Rather, the use of the term exemplary is intended to present concepts in a concrete manner. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise stated or clear from the context, "X uses A or B" is intended to mean any natural inclusive arrangement. That is, if X uses A; X uses B; or X uses both A and B, then in any of the foregoing cases, "X uses A or B" is satisfied. Additionally, the articles "a" and "an" used in this application and the appended claims can generally be construed to mean "one or more" unless otherwise stated or clearly indicated from the context to be in the singular form. Additionally, at least one of A and B, etc. generally means A or B or both A and B.

[0085] Devices and methods for manufacturing the devices are described herein. Comments made in connection with the described devices can also hold for the corresponding methods, and vice versa. For example, if a particular component of a device is described, the corresponding method for manufacturing the device can include the operation of providing the component in a suitable manner, even if the operation is not explicitly described or shown in the figures.

[0086] Although the present disclosure has been shown and described in conjunction with one or more embodiments, other those skilled in the art will, based at least in part on a reading and understanding of this specification and the drawings, conceive of equivalent changes and modifications. The present disclosure includes all such modifications and changes and is limited only by the scope of the concepts of the appended claims. In particular, with respect to the various functions performed by the above-described components (e.g., elements, resources, etc.), unless otherwise specified, the terms used to describe such components are intended to correspond to any component that performs the specific function of the described component (e.g., functionally equivalent), even if not structurally equivalent to the disclosed structure that performs the function in the exemplary embodiments shown herein. Additionally, although a particular feature of the present disclosure may have been disclosed in only one of several embodiments, such feature may be combined with one or more other features of the other embodiments as long as it may be desirable and advantageous for any given or particular application.

Claims

1. A semiconductor device, comprising: A semiconductor chip having a first chip contact pad on a first chip main surface and a second chip contact pad on a second chip main surface opposite to the first chip main surface; A first conductive layer disposed above the first chip main surface and electrically coupled to the first chip contact pad, wherein the first conductive layer extends in a direction parallel to the first chip main surface; A second conductive layer disposed above the first conductive layer and electrically coupled to the first conductive layer, wherein the second conductive layer extends in a direction parallel to the first conductive layer; An electrical through-connection structure directly and electrically coupled to the first conductive layer and the second conductive layer in parallel, wherein the electrical through-connection structure extends in a direction perpendicular to the first chip main surface, and in a top view of the first chip main surface, the electrical through-connection structure and the semiconductor chip do not overlap; A first via array electrically coupling the first chip contact pad and the first conductive layer; A second via array electrically coupling the first conductive layer and the second conductive layer such that the electrical through-connection structure is directly electrically coupled to the first chip contact pad through the first and second conductive layers and the first and second via arrays; A third conductive layer disposed below the second chip main surface and electrically coupled to the second chip contact pad, wherein the third conductive layer extends in a direction parallel to the second chip main surface; and A fourth conductive layer disposed below the third conductive layer and electrically coupled to the third conductive layer, wherein the fourth conductive layer extends in a direction parallel to the third conductive layer; wherein a surface of the second conductive layer facing away from the first chip main surface is completely exposed; wherein the fourth conductive layer includes a first device contact pad and a second device contact pad, each of the first device contact pad and the second device contact pad being disposed at a bottom device surface of the semiconductor device; wherein the first chip contact pad is electrically coupled to the second device contact pad through the first and second conductive layers and the electrical through-connection structure, the second chip contact pad is electrically coupled to the first device contact pad through the third conductive layer, and wherein when viewed in a direction perpendicular to the first chip main surface, the semiconductor chip at least partially overlaps with the first device contact pad and the second device contact pad.

2. The semiconductor device according to claim 1, wherein, The first conductive layer and the second conductive layer are configured to carry current in parallel between the first chip contact pad and the electrical through-connection structure.

3. The semiconductor device according to claim 1 or 2, wherein, The semiconductor chip includes a power transistor, and the first chip contact pad includes a drain contact pad of the power transistor.

4. The semiconductor device according to claim 1 or 2, wherein, The semiconductor device further includes: A first device main surface, wherein the first chip main surface faces the first device main surface; and A second device main surface disposed opposite to the first device main surface and serving as the bottom device surface.

5. The semiconductor device according to claim 1 or 2, wherein, The semiconductor device further includes: A laminate, wherein at least the semiconductor chip, the first conductive layer, and the electrical through-connection structure are embedded in the laminate.

6. The semiconductor device according to claim 1 or 2, wherein In a top view of the first chip main surface, the first conductive layer covers more than 50% of the first chip main surface.

7. The semiconductor device according to claim 1 or 2, wherein, In a direction perpendicular to the first chip main surface, a thickness of the first conductive layer is less than a thickness of the second conductive layer.

8. The semiconductor device according to claim 1 or 2, wherein In a direction perpendicular to the main surface of the first chip, the thickness of the first conductive layer is in the range from 15 micrometers to 45 micrometers.

9. The semiconductor device according to claim 1 or 2, wherein, In a direction perpendicular to the main surface of the first chip, the thickness of the second conductive layer is in the range from 30 micrometers to 90 micrometers.

10. The semiconductor device according to claim 1 or 2, wherein, The first via array covers more than 5% of the first chip contact pads.

11. The semiconductor device according to claim 1 or 2, wherein, The minimum distance between the first via array and the edge of the semiconductor chip is in the range from 50 micrometers to 350 micrometers.

12. The semiconductor device according to claim 1 or 2, wherein, In a top view of the main surface of the first chip, the via connection structures of the first via array and the second via array are arranged consistently.

13. The semiconductor device according to claim 4, wherein, The semiconductor device further includes: A third via array that electrically couples the second chip contact pads and the third conductive layer.

14. The semiconductor device according to claim 13, wherein, The semiconductor device further includes: A fourth via array that electrically couples the third conductive layer and the first device contact pads.

15. The semiconductor device according to claim 14, wherein, In a top view of the main surface of the first chip, the via connection structures of the third via array and the fourth via array are arranged consistently.

16. A method for manufacturing a semiconductor device, wherein, The method includes: Providing a semiconductor chip including first chip contact pads on a main surface of a first chip and second chip contact pads on a second chip main surface opposite to the first chip main surface; Forming a first conductive layer disposed above the main surface of the first chip and electrically coupled to the first chip contact pads, wherein the first conductive layer extends in a direction parallel to the main surface of the first chip; Forming a second conductive layer disposed above the first conductive layer and electrically coupled to the first conductive layer, wherein the second conductive layer extends in a direction parallel to the first conductive layer; Forming an electrical through-connection structure that is directly electrically coupled to the first conductive layer and the second conductive layer in parallel, wherein the electrical through-connection structure extends in a direction perpendicular to the main surface of the first chip, and in a top view of the main surface of the first chip, the electrical through-connection structure and the semiconductor chip do not overlap; Forming a first via array that electrically couples the first chip contact pads and the first conductive layer; Forming a second via array that electrically couples the first conductive layer and the second conductive layer such that the electrical through-connection structure is directly electrically coupled to the first chip contact pads through the first and second conductive layers and the first and second via arrays; Forming a third conductive layer disposed below the second chip main surface and electrically coupled to the second chip contact pads, wherein the third conductive layer extends in a direction parallel to the second chip main surface; and Forming a fourth conductive layer disposed below the third conductive layer and electrically coupled to the third conductive layer, wherein the fourth conductive layer extends in a direction parallel to the third conductive layer; wherein the surface of the second conductive layer facing away from the main surface of the first chip is completely exposed, wherein the fourth conductive layer includes first device contact pads and second device contact pads, and each of the first device contact pads and the second device contact pads is disposed at a bottom device surface of the semiconductor device, wherein the first chip contact pads are electrically coupled to the second device contact pads through the first and second conductive layers and the electrical through-connection structure, the second chip contact pads are electrically coupled to the first device contact pads through the third conductive layer, and Wherein, when viewed in a direction perpendicular to the main surface of the first chip, the semiconductor chip at least partially overlaps with the first device contact pad and the second device contact pad.

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