Power semiconductor module

Abstract

The invention relates to a power semiconductor module having a base and power semiconductor switches, wherein the base has an inner metallization load layer area, a first and a second outer metallization load layer area and a first and a second intermediate metallization load layer area, wherein the first intermediate metallization load layer area is arranged between the inner metallization load layer area and the first outer metallization load layer area and the second intermediate metallization load layer area is arranged between the inner metallization load layer area and the second outer metallization load layer area, wherein a first group and a second group of power semiconductor switches are arranged on the inner metallization load layer area, a third group of power semiconductor switches is arranged on the first intermediate metallization load layer area and a fourth group of power semiconductor switches is arranged on the second intermediate metallization load layer area.

Description

TECHNICAL FIELD

[0001] The invention relates to a power semiconductor module. BACKGROUND

[0002] During operation of a power semiconductor switch module, when opening the power semiconductor switches of the power semiconductor switch module, which are electrically connected to each other to form a half-bridge circuit, due to the parasitic inductance of the conductors electrically connected to the power semiconductor switches, an overvoltage can occur between the load current terminals of the power semiconductor switches, which can lead to a possible damage or destruction of the power semiconductor switches. In order to reduce or prevent the overvoltage, there is therefore a technical requirement to design the power semiconductor module with the lowest possible inductance.

[0003] The patent EP 3 246 945 B1 discloses a low-inductance power semiconductor module providing a half-bridge circuit, which has a substrate and power semiconductor switches arranged on the substrate. In order to provide mechanical protection of the power semiconductor switches, it is disadvantageous to arrange some of the power semiconductor switches providing the half-bridge circuit on the outer metallized load layer area of the substrate. SUMMARY

[0004] It is an object of the invention to create a low-inductance power semiconductor module with a half-bridge circuit, in which the power semiconductor switches of the half-bridge circuit are not arranged on the outer metallized load layer area of the substrate of the power semiconductor module.

[0005] The object is achieved by a power semiconductor module having a base which comprises a non-conducting insulating layer and a metallized load layer region arranged on the insulating layer, and having power semiconductor switches, each having a first load current terminal and a second load current terminal and a control terminal, wherein the base has an inner metallized load layer region which extends in a longitudinal direction, a first outer metallized load layer region and a second outer metallized load layer region which extend in the longitudinal direction, and a first intermediate metallized load layer region and a second intermediate metallized load layer region which extend in the longitudinal direction and are conductively connected to one another, wherein in a transverse direction which extends perpendicular to the longitudinal direction, the first intermediate metallized load layer region is arranged between the inner metallized load layer region and the first outer metallized load layer region and the second intermediate metallized load layer region is arranged between the inner metallized load layer region and the second outer metallized load layer region, wherein a first group and a second group of the power semiconductor switches are designed to implement a first arm of a half-bridge circuit and a third group and a fourth group of the power semiconductor switches are designed to implement a second arm of the half-bridge circuit, wherein the first group and the second group of the power semiconductor switches are arranged on the inner metallized load layer region and the first load current terminals of the power semiconductor switches of the first group and of the second group are in conductive contact with the inner metallized load layer region, wherein the second load current terminals of the power semiconductor switches of the first group are conductively connected to the first intermediate metallized load layer region and the second load current terminals of the power semiconductor switches of the second group are conductively connected to the second intermediate metallized load layer region, wherein the third group of the power semiconductor switches is arranged on the first intermediate metallized load layer region and the first load current terminals of the power semiconductor switches of the third group are in conductive contact with the first intermediate metallized load layer region, wherein the second load current terminals of the power semiconductor switches of the third group are conductively connected to the first outer metallized load layer region, wherein the fourth group of the power semiconductor switches is arranged on the second intermediate metallized load layer region and the first load current terminals of the power semiconductor switches of the fourth group are in conductive contact with the second intermediate metallized load layer region, wherein the second load current terminals of the power semiconductor switches of the fourth group are conductively connected to the second outer metallized load layer region.

[0006] It proves to be advantageous if the first and the second intermediate metallization carrier layer region are electrically conductively connected to each other by means of a first metallization connection layer region arranged on the insulating layer, the first metallization connection layer region being formed integrally with the first and the second intermediate metallization carrier layer region. As a result, the first and the second intermediate metallization carrier layer region are electrically conductively connected to each other with low inductance.

[0007] In addition, it proves to be advantageous if the first and the second outer metallization carrier layer region are electrically conductively connected to each other. Thereby, the first and the second outer metallization carrier layer region are already electrically conductively connected to each other on the power semiconductor module.

[0008] In this regard, it proves to be advantageous if the first and the second outer metallization carrier layer region are electrically conductively connected to each other by means of a second metallization connection layer region arranged on the insulating layer, the first metallization connection layer region being formed integrally with the first and the second intermediate metallization carrier layer region. Thereby, the first and the second outer metallization carrier layer region are electrically conductively connected to each other with low inductance.

[0009] It also proves to be advantageous if the power semiconductor switches of the first group of power semiconductor switches are arranged in a row to each other in the longitudinal direction and the power semiconductor switches of the second group of power semiconductor switches are arranged in a row to each other in the longitudinal direction, wherein the power semiconductor switches of the second group of power semiconductor switches are spaced apart from the power semiconductor switches of the first group of power semiconductor switches in the transverse direction. This creates a symmetrical arrangement of the power semiconductor switches of the first and the second group of power semiconductor switches, thereby calibrating the switching characteristics of the power semiconductor switches of the first and the second group of power semiconductor switches.

[0010] It also proves to be advantageous if the power semiconductor switches of the third group of power semiconductor switches are arranged in a row to each other in the longitudinal direction and the power semiconductor switches of the fourth group of power semiconductor switches are arranged in a row to each other in the longitudinal direction. This creates a symmetrical arrangement of the power semiconductor switches of the third and the fourth group of power semiconductor switches, thereby calibrating the switching characteristics of the power semiconductor switches of the third and the fourth group of power semiconductor switches.

[0011] Furthermore, it proves advantageous if the substrate comprises a first metallized control layer region arranged on the insulating layer and extending in the longitudinal direction, which is arranged in the transverse direction between the first group of power semiconductor switches and the second group of power semiconductor switches of the power semiconductor switches, wherein the control terminals of the power semiconductor switches of the first group of power semiconductor switches and of the second group of power semiconductor switches are electrically conductively connected to the first metallized control layer region. This makes a symmetrical activation of the power semiconductor switches of the first group of power semiconductor switches and of the second group of power semiconductor switches possible, whereby the switching characteristics of the power semiconductor switches of the first group of power semiconductor switches and of the second group of power semiconductor switches are aligned.

[0012] In this regard, it proves advantageous if the inner metallized load layer region surrounds, in particular completely surrounds, the first metallized load layer region. This makes a symmetrical activation of the power semiconductor switches of the first group of power semiconductor switches and of the second group of power semiconductor switches possible, whereby the switching characteristics of the power semiconductor switches of the first group of power semiconductor switches and of the second group of power semiconductor switches are aligned.

[0013] Furthermore, it proves advantageous if the substrate has a second metallized control layer region arranged on the insulating layer and extending in the longitudinal direction, which is arranged in the transverse direction between the first intermediate metallized load layer region and the inner metallized load layer region, wherein the control terminals of the power semiconductor switches of the third group of power semiconductor switches are electrically conductively connected to the second metallized control layer region, and the substrate comprises a third metallized control layer region arranged on the insulating layer and extending in the longitudinal direction, which is arranged in the transverse direction between the second intermediate metallized load layer region and the inner metallized load layer region, wherein the control terminals of the power semiconductor switches of the fourth group of power semiconductor switches are electrically conductively connected to the third metallized control layer region. This makes a symmetrical activation of the power semiconductor switches of the third group of power semiconductor switches and of the fourth group of power semiconductor switches possible, whereby the switching characteristics of the power semiconductor switches of the third group of power semiconductor switches and of the fourth group of power semiconductor switches are aligned.

[0014] Furthermore, it proves advantageous that, in each case with respect to the virtual line of symmetry extending in the longitudinal direction, the inner metallized load layer region is arranged mirror-symmetrically, the first outer metallized load layer region is mirror-symmetric to the second outer metallized load layer region, the first intermediate metallized layer region is mirror-symmetric to the second intermediate metallized layer region, and the first group of power semiconductor switches in the power semiconductor switches is mirror-symmetric to the second group of power semiconductor switches in the power semiconductor switches, and the third group of power semiconductor switches in the power semiconductor switches is mirror-symmetric to the fourth group of power semiconductor switches in the power semiconductor switches. This creates a symmetrical arrangement of the power semiconductor switches of the power semiconductor module, such that the stray inductances of the first and second arms of the half-bridge circuit are matched.

[0015] With respect to this, in order to provide an electrical connection of the third and fourth groups of power semiconductor switches in the power semiconductor switches to external control means for controlling the power semiconductor switches of the third and fourth groups of power semiconductor switches, it proves advantageous that the base includes a first and a second control terminal metallized layer region arranged on the insulating layer and on the line of symmetry, wherein the inner metallized load layer region encloses, in particular completely, the first and second control terminal layer regions, wherein the first control terminal metallized layer region is electrically conductively connected to the first and second outer metallized load layer regions, and the second control terminal metallized layer region is electrically conductively connected to the second and third metallized control layer regions. This makes it possible for the third and fourth groups of power semiconductor switches to be controlled particularly symmetrically by the external control means for controlling the power semiconductor switches, whereby the switching behavior of the power semiconductor switches of the third and fourth groups of power semiconductor switches is aligned.

[0016] Furthermore, it proves advantageous that, in operation of the power semiconductor module, the first and second outer metallized load layer regions are designed to exhibit a negative voltage potential, and, in operation of the power semiconductor module, the inner metallized load layer region is designed to exhibit a positive voltage potential, and, in operation of the power semiconductor module, the first and second intermediate metallized load layer regions are designed to exhibit an alternating voltage potential.

[0017] It has also proven advantageous if the power semiconductor module comprises an electrically conductive first load current terminal element which is electrically conductively connected to the internal metallized load layer area, an electrically conductive second load current terminal element which is electrically conductively connected to the first external metallized load layer area, an electrically conductive third load current terminal element which is electrically conductively connected to the second external metallized load layer area, and an electrically conductive fourth load current terminal element which is electrically conductively connected to the first intermediate metallized load layer area and to the second intermediate metallized load layer area. This allows a simple electrical connection of the power semiconductor module to external devices.

[0018] In this regard, it has proven advantageous if the first load current terminal element, the fourth load current terminal element and the second load current terminal element are arranged mirror-symmetrically to the third load current terminal element with respect to a virtual line of symmetry extending in the longitudinal direction. This creates a symmetrical arrangement of the load current terminal elements of the power semiconductor module such that the stray inductances of the first arm and the second arm of the half-bridge circuit are matched. BRIEF DESCRIPTION OF DRAWINGS

[0019] Exemplary embodiments of the present application are described below with reference to the accompanying drawings. In the drawings:

[0020] Figure 1 a circuit diagram of a power semiconductor module according to the present application is shown,

[0021] Figure 2 a plan view of a power semiconductor module according to the present application is shown, and

[0022] Figure 3 a sectional view of a portion of a base on which the power semiconductor components of the power semiconductor module according to the present application are arranged is shown.

[0023] The same elements are denoted by the same reference signs in the figures. DETAILED DESCRIPTION

[0024] Figure 1A circuit diagram of a power semiconductor module 1 according to the present application is shown. The power semiconductor module 1 comprises a half-bridge circuit 6. The half-bridge circuit 6 comprises a first arm Al formed by power semiconductor switches T electrically connected in parallel at load current terminals C and E, and a second arm A2 formed by power semiconductor switches T electrically connected in parallel at load current terminals C and E. The first arm Al and the second arm A2 are electrically connected in series. The power semiconductor module 1 comprises a first load current terminal element DC1+ which is electrically conductively connected to the load current terminals C of the power semiconductor switches T of the first arm Al, a second load current terminal element DC2- and a third load current terminal element DC3- which are electrically conductively connected to the second load current terminals E of the power semiconductor switches T of the second arm A2, and a fourth load current terminal element AC4 which is electrically conductively connected to the second load current terminals E of the power semiconductor switches T of the first arm Al and to the first load current terminals C of the power semiconductor switches T of the second arm A2. In operation of the power semiconductor module 1, a DC-link voltage Udc is present between the first load current terminals C of the power semiconductor switches T of the first arm Al and the second load current terminals E of the power semiconductor switches T of the second arm A2. The half-bridge circuit is used for rectifying or inverting a voltage. The power semiconductor switches T of the first arm Al and the power semiconductor switches T of the second arm A2 are alternately turned on and off with respect to each other via their respective control terminals G. The control terminals G of the power semiconductor switches T of the first arm Al are preferably electrically conductively connected to each other, and the control terminals G of the power semiconductor switches T of the second arm A2 are preferably electrically conductively connected to each other.

[0025] It should be noted that diodes can be electrically connected in anti-parallel to the power semiconductor switches T.

[0026] Figure 2 A plan view of a power semiconductor module 1 according to the present application is shown. Figure 3 A cross-sectional view of a portion of a base 2 on which the power semiconductor components T of the power semiconductor module 1 according to the present application are arranged is shown.

[0027] The power semiconductor module 1 comprises a base 2 with an electrically non-conducting insulation layer 3 and metallized load layer regions MI, MA1, MA2, MZ1 and MZ2 arranged on the insulation layer. The respective metallized load layer regions MI, MA1, MA2, MZ1 or MZ2 form a conductor track or, as in the exemplary embodiment, an area of conductor tracks arranged on the insulation layer 3. The base 2 can comprise a metal layer 5 arranged on the side of the insulation layer 3 opposite the metallized load layer regions MI, MA1, MA2, MZ1 and MZ2. The insulation layer 3 can be designed as a ceramic plate, for example. The base 2 can be implemented as a direct copper bonding base (DCB base), an active metal brazing base (AMB base) or an insulated metal substrate (IMS), for example.

[0028] The power semiconductor module 1 further comprises a plurality of power semiconductor switches T, each having a first load current terminal C and a second load current terminal E as well as a control terminal G. The power semiconductor switches T are preferably in the form of transistors, such as IGBTs (insulated gate bipolar transistors) or MOSFETs (metal oxide semiconductor field effect transistors). In the context of the exemplary embodiment, the power semiconductor switches T are in the form of IGBTs, wherein the first load current terminals C are in the form of collector metallizations of the IGBTs, the second load current terminals E are in the form of emitter metallizations of the IGBTs and the control terminals G are in the form of gate metallizations of the IGBTs. The load current terminals C and E as well as the control terminals G are arranged on a power semiconductor body 20 of the respective power semiconductor switch T. The power semiconductor body 20 forms a semiconductor structure of the respective power semiconductor switch T. The semiconductor material of the power semiconductor body 20 can consist of silicon or silicon carbide.

[0029] The base 2 has an inner metallized load layer region MI extending in the longitudinal direction L, a first outer metallized load layer region MA1 and a second outer metallized load layer region MA2 extending in the longitudinal direction L, and a first intermediate metallized layer region MZ1 and a second intermediate metallized layer region MZ2 extending in the longitudinal direction L, which are electrically conductively connected to one another. The first intermediate metallized load layer region MZ1 is arranged between the inner metallized load layer region MI and the first outer metallized load layer region MA1 in a transverse direction Q perpendicular to the longitudinal direction L. The second intermediate metallized load layer region MZ2 is arranged between the inner metallized load layer region MI and the second outer metallized load layer region MA2 in the transverse direction Q.

[0030] The first group of power semiconductor switches P1 and the second group of power semiconductor switches P2 of the power semiconductor switches T are arranged on the inner metallization load layer area Ml and the first load current terminals C of the first group of power semiconductor switches P1 and the second group of power semiconductor switches P2 of the power semiconductor switches T are in electrically conductive contact with the inner metallization load layer areas P1 and P2 via a connection layer 4, which can be formed as a sinter layer or a solder layer, for example. The second load current terminals E of the power semiconductor switches T of the first group of power semiconductor switches P1 are electrically conductively connected to the first intermediate metallization load layer area MZ1 via bond wires 10, for example, and the second load current terminals E of the power semiconductor switches T of the second group of power semiconductor switches P2 are electrically conductively connected to the second intermediate metallization load layer area MZ2 via bond wires 10, for example.

[0031] The first group of power semiconductor switches P1 and the second group of power semiconductor switches P2 of the power semiconductor switches T are arranged on the inner metallization load layer area Ml and the first load current terminals C of the first group of power semiconductor switches P1 and the second group of power semiconductor switches P2 of the power semiconductor switches T are in electrically conductive contact with the inner metallization load layer areas P1 and P2 via a connection layer 4, which can be formed as a sinter layer or a solder layer, for example. The second load current terminals E of the power semiconductor switches T of the first group of power semiconductor switches P1 are electrically conductively connected to the first intermediate metallization load layer area MZ1 via bond wires 10, for example, and the second load current terminals E of the power semiconductor switches T of the second group of power semiconductor switches P2 are electrically conductively connected to the second intermediate metallization load layer area MZ2 via bond wires 10, for example.

[0032] The first group of power semiconductor switches P1 and the second group of power semiconductor switches P2 of the power semiconductor switches T are arranged on the inner metallization load layer area Ml and the first load current terminals C of the first group of power semiconductor switches P1 and the second group of power semiconductor switches P2 of the power semiconductor switches T are in electrically conductive contact with the inner metallization load layer areas P1 and P2 via a connection layer 4, which can be formed as a sinter layer or a solder layer, for example. The second load current terminals E of the power semiconductor switches T of the first group of power semiconductor switches P1 are electrically conductively connected to the first intermediate metallization load layer area MZ1 via bond wires 10, for example, and the second load current terminals E of the power semiconductor switches T of the second group of power semiconductor switches P2 are electrically conductively connected to the second intermediate metallization load layer area MZ2 via bond wires 10, for example.

[0033] The present application creates a low-inductance power semiconductor module 1 with a half-bridge circuit 6 in which none of the power semiconductor switches T of the half-bridge circuit 6 are arranged on the outer metallization load layer areas MA1 and MA2 of the base 2 of the power semiconductor module 1.

[0034] The first and the second intermediate metallization load layer region MZ1, MZ2 are preferably conductively connected to each other by means of a first metallization connection layer region MV1 arranged on the insulation layer 3, the first metallization connection layer region MV1 being formed integrally with the first and the second intermediate metallization load layer region MZ1, MZ2. Thus, the first and the second intermediate metallization load layer region MZ1, MZ2 and the first metallization connection layer region MV1 are preferably an integral part of a common conductor track of the base 2 arranged on the insulation layer 3. Alternatively or additionally, the first and the second intermediate metallization load layer region MZ1, MZ2 can be conductively connected to each other, for example, by means of at least one bond wire 10 as well.

[0035] The first and the second outer metallization load layer region MA1, MA2 are preferably conductively connected to each other. Thus, the first and the second outer metallization load layer region MA1, MA2 are preferably conductively connected to each other by means of a second metallization connection layer region MV2 arranged on the insulation layer 3, the second metallization connection layer region MV2 being formed integrally with the first and the second outer metallization load layer region MA1, MA2. Thus, the first and the second outer metallization load layer region MA1, MA2 and the second metallization connection layer region MV2 are preferably an integral part of a common conductor track of the base 2 arranged on the insulation layer 3. Alternatively or additionally, the first and the second outer metallization load layer region MA1, MA2 can be conductively connected to each other, for example, by means of at least one bond wire 10 as well.

[0036] The power semiconductor switches T of the first group P1 are preferably arranged in a row in the longitudinal direction L and the power semiconductor switches T of the second group P2 are preferably arranged in a row in the longitudinal direction L, wherein the power semiconductor switches T of the second group P2 are spaced apart from the power semiconductor switches T of the first group P1 in the transverse direction Q.

[0037] The power semiconductor switches T of the third group P3 are preferably arranged in a row in the longitudinal direction L and the power semiconductor switches T of the fourth group P4 are preferably arranged in a row in the longitudinal direction L.

[0038] The substrate 2 is preferably composed of a first metallized control layer region MS1 arranged on the insulating layer 3 in the longitudinal direction L, which first metallized control layer region MS1 is arranged between a first group of power semiconductor switches P1 and a second group of power semiconductor switches P2 in the transverse direction Q, wherein the control terminals G of the power semiconductor switches T of the first group of power semiconductor switches P1 and the second group of power semiconductor switches P2 are electrically conductively connected to the first metallized control layer region MS1, for example via bond wires 10. The inner metallized load layer region MI is preferably encompassing, in particular completely encompassing, the first metallized layer region MS1.

[0039] The substrate 2 is preferably composed of a second metallized control layer region MS2 arranged on the insulating layer 3 and extending in the longitudinal direction L, which second metallized control layer region MS2 is arranged between a first intermediate metallized load layer region MZ1 and the inner metallized load layer region MI in the transverse direction Q. The control terminals G of the power semiconductor switches T of the third group of power semiconductor switches P3 are electrically conductively connected to the second metallized load layer region MS2, for example via bond wires 10. The substrate 2 is preferably composed of a third metallized control layer region MS3 arranged on the insulating layer 3 and extending in the longitudinal direction L, which third metallized control layer region MS3 is arranged between a second intermediate metallized load layer region MZ2 and the inner metallized load layer region MI in the transverse direction Q. The control terminals G of the power semiconductor switches T of the fourth group of power semiconductor switches P4 are electrically conductively connected to the third metallized control layer region MS3, for example via bond wires 10.

[0040] Each metallized control layer region MS1, MS2 and MS3 forms a conductor track or a region of conductor tracks arranged on the insulating layer 3, as in the exemplary embodiments described above. The respective metallized control layer region MS1, MS2 or MS3 electrically conductively connects the control terminals G of the respective group of power semiconductor switches P1, P2, P3 or P4 of the power semiconductor switches T to each other.

[0041] The inner metallized load layer region MI is preferably arranged mirror-symmetrically with respect to a virtual line of symmetry S extending in the longitudinal direction L. Furthermore, it is preferred that, in each case with respect to the virtual line of symmetry S extending in the longitudinal direction L, the first outer metallized load layer region MA1 and the second outer metallized load layer region MA2 are arranged mirror-symmetrically, the first intermediate metallized layer region MZ1 and the second intermediate metallized layer region MZ2 are arranged mirror-symmetrically, and the first group of power semiconductor switches P1 of the power semiconductor switches T and the second group of power semiconductor switches P2 of the power semiconductor switches T are arranged mirror-symmetrically, and the third group of power semiconductor switches P3 of the power semiconductor switches T and the fourth group of power semiconductor switches P4 of the power semiconductor switches T are arranged mirror-symmetrically.

[0042] In order to provide an electrical connection of the third group of power semiconductor switches P3 and the fourth group of power semiconductor switches P4 in the power semiconductor switches T with an external control device (not shown in the figures) for controlling the power semiconductor switches T in the third group of power semiconductor switches P3 and the fourth group of power semiconductor switches P4, the substrate 2 is preferably comprising a first control terminal metallization layer area SA1 and a second control terminal metallization layer area SA2 arranged on the insulation layer 2 and on the symmetry line S. The inner metallization load layer area MI extends around, in particular completely around, the first control terminal layer area SA1 and the second control terminal layer area SA2, wherein the first control terminal metallization layer area SA1 is electrically conductively connected to the first outer metallization load layer area MA1 and the second outer metallization load layer area MA2, for example via the bonding wires 10, and the second control terminal metallization layer area SA2 is electrically conductively connected to the second metallization control layer area MS2 and the third metallization control layer area MS3. The electrical connection of the power semiconductor switches T in the third group of power semiconductor switches P3 and the fourth group of power semiconductor switches P4 with the external control device can be realized, for example, via electrically conductive contact springs establishing a respective electrically conductive connection between a printed circuit board on which the external control device is arranged and the control terminal metallization layer areas SA1 and SA2 on which the contact springs are pressed.

[0043] The connection area A1 of the first metallization control layer area MS1, which is preferably arranged on the symmetry line S, and the connection area A2 of the first metallization connection layer area MV1, which is preferably arranged on the symmetry line S, are used to provide an electrical connection of the first group of power semiconductor switches P1 and the second group of power semiconductor switches P2 in the power semiconductor switches T with an external control device for controlling the power semiconductor switches T in the first group of power semiconductor switches P1 and the second group of power semiconductor switches P2. The electrical connection of the power semiconductor switches T in the first group of power semiconductor switches P1 and the second group of power semiconductor switches P2 with the external control device can be realized, for example, via electrically conductive contact springs establishing a respective electrically conductive connection between a printed circuit board on which the external control device is arranged and the connection areas A1 and A2 on which the contact springs are pressed.

[0044] During operation of the power semiconductor module 1, the first external metallized load layer region MA1 and the second external metallized load layer region MA2 are preferably designed to exhibit a negative voltage potential. During operation of the power semiconductor module 1, the internal metallized load layer region MI is preferably designed to exhibit a positive voltage potential. During operation of the power semiconductor module 1, the first intermediate metallized load layer region MZ1 and the second intermediate metallized load layer region MZ2 are preferably each designed to exhibit an AC voltage potential. Thus, during operation of the power semiconductor module 1, the DC link voltage Udc exists between the internal metallized load layer region MI and the first external metallized load layer region MA1 and the second external metallized load layer region MA2.

[0045] In the operation of the power semiconductor module 1, the first metallization control layer region MS1 ​​is designed to exhibit a first activation potential, and in the operation of the power semiconductor module 1, the second metallization control layer region MS2 and the third metallization control layer region MS3 are designed to exhibit a second activation potential.

[0046] The power semiconductor module 1 preferably includes: a conductive first load current terminal element DC1+, which is conductively connected to an inner metallized load layer region MI; a conductive second load current terminal element DC2-, which is conductively connected to a first outer metallized load layer region MA1; a conductive third load current terminal element DC3-, which is conductively connected to a second outer metallized load layer region MA2; and a conductive fourth load current terminal element AC4, which is conductively connected to a first intermediate metallized load layer region MZ1 and a second intermediate metallized load layer region MZ2. The first load current terminal element DC1+ is preferably disposed on and conductively contacted with the inner metallized load layer region MI. The second load current terminal element DC2- is preferably disposed on and conductively contacted with the first outer metallized load layer region MA1. The third load current terminal element DC3- is preferably disposed on and conductively contacted with the second outer metallized load layer region MA2. The fourth load current terminal element AC4 is preferably disposed on and in conductive contact with the first metallized connection layer region MV1.

[0047] The first load current terminal element DC1+ is preferably arranged in a mirror-symmetric manner about a virtual symmetry line S extending in the longitudinal direction L. The fourth load current terminal element AC4 is preferably arranged in a mirror-symmetric manner about the virtual symmetry line S. The second load current terminal element DC2- is preferably arranged in a mirror-symmetric manner about the virtual symmetry line S and the third load current terminal element DC3-.

[0048] It should be noted that the electrically conductive connection achieved in the above-described exemplary embodiments by means of the bonding wire 10 can also be achieved, for example, by means of an electrically conductive film composite.

Claims

1. A power semiconductor module having a base (2) comprising an electrically non-conducting insulating layer (3) and a metallized load layer region (MI, MA1, MA2, MZ1, MZ2) arranged on the insulating layer (3), and having power semiconductor switches (T), each of which comprises a first load current terminal (C) and a second load current terminal (E) and a control terminal (G), wherein, The substrate (2) has an inner metallization load layer region (MI) which extends in the longitudinal direction (L), a first outer metallization load layer region (MA1) and a second outer metallization load layer region (MA2) which extend in the longitudinal direction (L); and a first intermediate metallization carrier layer region (MZ1) and a second intermediate metallization carrier layer region (MZ2) which extend in the longitudinal direction (L) and are electrically conductively connected to one another; wherein, in a transverse direction (Q) perpendicular to the longitudinal direction (L), the first intermediate metallization carrier layer region (MZ1) is arranged between the inner metallization carrier layer region (MI) and the first outer metallization carrier layer region (MA1) and the second intermediate metallization carrier layer region (MZ2) is arranged between the inner metallization carrier layer region (MI) and the second outer metallization carrier layer region (MA2), wherein a first group (P1) and a second group (P2) of the power semiconductor switches (T) are arranged to realize a first arm (A1) of a half-bridge circuit (6), wherein a third group (P3) and a fourth group (P4) of the power semiconductor switches (T) are arranged to realize a second arm (A2) of the half-bridge circuit (6), wherein the first group (P1) and the second group (P2) of the power semiconductor switches (T) are arranged on the inner metallization carrier layer region (MI) and the first load current connection (C) of the first group (P1) and the second group (P2) of the power semiconductor switches (T) is in electrical conductive contact with the inner metallization carrier layer region (MI), wherein the second load current terminal (E) of the power semiconductor switches (T) of the first group (P1) is electrically conductively connected to the first intermediate metallization carrier layer region (MZ1) and the second load current terminal (E) of the power semiconductor switches (T) of the second group (P2) is electrically conductively connected to the second intermediate metallization carrier layer region (MZ2), wherein the third group (P3) of the power semiconductor switches (T) is arranged on the first intermediate metallization carrier layer region (MZ1) and the first load current terminal (C) of the third group (P3) of the power semiconductor switches (T) is in electrical conductive contact with the first intermediate metallization carrier layer region (MZ1), wherein the second load current terminal (E) of the power semiconductor switches (T) of the third group (P3) is electrically conductively connected to the first outer metallization carrier layer region (MA1), wherein the fourth group (P4) of the power semiconductor switches (T) is arranged on the second intermediate metallization carrier layer region (MZ2),and the first load current terminal (C) of the fourth group of power semiconductor switches (P4) of the power semiconductor switches (T) is in electrically conductive contact with the second intermediate metallization load layer region (MZ2), wherein the second load current terminal (E) of the power semiconductor switches (T) of the fourth group of power semiconductor switches (P4) is electrically conductively connected to the second outer metallization load layer region (MA2).

2. The power semiconductor module according to claim 1, characterized in that The first and second intermediate metallization load layer regions (MZ1, MZ2) are electrically conductively connected to one another by means of a first metallization connection layer region (MV1) which is arranged on the insulating layer (3) and is formed integrally with the first and second intermediate metallization load layer regions (MZ1, MZ2).

3. The power semiconductor module according to any one of claims 1-2, characterized in that, The first and second outer metallization load layer regions (MA1, MA2) are electrically conductively connected to one another.

4. The power semiconductor module according to claim 3, characterized in that The first and second outer metallization load layer regions (MA1, MA2) are electrically conductively connected to one another by means of a second metallization connection layer region (MV2) which is arranged on the insulating layer (3) and is formed integrally with the first and second outer metallization load layer regions (MA1, MA2).

5. The power semiconductor module according to any one of claims 1-2, characterized in that, The power semiconductor switches (T) of the first group of power semiconductor switches (P1) are arranged in a row next to one another in the longitudinal direction (L) and the power semiconductor switches (T) of the second group of power semiconductor switches (P2) are arranged in a row next to one another in the longitudinal direction (L), wherein the power semiconductor switches (T) of the second group of power semiconductor switches (P2) are spaced apart from the power semiconductor switches (T) of the first group of power semiconductor switches (P1) in the transverse direction (Q).

6. The power semiconductor module according to any one of claims 1-2, characterized in that, The power semiconductor switches (T) of the third group of power semiconductor switches (P3) are arranged in a row next to one another in the longitudinal direction (L) and the power semiconductor switches (T) of the fourth group of power semiconductor switches (P4) are arranged in a row next to one another in the longitudinal direction (L).

7. The power semiconductor module according to any one of claims 1-2, characterized in that, The substrate (2) comprises a first metallization control layer region (MS1) which is arranged on the insulating layer (3) and extends in the longitudinal direction (L), which is arranged between the first and second groups of power semiconductor switches (P1, P2) in the transverse direction (Q), wherein the control terminals of the power semiconductor switches (T) of the first and second groups of power semiconductor switches (P1, P2) are electrically conductively connected to the first metallization control layer region (MS1).

8. The power semiconductor module according to claim 7, characterized in that The inner metallization load layer region (MI) surrounds the first metallization control layer region (MS1).

9. The power semiconductor module according to any one of claims 1-2, characterized in that, The substrate (2) has a second metallization control layer region (MS2) arranged on the insulating layer (3) and extending in the longitudinal direction (L), which is arranged in the transverse direction (Q) between the first intermediate metallization load layer region (MZ1) and the inner metallization load layer region (MI), wherein the control terminals (G) of the power semiconductor switches (T) of the third group of power semiconductor switches (P3) are electrically conductively connected to the second metallization control layer region (MS2), and the substrate (2) comprises a third metallization control layer region (MS3) arranged on the insulating layer (3) and extending in the longitudinal direction (L), which is arranged in the transverse direction (Q) between the second intermediate metallization load layer region (MZ2) and the inner metallization load layer region (MI), wherein the control terminals (G) of the power semiconductor switches (T) of the fourth group of power semiconductor switches (P4) are electrically conductively connected to the third metallization control layer region (MS3).

10. The power semiconductor module according to claim 9, characterized in that In each case, the inner metallization load layer region (MI) is arranged mirror-symmetrically with respect to a virtual line of symmetry (S) extending in the longitudinal direction (L), the first outer metallization load layer region (MA1) is mirror-symmetric with the second outer metallization load layer region (MA2), the first intermediate metallization load layer region (MZ1) is mirror-symmetric with the second intermediate metallization load layer region (MZ2), and the first group of power semiconductor switches (P1) of the power semiconductor switches (T) is mirror-symmetric with the second group of power semiconductor switches (P2) of the power semiconductor switches (T), and the third group of power semiconductor switches (P3) of the power semiconductor switches (T) is mirror-symmetric with the fourth group of power semiconductor switches (P4) of the power semiconductor switches (T).

11. The power semiconductor module according to claim 10, characterized in that For the electrical connection of the third group of power semiconductor switches (P3) and the fourth group of power semiconductor switches (P4) in the power semiconductor switches (T) and external control devices for controlling the power semiconductor switches (T) in the third group of power semiconductor switches (P3) and the fourth group of power semiconductor switches (P4), the base (2) comprises a first control terminal metallization layer area (SA1) and a second control terminal metallization layer area (SA2) arranged on the insulating layer (3) and on the virtual symmetry line (S), wherein the inner metallization load layer area (MI) encloses the first control terminal metallization layer area (SA1) and the second control terminal metallization layer area (SA2), wherein the first control terminal metallization layer area (SA1) is electrically conductively connected to the first outer metallization load layer area (MA1) and the second outer metallization load layer area (MA2) and the second control terminal metallization layer area (SA2) is electrically conductively connected to the second metallization control layer area (MS2) and the third metallization control layer area (MS3).

12. The power semiconductor module according to any one of claims 1-2, characterized in that, In operation of the power semiconductor module (1), the first outer metallization load layer area (MA1) and the second outer metallization load layer area (MA2) are designed to exhibit a negative voltage potential and, in operation of the power semiconductor module, the inner metallization load layer area (MI) is designed to exhibit a positive voltage potential and, in operation of the power semiconductor module (1), the first intermediate metallization load layer area (MZ1) and the second intermediate metallization load layer area (MZ2) are designed to exhibit an alternating voltage potential.

13. The power semiconductor module according to any one of claims 1-2, characterized in that, The power semiconductor module (1) comprises an electrically conductive first load current terminal element (DC1+) which is electrically conductively connected to the inner metallization load layer area (MI), an electrically conductive second load current terminal element (DC2-) which is electrically conductively connected to the first outer metallization load layer area (MA1), an electrically conductive third load current terminal element (DC3-) which is electrically conductively connected to the second outer metallization load layer area (MA2) and an electrically conductive fourth load current terminal element (AC4) which is electrically conductively connected to the first intermediate metallization load layer area (MZ1) and the second intermediate metallization load layer area (MZ2).

14. The power semiconductor module according to claim 13, characterized in that The first load current terminal element (DC1+), the fourth load current terminal element (AC4) and the second load current terminal element (DC2-) are arranged mirror-symmetrically to the third load current terminal element (DC3-) with respect to a virtual symmetry line (S) extending in the longitudinal direction (L).

15. The power semiconductor module according to claim 7, characterized in that The inner metallization load layer region (MI) completely surrounds the first metallization control layer region (MS1).

16. The power semiconductor module of claim 11, characterized by The inner metallization load layer region (MI) completely surrounds the first control terminal metallization layer region (SA1) and the second control terminal metallization layer region (SA2).

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