Ferroelectric memory devices and methods of forming the same

Abstract

A ferroelectric memory device includes a multilayer stack, a channel layer, a ferroelectric layer, and an oxygen exclusion layer. The multilayer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers in an alternating stack. The channel layer penetrates the plurality of conductive layers and the plurality of dielectric layers. The ferroelectric layer is disposed between the channel layer and the plurality of conductive layers and the plurality of dielectric layers. The oxygen exclusion layer is disposed along sidewalls of the plurality of conductive layers. The plurality of oxygen exclusion layers laterally separates the ferroelectric layer from the plurality of conductive layers. Embodiments of the invention also relate to methods of forming ferroelectric memory devices.

Description

Technical Field

[0001] Embodiments of the present invention relate to ferroelectric memory devices and methods for forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate, and then using photolithography and etching techniques to pattern the individual material layers to form circuit components and elements on the material layers.

[0003] The semiconductor industry is constantly increasing the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the size of the smallest component, which allows more components to be integrated into a given area. However, as the size of the smallest component decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] An embodiment of the present invention provides a ferroelectric memory device, comprising: a multilayer stack disposed on a substrate and including a plurality of conductive layers and a plurality of dielectric layers stacked alternately; a channel layer penetrating the plurality of conductive layers and the plurality of dielectric layers; a ferroelectric layer disposed between the channel layer and the plurality of conductive layers and the plurality of dielectric layers; and a plurality of deoxygenating layers disposed along the sidewalls of the plurality of conductive layers, wherein the plurality of deoxygenating layers laterally separate the ferroelectric layer from the plurality of conductive layers.

[0005] Another embodiment of the present invention provides a ferroelectric memory device, comprising: a multilayer stack disposed on a substrate and including a plurality of gate electrode layers and a plurality of dielectric layers stacked alternately; a plurality of dielectric pillars disposed on the substrate and penetrating the multilayer stack; an oxide semiconductor layer including a first metal element and disposed between the multilayer stack and each of the dielectric pillars; a ferroelectric layer disposed between the oxide semiconductor layer and the multilayer stack; and a plurality of deoxygenation layers including a second metal element, wherein one of the plurality of deoxygenation layers is disposed between the ferroelectric layer and each of the plurality of gate electrode layers.

[0006] Another embodiment of the present invention provides a method for forming a ferroelectric memory device, comprising: forming a multilayer stack on a substrate, wherein the multilayer stack includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately, and having trenches penetrating the plurality of dielectric layers and the plurality of conductive layers; recessing the plurality of conductive layers exposed by the sidewalls of the trenches, thereby forming a plurality of recesses, one of the plurality of recesses being formed between two adjacent dielectric layers; forming a plurality of deoxygenating layers in the plurality of recesses respectively; forming a ferroelectric layer on the sidewalls of the trenches, wherein the ferroelectric layer covers the sidewalls of the deoxygenating layers and the sidewalls of the dielectric layers; and forming a channel layer on the ferroelectric layer. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figure 1A , Figure 1B and Figure 1C Simplified perspective views, circuit diagrams, and top views of ferroelectric memory devices according to some embodiments are shown.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22 , Figure 23 , Figure 24 , Figure 25A , Figure 25B , Figure 26A , Figure 26B , Figure 27A , Figure 27B , Figure 28A , Figure 28B , Figure 29A , Figure 29B , Figure 30A , Figure 30B , Figure 30C , Figure 30D , Figure 30E , Figure 30F , Figure 30G , Figure 30H and Figure 30I A variation view of the manufacture of a ferroelectric memory device is shown according to some embodiments.

[0010] Figure 31 A method for forming a ferroelectric memory device according to some embodiments is shown.

[0011] Figure 32 A simplified perspective view of a ferroelectric memory device according to some embodiments is shown.

[0012] Figure 33 A simplified perspective view of a ferroelectric memory device according to some embodiments is shown. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0015] Various embodiments provide memory devices such as 3D memory arrays. In some embodiments, a 3D memory array is a ferroelectric field-effect transistor (FeFET) memory circuit comprising a plurality of vertically stacked memory cells. In some embodiments, each memory cell is considered a FeFET, which includes a word line region serving as a gate electrode, a bit line region serving as a first source / drain electrode, and a source line region serving as a second source / drain electrode, a ferroelectric material as a gate dielectric, and an oxide semiconductor (OS) as a channel region. In some embodiments, each memory cell is considered a transistor, such as a thin-film transistor (TFT).

[0016] Figure 1A , Figure 1B and Figure 1C An example of a memory array according to some embodiments is shown. Figure 1A A partial example of a simplified ferroelectric memory device 200 is shown in a partial 3D diagram; Figure 1B A circuit diagram of the ferroelectric memory device 200 is shown; and Figure 1C A top view of a ferroelectric memory device 200 according to some embodiments is shown. The ferroelectric memory device 200 includes a plurality of memory cells 202, which can be arranged in a grid of rows and columns. The memory cells 202 can also be vertically stacked to provide a three-dimensional memory array, thereby increasing device density. The ferroelectric memory device 200 can be disposed in the back-end process (BEOL) of a semiconductor die. For example, the memory array can be disposed in the interconnect layer of the semiconductor die, such as above one or more active devices (e.g., transistors) formed on a semiconductor substrate.

[0017] In some embodiments, the ferroelectric memory device 200 is a flash memory array such as a NOR memory array. In some embodiments, the gate of each memory cell 202 is electrically coupled to a corresponding word line (e.g., wire 72), a first source / drain region of each memory cell 202 is electrically coupled to a corresponding bit line (e.g., wire 116B), and a second source / drain region of each memory cell 202 is electrically coupled to a corresponding source line (e.g., wire 116A) that grounds the second source / drain region. Memory cells 202 in the same horizontal row of the ferroelectric memory device 200 may share a common word line, while memory cells 202 in the same vertical column of the ferroelectric memory device 200 may share a common source line and a common bit line.

[0018] The ferroelectric memory device 200 includes a plurality of vertically stacked conductors 72 (e.g., word lines), with a dielectric layer 52 disposed between adjacent conductors 72. The conductors 72 are connected to the underlying substrate (in... Figure 1A and Figure 1B(Not explicitly shown) extends in a direction parallel to the main surface. The conductor 72 may have a stepped configuration, such that the lower conductor 72 is longer than the upper conductor 72 and extends laterally beyond the endpoint of the upper conductor 72. For example, in Figure 1A The diagram shows multiple stacked layers of wires 72, with the topmost wire 72 being the shortest and the bottommost wire 72 being the longest. The corresponding lengths of the wires 72 can increase in the direction toward the substrate below. In this way, a portion of each wire 72 can be accessed from above the ferroelectric memory device 200, and conductive contacts can be made to contact the exposed portions of the wires 72 respectively.

[0019] The ferroelectric memory device 200 also includes alternately arranged conductive posts 106 (e.g., electrically connected to bit lines) and conductive posts 108 (e.g., electrically connected to source lines). Each of the conductive posts 106 and 108 may extend in a direction perpendicular to the conductor 72. Dielectric materials 98A / 98B are disposed between adjacent conductive posts in the conductive posts 106 and 108 and isolate adjacent conductive posts in the conductive posts 106 and 108.

[0020] Pairs of conductive posts 106 and 108 and intersecting wires 72 define the boundary of each memory cell 202, and isolation posts 102 are disposed between adjacent pairs of conductive posts 106 and 108 and isolate adjacent pairs of conductive posts 106 and 108. In some embodiments, conductive posts 108 are electrically coupled to ground. Although Figure 1A A specific arrangement of conductive post 106 relative to conductive post 108 is shown, but it should be understood that the arrangement of conductive posts 106 and 108 may be interchanged in other embodiments.

[0021] In some embodiments, the ferroelectric memory device 200 may further include an oxide semiconductor (OS) material as a channel layer 92. The channel layer 92 can provide a channel region for the memory cell 202. For example, when an appropriate voltage (e.g., higher than the corresponding threshold voltage (V) of the corresponding memory cell 202) is applied through the corresponding wire 72... th When the channel layer 92 intersects with the conductor 72, the area where the channel layer 92 intersects with the conductor 72 can allow current to flow from the conductor 106 to the conductor 108 (e.g., in the direction shown by arrow 206).

[0022] In some embodiments, a ferroelectric layer 90 is disposed between the channel layer 92 and each of the wire 72 and the dielectric layer 52, and the ferroelectric layer 90 may serve as the gate dielectric of each memory cell 202. In some embodiments, the ferroelectric layer 90 comprises a ferroelectric material, such as hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, etc.

[0023] The ferroelectric layer 90 can be polarized in one of two different directions, and the polarization direction can be changed by applying an appropriate voltage difference across the ferroelectric layer 90 and generating an appropriate electric field. The polarization can be relatively localized (e.g., typically contained within each boundary of memory cell 202), and a continuous region of the ferroelectric layer 90 can extend across multiple memory cells 202. Depending on the polarization direction of a particular region of the ferroelectric layer 90, the threshold voltage of the corresponding memory cell 202 changes, and digital values ​​(e.g., 0 or 1) can be stored. For example, when a region of the ferroelectric layer 90 has a first polarization direction, the corresponding memory cell 202 can have a relatively low threshold voltage, and when a region of the ferroelectric layer 90 has a second polarization direction, the corresponding memory cell 202 can have a relatively high threshold voltage. The difference between the two threshold voltages can be called a threshold voltage offset. A larger threshold voltage offset makes reading the digital value stored in the corresponding memory cell 202 easier (e.g., less prone to error).

[0024] In some embodiments, due to high-temperature annealing or thermal processes at different stages of forming the memory array, the channel layer (e.g., an oxide semiconductor layer) and the ferroelectric layer (e.g., a metal oxide layer) may have an undesirable interface layer (e.g., an oxygen-rich metal oxide layer) formed between them. In some embodiments, the interface layer may completely cover the surface of the ferroelectric layer facing the channel layer. The quality of such an interface layer may have many defects and affect device performance, for example, V th Offset and lower durability. Oxygen in the interface layer can be absorbed by a deoxygenation layer 88 disposed between the ferroelectric layer 90 (e.g., a metal oxide layer) and each conductor 72 (e.g., a metal layer). The deoxygenation layer 88 can absorb oxygen in the interface layer through a "direct removal mechanism" or a "remote removal mechanism," which will be described in detail below, see [link to relevant documentation]. Figure 30C and Figure 30D Therefore, it is possible to realize memory devices without interface layers and improve the quality of channel surfaces on oxide semiconductors.

[0025] In some embodiments, the deoxidizing layer 88 may cover the sidewalls of the conductor 72. In some such embodiments, the deoxidizing layer 88 may include discrete segments that are perpendicularly separated from each other by the dielectric layer 52. In some embodiments, the discrete segments are disposed along the opposite sidewalls of the respective conductors 72. In some embodiments, the ferroelectric layer 90 may extend continuously and perpendicularly beyond the upper and lower surfaces of one or more discrete segments of the deoxidizing layer, while the discrete segments of the deoxidizing layer 88 may extend laterally beyond the opposite sides of one or more of the conductive posts 106 and 108.

[0026] In such an embodiment, in order to perform a write operation on memory cell 202, a write voltage is applied to the portion of ferroelectric layer 90 corresponding to memory cell 202. In some embodiments, the write voltage is applied, for example, by applying an appropriate voltage to the corresponding wire 72 (e.g., word line) and the corresponding conductive post 106 / 108 (e.g., bit line / source line). In such an embodiment, wire 72 is configured to serve as a gate electrode layer. By applying a write voltage to this portion of ferroelectric layer 90, the polarization direction of the region of ferroelectric layer 90 can be changed. As a result, the corresponding threshold voltage of the corresponding memory cell 202 can also be switched from a low threshold voltage to a high threshold voltage and vice versa, and a digital value can be stored in memory cell 202. Because wire 72 intersects with conductive posts 106 and 108, a single memory cell 202 can be selected for the write operation.

[0027] In such an embodiment, to perform a read operation on memory cell 202, a read voltage (a voltage between a low threshold voltage and a high threshold voltage) is applied to the corresponding conductor 72 (e.g., a word line). Depending on the polarization direction of the corresponding region of the ferroelectric layer 90, memory cell 202 may or may not be conductive. As a result, conductive post 106 may or may not discharge through conductive post 108 (e.g., a source line coupled to ground), and the digital value stored in memory cell 202 can be determined. Because conductor 72 intersects conductive posts 106 and 108, a single memory cell 202 can be selected for the read operation.

[0028] Figure 1A A reference cross-section of the ferroelectric memory device 200 used in the following figures is also shown. Cross-section B-B' is along the longitudinal axis of conductor 72 and in a direction, for example, parallel to the current flow direction of memory cell 202. Cross-section C-C' is perpendicular to cross-section B-B' and extends through dielectric materials 98A / 98B and insulating pillar 102. Cross-section D-D' is perpendicular to cross-section B-B' and extends through dielectric materials 98A / 98B and conductive pillar 106. For clarity, the following figures refer to these reference cross-sections.

[0029] exist Figure 2The diagram provides a substrate 50. Substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., and can be doped (e.g., with p-type or n-type dopants) or undoped. Substrate 50 can be an integrated circuit die, such as a logic die, a memory die, an ASIC die, etc. Substrate 50 can be a complementary metal-oxide-semiconductor (CMOS) die, and can be referred to as under-array CMOS (CUA). Substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate that is typically silicon or a glass substrate. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium arsenide phosphide; or combinations thereof.

[0030] Figure 2 A circuit that can be formed over a substrate 50 is also shown. This circuit includes a transistor located on the top surface of the substrate 50. The transistor may include a gate dielectric layer 302 located above the top surface of the substrate 50 and a gate electrode 304 located above the gate dielectric layer 302. Source / drain regions 306 are disposed in the substrate 50 on opposite sides of the gate dielectric layer 302 and the gate electrode 304. A gate spacer 308 is formed along the sidewall of the gate dielectric layer 302 and separates the source / drain regions 306 from the gate electrode 304 by an appropriate lateral distance. The transistor may include a fin field-effect transistor (FinFET), a nanostructure (e.g., nanosheet, nanowire, all-around gate, etc.) FET (nanoFET), a planar FET, or a combination thereof, and may be formed by a gate-first process or a gate-latency process.

[0031] A first interlayer dielectric (ILD) 310 surrounds and isolates the source / drain region 306, the gate dielectric layer 302, and the gate electrode 304, and a second ILD 312 is located above the first ILD 310. A source / drain contact 314 extends through the second ILD 312 and the first ILD 310 and is electrically coupled to the source / drain region 306. A gate contact 316 extends through the second ILD 312 and is electrically coupled to the gate electrode 304. An interconnect structure 320 is located above the second ILD 312, the source / drain contact 314, and the gate contact 316. For example, the interconnect structure 320 includes one or more stacked dielectric layers 324 and conductive members 322 formed in the one or more dielectric layers 324. The interconnect structure 320 can be electrically connected to the gate contact 316 and the source / drain contact 314 to form a functional circuit. In some embodiments, the functional circuitry formed by the interconnect structure 320 may include logic circuitry, memory circuitry, sensing amplifiers, controllers, input / output circuitry, image sensor circuitry, or combinations thereof. Although Figure 2 Transistors formed above substrate 50 have been discussed, but other active devices (e.g., diodes, etc.) and / or passive devices (e.g., capacitors, resistors, etc.) may also be formed as part of the functional circuit.

[0032] exist Figure 3 In Figure 2 A multilayer stack 58 is formed above the structure. For simplicity and clarity, the substrate 50, transistors, ILDs, and interconnect structures 320 can be omitted from the following figures. Although the multilayer stack 58 is shown in contact with the dielectric layer 324 of the interconnect structure 320, any number of intermediate layers can be provided between the substrate 50 and the multilayer stack 58. For example, one or more interconnect layers can be provided between the substrate 50 and the multilayer stack 58, and the one or more interconnect layers include conductive components located in an insulating layer (e.g., a low-k dielectric layer). In some embodiments, the conductive components can be patterned for active devices and / or ferroelectric memory devices 200 on the substrate 50 (see...). Figure 1A and Figure 1B It provides power lines, ground lines, and / or signal lines. In some embodiments, one or more interconnect layers including conductive components located in an insulating layer (e.g., a low-k dielectric layer) may be provided above the multilayer stack 58.

[0033] exist Figure 3In this configuration, the multilayer stack 58 includes alternating layers of sacrificial layers 53A-53D (collectively referred to as sacrificial layers 53) and dielectric layers 52A-52E (collectively referred to as dielectric layers 52). The sacrificial layers 53 may be patterned and replaced in subsequent stages to define conductors 72 (e.g., word lines). The sacrificial layers 53 may include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, etc. The dielectric layers 52 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, etc. The sacrificial layers 53 and dielectric layers 52 comprise different materials with different etch selectivity. In some embodiments, the sacrificial layer 53 comprises silicon nitride, and the dielectric layer 52 comprises silicon oxide. Each of the sacrificial layers 53 and dielectric layers 52 may be formed using, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), etc.

[0034] Although Figure 3 A specific number of sacrificial layers 53 and dielectric layers 52 are shown, but other embodiments may include different numbers of sacrificial layers 53 and dielectric layers 52. Furthermore, although the multilayer stack 58 is shown having dielectric layers as the top and bottom layers, the invention is not limited thereto. In some embodiments, at least one of the top and bottom layers of the multilayer stack 58 is a sacrificial layer.

[0035] Figures 4 to 12 This is a view of an intermediate stage in the stepped structure of manufacturing a ferroelectric memory device 200 according to some embodiments. Along Figure 1A The reference cross section B-B' shown indicates Figures 4 to 12 .

[0036] exist Figure 4 In this process, photoresist 56 is formed over the multilayer stack 58. In some embodiments, the photoresist 56 is formed by spin coating and patterned by an acceptable photolithography technique. Patterning the photoresist 56 can expose the multilayer stack 58 in region 60 while masking the remainder of the multilayer stack 58. For example, the top layer of the multilayer stack 58 (e.g., dielectric layer 52E) can be exposed in region 60.

[0037] exist Figure 5In this process, photoresist 56 is used as a mask to etch exposed portions of the multilayer stack 58 in region 60. Etching can be any acceptable etching process, such as dry etching (e.g., reactive ion etching (RIE), neutral beam etching (NBE), etc.), wet etching, or combinations thereof. Etching can be anisotropic. Etching can remove portions of the dielectric layer 52E and sacrificial layer 53D in region 60 and define opening 61. Since the dielectric layer 52E and sacrificial layer 53D have different material compositions, the etchants used to remove the exposed portions of these layers can be different. In some embodiments, the sacrificial layer 53D acts as an etch stop layer when etching the dielectric layer 52E, and the dielectric layer 52D acts as an etch stop layer when etching the sacrificial layer 53D. As a result, portions of the dielectric layer 52E and sacrificial layer 53D can be selectively removed without removing the remaining layers of the multilayer stack 58, and opening 61 can extend to a desired depth. Optionally, after opening 61 reaches the desired depth, a time-mode etching process can be used to stop etching of opening 61. In the resulting structure, dielectric layer 52D is exposed in region 60.

[0038] exist Figure 6 In this process, the photoresist 56 is trimmed to expose additional portions of the multilayer stack 58. In some embodiments, the photoresist 56 is trimmed using an acceptable removal technique such as lateral etching. As a result of the trimming, the width of the photoresist 56 is reduced, and portions of the multilayer stack 58 in regions 60 and 62 can be exposed. For example, the top surface of dielectric layer 52D can be exposed in region 60, and the top surface of dielectric layer 52E can be exposed in region 62.

[0039] exist Figure 7 In this process, using photoresist 56 as a mask, portions of dielectric layer 52E, sacrificial layer 53D, dielectric layer 52D, and sacrificial layer 53C in regions 60 and 62 are removed by an acceptable etching process. The etching can be any acceptable etching process, such as dry etching (e.g., RIE, NBE, etc.), wet etching, or a combination thereof. The etching can be anisotropic. The etching can further extend the opening 61 into the multilayer stack 58. Because sacrificial layers 53D and 53C, and dielectric layers 52E and 52D, have different material compositions, the etchants used to remove the exposed portions of these layers can be different. In some embodiments, portions of dielectric layers 52E and 52D in regions 62 and 60 are removed by using photoresist 56 as a mask and using the underlying sacrificial layers 53D and 53C as etch stop layers. Subsequently, the exposed portions of sacrificial layers 53D and 53C in regions 62 and 60 are removed by using photoresist 56 as a mask and using the underlying dielectric layers 52D and 52C as etch stop layers. In the resulting structure, dielectric layer 52C is exposed in region 60, and dielectric layer 52D is exposed in region 62.

[0040] exist Figure 8 In this process, the photoresist 56 is trimmed to expose additional portions of the multilayer stack 58. In some embodiments, the photoresist 56 is trimmed using an acceptable removal technique such as lateral etching. As a result of trimming, the width of the photoresist 56 is reduced, and portions of the multilayer stack 58 in regions 60, 62, and 64 can be exposed. For example, the top surface of dielectric layer 52C can be exposed in region 60; the surface of dielectric layer 52C can be exposed in region 60; the top surface of dielectric layer 52D can be exposed in region 62; and the top surface of dielectric layer 52E can be exposed in region 64.

[0041] exist Figure 9 In this process, photoresist 56 is used as a mask to remove portions of dielectric layers 52E, 52D, and 52C and sacrificial layers 53D, 53C, and 53B in regions 60, 62, and 64 using an acceptable etching process. The etching can be any acceptable etching process, such as dry etching (e.g., RIE, NBE, etc.), wet etching, or combinations thereof. The etching can be anisotropic. The etching can further extend the opening 61 into the multilayer stack 58. Because dielectric layers 52C-52E and sacrificial layers 53B-53D have different material compositions, the etchants used to remove the exposed portions of these layers can be different. In some embodiments, portions of dielectric layers 52E, 52D, and 52C in regions 64, 62, and 60 are removed by using photoresist 56 as a mask and using the underlying sacrificial layers 53D, 53C, and 53B as etch stop layers. Subsequently, the exposed portions of sacrificial layers 53D, 53C, and 53B in regions 64, 62, and 60 are removed by using photoresist 56 as a mask and the underlying dielectric layers 52D, 52C, and 52B as etch stop layers. In the resulting structure, dielectric layer 52B is exposed in region 60; dielectric layer 52C is exposed in region 62; and dielectric layer 52D is exposed in region 64.

[0042] exist Figure 10 In this process, the photoresist 56 is trimmed to expose additional portions of the multilayer stack 58. In some embodiments, the photoresist 56 is trimmed using an acceptable removal technique such as lateral etching. As a result of trimming, the width of the photoresist 56 is reduced, and portions of the multilayer stack 58 in regions 60, 62, 64, and 66 can be exposed. For example, the top surface of dielectric layer 52B can be exposed in region 60; the top surface of dielectric layer 52C can be exposed in region 62; and the top surface of dielectric layer 52D can be exposed in region 64; and the top surface of dielectric layer 52E can be exposed in region 66.

[0043] exist Figure 11In this process, using photoresist 56 as a mask, portions of dielectric layers 52E, 52D, 52C, and 52B in regions 60, 62, 64, and 66 are removed by an acceptable etching process. The etching can be any acceptable etching process, such as dry etching (e.g., RIE, NBE, etc.), wet etching, or combinations thereof. The etching can be anisotropic. The etching can further extend the opening 61 into the multilayer stack 58. In some embodiments, portions of dielectric layers 52E, 52D, 52C, and 52B in regions 66, 64, 62, and 60 are removed by using photoresist 56 as a mask and using the underlying sacrificial layers 53D, 53C, 53B, and 53A as etch stop layers. In the resulting structure, sacrificial layer 53A is exposed in region 60; sacrificial layer 53B is exposed in region 62; sacrificial layer 53C is exposed in region 64; and sacrificial layer 53D is exposed in region 66. The photoresist 56 can then be removed using an acceptable ashing or wet stripping process.

[0044] exist Figure 12 In this configuration, an intermetallic dielectric (IMD) 70 is deposited over a multilayer stack 58. The IMD 70 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, PECVD, flowable CVD (FCVD), etc. The dielectric material can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. In some embodiments, the IMD 70 can include oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), combinations thereof, etc. Other dielectric materials formed by any acceptable process can be used. The IMD 70 extends along the sidewalls of sacrificial layers 53B-53D and the sidewalls of dielectric layers 52B-52E. Furthermore, the IMD 70 can contact the top surfaces of the sacrificial layers 53A-53D and the dielectric layer 52E.

[0045] Subsequently, a removal process is applied to IMD 70 to remove excess dielectric material above the multilayer stack 58. In some embodiments, the removal process may be a planarization process, such as chemical mechanical polishing (CMP), etching, or a combination thereof. The planarization process exposes the multilayer stack 58 such that, after the planarization process is completed, the top surfaces of the multilayer stack 58 and IMD 70 are flush.

[0046] like Figure 12 As shown, this forms an intermediate stepped structure. The intermediate stepped structure comprises alternating layers of sacrificial layer 53 and dielectric layer 52. Subsequently, sacrificial layer 53 is replaced by conductive wire 72, which will... Figure 16A and Figure 16BDetailed description is provided below. The lower conductor 72 is longer and extends laterally beyond the upper conductor 72, and the width of each conductor 72 increases in the direction toward the substrate 50 (see [link]). Figure 1A ).

[0047] Figures 13 to 16B This is a view showing an intermediate stage in the manufacturing of the memory region of a ferroelectric memory device 200 according to some embodiments. Figures 13 to 16B In this process, a patterned multilayer stack 58 is used to form trenches 86 through the multilayer stack 58, and the sacrificial layer 53 is replaced with a conductive material to define a conductor 72. The conductor 72 may correspond to word lines in the ferroelectric memory device 200, and the conductor 72 may also provide gate electrodes for the resulting memory cells of the ferroelectric memory device 200. Along... Figure 1A The reference section C-C' shown indicates Figure 13 , Figure 14 , Figure 15B and Figure 16B . Figure 15A and Figure 16A It is shown in a partial 3D diagram.

[0048] exist Figure 13 In this configuration, a photoresist pattern 82 and a hard mask pattern 80 are formed above the multilayer stack 58. In some embodiments, a hard mask layer and a photoresist layer are sequentially formed above the multilayer stack 58. The hard mask layer may include materials such as silicon nitride and silicon oxynitride that can be deposited by CVD, PVD, ALD, PECVD, etc. For example, the photoresist layer may be formed by spin coating.

[0049] Subsequently, a photoresist layer is patterned to form a photoresist pattern 82 and a trench 86 between the photoresist patterns 82. For example, the photoresist is patterned using an acceptable photolithography technique. Then, the pattern of the photoresist pattern 82 is transferred to a hard mask layer to form a hard mask pattern 80 by using an acceptable etching process, such as by dry etching (e.g., RIE, NBE, etc.), wet etching, or a combination thereof. The etching can be anisotropic. Thus, a trench 86 extending through the hard mask layer is formed. Subsequently, the photoresist pattern 82 can optionally be removed by an ashing process, for example.

[0050] exist Figures 14 to 15BIn this process, the pattern of the hard mask pattern 80 is transferred to the multilayer stack 58 using one or more acceptable etching processes, such as dry etching (e.g., RIE, NBE, etc.), wet etching, or combinations thereof. The etching process can be anisotropic. Thus, trenches 86 extend through the bulk multilayer stack 58 and thus define strip sacrificial layers 53 and strip dielectric layers 52. In some embodiments, trenches 86 extend through a bulk step structure and thus define a strip step structure. The hard mask pattern 80 can then be removed by acceptable processes such as wet etching, dry etching, planarization, or combinations thereof.

[0051] exist Figures 16A to 16B In this embodiment, sacrificial layers 53A-53D (collectively referred to as sacrificial layers 53) are replaced by conductive lines 72A-72D (collectively referred to as conductive lines 72). In some embodiments, sacrificial layers 53 are removed by a process such as wet etching, dry etching, or an acceptable combination of both. Thereafter, conductive lines 72 are filled into the spaces between adjacent dielectric layers 52. In some embodiments, each conductive line 72 is made of a single material. For example, conductive lines 72 comprise metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), molybdenum nitride, zirconium nitride, hafnium nitride, etc. In other embodiments, each conductive line 72 comprises a different material. For example, each conductive line 72 comprises two pads (e.g., Ti, TiN, Ta, TaN, etc.) and a metal layer (e.g., W, Ru, Co, Cu, Al, Ni, Au, Ag, etc.) between the pads, with one of the pads located between the metal layer and an adjacent dielectric layer. In some embodiments, conductive material is formed in horizontal openings between adjacent dielectric layers 52 on the sidewalls of the multilayer stack 58 and fills trench 86. The conductive material can be formed by acceptable deposition processes such as CVD, PVD, ALD, PECVD, etc. The conductive material in the trench 86 is then removed by an etch-back process. An acceptable etch-back process can be performed to remove excess material from the sidewalls of the dielectric layers 52 and the bottom surface of the trench 86. Acceptable etch-back processes include dry etching (e.g., RIE, NBE, etc.), wet etching, etc., or combinations thereof. Acceptable etch-back processes can be anisotropic.

[0052] In some embodiments, after the replacement process, the sacrificial layer 53 of the strip-step structure is subsequently replaced by the conductor 72 (see...). Figure 1A ).

[0053] Figures 17A to 19B This illustrates the formation of a deoxygenation layer 88 on the sidewall of the conductor 72 of the multilayer stack 58. Figure 17A , Figure 18A and Figure 19A Presented as a partial 3D view. Figure 17B , Figure 18B and Figure 19B In the middle, along Figure 1A The line C-C' provides a cross-sectional view.

[0054] exist Figure 17A and Figure 17B In this process, the conductors 72 of the multilayer stack 58 are recessed, forming a groove 87 between two adjacent dielectric layers 52. The groove 87 connects to (e.g., spatially communicates with) a corresponding trench 86. Specifically, the ends of the conductors 72 are recessed by about 1-10 nm relative to the ends of the dielectric layers 52 exposed by the trench 86. In some embodiments, the conductors 72 of the multilayer stack 58 are trimmed using an acceptable removal technique such as lateral etching. Etching may include dry etching (e.g., RIE, NBE, etc.), wet etching, or combinations thereof. Etching may be anisotropic. In some embodiments, the recessing process includes an etching gas comprising CF4, O2, Ar, or combinations thereof, a gas flow rate of about 100 to 1000 sccm, a power of 50 to 500 W, and a chamber pressure of about 0.1 to 700 Torr. After the recessing process, the multilayer stack 58 has curved sidewalls. Specifically, the ends of the dielectric layers 52 protrude from the ends of the remaining conductors 72.

[0055] exist Figure 18A and Figure 19B In this process, an oxygen-removing layer 88 is formed within each groove 87. Here, the oxygen-removing layer of the present invention is configured to prevent the formation of an undesirable interface layer between the oxide semiconductor channel layer and the ferroelectric layer. In some examples, the oxygen-removing layer of the present invention is also referred to as an "oxygen-absorbing layer," "oxygen-trapping layer," or "oxygen-absorbing layer." The oxygen-removing layer 88 can absorb oxygen from the undesirable interface layer and thus mitigate the undesirable oxygen in the undesirable interface layer through a "direct removal mechanism" or a "remote removal mechanism," which will be described in detail below, see [link to relevant documentation]. Figure 30C and Figure 30D In some embodiments, in a direct scavenging mechanism, the deoxygenation layer 88 comprises Hf, La, Al, or combinations thereof. In other embodiments, in a remote scavenging mechanism, the deoxygenation layer 88 comprises TiSiN (TSN), TiAl, Ti, or combinations thereof.

[0056] In some embodiments, the deoxidizing layer 88 is conformally and continuously formed on the top and sidewalls of the multilayer stack 58. Specifically, the deoxidizing layer 88 is conformally deposited in trenches 86 along the sidewalls of the conductor 72 and the dielectric layer 52, and fills grooves 87 along the top surface of the dielectric layer 52E and the bottom surface of the trenches 86. In some embodiments, the method of forming the deoxidizing layer 88 includes performing appropriate deposition techniques such as CVD, PVD, ALD, PECVD, etc.

[0057] In some embodiments, the deoxygenation layer 88 has a thickness of about 1-10 nm. Other thickness ranges (e.g., greater than 10 nm) may be suitable. In some embodiments, the deoxygenation layer 88 is a single layer. In alternative embodiments, the deoxygenation layer 88 has a multilayer structure. For example, the deoxygenation layer 88 includes an inner deoxygenation layer (e.g., Hf, La, Al) in contact with the corresponding wire 72 and an outer deoxygenation layer (e.g., TiSiN, TiAl, Ti) located outside the inner deoxygenation layer. The multilayer structure can remove oxygen in different ways (e.g., by removing oxygen directly into the deoxygenation layer 88 and by removing it indirectly into adjacent layers), thereby increasing oxygen removal.

[0058] exist Figure 19A and Figure 19B In this process, an etch-back process is performed on the continuous deoxidizing layer 88. An acceptable etch-back process can be performed to remove excess material from the sidewalls of the dielectric layer 52 and / or the bottom surface of the trench 86. Acceptable etch-back processes include dry etching (e.g., RIE, NBE, etc.), wet etching, or combinations thereof. The etching can be anisotropic. In some embodiments, the etch-back process includes an etching gas comprising CF4, O2, Ar, or combinations thereof, a gas flow rate of about 100 to 1000 sccm, a power of 50 to 500 W, and a chamber pressure of about 0.1 to 700 Torr.

[0059] After the etch-back process Figure 18B Continuous deoxygenation layer in Figure 19B The structure is divided into multiple individual or discrete deoxygenation layers 88. Each individual deoxygenation layer 88 is embedded in a groove 87. In some embodiments, the individual deoxygenation layers 88 are referred to as discontinuous deoxygenation layers, and portions of the deoxygenation layers are embedded in the grooves 87. In some embodiments, such as... Figure 19B As shown in the enlarged view at the upper left, the sidewalls of each deoxygenation layer 88a are substantially flush with the sidewalls of the adjacent dielectric layer 52. In some embodiments, such as in Figure 19B As shown in the enlarged view at the upper right, the sidewalls of each deoxygenation layer 88b are slightly recessed from the sidewalls of the adjacent dielectric layer 52 by a non-zero distance d. This non-zero distance d is, for example, in the range of about 1-5 nm. In some additional embodiments (not shown), the deoxygenation layer 88 may have a greater thickness along the top and bottom surfaces of the respective individual deoxygenation layer 88 (e.g., along the surface of the individual deoxygenation layer 88 in contact with the dielectric layer 52) than it would be perpendicular to the area between the top and bottom surfaces.

[0060] Figures 20A to 25B The trench 86 is shown to be formed and patterned for memory cell 202 (see Figure 1A ) the channel area. Figure 20A , Figure 21A and Figure 25A Presented as a partial 3D view. Figure 20B , Figure 21B , Figure 22 , Figure 23 , Figure 24 and Figure 25B In the middle, along Figure 1A The line C-C' provides a cross-sectional view.

[0061] In some embodiments, Figure 18B The deoxygenation layer is also formed on the IMD 70 and along the sidewalls of each strip-shaped stepped structure, and the deoxygenation layer in the stepped area is also subjected to... Figure 19B The etch-back process. Therefore, as Figure 1A As shown, each conductive step of the stepped structure includes a conductor 72 and two deoxygenation layers 88 located next to the conductor 72.

[0062] exist Figures 20A to 23 In the trench 86, the ferroelectric layer 90, the channel layer 92, and the dielectric material 98A are deposited.

[0063] exist Figure 20A and Figure 20B In this configuration, the ferroelectric layer 90 may be conformally deposited in the trench 86 along the sidewalls of the dielectric layer 52 and the deoxidation layer 88, along the top surface of the dielectric layer 52E, and along the bottom surface of the trench 86. In some embodiments, the ferroelectric layer 90 may also be deposited on the IMD 70 and along the sidewalls of each step of the stepped structure in the stepped region. The ferroelectric layer 90 may include a material capable of switching between two different polarization directions by applying an appropriate voltage difference on the ferroelectric layer 90. For example, the ferroelectric layer 90 may include a high-k dielectric material, such as a hafnium (Hf)-based dielectric material. In some embodiments, the ferroelectric layer 90 may include hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, etc.

[0064] In some embodiments, the ferroelectric layer 90 may include barium titanate (BaTiO3), lead titanate (PbTiO3), lead zirconium oxide (PbZrO3), lithium niobate (LiNbO3), sodium niobate (NaNbO3), potassium niobate (KNbO3), potassium tantalate (KTaO3), bismuth scandium oxide (BiScO3), bismuth iron oxide (BiFeO3), and hafnium erbium oxide (HfO3). 1-x Er x O), hafnium oxide (Hf) 1-x La x O), hafnium oxide (Hf) 1- x Y x O), hafnium gadolinium oxide (Hf) 1-x Gd x O), hafnium oxide (Hf) 1-x Al x O), hafnium oxide (Hf) 1-xZr x O, HZO), hafnium titanium oxide (Hf) 1-x Ti x O), hafnium tantalum oxide (Hf) 1-x Ta x Specifically, the ferroelectric layer 90 includes HfZrO, HfAlO, HfLaO, HfCeO, HfO, HfGdO, HfSiO, or combinations thereof. In some embodiments, the method of forming the ferroelectric layer 90 includes performing appropriate deposition techniques, such as CVD, PECVD, metal oxide chemical vapor deposition (MOCVD), ALD, RPALD, PEALD, MBD, etc.

[0065] In some embodiments, the ferroelectric layer 90 has a thickness of about 1-20 nm, such as 5-10 nm. Other thickness ranges (e.g., greater than 20 nm or 5-15 nm) may be suitable. In some embodiments, the thickness ratio of the ferroelectric layer 90 to the deoxidizing layer 88 is in the range of about 1:1 to 20:1. In some embodiments, the ferroelectric layer 90 is formed in a completely amorphous state. In an alternative embodiment, the ferroelectric layer 90 is formed in a partially crystalline state; that is, the ferroelectric layer 90 is formed in a mixed crystalline-amorphous state and has a certain degree of structural order. In yet another alternative embodiment, the ferroelectric layer 90 is formed in a completely crystalline state. In some embodiments, the ferroelectric layer 90 is a monolayer. In an alternative embodiment, the ferroelectric layer 90 has a multilayer structure.

[0066] In some embodiments, such as Figure 20B As shown in the enlarged view at the upper left, the ferroelectric layer 90a is conformally formed on the sidewalls of the multilayer stack 58, thus having a substantially smooth sidewall profile. In some embodiments, the opposing surfaces of the ferroelectric layer 90a near and away from the deoxidizing layer 88a are substantially straight, as... Figure 20B The enlarged view in the upper left corner is shown below.

[0067] In some embodiments, such as Figure 20B As shown in the enlarged view at the upper right, the ferroelectric layer 90b is conformally formed on the sidewalls of the multilayer stack 58, thus having an uneven and wavy sidewall profile. In some embodiments, the opposing surfaces of the ferroelectric layer 90b near and away from the deoxidizing layer 88b are uneven and wavy, as shown in the image above. Figure 20B The enlarged view in the upper right corner is shown. In some embodiments (not shown), the surface of the ferroelectric layer 90b near the deoxidizing layer 88b is wavy, while the surface of the ferroelectric layer 90b away from the deoxidizing layer 88b is substantially straight.

[0068] Subsequently, an annealing process 91 is performed on the ferroelectric layer 90. In an environment containing N2, H2, Ar, or combinations thereof, the annealing process 91 is performed at a temperature ranging from about 350°C to about 450°C (e.g., 400°C) to achieve the desired lattice structure in the ferroelectric layer 90. In some embodiments, after annealing process 91, the ferroelectric layer 90 transforms from an amorphous state to a partially or fully crystalline state. In an alternative embodiment, after annealing, the ferroelectric layer 90 transforms from a partially crystalline state to a fully crystalline state.

[0069] exist Figure 21A and Figure 21B In this configuration, a channel layer 92 is conformally deposited in a trench 86 above the ferroelectric layer 90. The channel layer 92 includes features suitable for providing memory cells 202 (see [link to documentation]). Figure 1A The material provided for the channel region. For example, the channel layer 92 includes an oxide semiconductor (OS), such as zinc oxide (ZnO), indium tungsten oxide (InWO), indium gallium zinc oxide (InGaZnO, IGZO), indium zinc oxide (InZnO), indium tin oxide (ITO), combinations thereof, etc. The channel layer 92 can be deposited by CVD, PVD, ALD, PECVD, etc. The channel layer 92 can extend along the sidewalls and bottom surface of the trench 86 above the ferroelectric layer 90. In some embodiments, the channel layer 92 can also be deposited on the IMD 70 and along the sidewalls of each step of the stepped structure in the stepped region.

[0070] After depositing the channel layer 92, an annealing process 93 is performed on the channel layer 92. In some embodiments, the annealing process 93 is performed in an oxygen-associated environment at a temperature of about 300°C to about 450°C to activate the charge carriers of the channel layer 92.

[0071] exist Figure 22 In this structure, dielectric material 98A is deposited in a trench 86 above the channel layer 92. In some embodiments, dielectric material 98A includes silicon oxide, silicon nitride, silicon oxynitride, etc., which can be deposited by CVD, PVD, ALD, PECVD, etc. Dielectric material 98A may extend above the channel layer 92 along the sidewalls and bottom surface of the trench 86. In some embodiments, dielectric material 98A is optional and may be omitted as needed.

[0072] exist Figure 23 In this process, the dielectric material 98A and the bottom of the channel layer 92 are removed in the trench 86. The removal process includes acceptable etching processes such as dry etching (e.g., RIE, NBE, etc.), wet etching, or combinations thereof. The etching can be anisotropic. In some embodiments, the top of the dielectric material 98A and the channel layer 92 are removed from the multilayer stack 58. In some embodiments, the removal process includes a combination of photolithography and etching.

[0073] Therefore, the remaining dielectric material 98A and channel layer 92 can expose a portion of the ferroelectric layer 90 on the bottom surface of the trench 86. Consequently, portions of the channel layer 92 on opposite sidewalls of the trench 86 can be separated from each other, which improves the memory array 200 (see...). Figure 1A Isolation between memory cells 202.

[0074] exist Figure 24 In this process, dielectric material 98B is deposited to completely fill trench 86. Dielectric material 98B can be formed from one or more materials and can be formed using the same or similar processes as dielectric material 98A. In some embodiments, dielectric material 98A and dielectric material 98B can be formed using the same process (e.g., a single process). In other embodiments, dielectric material 98A and dielectric material 98B can be formed using separate processes. In some embodiments, dielectric material 98B and dielectric material 98A comprise different materials. In some embodiments, dielectric material 98B and dielectric material 98A comprise one or more of the same materials.

[0075] exist Figure 25A and Figure 25B In this process, a removal process is applied to the dielectric material 98A / 98B, the channel layer 92, and the ferroelectric layer 90 to remove excess material above the multilayer stack 58. In some embodiments, planarization processes such as CMP, etch-back processes, or combinations thereof may be utilized. The planarization process exposes the multilayer stack 58 such that, after the planarization process is completed, the top surfaces of the multilayer stack 58 (e.g., dielectric layer 52E), the ferroelectric layer 90, the channel layer 92, the dielectric material 98A / 98B, and the IMD 70 are flush.

[0076] Figures 26A to 29B An intermediate stage in fabricating conductive posts 106 and 108 (e.g., source / drain posts) in ferroelectric memory device 200 is shown. Conductive posts 106 and 108 can extend in a direction perpendicular to wire 72, such that individual cells of ferroelectric memory device 200 can be selected for read and write operations. Figure 26A , Figure 27A , Figure 28A and Figure 29A Presented as a partial 3D view. Figure 26B and Figure 27B In the middle, along Figure 1A The line C-C' provides a cross-sectional view. Figure 28B and Figure 29B In the middle, along Figure 1A The line D-D' provides a cross-sectional view.

[0077] exist Figure 26A and Figure 26BIn the process, trenches 100 are patterned through channel layer 92 and dielectric material 98A / 98B. For example, trenches 100 can be patterned by a combination of photolithography and etching. Trenches 100 can be disposed between opposing sidewalls of ferroelectric layer 90, and trenches 100 can physically separate adjacent stacks of memory cells in ferroelectric memory device 200 (see...). Figure 1A ).

[0078] exist Figure 27A and Figure 27B In this structure, isolation pillars 102 are formed in trench 100. In some embodiments, an isolation layer is deposited over a multilayer stack 58 filling the trench 100. The isolation layer may include, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., which can be deposited by CVD, PVD, ALD, PECVD, etc. The isolation layer may extend over the channel layer 92 along the sidewalls and bottom surface of the trench 100. After deposition, a planarization process (e.g., CMP, etch-back, etc.) may be performed to remove excess portions of the isolation layer. In the resulting structure, the top surfaces of the multilayer stack 58 (e.g., dielectric layer 52E), ferroelectric layer 90, channel layer 92, and isolation pillars 102 may be substantially flush (e.g., within process variations). In some embodiments, the materials of the dielectric materials 98A / 98B and the isolation pillars 102 may be selected such that they can be selectively etched relative to each other. For example, in some embodiments, the dielectric materials 98A / 98B comprise oxides, and the isolation pillars 102 comprise nitrides. In some embodiments, the dielectric material 98A / 98B comprises a nitride, and the insulating pillar 102 comprises an oxide. Other materials are also possible.

[0079] exist Figure 28A and Figure 28B In this context, trenches 104 are defined for subsequently formed conductive pillars 106 and 108. For example, trenches 104 are formed by patterning dielectric materials 98A / 98B through a combination of photolithography and etching. In some embodiments, such as… Figure 28A As shown, photoresist 118 is formed over the multilayer stack 58, dielectric materials 98A / 98B, isolation pillars 102, channel layer 92, and ferroelectric layer 90. In some embodiments, the photoresist 118 is patterned using an acceptable photolithography technique to define openings 120. Each opening 120 may expose two separate regions of the corresponding isolation pillar 102 and the dielectric material 98A / 98B adjacent to the isolation pillar 102. In this way, each opening 120 may define a pattern of conductive pillars 106 separated by the isolation pillars 102 and adjacent conductive pillars 108.

[0080] Subsequently, the portion of dielectric material 98A / 98B exposed by opening 120 can be removed by an acceptable etching process, such as dry etching (e.g., RIE, NBE, etc.), wet etching, or a combination thereof. The etching can be anisotropic. An etchant that etches dielectric material 98A / 98B without significantly etching the isolation pillars 102 can be used. As a result, even though opening 120 exposes the isolation pillars 102, the isolation pillars 102 are not significantly removed. The pattern of trench 104 can correspond to conductive pillars 106 and 108 (see...). Figure 29A and Figure 29B After patterning the trenches 104, the photoresist 118 can be removed, for example, by ashing.

[0081] exist Figure 29A and Figure 29B In this process, trench 104 is filled with a conductive material to form conductive pillars 106 and 108. The conductive material may include copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, and combinations thereof, which can be formed using methods such as CVD, ALD, PVD, PECVD, etc. After depositing the conductive material, planarization (e.g., CMP, etch-back, etc.) may be performed to remove excess portions of the conductive material, thereby forming conductive pillars 106 and 108. In the resulting structure, the top surfaces of the multilayer stack 58 (e.g., dielectric layer 52E), ferroelectric layer 90, channel layer 92, conductive pillars 106, and conductive pillars 108 may be substantially flush (e.g., within process variations). In some embodiments, conductive pillar 106 corresponds to and is electrically connected to bit lines in the memory array, and conductive pillar 108 corresponds to and is electrically connected to source lines in the ferroelectric memory device 200.

[0082] Therefore, as Figure 29A As shown, stacked memory cells 202 can be formed in a ferroelectric memory device 200. Each memory cell 202 includes a gate electrode (e.g., a portion of a corresponding wire 72), a gate dielectric (e.g., a portion of a corresponding ferroelectric layer 90), a channel region (e.g., a portion of a corresponding channel layer 92), and source / drain pillars (e.g., portions of corresponding conductive pillars 106 and 108). Isolation pillars 102 isolate adjacent memory cells 202 in the same column and at the same vertical level. The memory cells 202 can be configured as an array of vertically stacked rows and columns.

[0083] exist Figure 30A , Figure 30B , Figure 30G , Figure 30H and Figure 30IIn this configuration, IMD 74 is formed on the top surface of the multilayer stack 58 (e.g., dielectric layer 52E), ferroelectric layer 90, channel layer 92, conductive pillar 106, conductive pillar 108, and IMD 70. Conductive contacts 110, 112, and 114 are formed on the conductor 72, conductive pillar 106, and conductive pillar 108, respectively. Figure 30A A perspective view of the ferroelectric memory device 200 is shown. Figure 30B It shows along Figure 1A A cross-sectional view of the device with line D-D'. Figures 30C to 30F It shows Figure 30B Different magnified views of different parts of region R1. Figure 30G A top view of the ferroelectric memory device 200 is shown. Figure 30H It shows along Figure 30A A cross-sectional view of line E-E'. Figure 30I It shows along Figure 1A A cross-sectional view of the device along line B-B'.

[0084] IMD 74 can be formed of a dielectric material and can be deposited by any suitable method such as CVD, PECVD, flowable CVD (FCVD), etc. The dielectric material can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. In some embodiments, IMD 74 can include oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), combinations thereof, etc. Other dielectric materials formed by any acceptable process can be used. Subsequently, a removal process is applied to IMD 74 to remove excess dielectric material above the multilayer stack 58. In some embodiments, the removal process can be a planarization process, such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, etc.

[0085] In some embodiments, the stepped shape of the conductors 72 may provide a surface on each conductor 72 for the conductive contact 110 to rest on. In some embodiments, forming the conductive contact 110 may include, for example, patterning openings in the IMD 74 and IMD 70 using a combination of photolithography and etching to expose portions of the conductors 72. Pads (not shown), such as diffusion barrier layers, adhesive layers, etc., and conductive material are formed in the openings. Pads may include titanium, titanium nitride, tantalum, tantalum nitride, etc. Conductive materials may include copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the IMD 74. The remaining pads and conductive material form the conductive contact 110 in the openings.

[0086] For example Figure 30AAs shown in the perspective view, conductive contacts 112 and 114 can also be fabricated on conductive posts 106 and 108, respectively. Conductive contacts 112, 114, and 110 can be electrically connected to wires 116A, 116B, and 116C, respectively, which connect the memory array to the underlying / overhead circuitry (e.g., control circuitry) and / or signal lines, power lines, and ground lines in the semiconductor die. For example, as... Figure 30H As shown, conductive contact 110 may extend through IMD 74 and IMD 70 to electrically connect wire 116C to wire 72 and an underlying active device located on the substrate. Other conductive contacts or vias may be formed through IMD 74 to electrically connect wires 116A and 116B to an underlying active device located on the substrate. Other conductive contacts or vias may extend through the ferroelectric memory device 200, such as through isolation pillar 102 and ferroelectric layer 90, and such conductive contacts or vias may be electrically coupled to underlying conductive components, such as conductive component 322 of interconnect structure 320. In alternative embodiments, in addition to or replacing interconnect structure 320, wiring and / or power lines to and from the memory array may be provided by interconnect structures formed above the ferroelectric memory device 200. Thus, the ferroelectric memory device 200 can be completed.

[0087] Figures 30C to 30D It shows Figure 30B A magnified view of region R1 is provided to illustrate the relationship between the deoxygenation layer 88 and adjacent elements.

[0088] In some embodiments, such as Figure 30C As shown, when the deoxygenating layer 88 comprises Hf, La, Al, or combinations thereof, the deoxygenating layer 88 can absorb oxygen from the undesirable interface layer through a "direct scavenging mechanism." Specifically, in the high-k ferroelectric layer 90, the metal element M in the deoxygenating layer 88 combines / reacts with the oxygen element O at the interface between the ferroelectric layer 90 and the channel layer 92. In other words, the oxygen at the interface between the ferroelectric layer 90 and the channel layer 92 can be absorbed by the high-k layer and thus eliminated (direct scavenging).

[0089] In other embodiments, such as Figure 30D As shown, when the deoxygenation layer 88 comprises TiSiN (TSN), TiAl, Ti, or a combination thereof, the deoxygenation layer 88 can absorb oxygen from undesirable interface layers via a "remote scavenging mechanism." Specifically, the oxygen element O at the interface between the ferroelectric layer 90 and the channel layer 92 is removed by the deoxygenation layer 88 covering the conductive wire 72. In other words, the oxygen at the interface between the ferroelectric layer 90 and the channel layer 92 can be absorbed and thus removed (remote scavenging) by the covered or doped gate electrode. In some examples, the deoxygenation layer 88 is considered to be part of the corresponding gate electrode (e.g., conductive wire 72).

[0090] In some embodiments, such as Figure 30C and Figure 30D As shown, the thickness TH1 of the deoxidizing layer 88 is about 1 to 10 nm, the thickness TH2 of the ferroelectric layer 90 is about 1 to 20 nm, and the thickness TH3 of the channel layer 92 is about 1 to 20 nm. In some embodiments, the thickness ratio of the ferroelectric layer 90 to each of the plurality of deoxidizing layers 88 is about 1:1 to 20:1. In some embodiments, the thickness ratio of the channel layer 92 to each of the plurality of deoxidizing layers 88 is about 1:1 to about 20:1.

[0091] From another perspective, the deoxidizing layer 88 of the present invention can be selected based on the Gibb free energy changes between the two metal elements originating from the channel layer 92 and the deoxidizing layer 88, respectively. For example, the Gibb free energy of In₂O₃ (approximately -117 kcal / gfw), Ga₂O₃ (approximately -145 kcal / gfw), or ZnO (approximately -145 kcal / gfw) at 400°C is greater than that of Al₂O₃ (approximately -234 kcal / gfw) or HfO (approximately -238 kcal / gfw) at 400°C. The Gibb free energy represents the degree of simultaneous oxidation of metal elements based on thermodynamics. The smaller the Gibb free energy, the easier it is for simultaneous oxidation of the metal elements to occur. For example, the Gibbs free energy of In2O3 at 400 °C (approximately -117 kcal / gfw) is greater than that of HfO at 400 °C (approximately -238 kcal / gfw). Therefore, the Gibbs free energy between HfO and In2O3 is negative, indicating that Hf is a suitable scavenging element for removing oxide elements from the channel layer 92.

[0092] exist Figure 30C and Figure 30D In one embodiment, the memory cells of the memory device are formed as a device without an interface layer. However, the invention is not limited thereto. In other embodiments, such as Figure 30E and Figure 30F As shown, at least one memory cell of the memory device is formed having a very thin interface layer IL between the channel layer 92 and the ferroelectric layer 90. The interface layer IL of the memory device with a deoxygenation layer of the present invention is much thinner than the conventional interface layer of a conventional device without a deoxygenation layer. In some embodiments, the interface layer IL has a thickness TH4 in the range of about 1 to 5 nm.

[0093] Although Figures 1A to 30I The embodiments shown depict a specific pattern of conductive posts 106 and 108, but other configurations are also possible. For example, in these embodiments, conductive posts 106 and 108 have an interlaced pattern. However, in other embodiments, conductive posts 106 and 108 in the same row of the array are aligned with each other, as shown in the examples. Figure 32The ferroelectric memory device 200A is shown.

[0094] Figure 31 A method for forming a ferroelectric memory device according to some embodiments is illustrated. While the method is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the shown order or actions. Therefore, in some embodiments, actions may be performed in a different order than shown, and / or actions may be performed simultaneously. Furthermore, in some embodiments, the shown actions or events may be subdivided into multiple actions or events, which may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some shown actions or events may be omitted, and other actions or events not shown may be included.

[0095] At action 400, a multilayer stack is formed on the substrate. The multilayer stack includes multiple dielectric layers and multiple conductive layers stacked alternately, and has trenches penetrating the multiple dielectric layers and multiple conductive layers. Figures 13 to 16B Variations of some embodiments corresponding to action 400 are shown.

[0096] At action 402, multiple conductive layers exposed by the sidewalls of the trench are recessed, thus forming multiple grooves, and one of the multiple grooves is formed between two adjacent dielectric layers. In some embodiments, recessing the dielectric layers includes performing an etching process, such as a lateral etching process. Figures 17A to 17B Variations of some embodiments corresponding to action 402 are shown.

[0097] At action 404, multiple deoxidizing layers are formed in multiple grooves. In some embodiments, the method of forming the deoxidizing layers includes conformally and continuously forming a deoxidizing material on the sidewalls of the multilayer stack, and the deoxidizing material filling the grooves. Subsequently, an etch-back process is performed on the deoxidizing material to remove portions of the deoxidizing material on the sidewalls of the dielectric layers of the multilayer stack. Figures 18A to 19B Variations of some embodiments corresponding to action 404 are shown.

[0098] At action 406, a ferroelectric layer is formed on the sidewall of the trench, wherein the ferroelectric layer covers the sidewall of the deoxygenation layer and the sidewall of the dielectric layer. Figures 20A to 20B Variations of some embodiments corresponding to action 406 are shown.

[0099] At action 408, a first annealing process is performed on the ferroelectric layer. In some embodiments, the temperature range of the first annealing process is from about 350°C to about 450°C (e.g., 400°C) to achieve the desired lattice structure of the deoxygenated layer. Figures 20A to 20B Variations of some embodiments corresponding to action 408 are shown.

[0100] At action 410, a channel layer is formed on the ferroelectric layer. Figures 21A to 21B Variations of some embodiments corresponding to action 408 are shown.

[0101] At step 412, a second annealing process is performed on the channel layer. Figures 21A to 21B Variations of some embodiments corresponding to action 410 are shown.

[0102] Figure 33 A simplified perspective view of a ferroelectric memory device according to some embodiments is shown. Ferroelectric memory device 200' and... Figure 1A The ferroelectric memory device 200 is similar, but the deoxidation layer 88 is removed from the stepped region. Specifically, when in Figures 17A to 29A When defining the memory cell 202 during the manufacturing process, the stepped structure remains a volumetric stepped structure, instead of the aforementioned strip-shaped multi-stepped structure. Specifically, two volumetric stepped structures are positioned on both sides of the memory cell region. After defining the memory cell 202, the two volumetric stepped structures are divided into multiple strip-shaped stepped structures located on both sides of the memory cell region.

[0103] The following is for reference. Figures 1A to 33 The structure of the ferroelectric memory device of the present invention is described.

[0104] In some embodiments, the ferroelectric memory device 200 / 200A / 200' includes a multilayer stack 58, a channel layer 92, a ferroelectric layer 90, and a deoxygenation layer 88. The multilayer stack 58 is disposed above a substrate 50 and includes a plurality of conductive layers (e.g., wires 72) and a plurality of dielectric layers 52 stacked alternately. The channel layer 92 extends through the plurality of conductive layers (e.g., wires 72) and the plurality of dielectric layers 52. The ferroelectric layer 90 is disposed between the channel layer 92 and each of the plurality of conductive layers (e.g., wires) and the plurality of dielectric layers 52. The deoxygenation layer 88 includes Hf, La, Al, TiSiN, TiAl, Ti, or combinations thereof. One deoxygenation layer 88 is disposed between the ferroelectric layer 90 and each of the plurality of conductive layers (e.g., wires 72). Each deoxygenation layer 88 may be a single layer or have a multilayer structure. In some embodiments, the plurality of deoxygenation layers 88 have a thickness of about 1-10 nm.

[0105] In some embodiments, such as Figure 20B As shown, the end of the conductive layer (e.g., wire 72) is recessed from the end of the dielectric layer 52. In some embodiments, the sidewalls of the deoxidizing layer 88 are substantially flush with the sidewalls of the dielectric layer 52. In some embodiments, the sidewalls of the deoxidizing layer 88 are concave or convex relative to the sidewalls of the dielectric layer 52.

[0106] In some embodiments, the ferroelectric memory device does not have an undesirable interface layer between the channel layer 92 and the ferroelectric layer 90, such as Figure 30C and Figure 30D As shown. In some embodiments, the interface between the channel layer 92 and the ferroelectric layer 90 does not contain oxygen atoms.

[0107] In other embodiments, the ferroelectric memory device further includes a very thin interface layer IL located between the channel layer 92 and the ferroelectric layer 90, and the oxygen content of the interface layer IL is greater than that of the channel layer 92. In some embodiments, the channel layer 92 comprises ZnO, InWO, InGaZnO, InZnO, ITO, or combinations thereof, and the interface layer IL comprises oxygen-rich ZnO, InWO, InGaZnO, InZnO, ITO, or combinations thereof. In some embodiments, the interface layer IL has a thickness of about 1-5 nm. The interface layer IL is so thin that it does not affect the performance of the ferroelectric memory device.

[0108] In some embodiments, the ferroelectric memory device 200 / 200A / 200' includes a multilayer stack 58, a plurality of dielectric pillars (e.g., dielectric materials 98A / 98B), an oxide semiconductor layer (e.g., a channel layer 92), a ferroelectric layer 90, and a plurality of deoxygenation layers 88. The multilayer stack 58 is disposed on a substrate 50 and includes a plurality of alternately stacked gate electrode layers (e.g., wires 72) and a plurality of dielectric layers 52. The plurality of dielectric pillars (e.g., dielectric materials 98A / 98B) are disposed on the substrate 50 and penetrate the multilayer stack 58. The oxide semiconductor layer (e.g., the channel layer 92) includes a first metal element and is disposed between the multilayer stack 58 and each dielectric pillar (e.g., dielectric material 98A / 98B). The ferroelectric layer 90 is disposed between the oxide semiconductor layer (e.g., the channel layer 92) and the multilayer stack 58. The plurality of deoxidizing layers 88 include a second metal element, and one of the plurality of deoxidizing layers 88 is disposed between the ferroelectric layer 90 and each of the plurality of gate electrode layers (e.g., wires 72). In some embodiments, the Gibbs free energy of the oxide of the second metal element is less than the Gibbs free energy of the oxide of the first metal element.

[0109] In some embodiments, the second metal element includes Hf, La, Al, Ti, Al, or combinations thereof. In some embodiments, the deoxidizing layer 88 includes Hf, La, Al, TiSiN, TiAl, Ti, or combinations thereof.

[0110] In some embodiments, the first metal element includes Zn, In, W, Ga, Sn, or combinations thereof. In some embodiments, the oxide semiconductor layer (e.g., channel layer 92) includes ZnO, InWO, InGaZnO, InZnO, ITO, or combinations thereof.

[0111] In some embodiments, the oxygen density of the plurality of deoxygenation layers 88 further includes oxygen element. In some embodiments, the oxygen density in the plurality of deoxygenation layers 88 increases toward the ferroelectric layer 90. In some examples, the deoxygenation layer 88 is referred to as an oxide deoxygenation layer 88.

[0112] In some embodiments, the ferroelectric memory device 200 / 200A / 200' includes a multilayer stack 58, a plurality of dielectric pillars (e.g., dielectric materials 98A / 98B), a channel layer 92, and a ferroelectric layer 90. The multilayer stack 58 is disposed on a substrate 50 and includes a plurality of alternately stacked gate electrode layers (e.g., wires 72) and a plurality of dielectric layers 52. The dielectric pillars (e.g., dielectric materials 98A / 98B) are disposed on the substrate 50 and penetrate the multilayer stack 58. The channel layer 92 is disposed between the multilayer stack 58 and each dielectric pillar (e.g., dielectric material 98A / 98B). The ferroelectric layer 90 is disposed between the channel layer 92 and the multilayer stack 58, wherein the ferroelectric layer 90 contacts each gate electrode layer (e.g., wire 72) but is spaced apart from each dielectric layer 52.

[0113] In some embodiments, the ferroelectric memory device 200 / 200A / 200' further includes a plurality of conductive pillars 106 and 108 disposed on the substrate 50 and penetrating the multilayer stack 58. Each of the plurality of dielectric pillars (e.g., dielectric material 98A / 98B) has two conductive pillars 106 and 108 disposed at its two ends.

[0114] In some embodiments, the dielectric pillars (e.g., dielectric materials 98A / 98B) are arranged in a staggered manner. Specifically, adjacent columns of dielectric pillars are arranged in a staggered manner, such as... Figure 29A As shown. However, the invention is not limited thereto. In some embodiments, the dielectric pillars (e.g., dielectric materials 98A / 98B) in adjacent columns are arranged in a regular array and aligned with each other, as shown. Figure 32 As shown.

[0115] In some embodiments of the present invention, oxygen at the interface between the channel layer (e.g., an oxide semiconductor layer) and the ferroelectric layer (e.g., a metal oxide layer) can be absorbed and eliminated accordingly by an oxygen-removing layer disposed between the ferroelectric layer and each conductive gate. Therefore, an interface-free memory device can be realized, and the channel quality at the oxide semiconductor surface can be improved.

[0116] In the above embodiments, the ferroelectric memory device is formed using a "pre-stepping process," wherein a step structure is formed before the memory cells are formed. However, the invention is not limited thereto. In other embodiments, the ferroelectric memory device can be formed using a "post-stepping process," wherein the step structure is formed after the memory cells are formed.

[0117] In the above embodiments, gate electrodes (e.g., word lines) are formed by depositing a sacrificial dielectric layer and then replacing the sacrificial dielectric layer with a conductive layer. However, the invention is not limited thereto. In other embodiments, gate electrodes (e.g., word lines) can be formed in a first stage without the replacement step.

[0118] The present invention considers many variations of the above examples. It should be understood that different embodiments may have different advantages, and no particular advantage is required in all embodiments.

[0119] According to some embodiments of the present invention, a ferroelectric memory device includes a multilayer stack, a channel layer, a ferroelectric layer, and a deoxidizing layer. The multilayer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates the plurality of conductive layers and the plurality of dielectric layers. The ferroelectric layer is disposed between the channel layer and each of the plurality of conductive layers and the plurality of dielectric layers. The deoxidizing layer includes Hf, La, Al, TiSiN, TiAl, Ti, or combinations thereof, and one of the deoxidizing layers is disposed between the ferroelectric layer and each of the plurality of conductive layers.

[0120] In the aforementioned ferroelectric memory device, the end of the conductive layer is recessed from the end of the dielectric layer.

[0121] In the aforementioned ferroelectric memory device, the sidewall of the deoxidizing layer is flush with the sidewall of the dielectric layer.

[0122] In the aforementioned ferroelectric memory device, the plurality of deoxygenation layers are respectively disposed between adjacent dielectric layers in the plurality of dielectric layers.

[0123] In the aforementioned ferroelectric memory device, the channel layer comprises zinc oxide (ZnO), indium tungsten oxide (InWO), indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium tin oxide (ITO), or combinations thereof.

[0124] The ferroelectric memory device described above also includes an interface layer located between the channel layer and the ferroelectric layer, and the oxygen content of the interface layer is greater than the oxygen content of the channel layer.

[0125] The ferroelectric memory device described above further includes an interface layer located between the channel layer and the ferroelectric layer, wherein the oxygen content of the interface layer is greater than the oxygen content of the channel layer, and the ferroelectric layer extends continuously and vertically beyond two or more of the plurality of deoxygenation layers.

[0126] According to an optional embodiment of the present invention, a ferroelectric memory device includes a multilayer stack, a plurality of dielectric pillars, an oxide semiconductor layer, a ferroelectric layer, and a plurality of deoxygenation layers. The multilayer stack is disposed on a substrate and includes a plurality of alternately stacked gate electrode layers and a plurality of dielectric layers. The plurality of dielectric pillars are disposed on the substrate and penetrate the multilayer stack. The oxide semiconductor layer includes a first metal element and is disposed between the multilayer stack and each dielectric pillar. The ferroelectric layer is disposed between the oxide semiconductor layer and the multilayer stack. The plurality of deoxygenation layers include a second metal element, and one of the plurality of deoxygenation layers is disposed between the ferroelectric layer and each of the plurality of gate electrode layers. In some embodiments, the Gibbs free energy of the oxide of the second metal element is less than the Gibbs free energy of the oxide of the first metal element.

[0127] In the aforementioned ferroelectric memory device, the ferroelectric layer extends continuously beyond two or more of the plurality of deoxygenation layers.

[0128] The ferroelectric memory device further includes: a second plurality of dielectric pillars disposed on the substrate and penetrating the multilayer stack; a second oxide semiconductor layer disposed between the multilayer stack and each of the second plurality of dielectric pillars; a second ferroelectric layer disposed between the second oxide semiconductor layer and the multilayer stack; and a second plurality of deoxygenation layers disposed between the second ferroelectric layer and each of the plurality of gate electrode layers.

[0129] In the aforementioned ferroelectric memory device, the plurality of deoxygenation layers also include oxygen.

[0130] In the aforementioned ferroelectric memory device, the oxygen density in the plurality of deoxygenation layers increases toward the ferroelectric layer.

[0131] In the aforementioned ferroelectric memory device, the Gibbs free energy of the oxide of the second metal element is less than the Gibbs free energy of the oxide of the first metal element.

[0132] In the aforementioned ferroelectric memory device, the plurality of dielectric layers vertically separate adjacent deoxygenation layers among the plurality of deoxygenation layers.

[0133] In the aforementioned ferroelectric memory device, the interface between the oxide semiconductor layer and the ferroelectric layer is free of oxygen atoms.

[0134] The ferroelectric memory device further includes: a plurality of conductive pillars disposed on the substrate and penetrating the multilayer stack, wherein each of the plurality of dielectric pillars has two conductive pillars disposed along opposite sides of the dielectric pillars.

[0135] According to another optional embodiment of the present invention, a method for forming a ferroelectric memory device includes the following operations: Forming a multilayer stack on a substrate. The multilayer stack includes a plurality of alternately stacked dielectric layers and a plurality of conductive layers, and has trenches penetrating the plurality of dielectric layers and the plurality of conductive layers. Recessing the conductive layers exposed by the sidewalls of the trenches, such that a groove is formed between two adjacent dielectric layers. Forming a plurality of deoxygenating layers within the plurality of grooves. Forming a ferroelectric layer on the sidewalls of the trenches, wherein the ferroelectric layer covers the sidewalls of the deoxygenating layers and the sidewalls of the dielectric layers. Forming a channel layer on the ferroelectric layer.

[0136] In the above method, recessing the conductive layer includes performing a lateral etching process.

[0137] In the above method, forming the plurality of deoxidizing layers includes: conformally and continuously forming a deoxidizing material on the sidewalls of the multilayer stack, wherein the deoxidizing material fills the plurality of grooves; and performing an etch-back process on the deoxidizing material.

[0138] In the above method, the etch-back process removes the deoxygenating material from the sidewalls of the plurality of dielectric layers, while leaving the deoxygenating material along the sidewalls of the plurality of conductive layers.

[0139] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A ferroelectric memory device, comprising: A multilayer stack, disposed on a substrate and comprising multiple conductive layers and multiple dielectric layers stacked alternately; The channel layer penetrates the plurality of conductive layers and the plurality of dielectric layers; A ferroelectric layer is disposed between the channel layer and the plurality of conductive layers and the plurality of dielectric layers; as well as Multiple deoxidizing layers are disposed along the sidewalls of multiple conductive layers, wherein the multiple deoxidizing layers laterally separate the ferroelectric layer from the multiple conductive layers, wherein one of the multiple deoxidizing layers physically contacts one of the multiple conductive layers, the gate electrode includes the conductive layer and the deoxidizing layer, the ferroelectric layer directly contacts the sidewalls of the multiple dielectric layers and directly contacts the sidewalls of the multiple deoxidizing layers away from the multiple conductive layers, wherein the ferroelectric layer has a first side surface facing the channel layer and a second side surface opposite to the first side surface, the second side surface facing the multiple deoxidizing layers and the multiple dielectric layers, and the surface of the deoxidizing layer facing the ferroelectric layer is flush with the surface of the dielectric layer facing the ferroelectric layer.

2. The ferroelectric memory device according to claim 1, wherein, The end of the conductive layer is recessed from the end of the dielectric layer.

3. The ferroelectric memory device according to claim 1, wherein, The sidewalls of the deoxidizing layer are flush with the sidewalls of the dielectric layer. Each of the plurality of deoxidizing layers includes an inner deoxidizing layer that contacts a corresponding one of the plurality of conductive layers and an outer deoxidizing layer located outside the inner deoxidizing layer. The inner deoxidizing layer and the outer deoxidizing layer are made of different materials.

4. The ferroelectric memory device according to claim 1, wherein, The plurality of deoxygenation layers are respectively disposed between adjacent dielectric layers in the plurality of dielectric layers.

5. The ferroelectric memory device according to claim 1, wherein, The channel layer includes zinc oxide (ZnO), indium tungsten oxide (InWO), indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium tin oxide (ITO), or combinations thereof.

6. The ferroelectric memory device according to claim 1 further includes an interface layer located between the channel layer and the ferroelectric layer, wherein the oxygen content of the interface layer is greater than the oxygen content of the channel layer.

7. The ferroelectric memory device according to claim 6, wherein, The ferroelectric layer extends continuously and vertically beyond two or more of the plurality of deoxygenation layers.

8. A ferroelectric memory device, comprising: A multilayer stack, disposed on a substrate and comprising multiple gate electrode layers and multiple dielectric layers stacked alternately; Multiple dielectric pillars are disposed on the substrate and penetrate the multilayer stack; An oxide semiconductor layer, including a first metal element, is disposed between the multilayer stack and each of the dielectric pillars; A ferroelectric layer is disposed between the oxide semiconductor layer and the multilayer stack; as well as The plurality of gate electrode layers include a plurality of conductive layers and a plurality of deoxidizing layers. The plurality of deoxidizing layers include a second metal element, and one of the plurality of deoxidizing layers is disposed between the ferroelectric layer and each of the plurality of conductive layers. The plurality of deoxidizing layers are in physical contact with one of the plurality of conductive layers. The ferroelectric layer is in direct contact with the sidewall of the plurality of dielectric layers and is in direct contact with the sidewall of the plurality of deoxidizing layers opposite to the plurality of conductive layers. The ferroelectric layer has a first side surface facing the oxide semiconductor layer and a second side surface opposite to the first side surface. The second side surface faces the plurality of deoxygenated layers and the plurality of dielectric layers, and the surface of the deoxygenated layer facing the ferroelectric layer is flush with the surface of the dielectric layer facing the ferroelectric layer.

9. The ferroelectric memory device according to claim 8, wherein, The ferroelectric layer extends continuously beyond two or more of the plurality of deoxygenation layers.

10. The ferroelectric memory device according to claim 8, further comprising: A second plurality of dielectric pillars are disposed on the substrate and penetrate the multilayer stack; A second oxide semiconductor layer is disposed between the multilayer stack and each of the second plurality of dielectric pillars; A second ferroelectric layer is disposed between the second oxide semiconductor layer and the multilayer stack; as well as The second plurality of deoxygenation layers are disposed between the second ferroelectric layer and each of the plurality of conductive layers.

11. The ferroelectric memory device according to claim 8, wherein, The multiple deoxygenation layers also include oxygen.

12. The ferroelectric memory device according to claim 8, wherein, The oxygen density in the plurality of deoxygenated layers increases toward the ferroelectric layer.

13. The ferroelectric memory device according to claim 8, wherein, The Gibbs free energy of the oxide of the second metal element is less than that of the oxide of the first metal element.

14. The ferroelectric memory device according to claim 8, wherein, The plurality of dielectric layers vertically separate adjacent deoxygenation layers among the plurality of deoxygenation layers.

15. The ferroelectric memory device according to claim 8, wherein, The interface between the oxide semiconductor layer and the ferroelectric layer contains no oxygen atoms.

16. The ferroelectric memory device according to claim 8, further comprising: A plurality of conductive pillars are disposed on the substrate and penetrate the multilayer stack, wherein each of the plurality of dielectric pillars has two conductive pillars disposed along opposite sides of the dielectric pillars.

17. A method for forming a ferroelectric memory device, comprising: A multilayer stack is formed on a substrate, wherein the multilayer stack includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately, and has trenches penetrating the plurality of dielectric layers and the plurality of conductive layers; The plurality of conductive layers exposed by the sidewalls of the trench are recessed, thus forming a plurality of grooves, one of which is formed between two adjacent dielectric layers; Multiple deoxygenation layers are formed in the multiple grooves, wherein one of the multiple deoxygenation layers is in physical contact with one of the multiple conductive layers, and the gate electrode includes the conductive layer and the deoxygenation layer; A ferroelectric layer is formed on the sidewall of the trench, wherein the ferroelectric layer covers the sidewall of the deoxidizing layer and the sidewall of the dielectric layer, the ferroelectric layer directly contacts the sidewall of the plurality of dielectric layers, and directly contacts the sidewall of the plurality of deoxidizing layers opposite to the plurality of conductive layers; and A channel layer is formed on the ferroelectric layer; The plurality of deoxidizing layers laterally separate the ferroelectric layer from the plurality of conductive layers. The ferroelectric layer has a first side surface facing the channel layer and a second side surface opposite to the first side surface. The second side surface faces the plurality of deoxidizing layers and the plurality of dielectric layers. The surface of the deoxidizing layer facing the ferroelectric layer is flush with the surface of the dielectric layer facing the ferroelectric layer.

18. The method according to claim 17, wherein, Making the conductive layer recessed includes performing a lateral etching process.

19. The method of claim 17, wherein, Forming the plurality of deoxygenation layers includes: A deoxidizing material is conformally and continuously formed on the sidewalls of the multilayer stack, wherein the deoxidizing material fills the plurality of grooves; and The oxygen-removing material is subjected to a back-etching process.

20. The method according to claim 19, wherein, The etch-back process removes the deoxygenating material from the sidewalls of the plurality of dielectric layers, while leaving the deoxygenating material along the sidewalls of the plurality of conductive layers.

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