Semiconductor structure comprising a photodetector and method of forming a photodetector

Abstract

The photovoltaic unit includes a germanium-containing well embedded in a monocrystalline silicon substrate and extending to a proximal horizontal surface of the substrate, wherein the germanium-containing well comprises greater than 50% atomic percentage of germanium. A silicon-containing overlay structure is located on the top surface of the germanium-containing well and comprises greater than 42% atomic percentage of silicon. This silicon-containing overlay structure prevents oxidation of the germanium-containing well. A photovoltaic junction can be formed within or across a trench by implanting dopants of a first conductivity type and a second conductivity type. Embodiments of this application also relate to semiconductor structures including photodetectors and methods for forming photodetectors.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures including photodetectors and methods for forming photodetectors. Background Technology

[0002] Semiconductor image sensors can be used to sense electromagnetic radiation, such as visible light, infrared radiation, and / or ultraviolet radiation. Complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) and charge-coupled device (CCD) sensors can be used in a variety of applications, such as digital cameras or cameras integrated into mobile devices. These devices utilize pixel arrays (which may include photodiodes and transistors) to detect radiation by utilizing the photogeneration of electron-hole pairs. Summary of the Invention

[0003] Some embodiments of this application provide a semiconductor structure including a photodetector, wherein the photodetector includes: a germanium-containing well embedded in a single-crystal silicon substrate and extending to a proximal horizontal surface of the single-crystal silicon substrate, wherein the germanium-containing well includes more than 50% atomic percentage of germanium; and a silicon-containing overlay structure located on the top surface of the germanium-containing well and including more than 42% atomic percentage of silicon atoms, wherein: the germanium-containing well includes a photovoltaic junction, the photovoltaic junction including a first conductivity type germanium-containing region and a second conductivity type germanium-containing region.

[0004] Other embodiments of this application provide a semiconductor structure including a photodetector comprising: a germanium-containing well embedded in a monocrystalline silicon substrate and extending to a proximal horizontal surface of the monocrystalline silicon substrate, wherein the germanium-containing well comprises greater than 50% atomic percentage of germanium, and wherein the germanium-containing well comprises a photovoltaic junction; and a silicon-containing overlay structure located on the top surface of the germanium-containing well and comprising greater than 42% atomic percentage of silicon atoms, wherein: a portion of the monocrystalline silicon substrate surrounding the germanium-containing well comprises a silicon region of a first conductivity type; and the germanium-containing well comprises a germanium-containing region of a second conductivity type.

[0005] Further embodiments of this application provide a method for forming a photodetector, comprising: depositing and patterning a dielectric mask layer over a single-crystal silicon substrate; etching trenches in the single-crystal silicon substrate through openings in the dielectric mask layer; forming a germanium-containing well within the trenches, wherein the germanium-containing well comprises more than 50% atomic percentage of germanium; forming a silicon-containing overlay structure on the top surface of the germanium-containing well; and forming a photovoltaic junction within or across the trenches by implanting dopants of a first conductivity type and a second conductivity type. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1A This is a plan view of a first configuration of the pixel array of an image sensor according to an embodiment of the present invention.

[0008] Figure 1B This is a plan view of a second configuration of the pixel array of an image sensor according to another embodiment of the present invention.

[0009] Figures 2A to 2K This is a sequential vertical cross-sectional view of a first exemplary structure during the formation of pixels in an image sensor according to a first embodiment of the present invention.

[0010] Figure 2L This is a vertical cross-sectional view of an optional configuration of a first exemplary structure according to a first embodiment of the present invention.

[0011] Figure 3A and Figure 3B This is a vertical cross-sectional view of the configuration of a second exemplary structure including pixels of an image sensor according to a second embodiment of the present invention.

[0012] Figure 4A and Figure 4B This is a vertical cross-sectional view of the configuration of a third exemplary structure including pixels of an image sensor according to a second embodiment of the present invention.

[0013] Figures 5A to 5F This is a sequential vertical cross-sectional view of a fourth exemplary structure during the formation of pixels of an image sensor according to a fourth embodiment of the present invention.

[0014] Figures 6A to 6F This is a vertical cross-sectional view of an optional configuration of the fourth exemplary structure according to the fourth embodiment of the present invention.

[0015] Figures 7A to 7G This is a sequential vertical cross-sectional view of a fifth exemplary structure during the formation of pixels in an image sensor according to a fifth embodiment of the present invention.

[0016] Figure 7H This is a vertical cross-sectional view of an optional configuration of a fifth exemplary structure according to a fifth embodiment of the present invention.

[0017] Figure 8 This is a first process flow diagram illustrating an exemplary process sequence for forming an image sensor according to an embodiment of the present invention.

[0018] Figure 9 It shows the method used to form Figure 2K or Figure 2L The second process flow diagram shows an exemplary process sequence for the image sensor.

[0019] Figure 10 It shows the method used to form Figure 3A or Figure 3B The third process flow diagram is an exemplary process sequence for the image sensor shown.

[0020] Figure 11 It shows the method used to form Figure 4A or Figure 4B The fourth process flow diagram of the exemplary process sequence of the image sensor is shown.

[0021] Figure 12 It shows the method used to form Figure 5F and Figures 6A to 6F The fifth process flow diagram of the exemplary process sequence of the image sensor is shown.

[0022] Figure 13 It shows the method used to form Figure 7G and Figure 7H The sixth process flow diagram of the exemplary process sequence of the image sensor is shown. Detailed Implementation

[0023] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. It is assumed that elements having the same reference numerals have the same material composition.

[0024] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0025] Generally, the structures and methods of this invention can be used to fabricate germanium-based photodetectors and / or image sensors incorporating arrays of germanium-based photodetectors. Specifically, the structures and methods of this invention can be used to fabricate germanium-based photodetectors (i.e., silicon-germanium (GiS) photodetectors) formed on silicon substrates and / or image sensors including arrays of GiS photodetectors. Such photodetectors or image sensors can provide high quantum efficiency for a variety of sensing applications in the near-infrared (NIR) spectral range.

[0026] Typically, silicon-based photodetectors exhibit low sensitivity in the infrared range due to their low quantum efficiency. They also offer poor optical performance in wavelengths greater than 1,000 nm due to their low photon absorption. Germanium offers higher photon absorption in the infrared wavelength range, but fabricating complementary metal-oxide-semiconductor (CMOS) devices on germanium substrates presents numerous challenges.

[0027] According to an aspect of the invention, a germanium-based photodetector can be formed within a silicon substrate to provide the use of standard CMOS manufacturing processes on a silicon substrate. According to another aspect of the invention, the germanium-containing material portion comprising germanium or a silicon-germanium alloy can be passivated by the walls surrounding the trench around the silicon substrate and by a silicon-containing overlay structure comprising silicon nitride or crystalline silicon.

[0028] Embodiments of the present invention provide a controllable height of the germanium-containing material portion relative to the top surface of the silicon substrate. For example, a dielectric material layer may be formed to have a controllable thickness, and chemical mechanical planarization may be used to form the germanium-containing material portion having a top surface at the height of the top surface of the dielectric mask layer. The germanium-containing material portion may be formed as a crystalline phase. The germanium-containing material portion may be a single crystal epitaxially aligned with a single-crystal silicon material in the silicon substrate. In some embodiments, a selective epitaxial growth process may be used to maintain the epitaxial alignment between the germanium-containing material portion of the silicon substrate and the single-crystal silicon material.

[0029] The silicon-containing capping structure may include silicon. In one embodiment, the silicon material of the silicon-containing capping structure may be formed as a single-crystal silicon material to enhance its effectiveness as a passivation structure (i.e., as a diffusion barrier structure). Optionally, the silicon-containing capping structure may include silicon nitride.

[0030] Figure 1A This is a plan view of a first configuration of the pixel array of an image sensor according to an embodiment of the present invention. Figure 1B This is a plan view of a second configuration of the pixel array of an image sensor according to another embodiment of the present invention. (Reference) Figure 1A and Figure 1BThe corresponding plan view shows a first configuration and a second configuration of the array 1000 of pixels 900 of the image sensor. The image sensor may be a back-illuminated (BSI) image sensor device. However, for simplicity, embodiments of the invention are discussed as if used in a front-illuminated (FSI) image sensor.

[0031] To generate an image from an image sensor, each pixel 900 represents a minimum unit area. The region comprising the array 1000 of pixels 900 is referred to herein as a pixel array region. The pixels 900 within the pixel array region can be arranged in rows and columns. For example, the pixel array region may comprise M rows and N columns, where M and N are between 1 and 2. 16 (such as 2) 8 Up to 2 14 The rows of pixel 900 can be consecutively numbered integers from 1 to M, and the columns of pixel 900 can be consecutively numbered integers from 1 to N. Pixel P ij It refers to pixel 900 in the i-th row and j-th column.

[0032] Each pixel 900 includes at least one photodetector configured to detect radiation within a given wavelength range. Each pixel 900 may include multiple photodetectors configured to detect radiation within a corresponding wavelength range, and these multiple photodetectors may differ from each of the multiple photodetectors. In one embodiment, each pixel 900 may include multiple sub-pixels, each sub-pixel including a photodetector and a corresponding combination of electronic circuitry configured to detect radiation incident on the photodetector. For example, pixel 900 may include a sub-pixel configured to detect radiation in a red wavelength range (such as the range of 635 nm to 700 nm), a sub-pixel configured to detect radiation in a green wavelength range (such as the range of 520 nm to 560 nm), and a sub-pixel configured to detect radiation in a blue wavelength range (such as the range of 450 nm to 490 nm). These sub-pixels are referred to as red sub-pixels, green sub-pixels, and blue sub-pixels, respectively.

[0033] Typically, pixel 900 generates information about the incident radiation within a unit detection area. Subpixels generate information about the intensity of the incident radiation detected within a specific wavelength range within the unit detection area. Monochrome pixel 900 may consist of only a single subpixel. Pixel 900 configured to detect the spectral distribution of incident radiation includes multiple subpixels having at least two different detection wavelength ranges. The photodetector in the pixel array area may include a photodiode, a complementary metal-oxide-semiconductor (CMOS) image sensor, a charge-coupled device (CCD) sensor, an active sensor, a passive sensor, other suitable sensors, or combinations thereof.

[0034] Subpixels within an image sensor can be formed using germanium-containing wells formed within a single-crystal silicon substrate, as described below. Although the various exemplary structures described below depict only a single subpixel region including a photodetector region comprising a single germanium-based photodetector and a sensing circuit region comprising sensing circuitry for the germanium-based photodetector, it should be understood that multiple instances of the subpixel region can be arranged to provide a two-dimensional array of subpixels for an image sensor. Furthermore, it should be understood that additional subpixels, such as subpixels including silicon-based photodetectors, can optionally be incorporated into the image sensor. Therefore, for each exemplary structure described below, examples of various exemplary structures are explicitly covered to provide an embodiment of an image sensor including a pixel array.

[0035] Figures 2A to 2K This is a sequential vertical cross-sectional view of a first exemplary structure during pixel formation of an image sensor according to a first embodiment of the present invention. (Reference) Figure 2A This diagram illustrates a first exemplary structure according to a first embodiment of the present invention. The first exemplary structure includes a semiconductor substrate 500, which includes a monocrystalline silicon substrate 10. The monocrystalline silicon substrate 10 may have a pair of principal horizontal surfaces. The principal horizontal surface located on the top side is referred to herein as the proximal horizontal surface 7. The principal horizontal surface located on the back side is referred to herein as the distal horizontal surface 17. The monocrystalline silicon substrate 10 may be monocrystalline and may have doping of a suitable conductivity type (which may be p-type or n-type). In one embodiment, the monocrystalline silicon substrate 10 may have doping of a first conductivity type and may include atomic concentrations between 1.0 × 10⁻⁶. 13 / cm 3 Up to 1.0×10 17 / cm 3 The first conductivity type of dopant within the range, although smaller and larger dopant concentrations can also be used.

[0036] A first exemplary structure includes: a photodetector region 510, in which a germanium-based photodetector will subsequently be formed; and a sensing circuit region 520, in which sensing circuitry for the germanium-based photodetector will subsequently be formed. In one embodiment, a mask ion implantation process can be performed to form various doped regions of varying depths. For example, a second conductivity type doped well 60 with doping of a second conductivity type can be formed by ion implantation. The second conductivity type doped well 60 can be formed as a closed region laterally surrounding the single-crystal silicon substrate 10. The second conductivity type is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, then the second conductivity type is n-type, and vice versa. The depth of the second conductivity type doped well 60 can be in the range of 1 micrometer to 2 micrometers, although smaller and larger depths can also be used. The second conductivity type doped well 60 can include an atomic concentration between 1.0 × 10⁻⁶. 15 / cm 3Up to 1.0×10 18 / cm 3 The second conductivity type of dopant is within the range, although smaller and larger dopant concentrations can also be used.

[0037] By performing a mask ion implantation process, a doped well contact region 68 with doping of the second conductivity type can be formed in the upper part of the doped well 60. The doped well contact region 68 can be heavily doped to reduce contact resistance. The doped well contact region 68 may include an atomic concentration between 1.0 × 10⁻⁶. 19 / cm 3 Up to 1.0×10 22 / cm 3 The second conductivity type of dopant is within the range, although smaller and larger dopant concentrations can also be used.

[0038] A first-doped photodiode contact region 28, having a first conductivity type of doping, can be formed below the near-horizontal surface 7 of the single-crystal silicon substrate 10 within a region surrounded by a doped well 60 of a second conductivity type. The first-doped photodiode contact region 28 can be heavily doped to reduce contact resistance. The first-doped photodiode contact region 28 may include an atomic concentration between 1.0 × 10⁻⁶. 19 / cm 3 Up to 1.0×10 22 / cm 3 The second conductivity type of dopant is within the range, although smaller and larger dopant concentrations can also be used.

[0039] refer to Figure 2B A dielectric mask layer 12 can be formed on the near-horizontal surface 7 of a single-crystal silicon substrate 10. The dielectric mask layer 12 comprises a dielectric material such as silicon oxide. Other suitable materials are within the scope of this disclosure. The dielectric mask layer 12 can be formed by depositing a silicon oxide layer or by thermally oxidizing a portion of the surface of the single-crystal silicon substrate 10. The thickness of the dielectric mask layer 12 can be in the range of 50 nm to 300 nm, such as in the range of 80 nm to 150 nm, although smaller and larger thicknesses are also possible.

[0040] A photoresist layer 67 may be applied over the dielectric mask layer 12. The photoresist layer 67 may be photolithographically patterned to form openings in a region laterally surrounded by doped wells 60 of the second conductivity type. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer 67 through the dielectric mask layer 12 to the upper portion of the single-crystal silicon substrate 10. A trench 69 may be formed in the upper portion of the single-crystal silicon substrate 10. The trench 69 is laterally surrounded by and spaced laterally inward from the doped wells 60 of the second conductivity type. The depth of the trench 69 may be greater than, equal to, or less than the depth of the doped wells 60 of the second conductivity type. In one embodiment, the depth of the trench 69 may be in the range of 0.5 micrometers to 10 micrometers, such as in the range of 1 micrometer to 6 micrometers, although smaller and larger depths may also be used. The lateral dimensions of the trench 69 may be in the range of 0.5 micrometers to 30 micrometers, such as in the range of 1 micrometer to 15 micrometers, although smaller and larger lateral dimensions may also be used. The lateral dimension of trench 69 may be the diameter or main axis of the horizontal cross-sectional shape of trench 69 in embodiments where trench 69 has a circular or elliptical horizontal cross-sectional shape, or the length of the side of the rectangle in embodiments where the horizontal cross-sectional shape of trench 69 is rectangular. The photoresist layer 67 may then be removed, for example, by ashing.

[0041] refer to Figure 2C A first conductivity type dopant can be implanted around the region of trench 69. The first conductivity type dopant is implanted at least in the region laterally surrounded by a second conductivity type doped well 60. A multi-angle ion implantation process can be performed to implant the first conductivity type dopant through the sidewalls of trench 69. Additionally, the first conductivity type dopant can be implanted into the surface portion of the single-crystal silicon substrate 10 located below the proximal horizontal surface 7 of the single-crystal silicon substrate 10. Furthermore, the first conductivity type dopant can be implanted into the horizontal portion of the single-crystal silicon substrate 10 located below the bottom surface of trench 69. A first conductivity type silicon region 21 can be formed within the single-crystal silicon substrate 10. The first conductivity type silicon region 21 is connected to a first doped photodiode contact region 28, which is a contact region for the first conductivity type silicon region 21. The lateral width of the first conductivity type silicon region 21 surrounding each sidewall of trench 69 can be in the range of 100 nm to 1,000 nm, although smaller and larger lateral dimensions are also possible. The thickness of the horizontal portion of the first conductivity type silicon region 21 below the bottom surface of the trench 69 can be in the range of 100 nm to 1,000 nm, although smaller and larger thicknesses can also be used.

[0042] refer to Figure 2DIn some embodiments, the silicon pad 32 may optionally be grown from the physically exposed surface of the first conductivity type silicon region 21, which is the surface of the trench 69. The silicon pad 32 can be grown via a selective silicon epitaxial growth process, which grows epitaxial silicon only from the physically exposed semiconductor surface and not from the dielectric surface. The silicon pad 32 may comprise epitaxially grown silicon, i.e., single-crystal silicon epitaxially aligned with the single-crystal silicon material of the single-crystal silicon substrate 10. The silicon pad 32 may be intrinsic or may have a low level of doping. For example, the atomic concentration of the dopant within the silicon pad 32 may be between 1.0 × 10⁻⁶. 13 / cm 3 Up to 1.0×10 16 / cm 3 Within the range, although smaller and larger dopant concentrations may also be used. In embodiments where silicon pad 32 is not intrinsic, the conductivity type of silicon pad 32 may be a first conductivity type or a second conductivity type. The thickness of silicon pad 32 may be in the range of 5 nm to 200 nm, such as in the range of 10 nm to 100 nm, although smaller and larger thicknesses may also be used. Silicon pad 32 (if present) may be used as a buffer layer between the subsequently deposited germanium-containing material and the first conductivity type silicon region 21.

[0043] refer to Figure 2E In embodiments including silicon pad 32, a germanium-containing material may be grown from the physically exposed surface of silicon pad 32; or in embodiments not including silicon pad 32, a germanium-containing material may be grown from the physically exposed surface of a first conductivity type silicon region 21. The germanium-containing material comprises germanium with an atomic percentage greater than 50%. In one embodiment, the germanium-containing material may comprise doped or undoped germanium such that the atomic percentage of germanium is at least 99% and it is substantially free of silicon. In another embodiment, the germanium-containing material may comprise a silicon-germanium alloy wherein the atomic percentage of germanium is greater than 50% and the atomic percentage of silicon is less than 50%, such as 5% to 30%. A germanium-containing material layer 30L may be formed from the deposited germanium-containing material.

[0044] The germanium-containing material layer 30L can be formed by a selective deposition process or a non-selective deposition process. A selective deposition process is a process of growing germanium-containing material from physically exposed semiconductor surfaces (such as the physically exposed surface of silicon pad 32 or the physically exposed surface of silicon region 21 of the first conductivity type). In this embodiment, germanium-containing reactants (such as germanane or digermanane) may flow simultaneously or alternately with the flow of etchant gases (such as hydrogen chloride) into a process chamber containing the first exemplary structure. Typically, the growth rate of semiconductor material (such as germanium-containing material) on semiconductor surfaces is higher than the growth rate on dielectric surfaces. The flow rate and deposition temperature can be controlled such that the net deposition rate (i.e., deposition rate minus etch rate) is positive on semiconductor surfaces and negative on dielectric surfaces during selective deposition processes. In this embodiment, the growth of germanium-containing material occurs only on semiconductor surfaces. A non-selective deposition process is a deposition process in which germanium-containing material is grown from all physically exposed surfaces. In this embodiment, the deposition process may use germanium-containing reactants without using etchant gases.

[0045] In one embodiment, the selective or non-selective deposition process used to deposit the germanium-containing material layer 30L can be an epitaxial deposition process, i.e., a deposition process that aligns the crystal structure of the deposited germanium-containing material with the crystal structure of the physically exposed surface of the underlying material portion. Therefore, a portion of the germanium-containing material layer 30L deposited in the trench 69 can be epitaxially aligned with the crystal structure of the silicon pad 32 (in embodiments including the silicon pad 32) and / or the crystal structure of the first conductivity type silicon region 21. In embodiments where a selective epitaxial deposition process is used to deposit the germanium-containing material layer 30L, the material of the germanium-containing material layer 30L is grown from the physically exposed surface of the silicon pad 32 or the first conductivity type silicon region 21. In such embodiments, the entire germanium-containing material layer 30L can be single-crystal and can be epitaxially aligned with the single-crystal silicon material of the single-crystal silicon substrate 8. In embodiments where a non-selective epitaxial deposition process is used to deposit the germanium-containing material layer 30L, the material of the germanium-containing material layer 30L is grown from the physically exposed surface of the silicon pad 32 (in embodiments including the silicon pad 32) or the first conductivity type silicon region 21, and from the physically exposed surface of the dielectric mask layer 12. In this embodiment, the portion of the germanium-containing material layer 30L grown only from the physically exposed surface of the silicon pad 32 (in embodiments including the silicon pad 32) or the first conductivity type silicon region 21 may be monocrystalline, and the portion of the germanium-containing material layer 30L grown from the physically exposed surface of the dielectric mask layer 12 may be polycrystalline.

[0046] Typically, an epitaxial deposition process can be performed to grow a single-crystal germanium-containing material within the trench 69. At least a portion of the germanium-containing material layer 30L grown within the trench 69 can be single-crystal and can be formed to be epitaxially aligned with the single-crystal silicon material of the single-crystal silicon substrate 10. In this embodiment, the entire portion of the germanium-containing material layer 30L located within the trench 69 can be single-crystal.

[0047] The germanium-containing material layer 30L can be intrinsic or have a low level of doping. For example, the atomic concentration of the dopant in the germanium-containing material layer 30L can be between 1.0 × 10⁻⁶. 13 / cm 3 Up to 1.0×10 18 / cm 3 Within the range, although smaller and larger dopant concentrations can also be used.

[0048] refer to Figure 2F Excess germanium-containing material can be removed from above a horizontal plane including the top surface of the dielectric mask layer 12. In one embodiment, a chemical mechanical planarization (CMP) process can be performed to remove the portion of the germanium-containing material layer 30L located above the horizontal plane including the top surface of the dielectric mask layer 12. The remaining portion of the germanium-containing material layer 30L located within the trench 69 comprises a germanium-containing portion, referred herein as a germanium-containing well 30. The top surface of the germanium-containing well 30 may be within the same horizontal plane as the top surface of the dielectric mask layer 12.

[0049] Although the invention has been described using an embodiment in which the germanium-containing trap 30 is formed as a single-crystal germanium-containing material portion, the germanium-containing trap 30 may be formed as a polycrystalline material portion or an amorphous material portion, but with reduced efficiency. Such variations are explicitly covered herein.

[0050] refer to Figure 2G The remaining portion of the germanium-containing material may be vertically recessed within an opening in the dielectric mask layer 12. Specifically, for example, the upper portion of the germanium-containing well 30 and the optional silicon pad 32 may be optionally vertically recessed by performing a recess etching process. In such embodiments, the vertical recess distance may be greater than, equal to, or less than the thickness of the dielectric mask layer 12. Regardless of the vertical recess distance, the germanium-containing well 30 does not contact the dielectric mask layer 12, and the material of the germanium-containing well 30 does not contact any oxygen-containing material (such as silicon oxide) of the dielectric mask layer 12. In embodiments where the silicon pad 32 is not used, the vertical recess distance may be greater than the thickness of the dielectric mask layer 12 to prevent direct contact between the germanium-containing well 30 and the dielectric mask layer 12.

[0051] refer to Figure 2HA silicon-containing capping material can be deposited on the physically exposed top surface of the germanium-containing well 30. In embodiments where a silicon pad 32 is present, the silicon-containing capping material can be deposited on the top surface of the silicon pad 32. The silicon-containing capping material may include and / or may be substantially composed of a silicon-containing material component that prevents oxygen diffusion. For example, the silicon-containing capping material may include silicon or silicon nitride, and / or may be substantially composed of silicon or silicon nitride.

[0052] In one embodiment, a selective epitaxial growth process can be performed to grow silicon from the top surface of the germanium-containing well 30. In this embodiment, a passivation silicon region 340 comprising monocrystalline silicon can be formed above the germanium-containing well 30. Alternatively, a selective or non-selective silicon deposition process can be performed under conditions of forming polycrystalline silicon. In this embodiment, the passivation silicon region 340 may comprise polycrystalline silicon and / or may be substantially composed of polycrystalline silicon.

[0053] If a selective silicon deposition process (which may or may not be an epitaxial deposition process) is used, the passivation silicon region 340 can be formed only within the openings in the dielectric mask layer 12. In this embodiment, a planarization process is not required, and the top surface of the passivation silicon region 340 can be located at, below, or above the horizontal plane including the top surface of the dielectric mask layer 12. If a non-selective silicon deposition process is used, a planarization process such as chemical mechanical planarization can be performed to remove a portion of the deposited silicon material above the horizontal plane including the top surface of the dielectric mask layer 12. In this embodiment, the top surface of the passivation silicon region 340 can be located within the same horizontal plane as the top surface of the dielectric mask layer 12.

[0054] In one embodiment, the formed passivated silicon region 340 may include intrinsic silicon or lightly doped silicon, i.e., silicon with an atomic concentration between 1.0 × 10⁻⁶. 13 / cm 3 Up to 1.0×10 17 / cm 3 The passivation silicon region 340 is a region containing electrically doped silicon. The conductivity type of the dopants in the passivation silicon region 340 can be either a first conductivity type or a second conductivity type. Typically, depending on the deposition conditions, the passivation silicon region 340 can be formed as a monocrystalline silicon portion, a polycrystalline silicon portion, a microcrystalline silicon portion, or an amorphous silicon portion.

[0055] refer to Figure 2I A dopant of the second conductivity type can be implanted into the passivated silicon region 340 and the upper part of the germanium-containing well 30. The implanted portion of the germanium-containing well 30 can be converted into a germanium-containing region 302 of the second conductivity type, and the passivated silicon region 340 can be converted into a silicon region 342 of the second conductivity type. The atomic concentration of the second conductivity type dopant in the germanium-containing region 302 and the silicon region 342 of the second conductivity type can be between 1.0 × 10⁻⁶. 18 / cm 3 Up to 1.0×10 21 / cm 3Within the range, although smaller and larger atomic concentrations can also be used. The thickness of the germanium-containing region 302 of the second conductivity type can be in the range of 50 nm to 500 nm, although smaller and larger thicknesses can also be used. The thickness of the germanium-containing region 302 of the second conductivity type can be in the range of 50 nm to 300 nm, although smaller and larger thicknesses can also be used.

[0056] The unimplanted portion of the germanium-containing trap 30 is referred to herein as the intermediate germanium-containing region 308. The intermediate germanium-containing region 308 may be intrinsic or may have a concentration between 1.0 × 10⁻⁶. 13 / cm 3 Up to 1.0×10 18 / cm 3 The dopant atoms are doped within a certain range. The intermediate germanium-containing region 308 is in contact with the second conductivity type germanium-containing region 302 and is laterally surrounded by the first conductivity type silicon region 21. The combination of the intermediate germanium-containing regions 308 and 308 constitutes a germanium-containing well 30.

[0057] The first conductivity type silicon region 21, the intermediate germanium-containing region 308, and the second conductivity type germanium-containing region 302 together form a pin-type photovoltaic junction. That is, the photovoltaic junction includes a p-doped region, an n-doped region, and an intermediate semiconductor region located between the p-doped and n-doped regions. This intermediate semiconductor region comprises intrinsic semiconductor material or lightly doped semiconductor material. In one embodiment, the first conductivity type can be p-type, and the second conductivity type can be n-type. In another embodiment, the first conductivity type can be n-type, and the second conductivity type can be p-type. Because the first conductivity type silicon region 21 exists outside the trench 69, the photovoltaic junction can be formed across the trench 69, that is, it can extend spatially across the boundary of the trench 69. The intermediate germanium-containing region 308 is located within the trench 69 and serves as an intermediate semiconductor region comprising intrinsic semiconductor material or lightly doped semiconductor material.

[0058] In an optional embodiment, the intermediate germanium-containing region 308 may have doping of a second conductivity type, and the photovoltaic junction may include a pn junction formed between the intermediate germanium-containing region 308 and the silicon region 21 of the first conductivity type. In this embodiment, the intermediate germanium-containing region 308 may include an atomic concentration between 1.0 × 10⁻⁶. 17 / cm 3 Up to 1.0×10 20 / cm 3The second conductivity type of dopant within the arrangement can be used, although smaller and larger dopant concentrations may also be used. In embodiments excluding silicon pad 32, pn junctions may be formed at the sidewalls and bottom of trench 69. In embodiments including silicon pad 32, silicon pad 32 may be intrinsic, p-doped, or n-doped. Typically, the photovoltaic junction may comprise a pin junction or pn junction formed across a germanium-containing well 30 and a monocrystalline silicon substrate 10 containing a first conductivity type silicon region 21.

[0059] refer to Figure 2J The dielectric mask layer 12 can be removed, for example, by performing a wet etching process. In embodiments where the dielectric mask layer 12 comprises silicon oxide, a wet etching process using dilute hydrofluoric acid can be performed to remove the dielectric mask layer 12.

[0060] A shallow trench isolation structure 20 may be formed in the upper portion of a single-crystal silicon substrate 10. The shallow trench isolation structure 20 may include a dielectric filling material such as silicon oxide and provide electrical isolation from the semiconductor device to be subsequently formed. Various field-effect transistors (610, 630, 640) may be formed in the photodetector region 510 and the sensing circuit region 520. For example, a transmission transistor 610 may be formed in the photodetector region 510, and a p-type field-effect transistor 630 and an n-type field-effect transistor 640 may be formed in the sensing circuit region 520. Each field-effect transistor (610, 630, 640) may include a corresponding gate dielectric 50, a corresponding gate electrode 52, and a corresponding pair of source and drain regions. The source and drain regions are collectively referred to as source / drain regions. For example, the p-type field-effect transistor 630 may include a p-doped source / drain region 42, and the n-type field-effect transistor 640 may include an n-doped source / drain region 44. The transfer transistor 610 may include a source region 48 and a floating drain region 46 to be electrically connected to the second conductivity type germanium-containing region 302. The second conductivity type germanium-containing region 302 and the floating drain region 46 may have doping of the second conductivity type. Various doped wells may be formed in the sensing circuit region 520 as needed. Although only two field-effect transistors in the sensing circuit region 520 are shown in this invention, it should be understood that a complete set of field-effect transistors for providing sensing circuitry for sub-pixels may be formed in the sensing circuit region 520. The field-effect transistors in the sensing circuit region 520 may include transistors such as reset transistors, source follower transistors, and select transistors. Any sensing circuitry for sensing the charge stored in the second conductivity type germanium-containing region 302 may be formed.

[0061] refer to Figure 2KA dielectric material layer 90 and a metal interconnect structure 80 may be formed over the field-effect transistors (610, 630, 640) and the second conductivity type silicon region 342. Each dielectric material layer 90 includes a corresponding interlayer dielectric (ILD) material, such as undoped silicate glass, doped silicate glass, organosilicon glass, and / or porous dielectric material. The dielectric material layer 90 may include dielectric pads, such as silicon nitride dielectric pads, dielectric metal oxide dielectric pads, silicon carbide dielectric pads, and / or silicon oxynitride dielectric pads. The metal interconnect structure 80 may include a metal via structure 82 and a metal wire structure 84. The second conductivity type silicon region 342 may be electrically connected to the source region 48 of the transmission transistor 610 via the collector of the metal interconnect structure 80.

[0062] Figure 2L This is a vertical cross-sectional view of an optional configuration of a first exemplary structure according to a first embodiment of the present invention. (Reference) Figure 2L By using silicon nitride as the material for silicon-containing overlay structures, it is possible to obtain... Figure 2H The first exemplary structure is available in an optional configuration. A silicon nitride overlay structure 41 comprising and / or substantially composed of silicon nitride may be formed on the top surface of the germanium-containing well 30.

[0063] Subsequently, it can be executed Figure 2I The processing steps convert the upper part of the germanium-containing well 30 into a second conductivity type germanium-containing region 302. Then, the following steps can be performed. Figure 2J and Figure 2K The processing steps include forming a metal via structure 82 through a silicon nitride overlay structure 41 (including silicon nitride) to contact a germanium-containing region 302 of the second conductivity type.

[0064] Typically, a silicon-containing capping structure (342 or 41) may be located on the top surface of the germanium-containing well 30. The silicon-containing capping structure (342 or 41) includes a silicon-containing diffusion barrier material, which may be silicon or silicon nitride. If the silicon-containing capping structure (342 or 41) includes silicon (including the second conductivity type silicon region 342), the atomic percentage of silicon in the silicon-containing capping structure (including the second conductivity type silicon region 342) may be greater than 98% and greater than 99%, with the balance being an electrically conductive dopant of the second conductivity type. If the silicon-containing capping structure (including the silicon nitride capping structure 41) includes silicon nitride, the atomic percentage of silicon may be approximately 3 / 7 × 100%, approximately 42.8%. Typically, the silicon-containing capping structure (342 or 41) in embodiments of the present invention may include an atomic percentage of silicon greater than 42%.

[0065] Figure 3A and Figure 3B This is a vertical cross-sectional view of the configuration of a second exemplary structure including pixels of an image sensor according to a second embodiment of the present invention. Figure 3AThe diagram shows a configuration of a silicon-containing overlay structure including a silicon region 342 of a second conductivity type, and... Figure 3B The configuration of the silicon-containing overlay structure, including silicon nitride overlay structure 41, is shown.

[0066] In the second exemplary structure, a photovoltaic junction for each sub-pixel may be formed in a first semiconductor substrate 110. The first semiconductor substrate 110 may be a monocrystalline silicon substrate, which may be the same as the monocrystalline silicon substrate 10 described above. A first dielectric material layer 190 comprising a first subset of metal interconnect structures 80 may be formed over the first semiconductor substrate 110. A first bonding pad 188 may be formed on the first dielectric material layer 190. A substrate via structure 104 laterally surrounded by corresponding insulating spacers 102 may be formed in the first semiconductor substrate 110.

[0067] The sensing circuitry for each sub-pixel can be formed on a second semiconductor substrate 210, which may be a silicon substrate. In this embodiment, a transmission transistor 610 for a photodetector can be formed on the second semiconductor substrate 210. A second dielectric material layer 290 comprising a second subset of metal interconnect structures 80 can be formed over the second semiconductor substrate 210. A second bonding pad 288 can be formed on the second dielectric material layer 290.

[0068] A first wafer, including a first semiconductor substrate 110 and a first dielectric layer 190, can be bonded to a second wafer, including a second semiconductor substrate 210 and a second dielectric layer 290, via wafer-to-wafer bonding. For example, a first bonding pad 188 is aligned with and disposed on a second bonding pad 288, and metal-to-metal bonding can be initiated on each pair of mating first bonding pads 188 and second bonding pads 288. Subsequently, the back side of the first semiconductor substrate 110 can be thinned to physically expose the top surface of the through-substrate via structure 104. A back dielectric layer 106 can be formed on the back side of the first semiconductor substrate 110, and an external bonding pad 198 can be formed through the back dielectric layer 106 on the back surface of a corresponding through-substrate via structure in the through-substrate via structure 104. The bonding assembly of the first and second wafers can be diced to provide a bonded semiconductor die. Each bonded semiconductor die may include: a first semiconductor die 710, including a cut portion of a first semiconductor substrate 110 and a first dielectric material layer 190; and a second semiconductor die 720, including a cut portion of a second semiconductor substrate 210 and a second dielectric material layer 290.

[0069] Figure 4A and Figure 4B This is a vertical cross-sectional view of the configuration of a third exemplary structure including pixels of an image sensor according to a second embodiment of the present invention. Figure 4AThe diagram shows a configuration in which the silicon-containing overlay includes a silicon region 342 of a second conductivity type, and Figure 4B The configuration of the silicon-containing overlay structure, including silicon nitride overlay structure 41, is shown.

[0070] In the third exemplary structure, at least a subset of the photovoltaic junction of each sub-pixel and the sensing circuitry of each sub-pixel may be formed in a first semiconductor substrate 110, which may be the same as the monocrystalline silicon substrate 10 described above. A first dielectric material layer 190 comprising a first subset of metal interconnect structures 80 may be formed over the first semiconductor substrate 110. A substrate via structure 104 laterally surrounded by corresponding insulating spacers 102 may be formed in the first semiconductor substrate 110.

[0071] Additional semiconductor devices, such as p-type field-effect transistors 630 and n-type field-effect transistors, may be formed on a second semiconductor substrate 210, which may be a silicon substrate. The additional semiconductor devices may or may not include components for sensing circuitry used in the photovoltaic junction within the first semiconductor substrate 110. The additional semiconductor devices may include those usable in conjunction with sub-pixels of an image sensor. For example, the additional semiconductor devices may include memory devices or logic devices that support the operation of the image sensor.

[0072] Devices on the first semiconductor substrate 110 and devices on the second semiconductor substrate 210 can be connected face-to-face, back-to-back, or back-to-face. The illustrated configuration includes an embodiment of thinning the back side of the first semiconductor substrate 110, depositing a back side dielectric layer 106 on the back side of the first semiconductor substrate 110, and forming a first bonding pad 188 through the back side dielectric layer 106 on the surface of the through-hole structure 104. The first bonding pad 188 is bonded to a second bonding pad 288 disposed in a second dielectric material layer 290 covering the second semiconductor substrate 210.

[0073] Typically, any type of photovoltaic junction can be formed within or around the germanium-containing well 30. The photovoltaic junction can be a vertical pin junction, a lateral pin junction, a vertical pn junction, or a lateral pn junction. Furthermore, a pinned diode configuration using pinned layers or a single-photon avalanche diode (SPAD) configuration can also be used. Although specific embodiments of photovoltaic junctions formed within or around the germanium-containing well 30 have been described herein, it should be understood that the scope of the invention is not limited to any particular configuration of the photovoltaic junction, provided that the germanium well 30 is used as an element of the photovoltaic junction.

[0074] The germanium-containing material of the germanium-containing trap 30 can be germanium-doped or a doped silicon-germanium alloy comprising more than 50% atomic percentage of germanium. The germanium-containing trap 30 can be completely sealed by a combination of a first conductivity type silicon region 21 and a silicon-containing overlay structure (342 or 41), or by a combination of a silicon pad 32 and a silicon-containing overlay structure (342 or 41). Therefore, physical contact between the germanium-containing trap 30 and the dielectric material layer 90 or any other oxygen-containing element within the first, second, and third exemplary structures can be avoided, and the germanium-containing trap 30 can remain oxidation-free.

[0075] refer to Figures 2A to 4B Furthermore, according to various embodiments of the present invention, a semiconductor structure including a photodetector is provided. The photodetector includes: a germanium-containing well 30 embedded within a single-crystal silicon substrate (10, 110) and extending to a proximal horizontal surface 7 of the single-crystal silicon substrate (9, 10), wherein the germanium-containing well 30 comprises germanium with an atomic percentage greater than 50% (e.g., from 50% to 100%); and a silicon-containing overlay structure (342 or 41) located on the top surface of the germanium-containing well 30 and comprising silicon atoms with an atomic percentage greater than 42%. A portion of the single-crystal silicon substrate (10, 110) surrounding a trench 69 includes a silicon region 21 of a first conductivity type. The germanium-containing well 30 includes a germanium-containing region 302 of a second conductivity type.

[0076] In one embodiment, the photovoltaic junction may include pin junctions (21, 308, 302); and the germanium-containing well 30 includes an intermediate germanium-containing region 308, which has a density between 1.0 × 10⁻⁶. 13 / cm 3 Up to 1.0×10 18 / cm 3 The dopant atom concentration is within the range, and it is in contact with the second conductivity type germanium-containing region 302 and is laterally surrounded by the first conductivity type silicon region 21.

[0077] In one embodiment, the semiconductor structure may include: a single-crystal silicon pad 32, in contact with the inner sidewall of a first conductivity type silicon region 302, laterally surrounding a germanium-containing well 30, and epitaxially aligned with a single-crystal silicon substrate (9, 10). In one embodiment, the germanium-containing well 30 comprises a single-crystal germanium-containing semiconductor material epitaxially aligned with the single-crystal silicon pad 32 and the single-crystal silicon substrate (9, 10).

[0078] In one embodiment, a first conductivity type silicon region 21 continuously surrounds a germanium-containing well 30 and includes a first horizontal extension and a second horizontal extension in contact with the bottom surface of the germanium-containing well 30. The first horizontal extension is in contact with the bottom surface of the germanium-containing well, and the second horizontal extension 7 extends outward from the germanium-containing well below the near-side horizontal surface 30 of the monocrystalline silicon substrate (9, 10).

[0079] The semiconductor structure may include: a sensing circuit located on a single-crystal silicon substrate (10, 110) or on a semiconductor substrate 210 bonded to the single-crystal silicon substrate (10, 110) via a dielectric material layer (190, 290) and pads (188, 288) located within the dielectric material layer (190, 290); and a metal interconnect structure 80 providing an electrical connection between a second conductivity type germanium-containing region 302 and the sensing circuit.

[0080] Figures 5A to 5F This is a sequential vertical cross-sectional view of a fourth exemplary structure during the formation of pixels of an image sensor according to a fourth embodiment of the present invention. Figure 5A The fourth exemplary structure shown includes a first semiconductor substrate 110, which may be a single-crystal silicon substrate. In the first exemplary structure, the first semiconductor substrate 110 may be the same as the single-crystal silicon substrate 10. A proximal horizontal surface 7 may be located on the top surface of the first semiconductor substrate 110. A dielectric mask layer 12 may be formed on the proximal horizontal surface, and a trench 69 may be formed in the upper portion of the first semiconductor substrate 110 through an opening in the dielectric mask layer 12. By omitting the formation of the first doped photodiode contact region 28, the second conductivity type doped well 60, and the doped well contact region 68, it is possible to... Figure 2B The first exemplary structure is obtained Figure 5A The fourth exemplary structure.

[0081] refer to Figure 5B It can be executed sequentially. Figure 2D , Figure 2E , Figure 2F and Figure 2G The processing steps are used to form a silicon pad 32 and a germanium-containing well 30. The silicon pad 32 may have the same thickness and material composition as in the first embodiment. The germanium-containing well 30 may have the same material composition and crystallinity as in the first embodiment. The germanium-containing well 30 may be single-crystal and epitaxially aligned with the single-crystal semiconductor substrate of the first semiconductor substrate 110, or it may be polycrystalline or amorphous.

[0082] refer to Figure 5C Silicon can be deposited on the top surface of the germanium-containing well 30. In one embodiment, the deposited silicon may include undoped silicon. As used herein, undoped silicon refers to silicon in which no dopant was intentionally introduced during the deposition process. Therefore, the level of electrical dopant in undoped silicon may be at a residual level. For example, undoped silicon may be intrinsic or may include dopant concentrations of less than 1.0 × 10⁻⁶. 16 / cm 3 (such as 1.0×10) 12 / cm 3 Up to 1.0×10 15 / cm 3The undoped silicon provides relatively high resistivity and effectively suppresses leakage current. Undoped silicon can be grown using selective or non-selective deposition processes. In embodiments using a non-selective deposition process, excess portions of the deposited undoped silicon material can be removed from above a horizontal plane including the top surface of the dielectric mask layer 12. The remaining portion of the deposited undoped silicon includes a passivation silicon region 340. The top surface of the passivation silicon region 340 may lie within a horizontal plane including the top surface of the dielectric mask layer 12. In embodiments using a selective deposition process to deposit undoped silicon, a planarization process may not be necessary. The passivation silicon region 340 serves as a silicon-containing overlay structure for the germanium-containing well 30.

[0083] refer to Figure 5D A first mask ion implantation process can be used to implant a dopant of a first conductivity type into a portion of the passivated silicon region 340 and the upper portion of the germanium-containing well 30. The implanted portion of the passivated silicon region 340 includes a first conductivity type silicon region 341, and the implanted portion of the germanium-containing well 30 includes a first conductivity type germanium-containing region 301. The first conductivity type silicon region 341 and the first conductivity type germanium-containing region 301 can be heavily doped. For example, each of the first conductivity type silicon region 341 and the first conductivity type germanium-containing region 301 may include an atomic concentration between 1.0 x 10⁻⁶. 19 / cm 3 Up to 2.0x10 21 / cm 3 The first type of electrical dopant within the range.

[0084] A second conductivity type dopant can be implanted into another portion of the passivated silicon region 340 and another upper portion of the germanium-containing well 30 using a second mask ion implantation process. The implanted portion of the passivated silicon region 340 includes a second conductivity type silicon region 342, and the implanted portion of the germanium-containing well 30 includes a second conductivity type germanium-containing region 302. The second conductivity type silicon region 342 and the second conductivity type germanium-containing region 302 can be heavily doped. For example, each of the second conductivity type silicon region 342 and the second conductivity type germanium-containing region 302 may include an atomic concentration between 1.0 x 10⁻⁶. 19 / cm 3 Up to 2.0x10 21 / cm 3 The second type of electrical dopant within the range.

[0085] The remaining portion of the passivation silicon region 340 can provide lateral isolation between the first conductivity type silicon region 341 and the second conductivity type silicon region 342. The combination of the passivation silicon region 340, the first conductivity type silicon region 341, and the second conductivity type silicon region 342 includes a silicon overlay structure 34, which is a silicon-containing overlay structure.

[0086] The unimplanted portion of the germanium-containing trap 30 is referred to herein as the intermediate germanium-containing region 308. The intermediate germanium-containing region 308 may be intrinsic or may have a concentration between 1.0 × 10⁻⁶. 13 / cm 3 Up to 1.0×10 18 / cm 3 The dopant atoms are doped within a certain range. The intermediate germanium-containing region 308 provides a lateral spacing between the first conductivity type germanium-containing region 301 and the second conductivity type germanium-containing region 302. The combination of the intermediate germanium-containing region 308, the first conductivity type germanium-containing region 301, and the second conductivity type germanium-containing region 302 constitutes a germanium-containing well 30.

[0087] refer to Figure 5E The dielectric mask layer 12 can be removed, for example, by performing an isotropic etching process (such as a wet etching process). A first dielectric material layer 190, a substrate via structure 104, an insulating spacer 102 laterally surrounding the substrate via structure 104, a metal interconnect structure 80, and a first bonding pad 188 can be formed over the first semiconductor substrate 110.

[0088] refer to Figure 5F A method for setting can be formed on the second semiconductor substrate 210. Figure 5F The sensing circuit of the photodetector is formed on the first semiconductor substrate 110. It can be configured for placement on... Figure 5F An array of sensing circuits for an array of photodetectors on a first semiconductor substrate 110. For example, each sensing circuit for a photodetector may include: a transfer transistor 610, including a source region 48 and a floating drain region 46; and additional field-effect transistors, which may include a p-type field-effect transistor 630 and an n-type field-effect transistor. Disposed on a second semiconductor substrate 210 Figure 5F The sensing circuit can be with Figure 2K The sensing circuit is the same as that disposed on the single-crystal silicon substrate 10. A metal interconnect structure 80 formed within the second dielectric material layer 290 may be formed above the second semiconductor substrate 210 to provide electrical wiring to and from various semiconductor devices on the second semiconductor substrate 210. A second bonding pad 288 may be formed on the second dielectric material layer 290.

[0089] A first wafer, including a first semiconductor substrate 110 and a first dielectric layer 190, can be bonded to a second wafer, including a second semiconductor substrate 210 and a second dielectric layer 290, via wafer-to-wafer bonding. For example, a first bonding pad 188 is aligned with and disposed on a second bonding pad 288, and metal-to-metal bonding can be initiated on each pair of mating first bonding pads 188 and second bonding pads 288. Subsequently, the back side of the first semiconductor substrate 110 can be thinned to physically expose the top surface of the through-substrate via structure 104. A back dielectric layer 106 can be formed on the back side of the first semiconductor substrate 110, and an external bonding pad 198 can be formed through the back dielectric layer 106 on the back surface of a corresponding through-substrate via structure in the through-substrate via structure 104. The bonding assembly of the first and second wafers can be diced to provide a bonded semiconductor die. Each bonded semiconductor die may include: a first semiconductor die 710, including a cut portion of a first semiconductor substrate 110 and a first dielectric material layer 190; and a second semiconductor die 720, including a cut portion of a second semiconductor substrate 210 and a second dielectric material layer 290.

[0090] Figures 6A to 6F This is a vertical cross-sectional view of an optional configuration of a fourth exemplary structure according to a fourth embodiment of the present invention. (Reference) Figure 6A By omitting the formation of silicon pad 32, it is possible to... Figure 5F The fourth exemplary structure obtains a first optional configuration of the fourth exemplary structure. In this embodiment, the germanium-containing well 30 can be formed directly on the sidewalls and horizontal surface of the trench 69. Therefore, the germanium-containing well 30 can be in direct contact with the single-crystal silicon substrate including the first semiconductor substrate 110.

[0091] refer to Figure 6B By forming a silicon nitride overlay structure 41 instead of a silicon overlay structure 34, it is possible to achieve the following: Figure 6A The first optional configuration of the fourth exemplary structure leads to a second optional configuration of the fourth exemplary structure. In this embodiment, each of the first conductivity type germanium-containing region 301 and the second conductivity type germanium-containing region 302 can be directly contacted via structure 82 through a corresponding metal interconnect structure (such as a corresponding metal via) in the metal interconnect structure 80.

[0092] refer to Figure 6C By forming multiple germanium-containing regions of the first conductivity type 301 and / or multiple germanium-containing regions of the second conductivity type 302, it is possible to obtain... Figure 5F The fourth exemplary structure yields a third optional configuration of the fourth exemplary structure. In this embodiment, a plurality of first conductivity type silicon regions 341 and / or a plurality of second conductivity type silicon regions 342 may be formed.

[0093] refer to Figure 6DBy forming multiple germanium-containing regions of the first conductivity type 301 and / or multiple germanium-containing regions of the second conductivity type 302, it is possible to obtain... Figure 6A The first optional configuration of the fourth exemplary structure yields the fourth optional configuration of the fourth exemplary structure. In this embodiment, a plurality of first conductivity type silicon regions 341 and / or a plurality of second conductivity type silicon regions 342 may be formed.

[0094] refer to Figure 6E By doping the germanium-containing intermediate region 308 of the first conductivity type with a dopant to form an additional germanium-containing region 305 of the first conductivity type, it is possible to obtain... Figure 5F The fourth exemplary structure or Figure 6C The third alternative structure of the fourth exemplary structure yields the fifth alternative structure of the fourth exemplary structure. In this embodiment, the atomic concentration of the dopant of the first conductivity type within the germanium-containing region 305 of the additional first conductivity type can be between 1.0 × 10⁻⁶. 17 / cm 3 Up to 1.0×10 19 / cm 3 Within this range, although smaller and larger atomic concentrations can also be used. In this embodiment, the photovoltaic junction can be a pn junction.

[0095] refer to Figure 6F By doping the intermediate germanium-containing region 308 with a dopant of the first conductivity type at an atomic concentration equivalent to that of the dopant of the first conductivity type in the germanium-containing region 301, it is possible to obtain... Figure 6E The fifth optional configuration of the fourth exemplary structure yields the sixth optional configuration of the fourth exemplary structure. In this embodiment, a first conductivity type germanium-containing region 301 replaces the intermediate germanium-containing region 308. A pn ​​junction may be formed between the first conductivity type germanium-containing region 301 and the second conductivity type germanium-containing region 302. The germanium-containing well 30 includes and / or consists of the first conductivity type germanium-containing region 301 and the second conductivity type germanium-containing region 302.

[0096] Figures 7A to 7G This is a sequential vertical cross-sectional view of a fifth exemplary structure during pixel formation of an image sensor according to a fifth embodiment of the present invention. (Reference) Figure 7AA fifth exemplary structure according to a fifth embodiment of the present invention can be formed by providing a semiconductor substrate 500, which may include a monocrystalline silicon substrate 10. The monocrystalline silicon substrate 10 may be the same as in the first exemplary structure. Semiconductor devices for forming a sensing circuit may be formed on and / or in the upper portion of the monocrystalline silicon substrate 10. For example, the semiconductor devices may include a transfer transistor 610, a p-type field-effect transistor 630, and an n-type field-effect transistor 640. The transfer transistor 610 may be formed in the photodetector region 510, and the p-type field-effect transistor 630 and the n-type field-effect transistor 640 may be formed in the sensing circuit region 520. The various field-effect transistors (610, 630, 640) may be the same as in the first exemplary structure.

[0097] Dielectric materials such as silicon oxide can be deposited over a semiconductor device on a near-horizontal surface of a single-crystal silicon substrate 10 and can be planarized to provide a dielectric mask layer 92 with a horizontal top surface. The thickness of the dielectric mask layer 92 can be greater than the height of the gate electrode 52, and the dielectric mask layer 92 can cover the gate electrode 52.

[0098] refer to Figure 7B A photoresist layer 67 may be applied over the dielectric mask layer 12 and may be photolithographically patterned to form openings within the photodetector region 510. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer 67 through the dielectric mask layer 92 to the upper portion of the single-crystal silicon substrate 10. A trench 69 may be formed in the upper portion of the single-crystal silicon substrate 10. The depth of the trench 69 may be greater than, equal to, or less than the depth of the second conductivity type doped well 60. In one embodiment, the depth of the trench 69 may be in the range of 0.5 micrometers to 10 micrometers, such as in the range of 1 micrometer to 6 micrometers, although smaller and larger depths may also be used. The lateral dimension of the trench 69 may be in the range of 0.5 micrometers to 30 micrometers, such as in the range of 1 micrometer to 15 micrometers. The lateral dimension of trench 69 may be the diameter or main axis of the horizontal cross-sectional shape of trench 69 in embodiments where trench 69 has a circular or elliptical horizontal cross-sectional shape, or the length of the side of the rectangle in embodiments where the horizontal cross-sectional shape of trench 69 is rectangular. The photoresist layer 67 may then be removed, for example, by ashing.

[0099] refer to Figure 7C Executable Figure 2D and Figure 2E The processing steps are to form a silicon pad 32 and a germanium-containing material layer 30L. The silicon pad 32 may have the same thickness, the same crystallinity, and / or the same material composition as in the first exemplary structure. The germanium-containing material layer 30L may have the same crystallinity and the same material composition as in the first exemplary structure.

[0100] refer to Figure 7D Executable Figure 2F and Figure 2G The processing steps are to form a germanium-containing trap 30.

[0101] refer to Figure 7E Executable Figure 2H The processing steps are used to form the passivated silicon region 340. In one embodiment, the passivated silicon region 340 may have a top surface within a horizontal plane that includes the top surface of the dielectric mask layer 92.

[0102] refer to Figure 7F Executable Figure 5D The processing steps form a first conductivity type silicon region 341, a first conductivity type germanium-containing region 301, a second conductivity type silicon region 342, and a second conductivity type germanium-containing region 302. The remaining portion of the passivation silicon region 340 can provide lateral isolation between the first conductivity type silicon region 341 and the second conductivity type silicon region 342. The combination of the passivation silicon region 340, the first conductivity type silicon region 341, and the second conductivity type silicon region 342 includes a silicon overlay structure 34, which is a silicon-containing overlay structure. The combination of the intermediate germanium-containing region 308, the first conductivity type germanium-containing region 301, and the second conductivity type germanium-containing region 302 constitutes a germanium-containing well 30. Optionally, it can be formed Figures 6A to 6D Any pin junction structure shown or Figure 6E and Figure 6F The pn junction structure shown is used to replace Figure 6F The pin junction is shown. Typically, any of the pin junctions or any pn junctions described above can be formed in trench 69.

[0103] refer to Figure 7G Additional dielectric material layers 94 and metal interconnect structures 80 can be formed to provide electrical connections to and from the various nodes of the semiconductor device and the photodetector. For example, a germanium-containing region 302 of the second conductivity type can be connected to the source region 48 of the transmission transistor 610 via a subset of the metal interconnect structure and the silicon region 342 of the second conductivity type. A germanium-containing region 301 of the first conductivity type can be appropriately biased through another subset of the metal interconnect structure 80 by a bias circuit.

[0104] Figure 7H This is a vertical cross-sectional view of an optional configuration of a fifth exemplary structure according to a fifth embodiment of the present invention. (Reference) Figure 7H By forming a silicon nitride overlay structure 41 instead of a silicon overlay structure 34, it is possible to achieve the following: Figure 7G The fifth example structure yields an optional configuration of the fifth exemplary structure. In this embodiment, each of the first conductivity type germanium-containing region 301 and the second conductivity type germanium-containing region 302 can be directly contacted via structure 82 through a corresponding metal interconnect structure (such as a corresponding metal via) in the metal interconnect structure 80.

[0105] Typically, any type of photovoltaic junction can be formed within the germanium-containing well 30. The photovoltaic junction can be a vertical pin junction, a lateral pin junction, a vertical pn junction, or a lateral pn junction. Furthermore, a pinned diode configuration using pinned layers or a single-photon avalanche diode (SPAD) configuration can also be used. Although specific embodiments of photovoltaic junctions formed within the germanium-containing well 30 have been described herein, it should be understood that the scope of the invention is not limited to any particular configuration of the photovoltaic junction, provided that the germanium well 30 is used as an element of the photovoltaic junction.

[0106] The germanium-containing material of the germanium-containing trap 30 can be doped germanium or a doped silicon-germanium alloy comprising more than 50% atomic percentage of germanium. The germanium-containing trap 30 can be completely sealed by a combination of a first conductivity type silicon region 21 and a silicon-containing overlay structure (34 or 41), or by a combination of a silicon pad 32 and a silicon-containing overlay structure (34 or 41). Therefore, physical contact between the germanium-containing trap 30 and the dielectric material layer 90 or any other oxygen-containing element within the fourth or fifth exemplary structure can be avoided, and the germanium-containing trap 30 can remain oxidation-free.

[0107] refer to Figures 5A to 7H According to various embodiments of the present invention, a semiconductor structure including a photodetector is provided. The photodetector includes: a germanium-containing well 30 embedded in a single-crystal silicon substrate (10, 110) and extending to a proximal horizontal surface 7 of the single-crystal silicon substrate (10, 110), wherein the germanium-containing well 30 includes germanium with an atomic percentage greater than 50%; and a silicon-containing overlay structure (34 or 41) located on the top surface of the germanium-containing well 30 and including silicon atoms with an atomic percentage greater than 42%. The silicon-containing overlay structure (34 or 41) may include a silicon overlay structure 34 composed substantially of doped silicon, or a silicon nitride overlay structure 41 composed substantially of silicon nitride. The germanium-containing well 30 includes a photovoltaic junction including a first conductivity type germanium-containing region 301 and a second conductivity type germanium-containing region 302.

[0108] In one embodiment, the photovoltaic junction includes a pin junction; and the germanium-containing well 30 includes an intermediate germanium-containing region 308, the intermediate germanium-containing region 308 having a density between 1.0 × 10⁻⁶ and 10⁻⁶. 13 / cm 3 Up to 1.0×10 17 / cm 3 The dopant atom concentration is within the range, and it is in contact with the first conductivity type germanium-containing region 301 and the second conductivity type germanium-containing region 302.

[0109] In one embodiment, the silicon-containing overlay structure 34 includes: a first conductive type silicon region 341 in contact with a first conductive type germanium-containing region 301; and a second conductive type silicon region 342 in contact with a second conductive type germanium-containing region 302.

[0110] In one embodiment, the silicon-containing overlay structure 34 includes a passivated silicon region 340, the passivated silicon region 340 having a density between 1.0 × 10⁻⁶. 13 / cm 3 Up to 1.0×10 17 / cm 3 The dopant atom concentration is within the range of the first conductivity type silicon region 341 and the second conductivity type silicon region 342.

[0111] In one embodiment, the germanium-containing well 30 comprises a single-crystal germanium-containing semiconductor material epitaxially aligned with a single-crystal silicon substrate (10, 110). In one embodiment, the proximal surface of the silicon-containing overlay structure (34 or 41) contacts the germanium-containing well 30; and the distal surface of the silicon-containing overlay structure (34 or 41) is vertically offset away from the horizontal plane comprising the proximal horizontal surface 7 of the single-crystal silicon substrate (10, 110).

[0112] In one embodiment, the photovoltaic junction includes a pn junction; and the first conductivity type germanium-containing region 301 is in contact with the second conductivity type germanium-containing region 302.

[0113] In one embodiment, the semiconductor structure may include a sensing circuit comprising a field-effect transistor located on a monocrystalline silicon substrate (10, 110); and dielectric material layers 90, 190, (92, 94) located on a proximal horizontal surface 7 of the monocrystalline silicon substrate (10, 110) and comprising a metal interconnect structure 80. A subset of the metal interconnect structure 80 may provide a conductive path between a germanium-containing region 302 of a second conductivity type and a source / drain region of one of the field-effect transistors (such as the source region 48 of a transfer transistor 610).

[0114] In one embodiment, the semiconductor structure may include: a first dielectric layer 190 located on a proximal horizontal surface 7 of a single-crystal silicon substrate 110 and including a first metal interconnect structure 80 and a first bonding pad 188; a semiconductor die 720 including a semiconductor substrate 210; a sensing circuit including a field-effect transistor located on the semiconductor substrate 210; and a second dielectric layer 290 located on the semiconductor substrate 210 and including a second metal interconnect structure 80 and a second bonding pad 288. The second bonding pad 288 may be bonded to a corresponding first bonding pad in the first bonding pad 188, and a subset of the first and second metal interconnect structures 80 provides a conductive path between a germanium-containing region 302 of a second conductivity type and a source / drain region (such as the source region 48 of a transfer transistor 610) of one of the field-effect transistors in the sensing circuit.

[0115] refer to Figure 8 First process flow diagram 800 illustrates an exemplary process sequence for forming an image sensor according to an embodiment of the present invention. Refer to step 810 and... Figure 2B , Figure 5A and Figure 7A The dielectric mask layers (12, 92) can be deposited and patterned over the single-crystal silicon substrates (10, 110). Refer to step 820 and... Figure 2B , Figure 5A and Figure 7B Trench 69 can be etched in the single-crystal silicon substrate (10, 110) through openings in the dielectric mask layers (12, 92). Refer to step 830 and... Figures 2C to 2G , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5B , Figure 5F , Figures 6A to 6F , Figure 7C and Figure 7D and Figure 7H A germanium-containing well 30 can be formed within trench 69. The germanium-containing well 30 comprises germanium with an atomic percentage greater than 50%. In one embodiment, the germanium-containing well 30 may be single-crystal and epitaxially aligned with a single-crystal silicon substrate (10, 110). Refer to step 840 and... Figure 2H , Figure 2L , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5C , Figure 5F , Figures 6A to 6F , Figure 7E and Figure 7H A silicon-containing overlay structure (34 or 41) can be formed on the top surface of the germanium-containing well 30. Refer to step 850 and... Figures 2I to 2L , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figures 5D to 5F , Figures 6A to 6F and Figures 7F to 7H A photovoltaic junction can be formed within or across the trench 69 by injecting dopants of a first conductivity type and a second conductivity type.

[0116] refer to Figure 9 The second process flow diagram 900 shows the process for forming Figure 2K or Figure 2L The image sensor shown is an exemplary process sequence. Refer to step 921 and... Figure 2A A single-crystal silicon substrate 10 can be provided. Refer to steps 922 and... Figure 2B A patterned dielectric mask layer 12 can be formed on the top surface of the single-crystal silicon substrate 10, and this patterned dielectric mask layer 12 can be used as an etching mask to form trenches 69 in the upper part of the single-crystal silicon substrate 10. Refer to step 923 and... Figure 2C For example, by ion implantation of a dopant of the first conductivity type, a silicon region 21 of the first conductivity type can be formed around a trench 69 within a single-crystal silicon substrate 10. Refer to step 924 and... Figure 2D Optionally, a silicon pad 32 can be grown from the physically exposed surface of the silicon region 21 of the first conductivity type. Refer to step 925 and... Figure 2E A germanium-containing material layer 30L can be formed in the trench 69 and over the single-crystal silicon substrate (9, 10). In one embodiment, an epitaxial deposition process can be performed to grow a single-crystal germanium-containing material within the trench 69 to form the germanium-containing material layer 30L. Refer to step 926 and... Figure 2F The germanium-containing well 30 can be formed by performing a planarization process on the germanium-containing material layer 30L. Refer to step 927 and... Figure 2G Optionally, the germanium-containing trap 30 can be made vertically recessed. Refer to step 928 and... Figure 2H and Figure 2L A silicon-containing overlay structure (such as) can be formed on the top surface of the germanium-containing trap 30. Figure 2H The passivated silicon region 340 shown Figure 2L The silicon nitride overlay structure 41 is shown. Refer to step 929 and... Figure 2I and Figure 2L A germanium-containing region 302 of the second conductivity type can be formed by doping the upper part of the germanium-containing well 30 with a dopant of the second conductivity type. Refer to step 930 and... Figure 2J and Figure 2L Field-effect transistors (610, 630, 640) can be formed in the photodetector region 510 and the sensing circuit region 520 on the single-crystal silicon substrate 10. Refer to step 931 and... Figure 2K and Figure 2L A dielectric material layer 90 and a metal interconnect structure 80 can be formed above the field-effect transistors (610, 630, 640).

[0117] refer to Figure 10 The third process flow diagram 1000 shows the process used to form Figure 3A or Figure 3B The image sensor shown is an exemplary process sequence. Referring to step 1010, by performing... Figures 2A to 2I , Figure 2K and Figure 2L The corresponding Figure 9 The processing steps 921 to 929 and 930 in the second process flow diagram can form the photovoltaic junction of the sub-pixel in the first semiconductor substrate 110. In this embodiment, as Figure 3A and Figure 3B As shown, no field-effect transistors (610, 630, 640) are present on the first semiconductor substrate 110. Refer to step 1020 and... Figure 3A and Figure 3BThe sensing circuitry for the sub-pixels can be formed on a second semiconductor substrate 210, which may be a silicon substrate. A transmission transistor 610 for each photodetector can be formed on the second semiconductor substrate 210. Refer to step 1030 and... Figure 3A and Figure 3B A first wafer, including a first semiconductor substrate 110 and a first dielectric layer 190, can be bonded to a second wafer, including a second semiconductor substrate 210 and a second dielectric layer 290, via wafer-to-wafer bonding. Subsequently, the first semiconductor substrate 110 can be thinned, and the bonded components can be subsequently diced. Figure 3A An embodiment of a silicon-containing overlay structure is shown, including a passivated silicon region 340, and Figure 3B An embodiment of a silicon-containing overlay structure including a silicon nitride overlay structure 41 is shown.

[0118] refer to Figure 11 The fourth process flow diagram 1100 shows the process for forming Figure 4A or Figure 4B The image sensor shown is an exemplary process sequence. Referring to step 1110, it can be achieved by performing... Figures 2A to 2L The processing steps are used to form the photovoltaic junction of the sub-pixel in the first semiconductor substrate 110. In this case, as... Figure 4A and Figure 4B As shown, a field-effect transistor is formed on the first semiconductor substrate 110. Referring to step 1120 and... Figure 4A and Figure 4B Additional field-effect transistors (630, 640) may be formed on a second semiconductor substrate 210, which may be a silicon substrate. A transmission transistor 610 for a photodetector may be formed on a first semiconductor substrate 110, and field-effect transistors for a sensing circuit may be formed on the first semiconductor substrate 110 and / or the second semiconductor substrate 210. Refer to step 1130 and... Figure 4A and Figure 4B A first wafer, including a first semiconductor substrate 110 and a first dielectric layer 190, can be bonded to a second wafer, including a second semiconductor substrate 210 and a second dielectric layer 290, via wafer-to-wafer bonding. Subsequently, the first semiconductor substrate 110 can be thinned, and the bonded components can be subsequently diced. Figure 4A An embodiment of a silicon-containing overlay structure is shown, including a passivated silicon region 340, and Figure 4B An embodiment of a silicon-containing overlay structure including a silicon nitride overlay structure 41 is shown.

[0119] refer to Figure 12 The fifth process flow diagram 1200 shows the process used to form Figure 5F and Figures 6A to 6F The image sensor shown is an exemplary process sequence. Refer to step 1210 and... Figures 2A to 2C , Figure 5A and Figures 6A to 6F A trench 69 can be formed in the upper part of the first semiconductor substrate 110 through an opening in the dielectric mask layer 12. This can be achieved as follows: Figure 5F , Figure 6C , Figure 6E As shown, a silicon pad 32 is formed, or it can be formed as follows: Figure 6A , Figure 6B , Figure 6D and Figure 6F Silicon pad 32 is omitted in the diagram. Refer to steps 1220 and... Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 5B and Figures 6A to 6F This can form an optional silicon pad 32 and a germanium-containing trap 30. Refer to steps 1230 and... Figure 5C and Figures 6A to 6F A passivated silicon region 340 can be formed on the top surface of the germanium-containing well 30 within the opening in the dielectric mask layer 12. Refer to step 1240 and... Figure 5D and Figures 6A to 6F Electrodopersive agents can be implanted into the upper part of the germanium-containing well 30 and the passivated silicon region 340 to form, as shown in the figure. Figure 5D and Figures 6A to 6D The pin junction or formation shown is as follows Figure 6E and Figure 6F The pn junction is shown. Refer to step 1250 and... Figure 5E and Figures 6A to 6F The dielectric mask layer 12 can be removed, and a first dielectric material layer 190, a metal interconnect structure 80, and a first bonding pad 188 can be formed over the first semiconductor substrate 110. Refer to step 1260 and... Figure 5F and Figures 6A to 6F A first wafer, including a first semiconductor substrate 110 and a first dielectric layer 190, can be bonded to a second wafer, including a second semiconductor substrate 210 and a second dielectric layer 290, via wafer-to-wafer bonding. Subsequently, the first semiconductor substrate 110 can be thinned, and the bonded components can be subsequently diced.

[0120] refer to Figure 13 The sixth process flow diagram 1300 shows the process used to form Figure 7G and Figure 7H The image sensor shown is an exemplary process sequence. Refer to step 1310 and... Figure 7A The semiconductor devices for the sensing circuit can be formed on and / or in the upper part of the single-crystal silicon substrate 10. Refer to step 1320 and... Figure 7B A trench 69 can be formed in the upper part of the single-crystal silicon substrate 10 through the dielectric mask layer 92. Refer to step 1330 and... Figure 7CAn optional silicon pad 32 and a germanium-containing material layer 30L can be formed in the trench 69. Refer to step 1340 and... Figure 7D A germanium-containing well 30 can be formed in the trench 60 by patterning the germanium-containing material layer 30L. Refer to step 1350 and... Figure 7E and Figure 7H A silicon-containing overlay structure, including a passivation silicon region 34 or a silicon nitride overlay structure 41, can be formed on top of the germanium-containing well 30. Refer to step 1360 and... Figure 7F and Figure 7H An ion implantation process can be performed to form a pin junction or pn junction in trench 69. Refer to step 1370 and... Figure 7G and Figure 7H An additional dielectric material layer 94 and a metal interconnect structure 80 can be formed on the single-crystal silicon substrate 10 to provide electrical connections to and from the nodes of the semiconductor device and the photodetector.

[0121] The germanium-based photodetector of this invention provides high quantum efficiency in the infrared wavelength range. Furthermore, compared to silicon-based photodetectors, the germanium-based photodetector of this invention offers higher operating speeds and faster response times for high-speed motion applications such as high-speed distance measurement. The germanium-based photodetector of this invention is integrated with standard CMOS logic devices (such as CMOS field-effect transistors) into a semiconductor die.

[0122] Some embodiments of this application provide a semiconductor structure including a photodetector, wherein the photodetector includes: a germanium-containing well embedded in a single-crystal silicon substrate and extending to a proximal horizontal surface of the single-crystal silicon substrate, wherein the germanium-containing well includes greater than 50% atomic percentage of germanium; and a silicon-containing overlay structure located on the top surface of the germanium-containing well and including greater than 42% atomic percentage of silicon atoms, wherein: the germanium-containing well includes a photovoltaic junction, the photovoltaic junction including a first conductivity type germanium-containing region and a second conductivity type germanium-containing region. In some embodiments, the photovoltaic junction includes a pin junction; and the germanium-containing well includes an intermediate germanium-containing region having a density between 1.0 x 10⁻⁶. 13 / cm 3 Up to 1.0x10 17 / cm 3 The dopant atom concentration is within the range specified in the original text, and it is in contact with both the first conductivity type germanium-containing region and the second conductivity type germanium-containing region. In some embodiments, the silicon-containing overlay structure includes: a first conductivity type silicon region in contact with the first conductivity type germanium-containing region; and a second conductivity type silicon region in contact with the second conductivity type germanium-containing region. In some embodiments, the silicon-containing overlay structure includes a passivated silicon region having a dopant atom concentration between 1.0 x 10⁻⁶ and 10⁻⁶. 13 / cm 3 Up to 1.0x10 17 / cm 3 The dopant atom concentration is within a certain range and is located between the first conductivity type silicon region and the second conductivity type silicon region. In some embodiments, the germanium-containing well comprises a single-crystal germanium-containing semiconductor material epitaxially aligned with the single-crystal silicon substrate. In some embodiments, the proximal surface of the silicon-containing overlay structure contacts the germanium-containing well; and the distal surface of the silicon-containing overlay structure is vertically offset away from the horizontal plane comprising the proximal horizontal surface of the single-crystal silicon substrate. In some embodiments, the photovoltaic junction comprises a pn junction; and the first conductivity type germanium-containing region contacts the second conductivity type germanium-containing region. In some embodiments, the semiconductor structure further comprises: a sensing circuit including a field-effect transistor located on the single-crystal silicon substrate; and a dielectric material layer located on the proximal horizontal surface of the single-crystal silicon substrate, and comprising a metal interconnect structure therein, wherein a subset of the metal interconnect structure provides a conductive path between the second conductivity type germanium-containing region and a source / drain region in one of the field-effect transistors. In some embodiments, the semiconductor structure further includes: a first dielectric layer located on a proximal horizontal surface of the single-crystal silicon substrate and containing a first metal interconnect structure and a first bonding pad; a semiconductor die including a semiconductor substrate, a sensing circuit including a field-effect transistor located on the semiconductor substrate, and a second dielectric layer located on the semiconductor substrate, the second dielectric layer containing a second metal interconnect structure and a second bonding pad, wherein the second bonding pad is bonded to a corresponding first bonding pad in the first bonding pad, and a subset of the first metal interconnect structure and the second metal interconnect structure provides a conductive path between a germanium-containing region of the second conductivity type and a source / drain region in one of the field-effect transistors in the sensing circuit.

[0123] Other embodiments of this application provide a semiconductor structure including a photodetector, the photodetector comprising: a germanium-containing well embedded within a monocrystalline silicon substrate and extending to a proximal horizontal surface of the monocrystalline silicon substrate, wherein the germanium-containing well comprises greater than 50% atomic percentage of germanium, and wherein the germanium-containing well comprises a photovoltaic junction; and a silicon-containing overlay structure located on the top surface of the germanium-containing well and comprising greater than 42% atomic percentage of silicon atoms, wherein: a portion of the monocrystalline silicon substrate surrounding the germanium-containing well comprises a silicon region of a first conductivity type; and the germanium-containing well comprises a germanium-containing region of a second conductivity type. In some embodiments, the photovoltaic junction comprises a pin junction; and the germanium-containing well comprises an intermediate germanium-containing region having a density between 1.0 x 10⁻⁶. 13 / cm 3 Up to 1.0x10 18 / cm 3The semiconductor structure includes a dopant atom concentration within a certain range, contacts the germanium-containing region of the second conductivity type, and is laterally surrounded by the silicon region of the first conductivity type. In some embodiments, the semiconductor structure further includes a single-crystal silicon pad that contacts the inner sidewall of the first conductivity type silicon region, laterally surrounds the germanium-containing well, and is epitaxially aligned with the single-crystal silicon substrate. In some embodiments, the germanium-containing well comprises a single-crystal germanium-containing semiconductor material epitaxially aligned with the single-crystal silicon pad and the single-crystal silicon substrate. In some embodiments, the first conductivity type silicon region continuously surrounds the germanium-containing well and includes a first horizontal extension and a second horizontal extension, the first horizontal extension contacting the bottom surface of the germanium-containing well, and the second horizontal extension extending outward from the germanium-containing well below the proximal horizontal surface of the single-crystal silicon substrate. In some embodiments, the semiconductor structure further includes a sensing circuit located on the single-crystal silicon substrate or a semiconductor substrate, the semiconductor substrate being bonded to the single-crystal silicon substrate through a dielectric material layer and bonding pads located within the dielectric material layer; and a metal interconnect structure providing an electrical connection between the second conductivity type germanium-containing region and the sensing circuit.

[0124] Further embodiments of this application provide a method for forming a photodetector, comprising: depositing and patterning a dielectric mask layer over a single-crystal silicon substrate; etching trenches in the single-crystal silicon substrate through openings in the dielectric mask layer; forming a germanium-containing well within the trenches, wherein the germanium-containing well comprises more than 50% atomic percentage of germanium; forming a silicon-containing overlay structure on the top surface of the germanium-containing well; and forming a photovoltaic junction within or across the trenches by implanting dopants of a first conductivity type and a second conductivity type. In some embodiments, dopants of the first conductivity type are implanted into a first portion of the germanium-containing well to form a first conductivity type germanium-containing region; dopants of the second conductivity type are implanted into a second portion of the germanium-containing well to form a second conductivity type germanium-containing region; and the photovoltaic junction comprises a pin junction or a pn junction formed within the germanium-containing well. In some embodiments, a dopant of the first conductivity type is implanted through the sidewalls and bottom of the trench to form a silicon region of the first conductivity type within the monocrystalline silicon substrate; a dopant of the second conductivity type is implanted into a portion of the germanium-containing well to form a germanium-containing region of the second conductivity type; and the photovoltaic junction includes a pin junction or pn junction formed across the germanium-containing well and the monocrystalline silicon substrate. In some embodiments, the germanium-containing well is formed by performing the following operations: performing an epitaxial deposition process to grow a germanium-containing material, wherein a portion of the growth of the germanium-containing material within the trench is formed to be epitaxially aligned with the monocrystalline silicon substrate within the trench; removing an excess portion of the germanium-containing material from above a horizontal plane including the top surface of the dielectric mask layer; and vertically recessing the remaining portion of the germanium-containing material within an opening in the dielectric mask layer. In some embodiments, the method further includes: forming a sensing circuit on the monocrystalline silicon substrate or on a semiconductor substrate different from the monocrystalline silicon substrate; and electrically connecting the second conductivity type germanium-containing region and the sensing circuit by forming a metal interconnect structure on the second conductivity type germanium-containing region and the sensing circuit.

[0125] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor structure including a photodetector, wherein, The photodetector includes: A germanium-containing trap, embedded in a monocrystalline silicon substrate and extending to a proximal horizontal surface of the monocrystalline silicon substrate, wherein the germanium-containing trap comprises greater than 50% atomic percentage of germanium; and A silicon-containing overlay structure is located on the top surface of the germanium-containing trap and comprises more than 42% atomic percentage of silicon atoms. in: The germanium-containing well includes a photovoltaic junction, and the photovoltaic junction includes a first conductivity type germanium-containing region and a second conductivity type germanium-containing region. The silicon-containing overlay structure includes: A silicon region of the first conductivity type is in contact with a germanium-containing region of the first conductivity type; and The silicon region of the second conductivity type is in contact with the germanium-containing region of the second conductivity type.

2. The semiconductor structure according to claim 1, wherein: The photovoltaic junction includes a pin junction; and The germanium-containing trap includes an intermediate germanium-containing region having a density between 1.0 x 10⁻⁶. 13 / cm 3 Up to 1.0x 10 17 / cm 3 The dopant atom concentration is within the range of [specific range], and it is in contact with the first conductivity type germanium-containing region and the second conductivity type germanium-containing region.

3. The semiconductor structure according to claim 1, further comprising: A single-crystal silicon pad laterally surrounds the germanium-containing well and is epitaxially aligned with the single-crystal silicon substrate.

4. The semiconductor structure according to claim 3, wherein, The silicon-containing overlay structure includes a passivated silicon region, the passivated silicon region having a size between 1.0 x 10⁻⁶. 13 / cm 3 Up to 1.0x 10 17 / cm 3 The dopant atom concentration is within the range of the first conductivity type silicon region and the second conductivity type silicon region.

5. The semiconductor structure according to claim 1, wherein, The germanium-containing well comprises a single-crystal germanium-containing semiconductor material epitaxially aligned with the single-crystal silicon substrate.

6. The semiconductor structure according to claim 1, wherein: The proximal surface of the silicon-containing capping structure is in contact with the germanium-containing trap; and The distal surface of the silicon-containing overlay structure is vertically spaced from the horizontal plane that includes the proximal horizontal surface of the monocrystalline silicon substrate.

7. The semiconductor structure according to claim 1, wherein: The photovoltaic junction includes a pn junction; and The first conductive type germanium-containing region is in contact with the second conductive type germanium-containing region.

8. The semiconductor structure according to claim 1, further comprising: The sensing circuit includes a field-effect transistor located on the monocrystalline silicon substrate; as well as A dielectric material layer is located on the near-side horizontal surface of the single-crystal silicon substrate and contains a metal interconnect structure. The subset of the metal interconnect structure provides a conductive path between the germanium-containing region of the second conductivity type and the source / drain region of one of the field-effect transistors.

9. The semiconductor structure according to claim 1, further comprising: A first dielectric material layer is located on the near-side horizontal surface of the single-crystal silicon substrate and contains a first metal interconnect structure and a first bonding pad. A semiconductor die includes a semiconductor substrate, a sensing circuit including a field-effect transistor located on the semiconductor substrate, and a second dielectric material layer located on the semiconductor substrate, the second dielectric material layer including a second metal interconnect structure and a second bonding pad. The second bonding pad is bonded to a corresponding first bonding pad in the first bonding pad, and a subset of the first metal interconnect structure and the second metal interconnect structure provide a conductive path between the germanium-containing region of the second conductivity type and the source / drain region in a field-effect transistor of the sensing circuit.

10. A semiconductor structure including a photodetector, the photodetector comprising: A germanium-containing trap, embedded within a monocrystalline silicon substrate and extending to a proximal horizontal surface of the monocrystalline silicon substrate, wherein the germanium-containing trap comprises greater than 50% atomic percentage of germanium, and wherein the germanium-containing trap comprises a photovoltaic junction; and A silicon-containing overlay structure is located on the top surface of the germanium-containing trap and comprises more than 42% atomic percentage of silicon atoms. in: The monocrystalline silicon substrate surrounding a portion of the germanium-containing well includes a silicon region of a first conductivity type; and The germanium-containing well includes a germanium-containing region of a second conductivity type and an intermediate germanium-containing region in contact with the germanium-containing region of the second conductivity type.

11. The semiconductor structure according to claim 10, wherein: The photovoltaic junction includes a pin junction; and The intermediate germanium-containing region has a density between 1.0 x 10⁻⁶. 13 / cm 3 Up to 1.0x 10 18 / cm 3 The dopant atom concentration is within a certain range and is laterally surrounded by the silicon region of the first conductivity type.

12. The semiconductor structure according to claim 10, further comprising: A single-crystal silicon pad contacts the inner wall of the first conductivity type silicon region, laterally surrounds the germanium-containing trap, and is epitaxially aligned with the single-crystal silicon substrate.

13. The semiconductor structure according to claim 12, wherein, The germanium-containing well comprises a single-crystal germanium-containing semiconductor material epitaxially aligned with the single-crystal silicon pad and the single-crystal silicon substrate.

14. The semiconductor structure according to claim 10, wherein, The first conductivity type silicon region continuously surrounds the germanium-containing well and includes a first horizontal extension and a second horizontal extension. The first horizontal extension is in contact with the bottom surface of the germanium-containing well, and the second horizontal extension extends outward from the germanium-containing well below the near-side horizontal surface of the single-crystal silicon substrate.

15. The semiconductor structure according to claim 10, further comprising: A sensing circuit is located on the monocrystalline silicon substrate or a semiconductor substrate, wherein the semiconductor substrate is bonded to the monocrystalline silicon substrate through a dielectric material layer and bonding pads located within the dielectric material layer. as well as A metal interconnect structure provides an electrical connection between the germanium-containing region of the second conductivity type and the sensing circuit.

16. A method for forming a photodetector, comprising: A dielectric mask layer is deposited and patterned on a single-crystal silicon substrate; Trenches are etched in the single-crystal silicon substrate through openings in the dielectric mask layer; A germanium-containing trap is formed within the trench, wherein the germanium-containing trap comprises more than 50% atomic percentage of germanium; A silicon-containing overlay structure is formed on the top surface of the germanium-containing trap; and A photovoltaic junction is formed in the trench by injecting dopants of a first conductivity type and a second conductivity type.

17. The method of claim 16, wherein: A dopant of the first conductivity type is implanted into the first portion of the germanium-containing well to form a germanium-containing region of the first conductivity type; The second conductivity type dopant is implanted into the second portion of the germanium-containing well to form a germanium-containing region of the second conductivity type; and The photovoltaic junction includes a pin junction or a pn junction formed within the germanium-containing trap.

18. The method of claim 16, wherein: The silicon-containing overlay structure includes a passivated silicon region, the passivated silicon region having a size between 1.0 x 10⁻⁶. 13 / cm 3 Up to 1.0x 10 17 / cm 3 The dopant atom concentration within the range.

19. The method of claim 16, wherein, The germanium-containing trap is formed by performing the following operations: An epitaxial deposition process is performed to grow a germanium-containing material, wherein a portion of the growth of the germanium-containing material within the trench is formed to be epitaxially aligned with the single-crystal silicon substrate within the trench; Remove excess of the germanium-containing material from above the horizontal plane including the top surface of the dielectric mask layer; The remaining portion of the germanium-containing material is vertically recessed within the opening in the dielectric mask layer.

20. The method of claim 16, further comprising: The sensing circuit is formed on the single-crystal silicon substrate or on a semiconductor substrate different from the single-crystal silicon substrate; as well as The second conductivity type germanium-containing region is electrically connected to the sensing circuit by forming a metal interconnect structure on the second conductivity type germanium-containing region and the sensing circuit.

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