MTJ memory device and method for forming the same, and method for forming a memory device

Abstract

A magnetic tunnel junction (MTJ) memory cell and a metal etch mask portion are formed above a substrate. At least one dielectric etch stop layer is deposited above the metal etch mask portion, and a via-level dielectric layer is deposited above the at least one dielectric etch stop layer. A via cavity can be etched through the via-level dielectric layer, and a top surface of at least one dielectric etch stop layer is physically exposed. The via cavity can be vertically extended by removing portions of at least one dielectric etch stop layer and the metal etch mask portion. A contact via structure is formed directly on a top surface of a top electrode located in the via cavity to provide a low resistance contact to the top electrode. Embodiments of the present application also relate to MTJ memory devices, methods of forming the same, and methods of forming memory devices.

Description

Technical Field

[0001] Embodiments of the present application relate to an MTJ memory device and a method of forming the same, and a method of forming the memory device. Background Art

[0002] A magnetic tunnel junction (MTJ) device consists of two layers of ferromagnetic material separated by a thin insulating or dielectric layer. By providing a sufficiently thin (usually a few nanometers) insulating or dielectric layer, electrons can tunnel from one ferromagnetic layer through the insulating / dielectric layer to the other ferromagnetic layer. The directions of the two magnetizations of the ferromagnetic layers can be controlled individually by an external magnetic field. If the magnetizations are oriented in parallel, the electrons will tunnel through the insulating / dielectric layer. If the magnetizations are oriented in the opposite (antiparallel) direction, the electrons will not tunnel through the insulating / dielectric layer. Therefore, this junction device can switch between two states of resistance, one with low resistance and the other with very high resistance. These two states allow the MTJ device to be used as a memory cell. The electrodes of the MTJ memory cell in the back-end process level can be electrically connected to the front-end process level drive circuit through a metal interconnect structure. Summary of the invention

[0003] Some embodiments of the present application provide a method for forming a magnetic tunnel junction memory device, comprising: forming a magnetic tunnel junction (MTJ) memory cell and a metal etching mask portion above a substrate, wherein the magnetic tunnel junction memory cell includes a bottom electrode, a magnetic tunnel junction structure, and a top electrode, and the metal etching mask portion is located above the top electrode; forming at least one dielectric etch stop layer above the metal etching mask portion; forming a via-level dielectric layer above the at least one dielectric etch stop layer; forming a via cavity through the via-level dielectric layer, wherein the top surface of the at least one dielectric etch stop layer is physically exposed; vertically extending the via cavity by removing portions of the at least one dielectric etch stop layer and the metal etching mask portion; and forming a contact via structure directly on the top surface of the top electrode in the via cavity.

[0004] Some other embodiments of the present application provide a method for forming a memory device, comprising: depositing a layer stack including a bottom electrode material layer, a memory material layer, a top electrode material layer and a metal etching mask material layer over a substrate; patterning the layer stack into an array of memory cells and an array of metal etching mask portions, wherein each of the memory cells includes a bottom electrode, a memory material stack and a top electrode, and each of the metal etching mask portions is a patterned portion of the metal etching mask material layer located above a corresponding one of the memory cells; depositing a via-level dielectric layer over the array of metal etching mask portions; etching an array of via cavities through the via-level dielectric layer, wherein a top surface of the metal etching mask portion is physically exposed beneath the array of via cavities; removing the array of metal etching mask portions, wherein a top surface of the top electrode is physically exposed beneath the array of via cavities; and forming an array of contact via structures on the top surface of the top electrode located in the array of via cavities.

[0005] Still other embodiments of the present application provide a magnetic tunnel junction memory device, comprising: a magnetic tunnel junction (MTJ) memory cell array located above a substrate; a dielectric spacer array, wherein each dielectric spacer selected from the dielectric spacer array laterally surrounds and contacts the sidewalls of a corresponding one of the magnetic tunnel junction memory cells and protrudes above a horizontal plane including the topmost surface of the magnetic tunnel junction memory cells; a memory-level dielectric layer embedded in the dielectric spacer array and the magnetic tunnel junction memory cell array; a via-level dielectric layer located above the memory-level dielectric layer; and an array of contact via structures embedded in the via-level dielectric layer, wherein each of the contact via structures includes an upper portion embedded in the via-level dielectric layer and a downwardly protruding portion of a sidewall of a corresponding one of the dielectric spacers contacting the dielectric spacers and a top electrode of a corresponding one of the magnetic tunnel junction memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 is a vertical cross-sectional view of an exemplary structure after forming a complementary metal oxide semiconductor (CMOS) transistor and a metal interconnect structure formed in a dielectric material layer in accordance with an embodiment of the present invention.

[0008] Figure 2is a vertical cross-sectional view of an exemplary structure after forming an array of connecting via structures according to an embodiment of the present invention.

[0009] Figure 3 is a vertical cross-sectional view of an exemplary structure after forming a bottom electrode material layer, a nonmagnetic metal buffer layer, a synthetic antiferromagnetic layer, a nonmagnetic tunnel barrier layer, a free magnetization layer, a top electrode material layer, and a metal etching mask material layer according to an embodiment of the present invention.

[0010] Figure 4 is a vertical cross-sectional view of an exemplary structure after patterning a metal etch mask material layer into a metal etch mask portion in accordance with an embodiment of the present invention.

[0011] Figure 5 is a vertical cross-sectional view of an exemplary structure after forming a memory cell array and a metal etch stop portion array in accordance with an embodiment of the present invention.

[0012] Figure 6 is a vertical cross-sectional view of an exemplary structure after forming a partial array of inner dielectric spacers in accordance with an embodiment of the present invention.

[0013] Figure 7 is a vertical cross-sectional view of an exemplary structure after forming a partial array of outer dielectric spacers in accordance with an embodiment of the present invention.

[0014] Figure 8 is a vertical cross-sectional view of an exemplary structure after forming a memory level dielectric layer in accordance with an embodiment of the present invention.

[0015] Fig. 9 is a vertical cross-sectional view of an exemplary structure after forming a dielectric etch stop layer and a via-level dielectric layer in accordance with an embodiment of the present invention.

[0016] Fig.10 is a vertical cross-sectional view of an exemplary structure after depositing and patterning a via-level metal etch mask layer in accordance with an embodiment of the present invention.

[0017] Fig.11 is a vertical cross-sectional view of an exemplary structure after forming a through via cavity array according to an embodiment of the present invention.

[0018] Fig.12 is a vertical cross-sectional view of the exemplary structure after etching through the physically exposed portion of the second dielectric etch stop layer in accordance with an embodiment of the present invention.

[0019] Fig.13 is a vertical cross-sectional view of the exemplary structure after etching through the physically exposed portion of the first dielectric etch stop layer in accordance with an embodiment of the present invention.

[0020] Fig.14 is a vertical cross-sectional view of an exemplary structure after removing a metal etch mask portion according to an embodiment of the present invention.

[0021] Fig.15 is a vertical cross-sectional view of the exemplary structure after depositing a metal barrier layer and a metal fill material layer in and over the via cavity in accordance with an embodiment of the present invention.

[0022] Fig.16 is a vertical cross-sectional view of an exemplary structure after forming an array of contact via structures according to an embodiment of the present invention.

[0023] Fig.17A is a vertical cross-sectional view of an exemplary structure after forming a line-level dielectric layer and a metal line structure in accordance with an embodiment of the present invention.

[0024] Fig. 17B is perpendicular to Fig.17A The vertical cross-section of the plane is perpendicular to the Fig.17A Another vertical cross-sectional view of an exemplary structure of .

[0025] Fig.18 is a vertical cross-sectional view of a first alternative embodiment of the exemplary structure after physically exposing a top surface of a metal etch mask portion underlying the array of via cavities in accordance with an embodiment of the present invention.

[0026] Fig.19 is a vertical cross-sectional view of a first alternative embodiment of an exemplary structure after removal of a metal etch mask portion in accordance with an embodiment of the present invention.

[0027] Fig. 20 is a vertical cross-sectional view of a first alternative embodiment of an exemplary structure after forming a line-level dielectric layer and a metal line structure in accordance with an embodiment of the present invention.

[0028] Fig.21 is a vertical cross-sectional view of a second alternative embodiment of the exemplary structure after physically exposing a top surface of a metal etch mask portion underlying the array of via cavities in accordance with an embodiment of the present invention.

[0029] Fig. 22 is a vertical cross-sectional view of a second alternative embodiment of the exemplary structure after forming a line-level dielectric layer and a metal line structure in accordance with an embodiment of the present invention.

[0030] Fig.23 is a first flow chart showing the general processing steps of the method of the present invention.

[0031] Fig.24 is a second flow chart showing the general processing steps of the method of the present invention. DETAILED DESCRIPTION

[0032] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0033] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0034] Some types of semiconductor memory cells, such as magnetic tunnel junction memory cells, use a top electrode that includes an etch-resistant metal material, such as a metal nitride material. Such etch-resistant metal materials tend to have a high resistivity and increase the contact resistance to the memory cell. In general, the structures and methods of the present invention can be used to form memory cells and / or memory cell arrays. Specifically, the structures and methods of the present invention can be used to form magnetic tunnel junction memory cells and / or magnetic tunnel junction memory cell arrays. Although the present invention is described using an exemplary structure including a magnetic tunnel junction memory cell, the methods of the present invention can be used to form any memory cell or any memory cell array that includes a vertical stack of patterned material portions that constitute the memory cell and includes a top electrode.

[0035] Integrated circuit and discrete device designs seek to minimize size, power consumption, while maximizing speed and performance. As device sizes become smaller and smaller, it becomes difficult to form contact via structures on memory cells without electrical shorts (i.e., accidental electrical connections of structures and nodes). In many embodiments, the contact via structure may have a lateral dimension larger than the lateral dimension of the top electrode of the memory cell. In embodiments utilizing a magnetic tunnel junction memory cell, a metal etching mask portion located above the top electrode may be used as an etching mask for patterning various layers within the memory cell. For example, a conductive metal nitride material such as TiN, TaN, or WN may be used as an etching mask material for patterning various material layers within a magnetic tunnel junction memory cell. Although effectively used as an etching mask material, such a conductive metal nitride material has a higher resistivity than an elemental metal such as W, Co, Cu, Mo, or Ru. Therefore, such a metal etching mask portion may interfere with or provide an undesirable resistance at the electrode location. Embodiments of the present invention provide for removing the metal etching mask portion after patterning the memory cell and before forming the contact via structure. Therefore, the contact via structure can directly contact the top electrode of the memory cell, and a low resistance contact can be provided between the top electrode and the contact via structure. In addition, the contact via structure of the present invention can be self-aligned with the top electrode below, thereby reducing and / or avoiding undesired electrical connection between the contact via structure and the components of the memory cell located below the top electrode. Various aspects of embodiments of the present invention are now described with reference to the accompanying drawings.

[0036] It should be understood that the memory device according to the embodiments of the present invention may include a single discrete memory cell, a one-dimensional memory cell array, or a two-dimensional memory cell array. It should also be understood that the one-dimensional memory cell array of the present invention may be implemented as a periodic one-dimensional memory cell array, and the two-dimensional memory cell array of the present invention may be implemented as a periodic two-dimensional memory cell array. In addition, although the present invention is described using an embodiment in which a two-dimensional memory cell array is formed within a specific metal interconnect layer, embodiments in which a two-dimensional memory cell array is formed within different metal interconnect layers are explicitly contemplated herein.

[0037] refer to Figure 1 , showing an exemplary structure according to an embodiment of the present invention. Figure 1is a vertical cross-sectional view of an exemplary structure after forming a complementary metal oxide semiconductor (CMOS) transistor and a metal interconnect structure formed in a dielectric material layer according to an embodiment of the present invention. The exemplary structure includes a substrate 9, which can be a semiconductor substrate, such as a commercial silicon substrate. A shallow trench isolation structure 720 including a dielectric material such as silicon oxide can be formed in the upper portion of the substrate 9. Suitable doped semiconductor wells, such as p-type wells and n-type wells, can be formed in each region laterally surrounded by a portion of the shallow trench isolation structure 720. Field effect transistors can be formed above the top surface of the substrate 9. For example, each field effect transistor can include a source region 732, a drain region 738, a semiconductor channel 735, and a gate structure 750, the semiconductor channel 735 including a surface portion of the substrate 9 extending between the source region 732 and the drain region 738. Each gate structure 750 can include a gate dielectric 752, a gate electrode 754, a gate cap dielectric 758, and a dielectric gate spacer 756. A source-side metal semiconductor alloy region 742 may be formed on each source region 732 , and a drain-side metal semiconductor alloy region 748 may be formed on each drain region 738 .

[0038] The exemplary structure may include a memory array region 100 in which a memory element array is subsequently formed, and a logic region 200 in which logic devices supporting the operation of the memory element array are formed. In one embodiment, the devices (such as field effect transistors) in the memory array region 100 may include a bottom electrode access transistor that provides access to the bottom electrode of the memory cell to be formed subsequently. In this processing step, a top electrode access transistor that provides access to the top electrode of the memory cell to be formed subsequently may be formed in the logic region 200. The devices (such as field effect transistors) in the logic region 200 may provide the functions required to operate the memory cell array to be formed subsequently. Specifically, the devices in the logic region may be configured to control the programming operation, the erasing operation, and the sensing (reading) operation of the memory cell array. For example, the devices in the logic region may include a sensing circuit and / or a top electrode bias circuit. The devices formed on the top surface of the substrate 9 may include complementary metal oxide semiconductor (CMOS) transistors and optionally additional semiconductor devices (such as resistors, diodes, capacitors, etc.), and are collectively referred to as CMOS circuits 700.

[0039] Various metal interconnect structures formed in the dielectric material layer may then be formed over the substrate 9 and devices such as field effect transistors. The dielectric material layer may include, for example, a contact-level dielectric material layer 601, a first metal line-level dielectric material layer 610, a second line and via-level dielectric material layer 620, a third line and via-level dielectric material layer 630, and a fourth line and via-level dielectric material layer 640. The metal interconnect structure may include a device contact via structure 612 formed in the contact-level dielectric layer 601 and contacting respective components of the CMOS circuit 700, a first metal line structure 618 formed in the first metal line-level dielectric layer 610, a first metal via structure 622 formed in a lower portion of the second line-and-via-level dielectric layer 620, a second metal line structure 628 formed in an upper portion of the second line-and-via-level dielectric layer 620, a second metal via structure 632 formed in a lower portion of the third line-and-via-level dielectric layer 630, a third metal line structure 638 formed in an upper portion of the third line-and-via-level dielectric layer 630, a third metal via structure 642 formed in a lower portion of the fourth line-and-via-level dielectric layer 640, and a fourth metal line structure 648 formed in an upper portion of the fourth line-and-via-level dielectric layer 640. In one embodiment, the second metal line structure 628 may include a source line connected to a source-side power supply for the memory element array. A voltage provided by the source line may be applied to the bottom electrode through an access transistor provided in the memory array region 100 .

[0040] Each of the dielectric material layers (601, 610, 620, 630, 640) may include a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) may include at least one conductive material, which may be a combination of a metal liner layer (such as a metal nitride or a metal carbide) and a metal filler material. Each metal liner layer may include TiN, TaN, WN, TiC, TaC, and WC, and each metal filler material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable materials within the scope of the disclosure may also be used. In one embodiment, the first metal via structure 622 and the second metal line structure 628 may be formed as an integrated line and via structure by a dual damascene process, the second metal via structure 632 and the third metal line structure 638 may be formed as an integrated line and via structure, and / or the third metal via structure 642 and the fourth metal line structure 648 may be formed as an integrated line and via structure. Although the present invention is described using an embodiment in which a memory cell array is formed above the fourth line and via level dielectric material layer 640, embodiments in which the memory cell array may be formed at different metal interconnect layers are expressly contemplated herein.

[0041] A dielectric cap layer 108 and a connecting via level dielectric layer 110 may be sequentially formed over the metal interconnect structures and dielectric material layers. For example, a dielectric cap layer 108 may be formed on a top surface of the fourth metal line structure 648 and on a top surface of the fourth line and via level dielectric material layer 640. The dielectric cap layer 108 includes a dielectric capping material that may protect underlying metal interconnect structures such as the fourth metal line structure 648. In one embodiment, the dielectric cap layer 108 may include a material that may provide high etch resistance (i.e., a dielectric material) and may also be used as an etch stop material during a subsequent anisotropic etch process for etching the connecting via level dielectric layer 110. For example, the dielectric cap layer 108 may include silicon carbide or silicon nitride and may have a thickness in the range of 5 nm to 30 nm, although lesser and greater thicknesses may also be used.

[0042] The connecting via level dielectric layer 110 may include any material that may be used for the dielectric material layers (601, 610, 620, 630, 640). For example, the connecting via level dielectric layer 110 may include undoped silicate glass or doped silicate glass deposited by decomposing tetraethyl orthosilicate (TEOS). The thickness of the connecting via level dielectric layer 110 may be in the range of 50 nm to 200 nm, although lesser and greater thicknesses may also be used. The dielectric cap layer 108 and the connecting via level dielectric layer 110 may be formed as a planar blanket layer (unpatterned) having a respective planar top surface and a respective planar bottom surface extending throughout the memory array region 100 and the logic region 200.

[0043] Figure 2 is a vertical cross-sectional view of an exemplary structure after forming an array of connecting via structures according to an embodiment of the present invention. Figure 2 , a through-hole cavity can be formed through the connecting via-level dielectric layer 110 and the dielectric cap layer 108. For example, a photoresist layer (not shown) can be applied and patterned above the connecting via-level dielectric layer 110 to form an opening in the area of ​​the memory array region 100 located above a corresponding one of the fourth metal line structures 648. Anisotropic etching can be implemented to transfer the pattern in the photoresist layer by connecting the via-level dielectric layer 110 and the dielectric cap layer 108. The through-hole cavity formed by the anisotropic etching process is referred to as the lower electrode contact through-hole cavity here, because the bottom electrode connection through-hole structure is subsequently formed in the lower electrode contact through-hole cavity. The lower electrode contact through-hole cavity can have a tapered sidewall having a taper angle (relative to the vertical direction) in the range of 1 degree to 10 degrees. The top surface of the fourth metal line structure 648 can be physically exposed at the bottom of each lower electrode contact through-hole cavity. The photoresist layer can then be removed, for example, by ashing.

[0044] The metal barrier layer can be formed as a material layer. The metal barrier layer can cover the physically exposed top surface of the fourth metal line structure 648, the tapered sidewalls of the lower electrode contact via cavity, and the top surface of the via-level dielectric layer 110 without any holes passing therethrough. The metal barrier layer can include a conductive metal nitride, such as TiN, TaN and / or WN. Other suitable materials within the scope of the disclosure may also be used. The thickness of the metal barrier layer may be in the range of 3nm to 20nm, but smaller and larger thicknesses may also be used.

[0045] A metal fill material such as tungsten or copper may be deposited in the remaining volume of the lower electrode contact via. Portions of the metal fill material and the metal barrier layer located at a horizontal plane including the topmost surface of the connecting via level dielectric layer 110 may be removed by a planarization process such as chemical mechanical planarization. Each remaining portion of the metal fill material located in a corresponding via cavity includes a metal via fill material portion 124. Each remaining portion of the metal barrier layer located in a corresponding via cavity includes a metal barrier layer 122. Each combination of the filled via cavity of the metal barrier layer 122 and the metal fill material portion 124 constitutes a connecting via structure (122, 124). An array of connecting via structures (122, 124) may be formed in the connecting via level dielectric layer 110 on the underlying metal interconnect structure.

[0046] Figure 3 is a vertical cross-sectional view of an exemplary structure after forming a bottom electrode material layer, a nonmagnetic metal buffer layer, a synthetic antiferromagnetic layer, a nonmagnetic tunnel barrier layer, a free magnetization layer, a top electrode material layer, and a metal etching mask material layer according to an embodiment of the present invention. Figure 3 , a layer stack may be formed above the metal barrier layer and the metal via filling material portion 124, the layer stack including a bottom electrode material layer 126L, a non-magnetic metal buffer material layer 130L, a synthetic antiferromagnetic layer 140L, a non-magnetic tunnel barrier material layer 146L, a free magnetization material layer 148L, a top electrode material layer 158L, and a metal etching mask material layer 159L. The layers within the layer stack may be deposited by a corresponding chemical vapor deposition process or a corresponding physical vapor deposition process. Each layer within the layer stack may be deposited as a planar blanket material layer that always has a corresponding uniform thickness. The non-magnetic metal buffer material layer 130L, the synthetic antiferromagnetic layer 140L, the non-magnetic tunnel barrier material layer 146L, and the free magnetization material layer 148L are collectively referred to as a memory material layer. In other words, a memory material layer is formed between the bottom electrode material layer 126L and the top electrode material layer 158L.

[0047] Although the present invention is described using an embodiment in which the memory material layer includes a nonmagnetic metal buffer material layer 130L, a synthetic antiferromagnetic layer 140L, a nonmagnetic tunnel barrier material layer 146L, and a free magnetization material layer 148L, the method and structure of the present invention can be applied to any structure in which the memory material layer includes a stack of different layers provided between the bottom electrode material layer 126L and the top electrode material layer 158L and includes a material layer that can store information in any manner. Modifications of the present invention are expressly contemplated herein in which the memory material layer includes a phase change memory material, a ferroelectric memory material, or a vacancy modulation conductive oxide material.

[0048] The bottom electrode material layer 126L includes at least one non-magnetic metal material, such as TiN, TaN, WN, W, Cu, Al, Ti, Ta, Ru, Co, Mo, Pt, their alloys and / or their combinations. Other suitable materials within the scope of public considerations may also be used. For example, the bottom electrode material layer 126L may include and / or may be substantially composed of elemental metals such as W, Cu, Ti, Ta, Ru, Co, Mo or Pt. The thickness of the bottom electrode material layer 126L may be in the range of 10nm to 100nm, but smaller and larger thicknesses may also be used.

[0049] The non-magnetic metal buffer material layer 130L includes a non-magnetic material that can be used as a seed layer. Specifically, the non-magnetic metal buffer material layer 130L can provide a template crystal structure that aligns the polycrystalline grains of the material of the synthetic antiferromagnetic layer 140L in a direction that maximizes the magnetization of the reference layer in the synthetic antiferromagnetic layer 140L. The non-magnetic metal buffer material layer 130L may include Ti, CoFeB alloy, NiFe alloy, ruthenium, or a combination thereof. The thickness of the non-magnetic metal buffer material layer 130L can be in the range of 3nm to 30nm, but smaller and larger thicknesses can also be used.

[0050] The synthetic antiferromagnet (SAF) layer 140L may include a layer stack of a ferromagnetic hard layer 141, an antiferromagnetic coupling layer 142, and a reference magnetization layer 143. Each of the ferromagnetic hard layer 141 and the reference magnetization layer 143 may have a corresponding fixed magnetization direction. The antiferromagnetic coupling layer 142 provides an antiferromagnetic coupling between the magnetization of the ferromagnetic hard layer 141 and the magnetization of the reference magnetization layer 143, so that during the operation of the memory cell to be formed later, the magnetization direction of the ferromagnetic hard layer 141 and the magnetization direction of the reference magnetization layer 143 remain fixed. The ferromagnetic hard layer 141 may include a hard ferromagnetic material such as PtMn, IrMn, RhMn, FeMn, OsMn, etc. The reference magnetization layer 143 may include a hard ferromagnetic material such as Co, CoFe, CoFeB, CoFeTa, NiFe, CoPt, CoFeNi, etc. Other suitable materials within the scope of the disclosure may also be used. The antiferromagnetic coupling layer 142 may include ruthenium or iridium. The thickness of the antiferromagnetic coupling layer 142 may be selected so that the exchange interaction caused by the antiferromagnetic coupling layer 142 stabilizes the relative magnetization directions of the ferromagnetic hard layer 141 and the reference magnetization layer 143 in opposite directions, i.e., antiparallel alignment. In one embodiment, the net magnetization of the SAF layer 140L is formed by matching the magnetization of the ferromagnetic hard layer 141 with the magnetization of the reference magnetization layer 143. The thickness of the SAF layer 140L may be in the range of 5 nm to 30 nm, although smaller and larger thicknesses may also be used.

[0051] The non-magnetic tunnel barrier material layer 146L may include a tunnel barrier material, which may be an electrically insulating material having a thickness that allows electrons to tunnel. For example, the non-magnetic tunnel barrier material layer 146L may include magnesium oxide (MgO), aluminum oxide (Al2O3), aluminum nitride (AlN), aluminum oxynitride (AlON), hafnium oxide (HfO2), or zirconium oxide (ZrO2). Other suitable materials within the scope of public considerations may also be used. The thickness of the non-magnetic tunnel barrier material layer 146L may be 0.7nm to 1.3nm, but smaller and larger thicknesses may also be used.

[0052] The free magnetization material layer 148L includes a ferromagnetic material having two stable magnetization directions that are parallel or antiparallel to the magnetization direction of the reference magnetization layer 143. The free magnetization material layer 148L includes a hard ferromagnetic material such as Co, CoFe, CoFeB, CoFeTa, NiFe, CoPt, CoFeNi, etc. Other suitable materials within the scope of the disclosure may also be used. The thickness of the free magnetization material layer 148L may be in the range of 1 nm to 6 nm, but smaller and larger thicknesses may also be used.

[0053] The top electrode material layer 158L includes a top electrode material, which may include any non-magnetic material that may be used for the bottom electrode material layer 126L. Exemplary metal materials that may be used for the top electrode material layer 158L include, but are not limited to, TiN, TaN, WN, W, Cu, Al, Ti, Ta, Ru, Co, Mo, Pt, their alloys and / or their combinations. Other suitable materials within the scope of public considerations may also be used. For example, the bottom electrode material layer 126L may include and / or may be substantially composed of elemental metals such as W, Cu, Ti, Ta, Ru, Co, Mo or Pt. The thickness of the top electrode material layer 158L may be in the range of 10nm to 100nm, but smaller and larger thicknesses may also be used.

[0054] The metal etching mask material layer 159L includes a metal etching stop material that provides high resistance to an anisotropic etching process that will be used to etch dielectric materials (which may include, for example, undoped silicate glass, doped silicate glass, or organic silicate glass). In one embodiment, the metal etching mask material layer 159L may include a conductive metal nitride material (such as TiN, TaN, or WN) or a conductive metal carbide material (such as TiC, TaC, or WC). In one embodiment, the metal etching mask material layer 159L includes and / or is substantially composed of TiN. The metal etching mask material layer 159L can be deposited by chemical vapor deposition or physical vapor deposition. The thickness of the metal etching mask material layer 159 can be in the range of from 2nm to 20nm, such as from 3nm to 10nm, but smaller and larger thicknesses can also be used.

[0055] Figure 4 is a vertical cross-sectional view of an exemplary structure after patterning a metal etch mask material layer into a metal etch mask portion according to an embodiment of the present invention. Figure 4 , a photoresist layer 177 may be applied over the metal etching mask material layer 159L and may be photolithographically patterned to form an array of discrete photoresist material portions. Each discrete photoresist material portion in the array of discrete photoresist material portions may be located above a corresponding one of the connecting via structures (122, 124). In one embodiment, the connecting via structures (122, 124) may be arranged as a two-dimensional periodic array having a first spacing along a first horizontal direction and a second spacing along a second horizontal direction. The discrete photoresist material portions may be arranged as a two-dimensional periodic array having the same periodicity as the two-dimensional periodic array of the connecting via structures (122, 124).

[0056] A first anisotropic etching process may be performed to etch unmasked areas of the metal etching mask material layer 159L. The first anisotropic etching process uses the photoresist layer 177 as an etching mask, and the patterned portion of the metal etching mask material layer 159L includes the metal etching mask portion 159. The first anisotropic etching process patterns the metal etching mask material layer 159L into a two-dimensional array of metal etching mask portions 159. The two-dimensional array of metal etching mask portions 159 may replicate the pattern of the photoresist layer 177. The photoresist layer 177 may be removed after the first anisotropic etching process, or may remain on the two-dimensional array of metal etching mask portions 159 during a subsequent second anisotropic etching process.

[0057] Figure 5 is a vertical cross-sectional view of an exemplary structure after forming a memory cell array and a metal etch stop portion array according to an embodiment of the present invention. Figure 5, a second anisotropic etching process may be performed to transfer the pattern of the two-dimensional array of metal etching mask portions 159 through a layer stack, the layer stack including a top electrode material layer 158L, a free magnetization material layer 148L, a non-magnetic tunnel barrier material layer 146L, a synthetic antiferromagnetic layer 140L, a non-magnetic metal buffer material layer 130L, and a bottom electrode material layer 126L. During the second anisotropic etching process, portions (158L, 148L, 146L, 140L, 130L, 126L) of the layer stack that are not masked by the metal etching mask portions 159 are etched. In embodiments where a photoresist layer 177 is present at the start of the second anisotropic etching process, the photoresist layer 177 may be consumed in parallel during the second anisotropic etching process, and the metal etching mask portions 159 may be used as an etching mask at least during patterning of the bottom electrode material layer 126L. Alternatively, in embodiments where the photoresist layer 177 is removed prior to the second anisotropic etching process, the metal etching mask portion 159 may be used as an etching mask throughout the second anisotropic etching process.

[0058] The second anisotropic etching process may include a series of anisotropic etching steps that sequentially etch the various material layers of the underlying layer stack. In one embodiment, the patterned portion of the layer stack may include sidewalls having a non-zero taper angle, i.e., having a non-vertical surface. The taper angle may vary layer by layer, and may typically be in the range of 3 to 30 degrees, such as from 6 to 20 degrees, but smaller and larger taper angles may also be used. The unmasked portion of the connecting via-level dielectric layer 110 may be vertically recessed by the second anisotropic etching process.

[0059] The layer stack (159L, 158L, 148L, 146L, 140L, 130L, 126L) of the metal etch mask material layer 159L, the top electrode material layer 158L, the free magnetization material layer 148L, the non-magnetic tunnel barrier material layer 146L, the synthetic antiferromagnetic layer 140L, the non-magnetic metal buffer material layer 130L and the bottom electrode material layer 126L can be patterned into an array of memory cells (126, 130, 140, 146, 158) and an array of metal etch mask portions 159. Each of the memory cells (126, 130, 140, 146, 158) includes a bottom electrode 126, a memory material stack (130, 140, 146, 148) and a top electrode 158. Each of the metal etch mask portions 159 is a patterned portion of the metal etch mask material layer 159L that is located over a corresponding one of the memory cells (126, 130, 140, 146, 158).

[0060] In one embodiment, each memory cell (126, 130, 140, 146, 148, 158) may be a magnetic tunnel junction (MTJ) memory cell. Each MTJ memory cell (126, 130, 140, 146, 148, 158) may include a bottom electrode 126, a magnetic tunnel junction structure (140, 146, 148), and a top electrode 158. Each magnetic tunnel junction (140, 146, 148) may include a synthetic antiferromagnet (SAF) structure 140, a nonmagnetic tunnel barrier layer 146, and a free magnetization layer 148. A nonmagnetic metal buffer layer 130 may be provided between the bottom electrode 126 and the magnetic tunnel junction (140, 146, 148). Each bottom electrode 126 is a patterned portion of a bottom electrode material layer 126L. Each SAF structure 140 is a patterned portion of a SAF layer 140L. Each nonmagnetic tunnel barrier 146 is a patterned portion of a nonmagnetic tunnel barrier material layer 146L. Each free magnetization layer 148 is a patterned portion of a free magnetization material layer 148L. Each top electrode 158 is a patterned portion of a metal etch mask material layer 159L. In one embodiment, the metal etch mask portion 159 includes and / or consists essentially of a conductive metal nitride material such as TiN, TaN, or WN, and each of the memory cells (126, 130, 140, 146, 148, 158) includes a vertical stack that includes a synthetic antiferromagnetic structure 140, a nonmagnetic tunnel barrier layer 146, and a free magnetization layer 148.

[0061] Figure 6 is a vertical cross-sectional view of an exemplary structure after forming a partial array of inner dielectric spacers according to an embodiment of the present invention. Figure 6 A first dielectric material such as silicon nitride may be conformally deposited over the array of memory cells (126, 130, 140, 146, 148, 158) and the array of metal etch mask portions 159. For example, the first dielectric material may be deposited by a chemical vapor deposition process. The thickness of the first dielectric material above the horizontal surface may be in the range of 2nm to 20nm, such as from 4nm to 10nm, but smaller and larger thicknesses may also be used. An anisotropic etching process may be performed to remove the horizontal portion of the first dielectric material. The remaining portion of the first dielectric material includes an array of internal dielectric spacer portions 162 that laterally surround the array of memory cells (126, 130, 140, 146, 148, 158). In one embodiment, the duration of the anisotropic etching process may be selected so that the sidewalls of the array of metal etch mask portions 159 are partially or completely physically exposed. The maximum thickness of each internal dielectric spacer portion 162 may be in the range of 2nm to 20nm, such as from 4nm to 10nm, but smaller and larger thicknesses may also be used.

[0062] Figure 7 is a vertical cross-sectional view of an exemplary structure after forming a partial array of outer dielectric spacers according to an embodiment of the present invention. Figure 7 , a second dielectric material such as a dielectric metal oxide may be conformally deposited over the array of inner dielectric spacer portions 162. For example, the second dielectric material may include aluminum oxide, hafnium oxide, lanthanum oxide, or yttrium oxide, and may be deposited by a chemical vapor deposition process. The thickness of the second dielectric material above the horizontal surface may be in the range of 2nm to 20nm, such as from 4nm to 10nm, but smaller and larger thicknesses may also be used. An anisotropic etching process may be implemented to remove the horizontal portion of the second dielectric material. The remaining portion of the second dielectric material includes an array of outer dielectric spacer portions 164 surrounding the array of inner dielectric spacer portions 162. In one embodiment, the outer dielectric spacer portions 164 may be deposited directly on the sidewalls of the metal etching mask portion 159. In one embodiment, the entirety of each sidewall of the metal etching mask portion 159 may contact the corresponding outer dielectric spacer portion 164. The maximum thickness of each outer dielectric spacer portion 164 may be in the range of 2nm to 20nm, such as from 4nm to 10nm, but smaller and larger thicknesses may also be used.

[0063] Each combination of inner dielectric spacer portions 162 and outer dielectric spacer portions 164 constitutes a dielectric spacer (162, 164). The array of dielectric spacers (162, 164) laterally surrounds the array of memory cells (126, 130, 140, 146, 148, 158) and the array of metal etch mask portions 159. Although the present invention is described using an embodiment in which the dielectric spacers (162, 164) include inner dielectric spacer portions 162 and outer dielectric spacer portions 164, embodiments in which the dielectric spacers consist of either inner dielectric spacer portions 162 or outer dielectric spacer portions 164 are expressly contemplated herein. In general, the dielectric spacers (162, 164) may be formed around each metal etch mask portion 159 within the array of metal etch mask portions 159. Each dielectric spacer (162, 164) may be formed directly on and around the sidewalls of the corresponding metal etch mask portion 159.

[0064] Figure 8 is a vertical cross-sectional view of an exemplary structure after forming a memory level dielectric layer according to an embodiment of the present invention. Figure 8, a memory-level dielectric layer 170 may be formed around the array of dielectric spacers (162, 164). The memory-level dielectric layer 170 includes a planarizable dielectric material, such as undoped silicate glass or doped silicate glass. The dielectric material of the memory-level dielectric layer 170 may be deposited by a conformal deposition process, such as a chemical vapor deposition process, or a self-planarizing deposition process, such as spin coating. A chemical mechanical planarization process may be performed to remove portions of the deposited dielectric material from above a horizontal plane including the top surface of the metal etch mask portion 159. Various planarization assist structures (not shown), such as electrically isolated patterned portions of the metal etch mask material layer 159L and the underlying material layer, may be used in the logic region 200 to assist in planarizing the deposited dielectric material. After the planarization process, the remaining portion of the deposited dielectric material constitutes the memory-level dielectric layer 170. The top surface of the memory-level dielectric layer 170 may be located in the same horizontal plane as the top surface of the metal etch mask portion 159. In one embodiment, top surfaces of the dielectric spacers ( 162 , 164 ), such as the top surface of the outer dielectric spacer portion 164 , can be located in the same horizontal plane as the top surface of the memory level dielectric layer 170 .

[0065] Fig. 9 is a vertical cross-sectional view of an exemplary structure after forming a dielectric etch stop layer and a via-level dielectric layer according to an embodiment of the present invention. Fig. 9 , a first dielectric etch stop layer 172 and a second dielectric etch stop layer 174 may be sequentially deposited over the memory-level dielectric layer 170. The first dielectric etch stop layer 172 includes a dielectric material different from the dielectric material of the memory-level dielectric layer 170. In one embodiment, the memory-level dielectric layer 170 may include a silicon oxide-based dielectric material, such as undoped silicate glass or doped silicate glass, and the first dielectric etch stop layer 172 may include a silicon-containing dielectric material, such as silicon nitride, silicon oxynitride, silicon carbide, or silicon carbonitride. The first dielectric etch stop layer 172 may be deposited by a conformal or non-conformal deposition process. In one embodiment, the first dielectric etch stop layer 172 may be formed by chemical vapor deposition, atomic layer deposition, or physical vapor deposition. The thickness of the first dielectric etch stop layer 172 may be in the range of 2 nm to 20 nm, such as from 3 nm to 12 nm, but smaller and larger thicknesses may also be used.

[0066] The second dielectric etch stop layer 174 includes a dielectric material different from the dielectric material of the first dielectric etch stop layer 172. In one embodiment, the second dielectric etch stop layer 174 may include a dielectric metal oxide material, such as aluminum oxide, hafnium oxide, titanium oxide, tantalum oxide, yttrium oxide and / or lanthanum oxide. The second dielectric etch stop layer 174 may be deposited by a conformal or non-conformal deposition process. In one embodiment, the second dielectric etch stop layer 174 may be formed by chemical vapor deposition, atomic layer deposition, or physical vapor deposition. The thickness of the second dielectric etch stop layer 174 may be in the range of 2nm to 20nm, such as from 3nm to 12nm, but smaller and larger thicknesses may also be used.

[0067] The first dielectric etch stop layer 172 and the second dielectric etch stop layer 174 may then be patterned such that the first dielectric etch stop layer 172 and the second dielectric etch stop layer 174 remain in the memory array region 100 and are removed from the logic region 200. For example, a photoresist layer (not shown) may be applied over the second dielectric etch stop layer 174 and may be photolithographically patterned to cover the memory array region 100 without covering the logic region 200. An etching process, such as a wet etching process, may be performed to etch unmasked portions of the first dielectric etch stop layer 172 and the second dielectric etch stop layer 174. The photoresist layer may then be removed, for example, by ashing.

[0068] A via-level dielectric layer 176 may be formed over the dielectric etch stop layer (172, 174). The via-level dielectric layer 176 includes a dielectric material such as undoped silicate glass, doped silicate glass, or organosilicate glass. The dielectric material of the via-level dielectric layer 176 may be deposited by a conformal deposition process such as a chemical vapor deposition process or a self-planarizing deposition process such as spin coating. The thickness of the via-level dielectric layer 176 in the memory array region 100 may be in the range of 50 nm to 300 nm, such as from 80 nm to 200 nm, although lesser and greater thicknesses may also be used.

[0069] A via-level metal etch mask layer 178 may be formed over the via-level dielectric layer 176. The via-level metal etch mask layer 178 includes a metal material that may be used as an etch mask in a subsequent anisotropic etching process. For example, the via-level metal etch mask layer 178 may include a conductive metal nitride material (such as TiN, TaN, or WN) or a conductive metal carbide material (such as TiC, TaC, or WC). In one embodiment, the via-level metal etch mask layer 178 includes the same material as the metal etch mask portion 159. In one embodiment, the via-level metal etch mask layer 178 and the metal etch mask portion 159 include and / or are substantially composed of titanium nitride. The via-level metal etch mask layer 178 may be formed by chemical vapor deposition or physical vapor deposition. The thickness of the via-level metal etch mask layer 178 may be in the range of 2nm to 20nm, such as from 3nm to 10nm, but smaller and larger thicknesses may also be used.

[0070] Fig.10 is a vertical cross-sectional view of an exemplary structure after depositing and patterning a via-level metal etch mask layer in accordance with an embodiment of the present invention. Fig.10 , a photoresist layer 77 may be applied over the via-level metal etching mask layer 178 and may be photolithographically patterned to form an array of openings in the area located in the array of metal etching mask portions 159. The area of ​​each opening in the photoresist layer 77 may be greater than, less than, or equal to the area of ​​the underlying metal etching mask portion 159. The periphery of each opening in the photoresist layer 77 may be located outside the sidewalls of the underlying metal etching mask portion 159, may be located inside the sidewalls of the underlying metal etching mask portion 159, or may coincide with the sidewalls of the underlying metal etching mask portion 159 in a plan view (i.e., a view in a vertical direction). Additional openings may be formed in the photoresist layer 77 within the logic region 200. The area of ​​the openings in the photoresist layer 77 in the logic region 200 may be located above an area of ​​an underlying metal interconnect structure such as the fourth metal line structure 648.

[0071] An etching process may be performed to transfer the pattern in the photoresist layer 77 through the via-level metal etching mask layer 178. The etching process may include an anisotropic etching process or an isotropic etching process. In one embodiment, an anisotropic etching process such as a reactive ion etching process may be performed to transfer the pattern in the photoresist layer 77 through the via-level metal etching mask layer 178. The photoresist layer 77 may then be removed, for example, by ashing.

[0072] Fig.11 is a vertical cross-sectional view of an exemplary structure after forming a through-hole cavity array according to an embodiment of the present invention. Fig.11, a first anisotropic etching process may be performed using the via-level metal etching mask layer 178 as an etching mask. The first anisotropic etching process may include a reactive ion etching process that etches the dielectric material of the via-level dielectric layer 176, the memory-level dielectric layer 170, and the connecting via-level dielectric layer 110 while being selective to the material of the second dielectric etch stop layer 174 and the dielectric cap layer 108. In one embodiment, the via-level dielectric layer 176, the memory-level dielectric layer 170, and the connecting via-level dielectric layer 110 may include a silicon oxide-based dielectric material, such as undoped silicate glass, doped silicate glass, or organic silicate glass, and the first anisotropic etching process may include a reactive ion etching process that etches the silicon oxide-based dielectric material while being selective to the dielectric material of the second dielectric etch stop layer 174 and the dielectric cap layer 108.

[0073] A via cavity (179, 279) may be formed below the opening through the via-level metal etch mask layer 178. Specifically, a first via cavity 179 may be formed in the memory array region 100, extending vertically through the via-level dielectric layer 176. The top surface of the second dielectric etch stop layer 174 may be physically exposed at the bottom of each first via cavity 179. An array of first via cavities 179 may be formed above the array of memory cells (126, 130, 140, 146, 148, 158). A second via cavity 279 may be formed in the logic region 200, extending vertically through the via-level dielectric layer 176, the memory-level dielectric layer 170, and the connecting via-level dielectric layer 110. The top surface of the dielectric cap layer 108 may be physically exposed at the bottom of each second via cavity 279.

[0074] In one embodiment, each first via cavity 179 formed through the via-level dielectric layer 176 may have a lateral extent greater than the lateral extent of each metal etch mask portion 159. In one embodiment, each metal etch mask portion 159 may have a circular horizontal cross-sectional shape, an elliptical horizontal cross-sectional shape, a rectangular horizontal cross-sectional shape, or a rounded rectangular horizontal cross-sectional shape. In this embodiment, each first via cavity 179 may have a horizontal cross-sectional shape that is an enlargement of the horizontal cross-sectional shape of one of the metal etch mask portions 159. In an illustrative example, the maximum lateral dimension of each first via cavity 179 may be in the range of 100.1% to 150% of the maximum lateral dimension of one of the metal etch mask portions 159.

[0075] Fig.12 is a vertical cross-sectional view of an exemplary structure after etching through a physically exposed portion of a second dielectric etch stop layer in accordance with an embodiment of the present invention. Fig.12, the first via cavity 179 may be vertically extended by etching the physically exposed portion of the second dielectric etch stop layer 174. For example, a first wet etching process may be performed to remove the physically exposed portion of the second dielectric etch stop layer 174. For example, if the second dielectric etch stop layer 174 includes a dielectric metal oxide material, the wet etching process etches the dielectric metal oxide material while being selective to the dielectric materials of the via-level dielectric layer 176, the memory-level dielectric layer 170, the connecting via-level dielectric layer 110, the first dielectric etch stop layer 172, and the dielectric cap layer 108.

[0076] Fig.13 is a vertical cross-sectional view of an exemplary structure after etching through a physically exposed portion of a first dielectric etch stop layer in accordance with an embodiment of the present invention. Fig.13 , the first via cavity 179 and the second via cavity 279 may be vertically extended by etching the physically exposed portions of the first dielectric etch stop layer 172 and the dielectric cap layer 108. For example, a second anisotropic etching process may be performed to remove the physically exposed portions of the first dielectric etch stop layer 172 and the dielectric cap layer 108 using the via-level metal etch mask layer 178. The chemistry of the second anisotropic etching process may be selective to the materials of the metal etch mask portion 159, the outer dielectric spacer portion 164, and the memory-level dielectric layer 170. For example, the first dielectric etch stop layer 172 and the dielectric cap layer 108 may include silicon nitride, and the second anisotropic etching process may include a reactive ion etching process that etches the silicon nitride while being selective to the dielectric materials of the outer dielectric spacer portion 164 and the memory-level dielectric layer 170, and being selective to the metal material of the metal etch mask portion 159. In an illustrative example, the second anisotropic etching process may include using HBr, CF4, O2, N2, CH x F y , Ar and / or He as process gases.

[0077] The first via cavities 179 extend vertically through the via-level dielectric layer 176 and the dielectric etch stop layer (172, 174), and the sidewalls of the dielectric etch stop layer (172, 174) are physically exposed around each first via cavity 179. The top surface of the metal etch mask portion 159 may be physically exposed below the array of first via cavities 179. In one embodiment, the array of first via cavities 179 may be formed as a two-dimensional periodic array.

[0078] Fig.14 is a vertical cross-sectional view of an exemplary structure after removing a portion of a metal etch mask according to an embodiment of the present invention. Fig.14, an etching process may be performed to etch the metal material of the metal etching mask portion 159 and the via-level metal etching mask layer 178. The etching process may include an isotropic etching process. For example, a second wet etching process may be performed to remove the metal etching mask portion 159 and the via-level metal etching mask layer 178. In an embodiment where the metal etching mask portion 159 and the via-level metal etching mask layer 178 include titanium nitride, the wet etching process for etching the metal etching mask portion 159 and the via-level metal etching mask layer 178 may include a combination of nitric acid and hydrofluoric acid or an SC1 solution (a combination of ammonium hydroxide, hydrogen peroxide, and water). The metal etching mask portion 159 and the via-level metal etching mask layer 178 may be removed simultaneously by the second wet etching process.

[0079] Typically, the metal etch mask portion 159 can be removed while being selective to the materials of the top electrode 158, the external dielectric spacer portion 164, the memory level dielectric layer 170, and the via level dielectric layer 176. In other words, the etching process can be a selective etching process. In one embodiment, the metal etch mask portion 159 array and the via level metal etch mask layer 178 can include the same conductive metal nitride material and can be removed simultaneously by an etching process that can be a wet etching process. The top surface of the top electrode 158 can be physically exposed below the first via cavity 179 array. In one embodiment, the inner sidewall of each dielectric spacer (162, 164) can be physically exposed when the metal etch mask portion 159 array is removed. The top surface of the metal interconnect structure (such as the fourth metal line structure 648) can be physically exposed at the bottom of each second via cavity 279.

[0080] In one embodiment, each first via cavity 179 may have an upper portion laterally surrounded by the dielectric etch stop layer (172, 174) and the via-level dielectric layer 176, and a downwardly protruding portion laterally surrounded by the corresponding dielectric spacer (162, 164). In one embodiment, the downwardly protruding portion may have a smaller lateral dimension than the upper portion of each first via cavity 179. In this embodiment, the horizontal top surface of the dielectric spacer (162, 164) and the horizontal top surface of the optional memory-level dielectric layer 170 may be physically exposed to each first via cavity 179.

[0081] Fig.15 is a vertical cross-sectional view of an exemplary structure after depositing a metal barrier layer and a metal fill material layer in and over the via cavity according to an embodiment of the present invention. Fig.15, a metal barrier layer 82L and a metal filler material layer 84L may be sequentially deposited in and over each of the via cavities (179, 279). The metal barrier layer 82L includes a metal barrier material, i.e., a metal material that acts as a diffusion barrier. In addition, the material of the metal barrier layer 82L may enhance the adhesion of the metal filler material layer 84L to the dielectric surface surrounding the via cavity (179, 279). In one embodiment, the metal barrier layer 82L may include a metal nitride material, such as TiN, TaN, or WN. Typically, a metal nitride material has a higher resistivity than an elemental metal or an intermetallic alloy of at least two elemental metals. Therefore, the thickness of the metal barrier layer 82L may be selected to be a minimum level, as long as the metal barrier layer 82L provides sufficient adhesion and diffusion barrier properties. The thickness of the vertically extending portion of the metal barrier layer 82L may be in the range of 2nm to 12nm, such as from 3nm to 6nm, but smaller and larger thicknesses may also be used. The metal barrier layer 82L may be deposited by chemical vapor deposition or physical vapor deposition. The metal barrier layer 82L directly contacts the top surface of the top electrode 158. Therefore, there is no intervening metal barrier material between the metal barrier layer 82L and the top electrode 158.

[0082] The metal filler material layer 84L includes a metal material that provides high electrical conductivity. For example, the metal filler material layer 84L may include an elemental metal or an intermetallic alloy of at least two elemental metals. In one embodiment, the metal filler material layer 84L may include W, Cu, Co, Ru, Mo, Al, their alloys and / or their layer stacks. Other suitable materials within the scope of the disclosure may also be used. The metal filler material layer 84L may be deposited by physical vapor deposition, chemical vapor deposition, electroplating and / or chemical plating.

[0083] Fig.16 is a vertical cross-sectional view of an exemplary structure after forming an array of contact via structures according to an embodiment of the present invention. Fig.16 A chemical mechanical planarization (CMP) process may be performed to remove portions of the metal fill material layer 84L and the metal barrier layer 82L that are located above a horizontal plane including a top surface of the via-level dielectric layer 176. Each remaining portion of the metal fill material layer 84L and the metal barrier layer 82L that fills the first via cavity 179 includes a contact via structure 180. Each remaining portion of the metal fill material layer 84L and the metal barrier layer 82L that fills the second via cavity 279 includes a connection via structure 280. Each contact via structure 180 includes a corresponding metal barrier layer 182 and a corresponding metal fill material portion 184. Each connection via structure 280 includes a corresponding metal barrier layer 282 and a corresponding metal fill material portion 284. Each metal barrier layer (182, 282) is Fig.15Each metal fill material portion (184, 284) is a patterned portion of the metal barrier layer 82L deposited in the processing step of Fig.15 The top surfaces of the contact via structure 180 and the connecting via structure 280 may be located in the same horizontal plane as the top surface of the via-level dielectric layer 176 .

[0084] In general, the contact via structure 180 may be formed by depositing at least one conductive material in the first via cavity 179, and the connection via structure 280 may be formed by depositing at least one conductive material in the second via cavity 279. Each contact via structure 180 may be formed directly on the top surface of the corresponding top electrode 158 and within the corresponding first via cavity 179. An array of contact via structures 180 may be formed on the top surface of the top electrode 158 located in the array of first via cavities 179. In an embodiment where the upper portion of each first via cavity 179 has a greater lateral extent than the downwardly protruding portion of the corresponding first via cavity 179, the horizontal bottom surface of each contact via structure 180 may contact the horizontal surface of the dielectric spacer (162, 164) and / or the horizontal surface of the memory level dielectric layer 170. In one embodiment, the horizontal surface of the contact via structure 180 that contacts the dielectric spacer (162, 164) and / or the memory level dielectric layer 170 may include an annular bottom surface of the upper portion of the contact via structure 180.

[0085] Fig.17A is a vertical cross-sectional view of an exemplary structure after forming a line-level dielectric layer and a metal line structure in accordance with an embodiment of the present invention. Fig. 17B is perpendicular to Fig.17A The vertical cross-section of the plane is perpendicular to the Fig.17A Another vertical cross-sectional view of an exemplary structure of FIG. Fig.17A and Fig. 17B , a line-level dielectric layer 190 may be deposited over the via-level dielectric layer 176. The line-level dielectric layer 190 may include any interlayer dielectric (ILD) material. The thickness of the line-level dielectric layer 190 may be in the range of 100 nm to 600 nm, such as from 150 nm to 300 nm, although lesser and greater thicknesses may also be used.

[0086] A line trench may be formed through the line-level dielectric layer 190, for example, by applying and patterning a photoresist layer over the line-level dielectric layer 190, and transferring the pattern in the photoresist layer through the line-level dielectric layer 190 by performing an anisotropic etching process. The photoresist layer may then be removed, for example, by ashing. At least one contact via structure 180 and / or at least one connection via structure 280 may be physically exposed at the bottom of each line trench. At least one conductive material (such as a combination of a metal barrier material and a metal fill material) may be deposited in the line trench, and an excess portion of the at least one conductive material may be removed from above a horizontal plane including the top surface of the line-level dielectric layer 190 by a planarization process such as a chemical mechanical planarization process. The remaining portion of the filled line trench of the at least one conductive material comprises a metal line structure (192, 198). The metal line structure (192, 198) may include an array connection metal line 192 that contacts at least one of the contact via structures 180 and a logic area metal line 198 that does not directly contact the contact via structure 180. In one embodiment, the array connection metal lines 192 may include word lines or bit lines for a two-dimensional array of memory cells (126, 130, 140, 146, 148, 158).

[0087] Fig.18 is a vertical cross-sectional view of a first alternative embodiment of an exemplary structure after physically exposing a top surface of a metal etch mask portion underlying the via cavity array in accordance with an embodiment of the present invention. Fig.18 , the lateral dimension of the first through hole cavity 179 can be reduced from Fig.13 The exemplary structure of the first alternative embodiment of the exemplary structure is obtained, so that each first via cavity 179 has a lateral dimension (i.e., a maximum lateral dimension) that is smaller than the lateral dimension of the corresponding underlying metal etching mask portion 159. In this embodiment, the entire bottom surface of each first via cavity 179 can be part of the top surface of the corresponding underlying metal etching mask portion 159.

[0088] Fig.19 is a vertical cross-sectional view of a first alternative embodiment of an exemplary structure after removing a metal etch mask portion according to an embodiment of the present invention. Fig.19 , can be implemented Fig.14 The processing steps are to simultaneously remove the metal etch mask portion 159 and the via-level metal etch mask layer 178. Each first via cavity 179 can have an upper portion and a downwardly protruding portion, the downwardly protruding portion having a lateral extent greater than the upper portion. The inner sidewalls of the dielectric spacers (162, 164) can be physically exposed around the downwardly protruding portion of the first via cavity 179. The top surface of the top electrode 158 is physically exposed at the bottom of each first via cavity 179.

[0089] Fig. 20is a vertical cross-sectional view of a first alternative embodiment of an exemplary structure after forming a line-level dielectric layer and a metal line structure according to an embodiment of the present invention. Fig. 20 , can be implemented Figures 15 to 17B Each contact via structure 180 may have an upper portion and a downwardly protruding portion. The upper portion of each contact via structure 180 has a smaller lateral extent than the downwardly protruding portion of the contact via structure 180. The horizontal bottom surface of each contact via structure 180 may contact a horizontal surface of a dielectric etch stop layer, such as a horizontal surface of the first dielectric etch stop layer 172. In one embodiment, the horizontal surface of the contact via structure 180 that contacts the first dielectric etch stop layer 172 may include an annular top surface of the downwardly protruding portion of the contact via structure 180.

[0090] Fig.21 is a vertical cross-sectional view of a second alternative embodiment of the exemplary structure after physically exposing a top surface of a portion of the metal etch mask beneath the array of via cavities in accordance with an embodiment of the present invention. Fig.21 , the lateral dimension of the first through hole cavity 179 can be reduced from Fig.13 The exemplary structure of the second alternative embodiment of the exemplary structure is obtained, so that each first via cavity 179 has the same lateral dimension (i.e., the maximum lateral dimension) as the corresponding underlying metal etching mask portion 159. In this embodiment, the bottom periphery of the first via cavity 179 can coincide with the periphery of the top surface of the underlying metal etching mask portion 159.

[0091] Fig. 22 is a vertical cross-sectional view of a second alternative embodiment of an exemplary structure after forming a line-level dielectric layer and a metal line structure according to an embodiment of the present invention. Fig. 22 , can be implemented Figures 15 to 17B Each contact via structure 180 may have an upper portion and a downwardly protruding portion having the same lateral extent as the upper portion. The upper portion of each contact via structure 180 may be located above a horizontal plane including the top surface of the memory-level dielectric layer 170, and the downwardly protruding portion of each contact via structure 180 may be located below a horizontal plane including the top surface of the memory-level dielectric layer 170.

[0092] refer to Fig.23 , the first flow chart shows the general processing steps of the method of the present invention for forming a single magnetic tunnel junction memory cell (126, 130, 140, 146, 148, 258) and its contact via structure 180. A magnetic tunnel junction memory device can be formed by this method. Referring to steps 2310 and Figures 1 to 5, a magnetic tunnel junction (MTJ) memory cell (126, 130, 140, 146, 148, 258) and a metal etching mask portion 159 can be formed over the substrate 9. The MTJ memory cell (126, 130, 140, 146, 148, 258) includes a bottom electrode 126, a magnetic tunnel junction structure (140, 146, 148) and a top electrode 158, and the metal etching mask portion 159 is located above the top electrode. Referring to steps 2320 and Figures 6 to 9 At least one dielectric etch stop layer (172, 174) may be deposited over the metal etch mask portion 159. Referring to steps 2330 and Fig. 9 , a via-level dielectric layer 176 may be deposited over at least one dielectric etch stop layer (172, 174). Referring to steps 2340 and Fig.10 and Fig.11 , a via cavity 179 may be etched through the via-level dielectric layer 176. A top surface of at least one dielectric etch stop layer (172, 174) is physically exposed below the via cavity 179. Referring to step 2350 and Figure 12 to Figure 14 , Fig.18 , Fig.19 and Fig.21 , the via cavity 179 may be vertically extended by removing at least a portion of the dielectric etch stop layer (172, 174) and the metal etch mask portion 159. Referring to step 2360 and Figures 16 to 17B , Fig. 20 and Fig. 22 , a contact via structure 180 may be formed directly on the top surface of the top electrode 158 located in the via cavity 179 .

[0093] refer to Fig.24 The second flow chart shows the general processing steps of the method for forming a memory device of the present invention. Referring to steps 2410 and Figures 1 to 3 , a layer stack including a bottom electrode material layer 126L, memory material layers (130L, 140L, 146L, 148L), a top electrode material layer 158L, and a metal etching mask material layer 159L is formed over the substrate 9. Referring to step 2420 and Figure 4 and Figure 5, patterning the layer stack (126L, 130L, 140L, 146L, 148L, 159L, 159L) into an array of memory cells (126, 130, 140, 146, 148, 158) and an array of metal etch mask portions 159. Each of the memory cells (126, 130, 140, 146, 148, 158) includes a bottom electrode 126, a memory material layer stack (130, 140, 146, 148), and a top electrode 158. Each of the metal etch mask portions 159 is a patterned portion of the metal etch mask material layer 159L that is located above a corresponding one of the memory cells (126, 130, 140, 146, 148, 158). Referring to steps 2430 and Figures 6 to 9 , depositing a via-level dielectric layer 176 over the array of metal etch mask portions 159. Referring to steps 2440 and Fig.10 and Fig.11 , an array of via cavities 179 is etched through the via-level dielectric layer 176. The top surface of the metal etch mask portion 159 is physically exposed below the array of via cavities 179. Referring to step 2450 and Fig.12 , Fig.14 , Fig.18 , Fig.19 and Fig.21 , removing the metal etch mask portion 159 array. The top surface of the top electrode 158 is physically exposed below the array of via cavities 179. Referring to step 2460 and Figures 16 to 17B , Fig. 20 and Fig. 22 , an array of contact via structures 180 are formed on the top surface of the top electrode 158 located in the array of via cavities 179 .

[0094] According to another aspect of the present invention, a method for forming a semiconductor device is provided, the method comprising: forming a magnetic tunnel junction (MTJ) memory cell (126, 130, 140, 146, 148, 158) and a metal etching mask portion 159 comprising a metal nitride material over a substrate 9; sequentially forming a first dielectric etch stop layer 172, a second dielectric etch stop layer 174, a via-level dielectric layer 176, and a via-level metal etching mask layer 178 over the metal etching mask portion 159; forming a via cavity 179 by removing portions of the via-level metal etching mask layer 178 and the via-level dielectric layer 176 using a first dry etching process; vertically extending the via cavity 179 by removing portions of the second dielectric etch stop layer using a first wet etching process; vertically extending the via cavity 179 by removing portions of the first dielectric etch stop layer 172 using a second dry etching process; and removing the metal etching mask portion 159 using a second wet etching process.

[0095] With reference to all the accompanying drawings and in accordance with various embodiments of the present invention, a magnetic tunnel junction memory device is provided, the magnetic tunnel junction memory device comprising: an array of magnetic tunnel junction (MTJ) memory cells (126, 130, 140, 146, 148, 158) located above a substrate 9, wherein each of the MTJ memory cells (126, 130, 140, 146, 148, 158) comprises a bottom electrode 126, a synthetic antiferromagnetic structure 140, a nonmagnetic tunnel barrier layer 146, a free magnetization layer 148 and a top electrode 158; an array of dielectric spacers (162, 164), wherein each dielectric spacer (162, 164) selected from the array of dielectric spacers (162, 164) laterally surrounds and contacts a sidewall of a corresponding one of the MTJ memory cells (126, 130, 140, 146, 148, 158) and is disposed within the array. The invention relates to a memory-level dielectric layer 170, comprising a top surface protruding above the horizontal plane of the topmost surfaces of the MTJ memory cells (126, 130, 140, 146, 148, 158) (i.e., above the top surface of the top electrode 158); a memory-level dielectric layer 170, embedding the array of dielectric spacers (162, 164) and the array of MTJ memory cells (126, 130, 140, 146, 148, 158); a via-level dielectric layer 176, located above the memory-level dielectric layer 170; and an array of contact via structures 180, embedded in the via-level dielectric layer 176, wherein each of the contact via structures 180 includes an upper portion embedded in the via-level dielectric layer 176 and a sidewall of a corresponding one of the contact dielectric spacers (162, 164) and a downwardly protruding portion of the top electrode 158 of a corresponding one of the MTJ memory cells (126, 130, 140, 146, 148, 158). In one embodiment, each of the contact via structures 180 can be formed as an integral structure, i.e., a single continuous extended structure. Each contact via structure 180 can be composed of a metal barrier layer 182 having a first metal composition (such as a metal nitride composition) and a metal fill material portion 184 having a second metal composition (such as an elemental metal or an intermetallic alloy composition).

[0096] In one embodiment, each contact via structure 180 within the array of contact via structures 180 includes a horizontal surface that connects the vertical or tapered sidewalls of the upper portion of the contact via structure 180 and the vertical or tapered sidewalls of the downwardly protruding portion of the contact via structure 180. In one embodiment, the upper portion has a greater lateral extent than the downwardly protruding portion, and the horizontal surface includes an annular bottom surface of the upper portion of the corresponding contact via structure 180, such as Fig.16 , Fig.17A and Fig. 17B In one embodiment, the upper portion has a smaller lateral extent than the downwardly protruding portion, and the horizontal surface includes an annular top surface of the downwardly protruding portion of the corresponding contact via structure 180, as shown. Fig. 20 shown.

[0097] In one embodiment, at least one dielectric etch stop layer (172, 174) may be located between the memory level dielectric layer 170 and the via level dielectric layer 176. An upper portion of each contact via structure 180 contacts a corresponding sidewall of the at least one dielectric etch stop layer (172, 174).

[0098] Various embodiments of the present invention may be used to reduce the contact resistance between the top electrode 158 and the contact via structure 180. The contact via structure 180 directly contacts the top surface of the top electrode 158. Therefore, by incorporating the structure of the present invention into any memory cell including the top electrode 158 and the underlying memory material layer, the contact resistance between the top electrode 158 and the contact via structure 180 may be minimized. At least one dielectric etch stop layer (172, 174) provides a controllable selective etch of the metal etch stop material portion 159 while minimizing the parallel etching of the dielectric spacers (162, 164) and the memory level dielectric layer 170.

[0099] Some embodiments of the present application provide a method for forming a magnetic tunnel junction memory device, comprising: forming a magnetic tunnel junction (MTJ) memory cell and a metal etching mask portion above a substrate, wherein the magnetic tunnel junction memory cell includes a bottom electrode, a magnetic tunnel junction structure, and a top electrode, and the metal etching mask portion is located above the top electrode; forming at least one dielectric etch stop layer above the metal etching mask portion; forming a via-level dielectric layer above the at least one dielectric etch stop layer; forming a via cavity through the via-level dielectric layer, wherein the top surface of the at least one dielectric etch stop layer is physically exposed; vertically extending the via cavity by removing portions of the at least one dielectric etch stop layer and the metal etching mask portion; and forming a contact via structure directly on the top surface of the top electrode in the via cavity.

[0100] In some embodiments, the method further comprises: forming a dielectric spacer around the magnetic tunnel junction memory cell and the metal etch mask portion; and forming a memory-level dielectric layer around the dielectric spacer, wherein the via-level dielectric layer is formed above the memory-level dielectric layer. In some embodiments, the dielectric spacer is formed directly on and around the sidewalls of the metal etch mask portion; and removing the metal etch mask portion is performed, the removal being selective to the dielectric spacer and the memory-level dielectric layer. In some embodiments, the metal etch mask portion includes a conductive metal nitride material; and removing the metal etch mask portion is performed using a wet etch process that removes the conductive metal nitride material. In some embodiments, forming the magnetic tunnel junction (MTJ) memory cell and the metal etching mask portion further comprises: depositing a layer stack including a bottom electrode material layer, a magnetic tunnel junction layer, a top electrode material layer, and a metal etching mask material layer over a substrate; applying and patterning a photoresist layer over the layer stack; and etching the metal etching mask material layer by performing a first anisotropic etching process using the photoresist layer as an etching mask, wherein the patterned portion of the metal etching mask material layer comprises the metal etching mask portion. In some embodiments, forming the magnetic tunnel junction (MTJ) memory cell and the metal etching mask portion further comprises performing a second anisotropic etching process, wherein the second anisotropic etching process etches a portion of the layer stack that is not masked by the metal etching mask portion, wherein the metal etching mask portion is used as an etching mask for the second anisotropic etching process at least during patterning of the bottom electrode material layer. In some embodiments, the method includes forming a memory-level dielectric layer around the magnetic tunnel junction memory cell and the metal etch mask portion, wherein the via-level dielectric layer is formed over the memory-level dielectric layer; the via cavity formed through the via-level dielectric layer has a lateral extent greater than a lateral extent of the metal etch mask portion; and removing the metal etch mask portion by performing a selective etching process, the selective etching process etching the metal etch mask portion selective to the via-level dielectric layer and the memory-level dielectric layer. In some embodiments, the via cavity formed through the via-level dielectric layer has a lateral extent less than a lateral extent of the metal etch mask portion; removing the metal etch mask portion by performing a selective etching process, the selective etching process etching the metal etch mask portion selective to the via-level dielectric layer; and the contact via structure is formed by depositing at least one conductive material in the via cavity.In some embodiments, the method further comprises: forming a via-level metal etch mask layer above the via-level dielectric layer; patterning an opening through the via-level metal etch mask layer; etching a portion of the via-level dielectric layer located within the opening through the via-level metal etch mask layer, wherein the via cavity is formed below the opening through the via-level metal etch mask layer; and removing the via-level metal etch mask layer and the metal etch mask portion simultaneously. In some embodiments, the at least one dielectric etch stop layer comprises: a first dielectric etch stop layer comprising silicon nitride and a second dielectric etch stop layer comprising a dielectric metal oxide material; the via-level dielectric layer comprises undoped silicate glass, doped silicate glass, or organosilicate glass; performing a first anisotropic etching process to etch a via cavity through the via-level dielectric layer; performing a wet etching process to etch a portion of the second dielectric etch stop layer; and performing a second anisotropic etching process to etch a portion of the first dielectric etch stop layer.

[0101] Some other embodiments of the present application provide a method for forming a memory device, comprising: depositing a layer stack including a bottom electrode material layer, a memory material layer, a top electrode material layer and a metal etching mask material layer over a substrate; patterning the layer stack into an array of memory cells and an array of metal etching mask portions, wherein each of the memory cells includes a bottom electrode, a memory material stack and a top electrode, and each of the metal etching mask portions is a patterned portion of the metal etching mask material layer located above a corresponding one of the memory cells; depositing a via-level dielectric layer over the array of metal etching mask portions; etching an array of via cavities through the via-level dielectric layer, wherein a top surface of the metal etching mask portion is physically exposed beneath the array of via cavities; removing the array of metal etching mask portions, wherein a top surface of the top electrode is physically exposed beneath the array of via cavities; and forming an array of contact via structures on the top surface of the top electrode located in the array of via cavities. In some embodiments, the method further comprises: depositing and patterning a via-level metal etch mask layer over the via-level dielectric layer; performing an anisotropic etching process, the anisotropic etching process transferring the pattern in the via-level metal etch mask layer through the via-level dielectric layer, thereby forming the via cavity array through the via-level dielectric layer; and removing the metal etch mask portion array and the via-level metal etch mask layer simultaneously by performing a wet etching process. In some embodiments, the metal etch mask portion array and the via-level metal etch mask layer comprise the same conductive metal nitride material. In some embodiments, the method further comprises: forming a dielectric spacer around each metal etch mask portion of the metal etch mask portion array; forming at least one dielectric etch stop layer over the dielectric spacer and the metal etch mask portion array, wherein the via-level dielectric layer is formed over the at least one dielectric etch stop layer; and extending the via cavity array through the at least one dielectric etch stop layer by performing at least one etching process, wherein the inner sidewalls of the corresponding dielectric spacers are physically exposed when the metal etch mask portion array is removed. In some embodiments, the memory material layer comprises a layer stack comprising a synthetic antiferromagnetic layer, a nonmagnetic tunnel barrier layer, and a free magnetization layer; and each of the memory cells comprises a vertical stack comprising a synthetic antiferromagnetic structure, a nonmagnetic tunnel barrier layer, and a free magnetization layer.

[0102] Still other embodiments of the present application provide a magnetic tunnel junction memory device, comprising: a magnetic tunnel junction (MTJ) memory cell array located above a substrate; a dielectric spacer array, wherein each dielectric spacer selected from the dielectric spacer array laterally surrounds and contacts the sidewalls of a corresponding one of the magnetic tunnel junction memory cells and protrudes above a horizontal plane including the topmost surface of the magnetic tunnel junction memory cells; a memory-level dielectric layer embedded in the dielectric spacer array and the magnetic tunnel junction memory cell array; a via-level dielectric layer located above the memory-level dielectric layer; and an array of contact via structures embedded in the via-level dielectric layer, wherein each of the contact via structures includes an upper portion embedded in the via-level dielectric layer and a downwardly protruding portion of a sidewall of a corresponding one of the dielectric spacers contacting the dielectric spacers and a top electrode of a corresponding one of the magnetic tunnel junction memory cells. In some embodiments, each contact via structure within the array of contact via structures includes a horizontal surface connecting the vertical or tapered sidewalls of the upper portion and the vertical or tapered sidewalls of the downwardly protruding portion. In some embodiments, the upper portion has a larger lateral extent than the downwardly protruding portion; and the horizontal surface includes an annular bottom surface of the upper portion of the corresponding contact via structure. In some embodiments, the upper portion has a smaller lateral extent than the downwardly protruding portion; and the horizontal surface includes an annular top surface of the downwardly protruding portion of the corresponding contact via structure. In some embodiments, the magnetic tunnel junction memory device further includes: at least one dielectric etch stop layer located between the memory-level dielectric layer and the via-level dielectric layer, wherein the upper portion of each contact via structure contacts the corresponding sidewall of the at least one dielectric etch stop layer.

[0103] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a magnetic tunnel junction memory device, comprising: forming a magnetic tunnel junction (MTJ) memory cell and a metal etch mask portion over a substrate, wherein the magnetic tunnel junction memory cell includes a bottom electrode, a magnetic tunnel junction structure, and a top electrode, and the metal etch mask portion is located above the top electrode; forming dielectric spacers around the magnetic tunnel junction memory cell and the metal etch mask portion; forming at least one dielectric etch stop layer over the metal etch mask portion; forming a via level dielectric layer over the at least one dielectric etch stop layer; forming a via cavity through the via-level dielectric layer, wherein a top surface of the at least one dielectric etch stop layer is physically exposed; vertically extending the via cavity by removing portions of the at least one dielectric etch stop layer and a metal etch mask portion; and forming a contact via structure directly on a top surface of the top electrode in the via cavity, The dielectric spacer surrounds all sidewalls of the magnetic tunnel junction memory cell, and the dielectric spacer includes an inner spacer portion and an outer spacer portion, wherein the outer spacer portion is higher than a top surface of the top electrode of the magnetic tunnel junction memory cell.

2. The method according to claim 1, further comprising: A memory-level dielectric layer is formed around the dielectric spacers, wherein the via-level dielectric layer is formed over the memory-level dielectric layer.

3. The method according to claim 2, wherein: forming the dielectric spacers directly on and around sidewalls of the metal etch mask portion; as well as Removal of the metal etch mask portion is performed selective to the dielectric spacers and the memory level dielectric layer.

4. The method according to claim 1, wherein: The metal etch mask portion includes a conductive metal nitride material; and The removal of the metal etch mask portion is performed using a wet etch process that removes the conductive metal nitride material.

5. The method according to claim 1, wherein: Forming the magnetic tunnel junction (MTJ) memory cell and the metal etch mask portion further comprises: depositing a layer stack including a bottom electrode material layer, a magnetic tunnel junction layer, a top electrode material layer, and a metal etch mask material layer over the substrate; applying and patterning a photoresist layer over the layer stack; and The metal etch mask material layer is etched by performing a first anisotropic etching process using the photoresist layer as an etching mask, wherein the patterned portion of the metal etch mask material layer includes the metal etch mask portion.

6. The method according to claim 5, wherein: Forming the magnetic tunnel junction (MTJ) memory cell and the metal etching mask portion also includes implementing a second anisotropic etching process, which etches portions of the layer stack that are not masked by the metal etching mask portion, wherein the metal etching mask portion is used as an etching mask for the second anisotropic etching process at least during patterning of the bottom electrode material layer.

7. The method according to claim 1, wherein: The method includes forming a memory-level dielectric layer around the magnetic tunnel junction memory cell and the metal etch mask portion, wherein the via-level dielectric layer is formed over the memory-level dielectric layer; The via cavity formed through the via-level dielectric layer has a lateral extent greater than a lateral extent of the metal etch mask portion; and The metal etch mask portion is removed by performing a selective etching process that etches the metal etch mask portion selective to the via-level dielectric layer and the memory-level dielectric layer.

8. The method of claim 1, wherein: a via cavity formed through the via-level dielectric layer having a lateral extent that is smaller than a lateral extent of the metal etch mask portion; removing the metal etch mask portion by performing a selective etching process that etches the metal etch mask portion selective to the via-level dielectric layer; as well as The contact via structure is formed by depositing at least one conductive material in the via cavity.

9. The method according to claim 1, further comprising: forming a via-level metal etch mask layer over the via-level dielectric layer; patterning openings through the via-level metal etching mask layer; etching a portion of the via-level dielectric layer within the opening through the via-level metal etch mask layer, wherein the via cavity is formed below the opening through the via-level metal etch mask layer; as well as The via level metal etch mask layer and the metal etch mask portion are removed simultaneously.

10. The method of claim 1, wherein: The at least one dielectric etch stop layer comprises: a first dielectric etch stop layer comprising silicon nitride and a second dielectric etch stop layer comprising a dielectric metal oxide material; The via-level dielectric layer comprises undoped silicate glass, doped silicate glass or organosilicate glass; performing a first anisotropic etching process to etch a via cavity through the via-level dielectric layer; performing a wet etching process to etch a portion of the second dielectric etch stop layer; and A second anisotropic etching process is performed to etch a portion of the first dielectric etch stop layer.

11. A method of forming a memory device, comprising: depositing a layer stack including a bottom electrode material layer, a memory material layer, a top electrode material layer, and a metal etch mask material layer over the substrate; patterning the layer stack into an array of memory cells and an array of metal etch mask portions, wherein each of the memory cells comprises a bottom electrode, a memory material stack, and a top electrode, and each of the metal etch mask portions is a patterned portion of the metal etch mask material layer that is located above a respective one of the memory cells; forming a dielectric spacer around each metal etch mask portion of the array of metal etch mask portions; depositing a via-level dielectric layer over the array of metal etch mask portions; etching an array of via cavities through the via-level dielectric layer, wherein a top surface of the metal etch mask portion is physically exposed beneath the array of via cavities; removing the array of metal etch mask portions, wherein a top surface of the top electrode is physically exposed beneath the array of via cavities; and forming an array of contact via structures on a top surface of the top electrode located in the array of via cavities, The dielectric spacer surrounds all sidewalls of the memory cell, and the dielectric spacer includes an inner spacer portion and an outer spacer portion, wherein the outer spacer portion is higher than a top surface of the top electrode of the memory cell.

12. The method according to claim 11, further comprising: depositing and patterning a via-level metal etch mask layer over the via-level dielectric layer; performing an anisotropic etching process, the anisotropic etching process transferring the pattern in the via-level metal etch mask layer through the via-level dielectric layer, thereby forming the via cavity array through the via-level dielectric layer; as well as The array of metal etch mask portions and the via-level metal etch mask layer are simultaneously removed by performing a wet etching process.

13. The method according to claim 12, wherein: The array of metal etch mask portions and the via-level metal etch mask layer include the same conductive metal nitride material.

14. The method according to claim 11, further comprising: forming at least one dielectric etch stop layer over the dielectric spacers and the array of metal etch mask portions, wherein the via-level dielectric layer is formed over the at least one dielectric etch stop layer; and extending the array of via cavities through the at least one dielectric etch stop layer by performing at least one etching process, Wherein, when the metal etching mask portion array is removed, the inner sidewalls of the corresponding dielectric spacers are physically exposed.

15. The method of claim 11, wherein: The memory material layer comprises a layer stack, the layer stack comprising a synthetic antiferromagnetic layer, a nonmagnetic tunnel barrier layer, and a free magnetization layer; as well as Each of the memory cells includes a vertical stack including a synthetic antiferromagnetic structure, a nonmagnetic tunnel barrier layer, and a free magnetization layer.

16. A magnetic tunnel junction memory device, comprising: a magnetic tunnel junction (MTJ) memory cell array disposed above the substrate; a dielectric spacer array, wherein each dielectric spacer selected from the dielectric spacer array laterally surrounds and contacts all of the sidewalls of a corresponding one of the magnetic tunnel junction memory cells, each dielectric spacer of the dielectric spacer array includes an inner spacer portion and an outer spacer portion, and the outer spacer portion protrudes above a horizontal plane including a topmost surface of the magnetic tunnel junction memory cell; a memory level dielectric layer embedding the array of dielectric spacers and the array of magnetic tunnel junction memory cells; a via-level dielectric layer located above the memory-level dielectric layer; and An array of contact via structures is embedded in the via-level dielectric layer, wherein each of the contact via structures includes an upper portion embedded in the via-level dielectric layer and a downwardly protruding portion that contacts the sidewalls of a corresponding one of the dielectric spacers and a top electrode of a corresponding one of the magnetic tunnel junction memory cells.

17. The magnetic tunnel junction memory device according to claim 16, wherein: Each contact via structure within the array of contact via structures includes a horizontal surface connecting the vertical or tapered sidewalls of the upper portion and the vertical or tapered sidewalls of the downwardly protruding portion.

18. The magnetic tunnel junction memory device according to claim 17, wherein: The upper portion has a greater lateral extent than the downwardly projecting portion; and The horizontal surface includes a corresponding annular bottom surface contacting the upper portion of the via structure.

19. The magnetic tunnel junction memory device according to claim 17, wherein: The upper portion has a smaller lateral extent than the downwardly projecting portion; and The horizontal surface includes a corresponding annular top surface of the downwardly protruding portion of the contact via structure.

20. The magnetic tunnel junction memory device according to claim 17, further comprising: At least one dielectric etch stop layer is located between the memory level dielectric layer and the via level dielectric layer, wherein the upper portion of each contact via structure contacts a corresponding sidewall of the at least one dielectric etch stop layer.

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