Transistor and method for manufacturing the same

Abstract

A transistor, an integrated semiconductor device and a manufacturing method are provided. The transistor includes a patterned gate electrode, a dielectric layer located above the patterned gate electrode and a patterned first oxide semiconductor layer, the patterned first oxide semiconductor layer includes a channel region and a source / drain region located on the side of the channel region. The thickness of the source / drain region is greater than the thickness of the channel region. The transistor also includes a contact disposed on the patterned first oxide semiconductor layer and connected to the source / drain region of the patterned first oxide semiconductor layer.

Description

Technical Field

[0001] Embodiments of the present application relate to transistors and methods for manufacturing the same. Background Art

[0002] In the semiconductor industry, there is a continuing desire to increase the areal density of integrated circuits. To this end, individual transistors have become increasingly smaller. However, the rate at which individual transistors can be made smaller has been slowing. Moving peripheral transistors from the front end of line (FEOL) of manufacturing to the back end of line (BEOL) of manufacturing can be advantageous because functionality can be added at the BEOL, while available chip area can be made in the FEOL. Thin film transistors (TFTs) made from oxide semiconductors are an attractive option for BEOL integration because TFTs can be processed at low temperatures and therefore will not damage previously manufactured devices. Summary of the invention

[0003] Some embodiments of the present application provide a transistor, comprising: a patterned gate electrode; a dielectric layer located above the patterned gate electrode; a patterned first oxide semiconductor layer including a channel region; and a patterned second oxide semiconductor layer including a source / drain region located on either side of the channel region, wherein the thickness of the source / drain region is greater than the thickness of the channel region.

[0004] Other embodiments of the present application provide a transistor, comprising: a patterned first oxide semiconductor layer, including a channel region; a dielectric layer located above the patterned first oxide semiconductor layer; a patterned gate electrode located above the dielectric layer; and a patterned second oxide semiconductor layer, including a source / drain region located on either side of the channel region, wherein the thickness of the source / drain region is greater than the thickness of the channel region.

[0005] Some other embodiments of the present application provide a method for manufacturing a transistor, comprising: depositing a first oxide semiconductor layer above an interconnect level dielectric layer; forming a channel region in the first oxide semiconductor layer; forming a source / drain region on either side of the channel region, wherein the thickness of the source / drain region is greater than the thickness of the channel region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1Ais a vertical cross-sectional view of an exemplary structure after formation of a complementary metal oxide semiconductor (CMOS) transistor, a metal interconnect structure embedded in a dielectric material layer, and a connecting via level dielectric material layer according to an embodiment of the present invention.

[0008] Figure 1B is a vertical cross-sectional view of a first exemplary structure during formation of a thin film transistor array according to an embodiment of the present invention.

[0009] Figure 1C is a vertical cross-sectional view of the first exemplary structure after forming a high-level metal interconnect structure according to an embodiment of the present invention.

[0010] Figure 2 is a vertical cross-sectional view showing a step of depositing a continuous metal gate layer over an interconnect level dielectric (ILD) layer in a method of manufacturing a transistor according to an embodiment of the present invention.

[0011] Figure 3A is a vertical cross-sectional view showing a step of patterning a continuous metal gate layer to form a gate electrode in a method of manufacturing a transistor according to an embodiment of the present invention.

[0012] Figure 3B is a vertical cross-sectional view showing the steps of depositing and patterning a photoresist layer in an alternative method of manufacturing a transistor according to an embodiment of the present invention.

[0013] Figure 3C is a vertical cross-sectional view showing a step of etching an ILD layer using a patterned photoresist layer as a mask in an alternative method of manufacturing a transistor according to an embodiment of the present invention.

[0014] Figure 4 is a vertical cross-sectional view showing a step of forming a metal electrode in an etched ILD layer in a method of manufacturing a transistor according to an embodiment of the present invention.

[0015] Figure 5 is a vertical cross-sectional view showing the steps of depositing a continuous high-k dielectric layer and a continuous oxide semiconductor layer in a method of manufacturing a transistor according to an embodiment of the present invention.

[0016] Figure 6 is a vertical cross-sectional view showing the steps of depositing and patterning a photoresist layer over a continuous high-k dielectric layer and a continuous oxide semiconductor layer in a method of manufacturing a transistor according to an embodiment of the present invention.

[0017] Fig. 7A is a vertical cross-sectional view showing patterning of a continuous high-k dielectric layer and a continuous oxide semiconductor layer using a patterned photoresist layer in a method of manufacturing a transistor according to an embodiment of the present invention.

[0018] Figure 7Bis a vertical cross-sectional view illustrating steps of patterning a continuous metal gate layer, a continuous high-k dielectric layer, and a continuous oxide semiconductor layer according to an alternative embodiment of the present invention.

[0019] Figure 8 is a diagram showing an embodiment of the present invention. Fig. 7A A vertical cross-sectional view of the step of depositing additional ILD material over the intermediate structure is shown.

[0020] Fig. 9 is a diagram showing an embodiment of the present invention. Figure 8 A vertical cross-sectional view of the steps of depositing and patterning a photoresist layer over the intermediate structure is shown.

[0021] Fig.10 is a vertical cross-sectional view illustrating a step of etching a contact via in an ILD layer using a patterned photoresist layer as a mask according to an embodiment of the present invention.

[0022] Fig.11 is a vertical cross-sectional view illustrating a step of depositing a semiconductor material layer in a contact via according to an embodiment of the present invention.

[0023] Fig. 12A is a vertical cross-sectional view illustrating a step of depositing a contact metal in a contact via above a dielectric material layer in the contact via according to an embodiment of the present invention.

[0024] Fig. 12B is a vertical cross-sectional view illustrating an alternative embodiment in which a layer of semiconductive material is conformally deposited on the sides and bottom of the contact via.

[0025] Fig.13 is a vertical cross-sectional view illustrating steps of depositing and forming a patterned high-k dielectric layer, a first patterned oxide semiconductor layer, and a second patterned oxide semiconductor layer according to an embodiment of the present invention.

[0026] Fig.14 is a diagram showing an embodiment of the present invention. Fig.13 A vertical cross-sectional view of the step of depositing additional ILD material over the intermediate structure is shown.

[0027] Fig.15 is a diagram showing an embodiment of the present invention. Fig.14 A vertical cross-sectional view of the step of depositing and patterning a photoresist layer over the intermediate layer over the intermediate structure, and etching the ILD layer using the patterned photoresist layer as a mask to expose the top surface of the second oxide semiconductor layer.

[0028] Fig.16 is a vertical cross-sectional view illustrating a step of etching a portion of the second oxide semiconductor layer according to an embodiment of the present invention.

[0029] Fig.17 is a vertical cross-sectional view illustrating a step of forming a contact through hole extending to the second oxide semiconductor layer according to an embodiment of the present invention.

[0030] Fig.18A is a vertical cross-sectional view showing a step of filling a contact via to form a metal contact according to an embodiment of the present invention.

[0031] Fig.18B is a vertical cross-sectional view showing a transistor according to an embodiment of the present invention, in which a portion of the patterned first oxide semiconductor layer over the active region is replaced with a patterned second oxide semiconductor layer.

[0032] Fig.18C is a vertical cross-sectional view showing a transistor according to an embodiment of the present invention, in which all of the patterned first oxide semiconductor layer over the active region is replaced with a patterned second oxide semiconductor layer.

[0033] Fig.18D is a vertical cross-sectional view showing a transistor according to an embodiment of the present invention, wherein a portion of a patterned first oxide semiconductor layer above an active region is replaced with a patterned second oxide semiconductor layer, and a portion of the patterned second oxide semiconductor layer is formed above a portion of the first patterned oxide semiconductor layer.

[0034] Fig.19 is a vertical cross-sectional view illustrating a step of depositing a continuous first oxide semiconductor layer and a continuous second oxide semiconductor layer over an ILD layer according to an embodiment of the present invention.

[0035] Fig. 20 is a vertical cross-sectional view illustrating a step of forming a patterned first oxide semiconductor layer and a patterned second oxide semiconductor layer on an ILD layer according to an embodiment of the present invention.

[0036] Fig.21 is a vertical cross-sectional view illustrating a step of etching the patterned second oxide semiconductor layer to form a channel region according to an embodiment of the present invention.

[0037] Fig. 22 is a vertical cross-sectional view showing the steps of depositing a conformal high-k dielectric layer and depositing a metal over the high-k dielectric material to form a gate electrode according to an embodiment of the present invention.

[0038] Fig.23 It is shown that according to an embodiment of the present invention, Fig. 22 A vertical cross-sectional view of the intermediate structure during the planarization step is shown.

[0039] Fig.24Ais a vertical cross-sectional view illustrating the steps of depositing additional ILD layer material and forming metal contacts to the active area and gate electrode, according to an embodiment of the present invention.

[0040] Fig. 24B is a vertical cross-sectional view showing a transistor according to an alternative embodiment of the present invention.

[0041] Fig.25 is a flow chart showing the general processing steps of an exemplary method of the present invention.

[0042] Fig.26 is a flow chart illustrating the general processing steps of an alternative exemplary method of the present invention. DETAILED DESCRIPTION

[0043] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0044] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0045] The present invention is directed to semiconductor transistors, and in particular to raised source / drain oxide semiconductor thin film transistors and methods of forming the same. Embodiments also include integrated circuits with raised source / drain oxide thin film transistors, in particular raised source / drain oxide thin film transistors formed in BEOL.

[0046] Although their performance (switching speed) is generally not sufficient to perform core logic functions, thin-film transistors (TFTs) have the potential to perform many non-core logic tasks, such as power gates, memory selectors, or interfaces (input / output, I / O). Since TFTs can be processed at low temperatures, they can be integrated in the BEOL. Moving peripheral devices (power gates, memory selectors, I / O transistors) from FEOL to BEOL (essentially stacking them on top of FEOL) can be part of the scaling path for manufacturing at the 3nm technology node, for example; moving peripheral devices out of FEOL and stacking them together can increase density by about 5-10% for a given device.

[0047] Peripheral transistors that can be moved from FEOL to BEOL include, but are not limited to, power gates, input / output transistors, and memory selectors. In current technology, a power gate is a large logic transistor located in the FEOL. A power gate can be used to turn off logic blocks in standby mode, thereby reducing static power consumption. I / O devices are interfaces between computing elements (e.g., CPUs) and the outside world (e.g., external memory) and are also processed in the FEOL. Selectors for storage elements, such as magnetoresistive random access memory (MRAM) or resistive random access memory (RRAM) are currently located in the FEOL and can be moved to the BEOL. Typically, each storage element has a selector TFT.

[0048] Oxide semiconductors are being developed as channel materials for TFTs. It has been found that oxide materials become semiconductive when thin (e.g., less than 8 nm); but semimetallic when thick (e.g., 15-150 nm). However, when the semiconductive oxide layer is thin, the contact resistance between the metal and the thin film oxide semiconductor is high. Typically, the current flowing through such thin film transistors is completely controlled by parasitic resistance, which is undesirable. It has been proven that it is difficult to make good electrical contacts to very thin oxide layers. In addition, poor contacts tend to dominate the performance of thin film transistors. However, contacts with low contact resistance can be reliably made into thick oxide layers, such as 15-150 nm.

[0049] Various embodiments disclosed herein employ transistor structures that combine the metallic properties of a thick indium tin oxide (ITO) layer with the semiconducting properties of a thin ITO layer to form a thin film transistor with low parasitic resistance. Various embodiments may apply other oxides, such as indium gallium zinc oxide (IGZO), which present the same tradeoff between channel modulation (requiring a thin layer) and low parasitic resistance (requiring a thick layer). Various embodiments provide channel optimization independent of any source / drain design or engineering. In addition, various embodiments do not require doping to form an active region, as the material thickness can define the electrical properties of different structures. In addition, various embodiments provide a scalable thin film transistor architecture.

[0050] Figure 1A is a vertical cross-sectional view of an exemplary structure after forming complementary metal oxide semiconductor (CMOS) transistors, metal interconnect structures embedded in dielectric material layers, and connecting via level dielectric material layers before forming an array of memory structures according to various embodiments of the present invention. Figure 1A , showing an exemplary structure according to an embodiment of the present invention. The exemplary structure includes a complementary metal oxide semiconductor (CMOS) transistor and a metal interconnect structure formed in a dielectric material layer. Specifically, the first exemplary structure includes a substrate 8, which includes a semiconductor material layer 10. The substrate 8 may include a bulk semiconductor substrate, such as a silicon substrate, wherein the semiconductor material layer extends continuously from the top surface of the substrate 8 to the bottom surface of the substrate 8, or an insulator-on-semiconductor layer including the semiconductor material layer 10, which serves as a top semiconductor layer located above a buried insulator layer (such as a silicon oxide layer). A shallow trench isolation structure 12 including a dielectric material such as silicon oxide may be formed in an upper portion of the substrate 8. Appropriate doped semiconductor wells, such as a p-type well and an n-type well, may be formed in each region, which may be laterally surrounded by a portion of the shallow trench isolation structure 12. A field effect transistor may be formed above the top surface of the substrate 8 in a front-end-of-line (FEOL) process. For example, each field effect transistor may include active source / drain regions 14, a semiconductor channel 15, and a gate structure 20, the semiconductor channel including a surface portion of the substrate 8 extending between the active source / drain regions 14. Each gate structure 20 may include a gate dielectric 22, a gate electrode 24, a gate cap dielectric 28, and a dielectric gate spacer 26. An active source / drain metal semiconductor alloy region 18 may be formed on each active source / drain region 14. Although planar field effect transistors are shown in the drawings, embodiments are expressly contemplated herein where the field effect transistors may additionally or alternatively include fin field effect transistors (FinFETs), gate-all-around field effect (GAA FET) transistors, or any other type of field effect transistor (FET).

[0051] The exemplary structure may include a memory array region 50 in which a memory element array may be subsequently formed, and a peripheral region 52 in which logic devices supporting the operation of the memory element array may be formed. In one embodiment, the devices (e.g., field effect transistors) in the memory array region 50 may include a bottom electrode access transistor that provides access to the bottom electrode of the subsequently formed memory cell. In this processing step, a top electrode access transistor that accesses the top electrode of the subsequently formed memory cell may be formed in the peripheral region 52.

[0052] The devices (e.g., field effect transistors) in the peripheral region 52 can provide the functions required to operate the memory cell array to be formed subsequently. Specifically, the devices in the peripheral region can be configured to control the programming operation, the erasing operation, and the sensing (reading) operation of the memory cell array. For example, the devices in the peripheral region may include a sensing circuit and / or a top electrode bias circuit. The devices formed on the top surface of the substrate 8 may include complementary metal oxide semiconductor (CMOS) transistors and optionally additional semiconductor devices (e.g., resistors, diodes, capacitors, etc.), and are collectively referred to as CMOS circuits 75.

[0053] A plurality of interconnection hierarchical structures may be subsequently formed, which are formed before forming the thin film transistor array and are referred to herein as lower interconnection hierarchical structures (L0, L1, L2). In the case where a two-dimensional array of TFTs is sequentially formed above two levels of interconnection hierarchical metal lines, the lower interconnection hierarchical structures (L0, L1, L2) may include an interconnection hierarchical structure L0, a first interconnection hierarchical structure L1, and a second interconnection hierarchical structure L2. The dielectric material layer may include, for example, a contact level dielectric material layer 31A, a first metal line level dielectric material layer 31B, and a second line and via level dielectric material layer 32. A plurality of metal interconnection structures embedded in the dielectric material layer may then be formed above the substrate 8 and the device (e.g., field effect transistor). These metal interconnect structures may include a device contact via structure 41V (interconnection level structure L0) formed in the contact level dielectric material layer 31A and contacting corresponding components of the CMOS circuit 75, a first metal line structure 41L (interconnection level structure L1) formed in the first metal line level dielectric material layer 31B, a first metal via structure 42V formed in the lower portion of the second line and via level dielectric material layer 32, and a second metal line structure 42L (interconnection level structure L2) formed in the upper portion of the second line and via level dielectric material layer 32.

[0054] Each dielectric material layer (31A, 31B and 32) may include a dielectric material, such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each metal interconnect structure (41V, 41L, 42V and 42L) may include at least one conductive material, which may be a combination of a metal liner layer (e.g., a metal nitride or a metal carbide) and a metal filler material. Each metal liner layer may include TiN, TaN, WN, TiC, TaC and WC, and each metal filler material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof and / or combinations thereof. Other suitable materials within the scope of the envisioned invention may also be used. In one embodiment, the first metal via structure 42V and the second metal wire structure 42L may be formed as an integrated wire and via structure by a dual damascene process, and the second metal via structure 43V and the third metal wire structure 43L may be formed as an integrated wire and via structure.

[0055] The dielectric material layer (31A, 31B and 32) can be located at a lower level relative to the memory cell array formed subsequently. Thus, the dielectric material layer (31A, 31B and 32) is referred to herein as a lower-level dielectric material layer, that is, a dielectric material layer located at a lower level relative to the memory cell array formed subsequently. The metal interconnect structure (41V, 41L, 42V and 42L) is referred to herein as a lower-level metal interconnect structure. A subset of the metal interconnect structure (41V, 41L, 42V and 42L) includes lower-level metal lines (e.g., a third metal line structure 42L), which are embedded in the lower-level dielectric material layer and whose top surface is located in a horizontal plane including the uppermost surface of the lower-level dielectric material layer. In general, the total number of metal line levels within the lower-level dielectric material layer (31A, 31B and 32) can be in the range of 1 to 3.

[0056] The exemplary structure may include a variety of device regions, which may include a memory array region 50 in which at least one array of nonvolatile memory cells may be subsequently formed. For example, the at least one array of nonvolatile memory cells may include resistive random access memory (RRAM or ReRAM), magnetic / magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), and phase change memory (PCM) devices. The exemplary structure may also include a peripheral logic region 52 in which electrical connections between each array of nonvolatile memory cells and peripheral circuits including field effect transistors may be subsequently formed. Areas of the memory array region 50 and the logic region 52 may be used to form various elements of the peripheral circuits.

[0057] refer to Figure 1B, an array 95 of nonvolatile memory cells and TFTs may be formed in the memory array region 50 above the second interconnect hierarchy structure L2. Details of the structure and processing steps of the array 95 of TFTs are described in detail below. A third interconnect hierarchy dielectric material layer 33 may be formed during the formation of the array 95 of nonvolatile gate ferroelectric memory cells. The collection of all structures formed at the level of the array 95 of nonvolatile memory cells and TFTs is referred to herein as the third interconnect hierarchy structure L3. Devices formed within the array 95 at the BEOL may be coupled to FEOL devices formed on the substrate 8 via a plurality of interconnect hierarchy metal interconnect structures, or coupled to subsequently formed devices in the upper layer via an upper interconnect hierarchy structure.

[0058] refer to Figure 1C , a third interconnection level metal interconnection structure (43V, 43L) may be formed in the third interconnection level dielectric material layer 33. The third interconnection level metal interconnection structure (43V, 43L) may include a second metal via structure 43V and a third metal line 43L. Additional interconnection level structures may be subsequently formed, which are referred to herein as upper interconnection level structures (L4, L5, L6, L7). For example, the upper interconnection level structures (L4, L5, L6, L7) may include a fourth interconnection level structure L4, a fifth interconnection level structure L5, a sixth interconnection level structure L6, and a seventh interconnection level structure L7. The fourth interconnection level structure L4 may include a fourth interconnection level dielectric material layer 34, the fourth interconnection level dielectric material layer having a fourth interconnection level metal interconnection structure (44V, 44L) formed therein, the fourth interconnection level metal interconnection structure may include a third metal via structure 44V and a fourth metal line 44L. The fifth interconnection level structure L5 may include a fifth interconnection level dielectric material layer 35 having a fifth interconnection level metal interconnection structure (45V, 45L) formed therein, which may include a fourth metal via structure 45V and a fifth metal line 45L. The sixth interconnection level structure L6 may include a sixth interconnection level dielectric material layer 36 having a sixth interconnection level metal interconnection structure (46V, 46L) formed therein, which may include a fifth metal via structure 46V and a sixth metal line 46L. The seventh interconnection level structure L7 may include a seventh interconnection level dielectric material layer 37 having a sixth metal via structure 47V (which is a seventh interconnection level metal interconnection structure) and a metal bonding pad 47B formed therein. Metal bond pad 47B may be configured for solder bonding (which may employ C4 ball bonding or wire bonding), or may be configured for metal-to-metal bonding (eg, copper-to-copper bonding).

[0059] Each interconnect level dielectric material layer may be referred to as an interconnect level dielectric material layer (ILD) layer 30 (i.e., 31A, 31B, 32, 33, 34, 35, 36, and 37). Each interconnect level metal interconnect structure may be referred to as a metal interconnect structure 40. Each continuous combination of a metal via structure and a metal line thereon within the same interconnect level structure (L2-L7) may be sequentially formed into two different structures by using two single damascene processes, or may be simultaneously formed into an integral structure by using a dual damascene process. Each metal interconnect structure 40 (i.e., 41V, 41L, 42V, 42L, 43V, 43L, 44V, 44L, 45V, 45L, 46V, 46L, 47V, 47B) may include a corresponding metal liner (e.g., a layer of TiN, TaN, or WN having a thickness ranging from 2 nm to 20 nm) and a corresponding metal filling material (e.g., W, Cu, Co, Mo, Ru, other elemental metals, or alloys or combinations thereof). Other suitable materials for use as metal liner and metal fill materials are within the contemplated scope of the invention disclosed. Various etch stop dielectric material layers and dielectric cap layers may be interposed between multiple pairs of vertically adjacent ILD layers 30 or may be incorporated into one or more ILD layers 30 .

[0060] Although the present invention is described using an embodiment in which an array 95 of nonvolatile memory cells and TFT selector devices can be formed as a component of a third interconnect hierarchy L3, it is expressly contemplated herein that an array 95 of nonvolatile memory cells and TFT selector devices can be formed as a component of any other interconnect hierarchy (e.g., L1-L7). In addition, although the present invention is described using an embodiment in which a set of eight interconnect hierarchical structures are formed, it is expressly contemplated herein that an embodiment in which a different number of interconnect hierarchical structures are used. In addition, it is expressly contemplated herein that an embodiment in which two or more arrays 95 of nonvolatile memory cells and TFT selector devices can be provided within multiple interconnect hierarchical structures in the memory array region 50. Although the present invention is described using an embodiment in which an array 95 of nonvolatile memory cells and TFT selector devices can be formed in a single interconnect hierarchy, it is expressly contemplated herein that an embodiment in which an array 95 of nonvolatile memory cells and TFT selector devices can be formed above two vertically adjacent interconnect hierarchical structures.

[0061] Figures 2 to 24B Various protruding (or raised source / drain region) TFTs and methods of manufacturing various protruding TFTs are shown. Figure 2, the continuous metal gate layer 102L can be deposited on the ILD 100 located in the BEOL of the integrated semiconductor device, such as the ILD layer (i.e., ILD 33). The ILD layer 100 can be formed of an ILD material such as undoped silicate glass, doped silicate glass, organic silicate glass, or a porous dielectric material. Other suitable materials used as the ILD layer 100 belong to the conceivable scope of the present invention. The ILD layer 100 can be formed by any deposition process, such as chemical vapor deposition, spin coating, physical vapor deposition (PVD) (also known as sputtering), atomic layer deposition (ALD), etc. The continuous metal gate layer 102L can be formed by a metal or a metal alloy, such as tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), titanium aluminum (TiAl), titanium nitride (TiN) or tantalum nitride (TaN) or a multilayer thereof. Other suitable metal materials for the metal gate layer belong to the conceivable scope of the present invention. The continuous metal layer 102L may be formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic level deposition (ALD), or any other suitable method.

[0062] Reference Figure 3A , the continuous metal gate layer 102L may be patterned to form a patterned gate electrode 102. In various embodiments, a photoresist layer (not shown) may be deposited over the continuous metal gate layer 102L and patterned by a photolithography process. The patterned photoresist layer may be used as a mask, and any suitable etchant may be used to etch the continuous metal gate layer 102L below. The photoresist layer may be removed by dissolving in a solvent or by ashing.

[0063] Reference Figure 3B , which shows steps in an alternative exemplary method of forming a patterned electrode. In this method, a photoresist layer 101 is deposited on the surface of the ILD layer 100 and patterned by a photolithography process. Figure 3B and Figure 3C The ILD layer 100 in the illustrated alternative embodiment may be thicker than Figure 3A The ILD layer 100 used in the exemplary method shown is thicker.

[0064] Reference Figure 3C , the ILD layer 100 can be patterned using the photoresist layer 101 as a mask, and any suitable etchant can be used to etch the underlying ILD layer 100. The photoresist layer can be removed by dissolving in a solvent or by ashing. Etching the ILD layer 100 can form trenches 100A in the ILD layer 100, and the photoresist layer 101 can be removed. As discussed above, the photoresist layer 101 can be removed by dissolving in a solvent or by ashing.

[0065] Reference Figure 4 , metal may be deposited in the trench 100A in the ILD layer 100. As described above, the metal may be deposited by any suitable method, such as CVD, PECVD, or ALD. In various embodiments, the surface of the ILD layer 100 and the patterned gate electrode 102 may be planarized by, for example, chemical mechanical polishing (CMP) to remove excess metal from the deposition process. Figure 3A In the illustrated embodiment, additional dielectric material similar to the material of the ILD layer 100 may be deposited over and around the patterned gate electrode 102. Planarization (e.g., CMP) may be performed on the excess dielectric material to remove the excess dielectric material and create a coplanar top surface between the dielectric material and the patterned gate electrode 102, such as Figure 4 shown.

[0066] Reference Figure 5 , a continuous high-k dielectric layer 104L may be deposited over the surface of the ILD layer 100 and the patterned gate electrode 102. A continuous first oxide semiconductor layer 106L may be deposited over the continuous high-k dielectric layer 104L. In various embodiments, the high-k dielectric material may be a dielectric constant higher than SiO 2 (dielectric constant k = 3.9). Exemplary high-k dielectric materials include HfO2, Al2O3, Ta2O5, ZrO2, TiO2, HfO2, HfZrO4 (HZO), HfSiO x 、HfLaO x and any other suitable material. In some embodiments, SiO2 may be used. In addition, the continuous high-k dielectric layer 104L may be formed of multiple layers of the above materials. The continuous first oxide semiconductor layer 106L may be formed of In x Ga y Zn z O w (IGZO), In2O3, Ga2O3, ZnO, In x Sn y O z (ITO) or any other suitable oxide semiconductor.

[0067] In another embodiment, the continuous first oxide semiconductor layer 106L may include a laminated structure. In one aspect, the plurality of layers of the laminated structure may include a plurality of In layers having different molar percentages of In, Ga, and Zn. x Ga y Zn zLayer O. In one embodiment, 0 < x ≤ 0.5, 0 < y ≤ 0.5, and 0 < z ≤ 0.5. In various embodiments, the plurality of layers of the laminate structure include layers of other oxides, such as but not limited to InWO, InZnO, InSnO, GaO x and InO x .

[0068] Referring Figure 6 , a photoresist layer 101 can be deposited above the surface of the intermediate structure shown. Then, the photoresist layer 101 can be patterned and used as a mask when etching the underlying continuous first oxide semiconductor layer 106L and the continuous high-k dielectric layer 104L. Figure 5

[0069] Referring Fig. 7A , a patterned photoresist layer (not shown) can be used as a mask to etch the continuous high-k dielectric layer 104L and the continuous first oxide semiconductor layer 106L to form a patterned high-k dielectric layer 104 and a patterned first oxide semiconductor layer 106. In multiple embodiments, as Fig. 7A shown, the patterned high-k dielectric layer 104 and the patterned first oxide semiconductor layer 106 can be longer in length than the patterned gate electrode 102. However, in alternative embodiments, the patterned high-k dielectric layer 104 and the patterned first oxide semiconductor layer 106 can be the same length as or shorter than the length of the patterned gate electrode 102.

[0070] Referring Figure 7B , an embodiment is shown in which the patterned high-k dielectric layer 104, the patterned first oxide semiconductor layer 106, and the patterned gate electrode 102 can have the same length. In this regard, this embodiment can be accomplished by first sequentially depositing a continuous metal gate layer 102L, a continuous high-k dielectric layer 104L, and a continuous first oxide semiconductor layer 106L. Then, a photoresist layer (not shown) can be deposited above the continuous first oxide semiconductor layer 106L and patterned. The patterned photoresist layer can be used as a mask, and the underlying continuous metal gate layer 102L, continuous high-k dielectric layer 104L, and continuous first oxide semiconductor layer 106L can be patterned to form a patterned gate electrode 102, a patterned high-k dielectric layer 104, and a patterned first oxide semiconductor layer 106 all of the same length. The continuous metal gate layer 102L, continuous high-k dielectric layer 104L, and continuous first oxide semiconductor layer 106L can be etched by wet etching and / or dry etching. Additionally, the continuous metal gate layer 102L, continuous high-k dielectric layer 104L, and continuous first oxide semiconductor layer 106L can be patterned in a single etching step or in a series of etching steps. ​

[0071] Reference Figure 8 , the ILD material can be deposited on Fig. 7A (or Figure 7B ) is above the intermediate structure shown in FIG. 1 , so that the patterned gate electrode 102, the patterned high-k dielectric layer 104 and the patterned first oxide semiconductor layer 106 can be embedded in the ILD layer 100.

[0072] Reference Fig. 9 , a photoresist layer 101 may be deposited on the ILD layer 100 and patterned by a photolithography process. The photoresist layer 101 may be made of a positive photoresist material or a negative photoresist material.

[0073] Reference Fig.10 The ILD layer 100 may be patterned using the patterned photoresist layer 101 as a mask. The ILD layer 100 may be patterned by wet etching or dry etching. The contact via 110 may be etched in the ILD layer 100 until a surface portion of the patterned first oxide semiconductor layer 106 may be exposed.

[0074] Reference Fig.11 , a second oxide semiconductor material may then be deposited in the contact via 110 over the exposed portion of the patterned first oxide semiconductor 106 to form a patterned second oxide semiconductor layer 112. In this manner, the thickness t of the patterned first and second oxide semiconductor layers 106, 112 in the active region (i.e., source / drain region) is S / D can be greater than the thickness t in the channel region chan In various embodiments, the patterned second oxide semiconductor layer 112 may be made of a material different from the patterned first oxide semiconductor layer 106. In such embodiments, there may be a clear material interface between the first oxide semiconductor layer 106 and the second oxide semiconductor layer 112. For example, the first oxide semiconductor layer 106 may be formed of an IGZO material. The second oxide semiconductor layer 112 may be formed of an ITO material. The active source / drain region may be oxygen-deficient. Oxygen vacancies may act as donors in the oxide semiconductor; materials with n+ doped materials may be advantageous in the active source / drain region, but undesirable in the channel region.

[0075] In an alternative embodiment, the patterned second oxide semiconductor layer 112 may be made of the same material as the patterned first oxide semiconductor layer 106. In still other embodiments, the patterned second oxide semiconductor layer 112 may be made of the same material as the patterned first oxide semiconductor layer 106, but have a different doping concentration than the patterned first oxide semiconductor layer 106.

[0076] Fig.11 Also shown is the thickness T of the patterned gate electrode 102. MG , the thickness t of the high-k dielectric layer 104 ox , the length of the channel region L chan and the length L of the active (source / drain) region S / D In various embodiments, although a longer or shorter channel region may be formed, the length L of the channel region is chan It may be in the range of 15-150 nm, for example 25-100 nm. In various embodiments, the length L of the active region may be 25-100 nm, although a longer or shorter active region may be formed. S / D It may be in the range of 15-150 nm, for example, 25-100 nm. In various embodiments, although a thicker or thinner channel region may be formed, the thickness t of the first oxide semiconductor layer 106 patterned in the channel region is t 25-100 nm. chan It may be in the range of 2-8 nm, for example, 4-6 nm. In various embodiments, the total thickness t of the patterned first oxide semiconductor layer 106 and the second oxide semiconductor layer 112 in the active region is t S / D The thickness of the high-k dielectric layer 104 may be in the range of 8-16 nm, for example 10-14 nm, but thicker or thinner active regions (source / drain regions) may be formed. ox The thickness t of the patterned gate electrode 102 may be in the range of 2-8 nm, for example 4-6 nm, although thicker or thinner dielectric layers may be formed. In various embodiments, although thicker or thinner metal gate layers may be formed, the thickness t of the patterned gate electrode 102 may be in the range of 2-8 nm, for example 4-6 nm, although thicker or thinner metal gate layers may be formed. MG It may be in the range of 2-16 nm, for example 4-14 nm. In various embodiments, the thickness of the source / drain region t S / D The thickness of the channel region t chan The ratio of may be in the range of 150:2 to 15:8. Thus, a thinner channel exhibiting semiconducting characteristics may be formed, while a thicker active region may be formed to exhibit better conducting characteristics at the electrode contact region.

[0077] refer to Fig. 12A , the remaining volume in the contact via 110 can be filled with a conductive material to form a contact 114 to the active area. The conductive material can be Al, Cu, W, Ti, Ta, TiN, TaN, TiAl or a combination thereof. Other suitable conductive materials are within the contemplated scope of the present invention. In this way, the transistor 300 can be completed. In this embodiment, the transistor 300 is a back-gate transistor, that is, the patterned gate electrode 102 is located below the channel region 106R. Fig. 12A The embodiment shown in can be easily scalable. In addition, Fig. 12AThe embodiment shown in the figure can be formed by depositing the second oxide semiconductor layer 112 by a PVD process, which is a low-cost deposition process relative to other deposition processes such as ALD. However, in order to obtain a desired thickness of the deposited second oxide semiconductor layer 112, the second oxide semiconductor layer 112 is often overfilled, and then an etch-back process can be performed. Since there is no etch stop layer, the etch-back process must be precisely controlled.

[0078] Fig. 12B An alternative embodiment of an alternative configuration with a patterned second oxide semiconductor layer 112 and a contact 114 is shown. In this embodiment, the patterned second oxide semiconductor layer 112 can be deposited in parallel in the contact via 110 in the ILD layer 100. For example, an ALD process can be used to conformally deposit the second oxide semiconductor layer 112 on the sidewalls and bottom of the contact via 110 in the ILD layer 100. The ALD process can be flexible to allow deposition of a variety of IGZO compositions. For example, in the ALD process, InGaZNo can be formed by cycling indium, gallium, and zinc. For compositions rich in indium, additional indium cycles can be performed during the ALD process. Next, the contact via 110 can be filled with a conductive material to form a contact 114 as in the previous embodiment. Fig. 12B The illustrated alternative embodiment can provide a larger surface area interface between the metal contact 114 and the source / drain region. Therefore, a lower contact resistance can be provided. However, such an embodiment may not be as scalable as other embodiments. Since the second oxide semiconductor layer 112 can be conformally deposited on both sidewalls of the contact via, as the cross-sectional area of ​​the contact via decreases, the area available for the metal contact 114 material also decreases.

[0079] Reference Fig.13 , which shows the steps in an alternative method. Figure 5 Starting with the intermediate structure shown, a continuous second oxide semiconductor layer 112L can be formed over the continuous first oxide semiconductor layer 106L and the continuous high-k dielectric layer 104L. In some embodiments, the continuous first oxide semiconductor layer 106L and the continuous second oxide semiconductor layer 112L can be formed in one ALD process. As described above, the ALD process can be flexible to allow deposition of a variety of IGZO compositions. By changing the cycle of materials in the ALD process, different compositions of the continuous first oxide semiconductor layer 106L and the continuous second oxide semiconductor layer 112L can be achieved. Next, as shown in FIG. Figure 6 and Fig. 7A As shown, a photoresist layer 101 may be deposited and patterned over the surface of the continuous second oxide semiconductor layer 112L. Then, similar to Fig. 7AIn the steps shown, the continuous second oxide semiconductor layer 112L, the continuous first oxide semiconductor layer 106L, and the continuous high-k dielectric layer 104L may be patterned to form a patterned second oxide semiconductor layer 112 , a patterned first oxide semiconductor layer 106 , and a patterned high-k dielectric layer 104 .

[0080] Reference Fig.14 , similar to Figure 8 The steps shown in the figure can deposit the ILD material on Fig.13 Thus, in this way, the patterned second oxide semiconductor layer 112 , the patterned first oxide semiconductor layer 106 , and the patterned high-k dielectric layer 104 may be embedded within the ILD layer 100 .

[0081] Reference Fig.15 , a photoresist layer 101 may be deposited over the ILD layer 100 and patterned by a photolithography process. Then, the ILD layer 100 may be etched to expose a surface portion of the patterned second oxide semiconductor layer 112 in the channel region. The etching step may be performed by wet etching or dry etching.

[0082] Reference Fig.16 , a subsequent anisotropic etching process may be performed to selectively remove the exposed portion 115 of the patterned second oxide semiconductor layer 112. For example, the subsequent etching process uses a dry etching or a wet etching process. In this way, the channel region 106R may be made thinner than the active region. In some embodiments, the photoresist layer 101 may be removed before the subsequent etching process for removing the patterned second oxide semiconductor layer 112. In other embodiments, the photoresist layer 101 may be removed after the subsequent etching process for removing the patterned second oxide semiconductor layer 112. The photoresist layer 101 may be removed, for example, by ashing or dissolving the photoresist layer 101.

[0083] Reference Fig.17 , the ILD material can be deposited on Fig.16 The intermediate structure shown in FIG. 1 is formed by depositing a photoresist layer (not shown) over the ILD layer 100 to fill the exposed portion 115 in the channel region 106R. A photoresist layer (not shown) may then be deposited over the ILD layer 100 and patterned to expose a portion of the ILD layer 100 over the active region. The portion of the ILD layer 100 over the active region may be etched to form a contact via 110 to a top surface of the patterned second oxide semiconductor layer 112 in the active region.

[0084] refer to Fig.18A, the contact via 110 can be filled with a conductive material to form a contact 114 to the active area. The conductive material can be Al, Cu, W, Ti, Ta, TiN, TaN, TiAl or a combination thereof. Other suitable conductive materials are within the contemplated scope of the present invention. In this way, the transistor 500 can be completed.

[0085] Fig.18B 1 shows an alternative embodiment in which a portion of the patterned first oxide semiconductor layer 106 above the active region can be removed. Figure 5 Starting from the intermediate structure shown, a patterned photoresist layer (not shown) can be used as a mask to etch the continuous high-k dielectric layer 104L and the continuous first oxide semiconductor layer 106L, thereby forming a patterned high-k dielectric layer 104 and a patterned first oxide semiconductor layer 106. In addition, a patterned photoresist layer (not shown) can be used to mask portions of the semiconductor layer 106 in the channel region 106, so that portions of the first oxide semiconductor layer 106 in the final active region can be removed. The removed portion of the first oxide semiconductor layer 106 can be replaced with a patterned second oxide semiconductor layer 112. Therefore, the material interface between the patterned first oxide semiconductor layer 106 and the second oxide semiconductor layer 112 can be more complex than a simple straight line interface. That is, as described below with reference to Fig.18B and Fig.18D As discussed in more detail, the interface between the patterned first oxide semiconductor layer 106 and the second oxide semiconductor layer 112 may include a plurality of surfaces to form a stepped shape. Fig.18B and Fig.18D As shown, the interface between the patterned first oxide semiconductor layer 106 and the second oxide semiconductor layer 112 may include a vertical surface and a horizontal surface. Fig.18B In the illustrated embodiment, the patterned first oxide semiconductor layer 106 may cover the entire width of each source region and drain region of the patterned second oxide semiconductor layer 112 .

[0086] Fig.18C An alternative embodiment is shown in which all of the patterned first oxide semiconductor layer 106 over the active region may be removed and replaced with a patterned second oxide semiconductor layer 112 .

[0087] Fig.18D Another optional embodiment is shown, in which the portion of the patterned first oxide semiconductor layer 106 covering the active region can be replaced with a patterned second oxide semiconductor layer 112, and a portion of the patterned second oxide semiconductor layer 112 can be formed over a portion of the first patterned oxide semiconductor layer 106. Fig.18BAs discussed in the illustrated embodiment, the interface between the patterned first oxide semiconductor layer 106 and the second oxide semiconductor layer 112 may include a plurality of surfaces to form a step shape. The interface between the patterned first oxide semiconductor layer 106 and the second oxide semiconductor layer 112 may include a vertical surface and a horizontal surface. Fig.18B In contrast to the embodiment shown, Fig.18D In the illustrated embodiment, the patterned first oxide semiconductor layer 106 may pad a portion of the width of each patterned second oxide semiconductor layer 112 portion. 18A to 18D The illustrated alternative embodiment changes the interface configuration between the patterned first oxide semiconductor layer 106 and the second oxide semiconductor layer 112. By changing the amount of source / drain layer intrusion into the channel region 106R in the second oxide semiconductor layer 112, the resistance of the source / drain contact can be modified. By extending the second oxide semiconductor layer 112 into the channel region 106R, the source / drain region resistance can be reduced. However, such a complex interface may require stronger process control during manufacturing.

[0088] Reference Fig.19 , which shows a method for manufacturing a top-gate or front-gate thin film transistor according to another embodiment. In a first step, a continuous first oxide semiconductor layer 106L may be deposited over the ILD layer 100. Next, a continuous second oxide semiconductor layer 112L may be deposited over the continuous first oxide semiconductor layer 106L.

[0089] Reference Fig. 20 , the continuous second oxide semiconductor layer 112L and the continuous first oxide semiconductor layer 106L may be patterned. The patterning may be achieved by covering the continuous second oxide semiconductor layer 112L with a photoresist layer (not shown) and patterning the photoresist. The patterned photoresist may be used as a mask to pattern the continuous second oxide semiconductor layer 112L and the continuous first oxide semiconductor layer 106L to form a patterned second oxide semiconductor layer 112 and a patterned first oxide semiconductor layer 106. Next, an additional ILD material 100 may be deposited on the patterned second oxide semiconductor layer 112 and the patterned first oxide semiconductor layer 106 so that the patterned second oxide semiconductor layer 112 and the patterned first oxide semiconductor layer 106 may be embedded within the ILD layer 100.

[0090] Reference Fig.21, the ILD layer 100 and the patterned second oxide semiconductor layer 112 may be etched in the channel region to form a groove in the ILD layer 100 and the patterned second oxide semiconductor layer 112. The etching may be achieved by first depositing a photoresist layer (not shown) and then patterning the photoresist layer. The ILD layer 100 and the patterned second oxide semiconductor layer 112 may be etched using the same etchant in the same step or in sequential etching steps. The ILD layer 100 and the patterned second oxide semiconductor layer 112 may be wet etched or dry etched.

[0091] Reference Fig. 22 A high-k dielectric layer 104 may be conformally deposited on the sidewalls and bottom of the trenches in the ILD layer 100 and the patterned second oxide semiconductor layer 112. Next, the remaining volume of the trenches may be filled with a gate electrode material to form a patterned gate electrode 102 over the channel region.

[0092] Reference Fig.23 , can be Fig.21 The surface of the intermediate structure shown is planarized to remove any excess high-k dielectric material 104 and / or any excess gate electrode 102 material. Planarization can be achieved by chemical mechanical polishing. After planarization, the top surfaces of the ILD 100, the patterned second oxide semiconductor layer 112, the high-k dielectric material 104, and the gate electrode 102 can be coplanar.

[0093] Reference Fig.24A , additional ILD material can be deposited on Fig.23 The intermediate structure shown in FIG. 6 is formed on the ILD layer 100. Next, a contact via (not shown) may be formed in the ILD layer 100. In various embodiments, a contact via is formed that exposes the top surface of the patterned second oxide semiconductor layer 112 in the active region and exposes the top surface of the patterned gate electrode 102 in the channel region. In this way, the transistor 600 may be completed. In this embodiment, the transistor 600 is a top-gate transistor.

[0094] Fig. 24B FIG. 6 shows a transistor 650 according to an alternative embodiment. In this embodiment, the transistor 650 includes only the patterned first oxide semiconductor layer 106. Fig.19 , instead of depositing the continuous first oxide semiconductor layer 106L and the continuous second oxide semiconductor layer 112L, a single continuous first oxide semiconductor layer 106L having a thickness approximately equal to the combined thickness of the continuous first oxide semiconductor layer 106L and the continuous second oxide semiconductor layer 112L of the previous embodiment may be deposited over the ILD layer 100. Figure 20-24A As shown, the process continues to produce transistor 650. Fig. 24BThe illustrated embodiment includes a single continuous first oxide semiconductor layer 106L, and thus the processing steps for forming the transistor 650 may be simplified.

[0095] Fig.25 is a flow chart illustrating an exemplary method 700 for manufacturing transistors 300, 400, 500. Referring to step 702, the method 700 includes depositing at least one oxide semiconductor layer 106, 112 over a substrate or interconnect level dielectric layer 100. Referring to step 704, the method 700 includes etching a central portion of the at least one oxide semiconductor layer 106, 112 to form a channel region 106R and source / drain regions on either side of the channel region 106R, wherein the total thickness of the channel region 106R is thinner than the total thickness of the source / drain regions.

[0096] Fig.26 8 is a flow chart illustrating an exemplary method 800 for manufacturing transistors 300, 400, 500. Referring to step 802, the method 800 includes depositing a first oxide semiconductor layer 106 over a substrate or interconnect level dielectric layer 100. Referring to step 804, the method 800 includes depositing a photoresist layer 101 over the first oxide semiconductor layer 106 and patterning it to expose a peripheral portion of the oxide semiconductor layer 106. Referring to step 806, the method 800 includes depositing a second oxide semiconductor layer 112 over the exposed peripheral portion of the first oxide semiconductor layer 106 to form source / drain regions, wherein the channel region 106R is located between the source / drain regions.

[0097] In general, the structures and methods of the present invention can be used to form thin film transistors (TFTs), which may be attractive for BEOL integration because they can be processed at low temperatures and functionality can be added to the BEOL while freeing up area in the FEOL. The use of TFTs in the BEOL can be used as a scaling path to the 3nm technology node or beyond by moving peripheral devices (such as power gates or I / O devices) from the FEOL to higher metal levels of the BEOL. For a given device, moving the TFT from the FEOL to the BEOL can contribute to an area reduction of approximately 5-10%.

[0098] The embodiments relate to transistors 300, 400, 500, which include a patterned gate electrode 102; a dielectric layer 104 located above the patterned gate electrode 102; a patterned first oxide semiconductor layer 106, which includes a channel region 106R; a patterned second oxide semiconductor layer 112, which includes source / drain regions located on either side of the channel region 106R, wherein the thickness of the source / drain region is t S / D Greater than the thickness t of the channel region 106R chan .

[0099] In one embodiment, the material of the patterned second oxide semiconductor layer 112 is different from the material of the patterned first oxide semiconductor layer 106. In another embodiment, the source / drain region can be made of the first oxide semiconductor layer 106 and the second oxide semiconductor layer 112. In some embodiments of the present invention, the patterned second oxide semiconductor layer 112 contacts the dielectric layer 104. Embodiments of the present invention include SiO2, Al2O3, HfO2, HZO, HfSiO x 、HfLaO x The dielectric layer 104 is formed of one or more of the above-mentioned layers. The embodiment of the present invention includes a patterned first oxide semiconductor layer 106, which may be formed of In x Ga y Zn z O w , In2O3, Ga2O3, ZnO or In x Sn y O z A formation in .

[0100] Another embodiment relates to a transistor 600, which includes a patterned first oxide semiconductor layer 106 including a channel region 106R; a dielectric layer 104 located on the patterned first oxide semiconductor layer 106; a patterned gate electrode 102 located above the dielectric layer 104; a patterned second oxide semiconductor layer 112 including source / drain regions located on either side of the channel region 106R, wherein the thickness of the source / drain region is t S / D Greater than the thickness t of the channel region 106R chan . Embodiments of the present invention include transistors in which the material of the patterned second oxide semiconductor layer 112 is different from the material of the patterned first oxide semiconductor layer 106. Still other embodiments of the present invention include source / drain regions made of the first oxide semiconductor layer 106 and the second oxide semiconductor layer 112. In some embodiments of the present invention, the patterned second oxide semiconductor layer 112 contacts the dielectric layer 104. Embodiments of the present invention include transistors that can be made of SiO2, Al2O3, HfO2, HZO, HfSiO x 、HfLaO x The dielectric layer 104 is formed of one or more of the above. The embodiment of the present invention includes a patterned first oxide semiconductor layer, which may be formed of In x Ga y Zn z O w , In2O3, Ga2O3, ZnO or In x Sn y O zIn various embodiments of the present invention, a thickness ratio of the source / drain region to the channel region 106R is in a range of 150:2 to 15:8.

[0101] Another embodiment relates to a method of manufacturing transistors 300, 400, 500, 600, including an operation of depositing a first oxide semiconductor layer 106 over the interconnect level dielectric layer 100. The exemplary method also includes an operation of forming a channel region 106R in the first oxide semiconductor layer 106. The exemplary method also includes an operation of forming source / drain regions on either side of the channel region 106R, wherein the thickness of the source / drain region is t S / D Greater than the thickness t of the channel region 106R chan .

[0102] In one embodiment, the method may further include an operation of depositing a second oxide semiconductor layer in the source / drain region, wherein the second oxide semiconductor layer 112 is a different material from the first oxide semiconductor layer 106. In one exemplary method, the second oxide semiconductor layer 112 is deposited over the first oxide semiconductor layer 106, wherein the source / drain region includes the first oxide semiconductor layer 106 and the second oxide semiconductor layer 112. In another embodiment, the method may further include the following operations: depositing a metal gate layer 102; and depositing a dielectric layer 104, wherein the dielectric layer 104 includes SiO2, Al2O3, HfO2, HZO, HfSiO x 、HfLaO x wherein the first oxide semiconductor layer 106 includes In x Ga y Zn z O w , In2O3, Ga2O3ZnO or In x Sn y O z In one exemplary method, the metal gate layer 102 is deposited under the first oxide semiconductor layer 106 and the dielectric layer 104. In another exemplary method, the metal gate layer 102 is deposited on the first oxide semiconductor layer 106 and the dielectric layer 104. In one exemplary method, the thickness ratio of the source / drain region to the channel region 106R is in the range of 150:2 to 15:8.

[0103] Some embodiments of the present application provide a transistor, including: a patterned gate electrode; a dielectric layer located above the patterned gate electrode; a patterned first oxide semiconductor layer including a channel region; and a patterned second oxide semiconductor layer including a source / drain region located on either side of the channel region, wherein the thickness of the source / drain region is greater than the thickness of the channel region. In some embodiments, the source / drain region further includes: the patterned first oxide semiconductor layer, wherein the material of the patterned second oxide semiconductor layer is different from the material of the patterned first oxide semiconductor layer. In some embodiments, the material of the patterned second oxide semiconductor layer is different from the material of the patterned first oxide semiconductor layer. In some embodiments, the patterned second oxide semiconductor layer contacts the dielectric layer. In some embodiments, the dielectric layer includes SiO2, Al2O3, HfO2, HZO, HfSiO x 、HfLaO x In some embodiments, the patterned first oxide semiconductor layer includes In x Ga y Zn z O w , In2O3, Ga2O3, ZnO or In x Sn y O z In some embodiments, an interface between the patterned first oxide semiconductor layer and the patterned second oxide semiconductor layer includes a vertical surface and a horizontal surface. In some embodiments, the patterned first oxide semiconductor layer is located below the entire width of each source region and drain region of the patterned second oxide semiconductor layer.

[0104] Some other embodiments of the present application provide a transistor, comprising: a patterned first oxide semiconductor layer, comprising a channel region; a dielectric layer, located above the patterned first oxide semiconductor layer; a patterned gate electrode, located above the dielectric layer; and a patterned second oxide semiconductor layer, comprising a source / drain region located on either side of the channel region, wherein the thickness of the source / drain region is greater than the thickness of the channel region. In some embodiments, the source / drain region further comprises: the patterned first oxide semiconductor layer, wherein the material of the patterned second oxide semiconductor layer is different from the material of the patterned first oxide semiconductor layer, and wherein the patterned second oxide semiconductor layer is formed above the patterned first oxide semiconductor layer. In some embodiments, the material of the patterned second oxide semiconductor layer is different from the material of the patterned first oxide semiconductor layer. In some embodiments, the dielectric layer comprises SiO2, Al2O3, HfO2, HZO, HfSiO x 、HfLaO x One or more layers thereof.

[0105] Some other embodiments of the present application provide a method for manufacturing a transistor, comprising: depositing a first oxide semiconductor layer above an interconnect level dielectric layer; forming a channel region in the first oxide semiconductor layer; forming a source / drain region on either side of the channel region, wherein the thickness of the source / drain region is greater than the thickness of the channel region. In some embodiments, the method further comprises: depositing a second oxide semiconductor layer in the source / drain region, wherein the second oxide semiconductor layer is a different material from the first oxide semiconductor layer. In some embodiments, the second oxide semiconductor layer is deposited above the first oxide semiconductor layer, wherein the source / drain region comprises the first oxide semiconductor layer and the second oxide semiconductor layer. In some embodiments, the method further comprises: depositing a metal gate layer; depositing a dielectric layer, wherein the dielectric layer comprises SiO2, Al2O3, HfO2, HZO, HfSiO x 、HfLaO x , one or more layers thereof, and wherein the first oxide semiconductor layer includes In x Ga y Zn z O w , In2O3, Ga2O3, ZnO, or In x SnyO zIn some embodiments, the metal gate layer is deposited below the first oxide semiconductor layer and the dielectric layer. In some embodiments, the metal gate layer is deposited above the first oxide semiconductor layer and the dielectric layer. In some embodiments, the method further comprises removing a portion of the first oxide semiconductor layer in the source / drain region before depositing the second oxide semiconductor layer in the source / drain region. In some embodiments, the method further comprises removing all of the first oxide semiconductor layer in the source / drain region before depositing the second oxide semiconductor layer in the source / drain region.

[0106] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A transistor, comprising: a patterned gate electrode; a dielectric layer located above the patterned gate electrode; a patterned first oxide semiconductor layer including a channel region; as well as a patterned second oxide semiconductor layer, comprising a source / drain region located on either side of the channel region, wherein the thickness of the source / drain region is greater than the thickness of the channel region, a pair of conductive contacts located on the patterned second oxide semiconductor layer, wherein outer sidewalls of the pair of conductive contacts are aligned with outer sidewalls of the patterned second oxide semiconductor layer and sidewalls of the patterned first oxide semiconductor layer, The material of the patterned second oxide semiconductor layer is different from that of the patterned first oxide semiconductor layer, and the patterned second oxide semiconductor layer contacts the dielectric layer.

2. The transistor according to claim 1, wherein The source / drain region further comprises: The patterned first oxide semiconductor layer, wherein a portion of the patterned second oxide semiconductor layer is formed over the patterned first oxide semiconductor layer.

3. The transistor according to claim 1, wherein A ratio of a thickness of the source / drain region to a thickness of the channel region is in a range of 150:2 to 15:

8.

4. The transistor according to claim 1, wherein: The pair of conductive contacts includes Al, Cu, W, Ti, Ta, TiN, TaN, TiAl, or a combination thereof.

5. The transistor according to claim 1, wherein The dielectric layer includes SiO2, Al2O3, HfO2, HZO, HfSiO x 、HfLaO x One or more layers thereof.

6. The transistor according to claim 1, wherein The patterned first oxide semiconductor layer includes In x Ga y Zn z O w , In2O3, Ga2O3, ZnO or In x Sn y O z One of them.

7. The transistor according to claim 1, wherein An interface between the patterned first oxide semiconductor layer and the patterned second oxide semiconductor layer includes a vertical surface and a horizontal surface.

8. A transistor comprising: a patterned gate electrode; a dielectric layer located above the patterned gate electrode; a patterned first oxide semiconductor layer including a channel region; as well as a patterned second oxide semiconductor layer, comprising a source / drain region located on either side of the channel region, wherein the thickness of the source / drain region is greater than the thickness of the channel region, a pair of conductive contacts located on the patterned second oxide semiconductor layer, wherein outer sidewalls of the pair of conductive contacts are aligned with outer sidewalls of the patterned second oxide semiconductor layer and sidewalls of the patterned first oxide semiconductor layer, The interface between the patterned first oxide semiconductor layer and the patterned second oxide semiconductor layer includes a vertical surface and a horizontal surface, and the patterned first oxide semiconductor layer is located below the entire width of each source / drain region of the patterned second oxide semiconductor layer.

9. A transistor comprising: a patterned first oxide semiconductor layer including a channel region; a dielectric layer located above the patterned first oxide semiconductor layer; a patterned gate electrode located above the dielectric layer; as well as a patterned second oxide semiconductor layer, comprising a source / drain region located on either side of the channel region, wherein the thickness of the source / drain region is greater than the thickness of the channel region, a pair of conductive contacts located on the patterned second oxide semiconductor layer, wherein outer sidewalls of the pair of conductive contacts are aligned with outer sidewalls of the patterned second oxide semiconductor layer and sidewalls of the patterned first oxide semiconductor layer, The material of the patterned second oxide semiconductor layer is different from that of the patterned first oxide semiconductor layer, and the patterned second oxide semiconductor layer contacts the dielectric layer.

10. The transistor according to claim 9, wherein The source / drain region further comprises: The patterned first oxide semiconductor layer, wherein a portion of the patterned second oxide semiconductor layer is formed over the patterned first oxide semiconductor layer.

11. The transistor according to claim 9, wherein A ratio of a thickness of the source / drain region to a thickness of the channel region is in a range of 150:2 to 15:

8.

12. The transistor according to claim 9, wherein The dielectric layer includes SiO2, Al2O3, HfO2, HZO, HfSiO x 、HfLaO x One or more layers thereof.

13. A method of manufacturing a transistor, comprising: depositing a first oxide semiconductor layer over the interconnect level dielectric layer; patterning the first oxide semiconductor layer, forming a channel region in the first oxide semiconductor layer and forming a patterned first oxide semiconductor layer; forming a source / drain region on either side of the channel region, wherein the thickness of the source / drain region is greater than the thickness of the channel region; depositing a second oxide semiconductor layer in the source / drain region; and patterning the second oxide semiconductor layer, and forming a pair of conductive contacts on the patterned second oxide semiconductor layer, wherein outer sidewalls of the pair of conductive contacts are aligned with outer sidewalls of the patterned second oxide semiconductor layer and sidewalls of the patterned first oxide semiconductor layer, The material of the patterned second oxide semiconductor layer is different from the material of the patterned first oxide semiconductor layer, and the patterned second oxide semiconductor layer contacts the interconnection level dielectric layer.

14. The method according to claim 13, wherein: A portion of the patterned second oxide semiconductor layer is formed over the patterned first oxide semiconductor layer.

15. The method according to claim 14, wherein: A portion of the second oxide semiconductor layer is deposited over the patterned first oxide semiconductor layer, wherein the source / drain region includes the patterned first oxide semiconductor layer and the patterned second oxide semiconductor layer.

16. The method according to claim 13, further comprising: depositing a metal gate layer; Depositing a dielectric layer, wherein the dielectric layer comprises SiO2, Al2O3, HfO2, HZO, HfSiO x 、HfLaO x , one or more layers thereof, and wherein the first oxide semiconductor layer includes In x Ga y Zn z O w , In2O3, Ga2O3, ZnO, or In x SnyO z One of them.

17. The method according to claim 16, wherein: The metal gate layer is deposited below the patterned first oxide semiconductor layer and the dielectric layer.

18. The method according to claim 16, wherein: The metal gate layer is deposited over the patterned first oxide semiconductor layer and the dielectric layer. 19 . The method of claim 14 , further comprising removing a portion of the first oxide semiconductor layer in the source / drain region before depositing the second oxide semiconductor layer in the source / drain region. 20 . The method of claim 14 , further comprising removing all of the first oxide semiconductor layer in the source / drain region before depositing the second oxide semiconductor layer in the source / drain region.

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