Incremental generation of quantum circuits

Abstract

A method comprising: detecting a submission of a first quantum circuit for compilation, the first quantum circuit comprising a first set of quantum logic gates; generating a first gate index comprising an ordered list of a subset of the set of quantum logic gates, each quantum logic gate of the subset of quantum logic gates comprising a corresponding set of qubits acted upon by the quantum logic gate; comparing the first gate index with a second gate index to determine structural equivalence of the first quantum circuit with the second quantum circuit; and in response to determining the structural equivalence of the first quantum circuit with the second quantum circuit, parameterizing a first set of parameters of a second set of quantum logic gates of the second quantum circuit with a second set of parameters of the first set of quantum logic gates.

Description

Technical Field

[0001] The present invention generally relates to variational algorithms using quantum computing. More specifically, the present invention relates to a method for incrementally generating quantum circuits. Background Art

[0002] In the following, a "Q" prefix in a word of a phrase indicates a reference to that word or phrase in the context of quantum computing, unless explicitly distinguished when used.

[0003] Molecules and subatomic particles obey the laws of quantum mechanics, the branch of physics that explores how the physical world works at the most fundamental level. At this level, particles behave in strange ways, assume more than one state at the same time, and interact with other particles that are very far away. Quantum computing exploits these quantum phenomena to process information.

[0004] The computers we use today are called classical computers (also referred to herein as "conventional" computers or conventional nodes, or "CNs"). Conventional computers use conventional processors, semiconductor memories, and magnetic or solid-state storage devices, manufactured using semiconductor materials and techniques, in the so-called Von Neumann architecture. Specifically, the processors in conventional computers are binary processors, i.e., they operate on binary data represented in 1s and 0s.

[0005] Quantum processors (q-processors) use the odd properties of entangled quantum bit devices (complexly referred to herein as "qubits", "qubits") to perform computational tasks. In the specific domain where quantum mechanics operates, particles of matter can exist in multiple states, such as an "on" state, an "off" state, and a simultaneous "on" and "off" state. Where binary computing using semiconductor processors is limited to using only on and off states (equivalent to 1 and 0 in binary code), quantum processors exploit these quantum states of matter to output signals that are useful in data computation.

[0006] Traditional computers encode information in bits. Each bit can take on a value of either 1 or 0. These 1s and 0s act as on / off switches that ultimately drive the computer's functions. Quantum computers, on the other hand, are based on qubits, which operate according to two key principles of quantum physics: superposition and entanglement. Superposition means that each qubit can represent both 1 and 0 at the same time. Entanglement means that qubits in superposition can be related to each other in a nonclassical way; that is, the state of one qubit (whether it is 1 or 0 or both) can depend on the state of another qubit, and there is more information about the two qubits that can be ascertained when they are entangled than when they are processed separately.

[0007] Using these two principles, qubits operate as more complex information processors, enabling quantum computers to function in a way that allows them to solve problems that are difficult to handle using conventional computers. IBM has successfully built and demonstrated the operability of a quantum processor using superconducting qubits (IBM is a registered trademark of International Business Machines Corporation in the United States and other countries.)

[0008] Quantum algorithms apply quantum operations (quantum gates) to subsets of qubits. Quantum gates are analogous to instructions in a classical computing program. Quantum circuits are representations of quantum algorithms using quantum gates. The illustrative embodiments recognize that currently available quantum computing models require that quantum algorithms be specified as quantum circuits on idealized hardware, rather than actual quantum computers. The illustrative embodiments further recognize that quantum algorithms need to be mapped into representations that can be executed by actual quantum computers through a process called quantum circuit compilation. These illustrative embodiments recognize that due to the physical constraints of actual quantum computers, compilation often requires the addition of additional gates in order to move the qubit state to the position where the desired gate acts on the qubit state.

[0009] The illustrative embodiments recognize that quantum processors can perform a wide variety of algorithms that conventional processors cannot. The illustrative embodiments further recognize that currently available quantum variational algorithms require quantum circuit compilation for each iteration. Conventional processors perform optimization algorithms that vary the parameters of a wave function. The quantum processor calculates the corresponding total energy of the wave function.

[0010] The illustrative embodiments recognize that the compilation of each quantum circuit represents a significant amount of the total running time of a quantum algorithm. The illustrative embodiments further recognize that many quantum algorithms are composed of quantum circuits of identical structure. The illustrative embodiments further recognize that a quantum circuit compiler never changes the temporal order in which a given gate appears on a given set of qubits. For example, an uncompiled quantum circuit may include a first measurement gate and a second measurement gate on a first qubit. After compilation, the compiled quantum circuit will include the first and second measurement gates on the first qubit and execute in the same order as the uncompiled quantum circuit. Summary of the invention

[0011] The illustrative embodiments provide a method, system, and computer program product for incremental generation of quantum circuits. In an embodiment, a method includes detecting a submission of a first quantum circuit for compilation, the first quantum circuit including a first set of quantum logic gates. In an embodiment, a method includes generating a first gate index for the first quantum circuit, the first gate index including an ordered table of:

[0012] The set of quantum logic gates subset, each quantum logic gate in the quantum logic gate subset includes a corresponding set of qubits acted upon by the quantum logic gate.

[0013] In an embodiment, a method includes comparing a first gate index to a second gate index of a second quantum circuit to determine structural equivalence of the first quantum circuit and the second quantum circuit. In an embodiment, the method includes parameterizing a first set of parameters of a second set of quantum logic gates of the second quantum circuit with a second set of parameters of the first set of quantum logic gates in response to determining structural equivalence of the first quantum circuit and the second quantum circuit. In an embodiment, the second quantum circuit is a previously compiled quantum circuit.

[0014] In an embodiment, a method includes compiling the first quantum circuit in response to determining that the first quantum circuit and the second quantum circuit are not structurally equivalent. In an embodiment, the structurally equivalent includes a number of quantum logic gates of a particular type of the first set of quantum logic gates being different from a number of quantum logic gates of a particular type of the second set of quantum logic gates.

[0015] In an embodiment, a method includes storing a set of previously compiled quantum circuits in a database. In an embodiment, the structural equality includes a number of quantum logic gates of each specific type of the first set of quantum logic gates being equal to a number of quantum logic gates of the same specific type of the second set of quantum logic gates.

[0016] In an embodiment, the method is embodied in a computer program product comprising one or more computer-readable storage devices and computer-readable program instructions stored on the one or more computer-readable tangible storage devices and executed by one or more processors.

[0017] Embodiments include a computer usable program product. The computer usable program product includes a computer readable storage device and program instructions stored on the storage device.

[0018] Embodiments include a computer system. The computer system includes a processor, a computer-readable memory and a computer-readable storage device, and program instructions stored on the storage device for execution by the processor via the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The novel features which are believed to be characteristic of the invention are set forth in the appended claims. However, the invention itself, as well as the preferred mode of use, further objects and advantages thereof, will be best understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings in which:

[0020] Figure 1 depicts a block diagram of a network of data processing systems in which the illustrative embodiments may be implemented;

[0021] Figure 2 depicts a block diagram of a data processing system in which the illustrative embodiments may be implemented;

[0022] Figure 3 depicts a block diagram of an exemplary configuration for incremental generation of quantum circuits according to one illustrative embodiment;

[0023] Figure 4 depicts a block diagram of an example configuration for incremental generation of quantum circuits according to one illustrative embodiment; and

[0024] Figure 5 Depicted is a flow chart of an exemplary method for incremental generation of quantum circuits in accordance with one illustrative embodiment. DETAILED DESCRIPTION

[0025] The illustrative embodiments used to describe the present invention generally address and solve the above-described problems of quantum circuit compilation.The illustrative embodiments provide a method for incremental generation of quantum circuits.

[0026] An embodiment provides a method for incrementally generating quantum circuits. Another embodiment provides a quantum computer usable program product, the quantum computer usable program product including a computer readable storage device and program instructions stored on the storage device, the stored program instructions including a method for incrementally generating quantum circuits. These instructions are executable using a conventional or quantum processor. Another embodiment provides a computer system, the computer system including a conventional or quantum processor, a computer readable memory, and a computer readable storage device, and program instructions stored on the storage device for execution by the processor via the memory, the stored program instructions including a method for incrementally generating quantum circuits.

[0027] The illustrative embodiments recognize that hybrid quantum algorithms, such as variational algorithms, include switching between generating inputs or modifications to a quantum circuit on a classical computer, running the circuit on a quantum computer, and serially generating subsequent quantum circuits using the output. A variational quantum eigensolver (VQE) is a non-limiting example of a variational algorithm executed with a quantum computer.

[0028] An embodiment detects a first quantum circuit submitted for compilation. The first quantum circuit is an uncompiled quantum circuit. An embodiment compares the first quantum circuit to a previously compiled quantum circuit. For example, an embodiment generates a first list of a first set of quantum gates of the first quantum circuit, each quantum gate acting on a corresponding qubit group of the first quantum circuit. The embodiment also generates a second list of a second set of quantum gates of the previously compiled quantum circuit, each quantum gate acting on a corresponding qubit group of the previously compiled quantum circuit.

[0029] The embodiment compares the first list to the second list to determine a structural similarity between the first circuit and the previously compiled circuit. In an embodiment, the first circuit is structurally equal to the previously compiled circuit when the number of gates of each type in the first list matches the number of gates of each type in the second list. In another example, the embodiment may determine that the number of gates of the first gate type in the first list is different from the number of gates of the first gate type in the second list. In response, the embodiment determines that the first circuit and the previously compiled circuit are not structurally equal. The embodiment compiles the first circuit in response to determining that the first circuit is not structurally equal to the previously compiled circuit.

[0030] In response to determining that the first quantum circuit and the previously compiled circuit are structurally equivalent, an embodiment parameterizes the previously compiled circuit with a parameter set for the first quantum circuit.

[0031] For clarity of description, and without implying any limitation thereto, some example configurations are used to describe the illustrative embodiments. In light of this disclosure, those of ordinary skill in the art will be able to conceive of many changes, adaptations, and modifications of the described configurations for achieving the described purposes, and these changes, adaptations, and modifications are considered within the scope of the illustrative embodiments.

[0032] In addition, simplified diagrams of data processing environments are used in the figures and illustrative embodiments. In an actual computing environment, additional structures or components not shown or described herein, or structures or components different from those shown but used for similar functions as described herein, may exist without departing from the scope of the illustrative embodiments.

[0033] Furthermore, the illustrative embodiments are described with respect to specific actual or hypothetical components only as examples. The steps described by the different illustrative embodiments may be adapted using different components that may be purposed or repurposed to provide the described functionality within a data processing environment, and such adaptations are contemplated within the scope of the illustrative embodiments.

[0034] The illustrative embodiments are described with respect to certain types of steps, applications, quantum logic gates, and data processing environments by way of example only. Any particular representation of these and other similar products is not intended to limit the invention. Any suitable representation of these and other similar products may be selected within the scope of the illustrative embodiments.

[0035] The examples in this disclosure are only for clarity of description and are not limited to the illustrative embodiments. Any advantages listed here are only examples and are not intended to limit these illustrative embodiments. Additional or different advantages can be achieved by specific illustrative embodiments. In addition, specific illustrative embodiments may have some, all or no advantages listed above.

[0036] With reference to the drawings and in particular to Figure 1 and 2 , these figures are exemplary diagrams of data processing environments in which illustrative embodiments may be implemented. Figure 1 and 2 These are examples only and are not intended to assert or imply any limitation with regard to the environments in which different embodiments may be implemented. Specific embodiments may make numerous modifications to the depicted environments based on the following description.

[0037] Figure 1 A block diagram of a network of data processing systems in which the illustrative embodiments may be implemented is depicted. Data processing environment 100 is a network of computers in which the illustrative embodiments may be implemented. Data processing environment 100 includes network 102. Network 102 is a medium used to provide communication links between different devices and computers connected together within data processing environment 100. Network 102 may include connections such as wired, wireless communication links, or fiber optic cables.

[0038] Client or server are merely example roles for certain data processing systems connected to network 102 and are not intended to exclude other configurations or roles for these data processing systems. Server 106 is coupled to network 102 along with storage unit 108. Server 106 is a conventional data processing system. Storage unit 108 includes database 109. Database 109 stores a set of previously compiled quantum circuit representations for performing quantum computing processes thereon. Quantum processing system 140 is coupled to network 102. Quantum processing system 140 is a quantum data processing system. The software application can be executed on any quantum data processing system in data processing environment 100. The software application described in Figure 1 Any software application executed in the quantum processing system 140 in can be configured to execute in another quantum data processing system in a similar manner. Figure 1 Any data or information stored or generated in a quantum processing system 140 in a quantum data processing system may be configured to be stored or generated in a similar manner in another quantum data processing system. A quantum data processing system such as quantum processing system 140 may contain data and may have a software application or software tool that performs quantum computing processes thereon.

[0039] Clients 110, 112, and 114 are also coupled to network 102. Conventional data processing systems, such as server 106 or clients 110, 112, or 114, may contain data and may have software applications or software tools that perform conventional computing processes thereon.

[0040] This is for example purposes only and does not imply any limitation on such architecture. Figure 1 Certain components that may be used in an example implementation of an embodiment are depicted. For example, server 106 and clients 110, 112, 114 are depicted as servers and clients only as an example, without implying a limitation to a client-server architecture. As another example, an embodiment may be distributed over several conventional data processing systems, quantum data processing systems, and data networks as shown, while another embodiment may be implemented on a single conventional data processing system or a single quantum data processing system within the scope of the illustrative embodiments. Conventional data processing systems 106, 110, 112, and 114 also represent example nodes in a cluster, partitions, and other configurations suitable for implementing an embodiment.

[0041] Device 132 is an example of a conventional computing device as described herein. For example, device 132 may take the form of a smartphone, a tablet computer, a laptop computer, a fixed or portable form of client 110, a wearable computing device, or any other suitable device. Figure 1 Any software application that is executed in another conventional data processing system in may be configured to execute in device 132 in a similar manner. Figure 1 Any data or information stored or generated in another conventional data processing system in may be configured to be stored or generated in device 132 in a similar manner.

[0042] Server 106, storage unit 108, quantum processing system 140, and clients 110, 112, and 114, and device 132 may be connected to network 102 using wired connections, wireless communication protocols, or other suitable data connectivity. Clients 110, 112, and 114 may be, for example, personal computers or network computers.

[0043] In the depicted example, server 106 may provide data, such as boot files, operating system images, and applications to clients 110, 112, and 114. In this example, clients 110, 112, and 114 may be clients to server 106. Clients 110, 112, 114, or some combination thereof, may include their own data, boot files, operating system images, and applications. Data processing environment 100 may include additional servers, clients, and other devices not shown.

[0044] In the depicted example, memory 144 may provide data, such as boot files, operating system images, and applications to quantum processor 142. Quantum processor 142 may include its own data, boot files, operating system images, and applications. Data processing environment 100 may include additional memory, quantum processors, and other devices not shown. According to one or more embodiments, memory 144 includes application 105, which may be configured to implement one or more functions described herein for converging a solution space for a variational algorithm for quantum computing.

[0045] In the depicted example, data processing environment 100 may be the Internet. Network 102 may represent a collection of networks and gateways that use Transmission Control Protocol / Internet Protocol (TCP / IP) and other protocols to communicate with each other. The core of the Internet is a backbone of data communication links between master nodes or host computers, including thousands of commercial, government, educational and other computer systems that route data and messages. Of course, data processing environment 100 may also be implemented as many different types of networks, such as an intranet, a local area network (LAN), or a wide area network (WAN). Figure 1 This is intended as an example, and not as an architectural limitation for the different illustrative embodiments.

[0046] Among other uses, data processing environment 100 may be used to implement a client-server environment in which the illustrative embodiments may be implemented. The client-server environment enables software applications and data to be distributed across a network so that the applications function by using interactions between conventional client data processing systems and conventional server data processing systems. Data processing environment 100 may also employ an interoperable service-oriented architecture.

[0047] Software components distributed across a network can be packaged together as a consistent business application. Data processing environment 100 can also take the form of a cloud and employ a cloud computing model of service delivery to facilitate on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be quickly provisioned and released with minimal management effort or interaction with service providers.

[0048] See also Figure 2 , which depicts a block diagram of a data processing system in which the illustrative embodiments may be implemented. Data processing system 200 is an example of a conventional computer, such as Figure 1 Servers 104 and 106, or clients 110, 112, and 114, or another type of device in which computer usable program code or instructions implementing the processes for the illustrative embodiments may be located.

[0049] Data processing system 200 also represents a conventional data processing system or configuration thereof, such as Figure 1 A conventional data processing system 132 in which computer usable program code or instructions implementing the processes of the illustrative embodiments may be located. Data processing system 200 is described as a computer only by way of example and is not limited thereto.

[0050] Other equipment (such as Figure 1 An implementation in the form of device 132 in the data processing system 200 may modify the data processing system 200, such as by adding a touch interface, and even eliminating certain depicted components from the data processing system 200, without departing from the general description of the operation and functionality of the data processing system 200 described herein.

[0051] In the depicted example, data processing system 200 employs a hub architecture including north bridge and memory controller hub (NB / MCH) 202 and south bridge and input / output (I / O) controller hub (SB / ICH) 204. Processing unit 206, main memory 208, and graphics processor 210 are coupled to north bridge and memory controller hub (NB / MCH) 202. Processing unit 206 may include one or more processors and may be implemented using one or more heterogeneous processor systems. Processing unit 206 may be a multi-core processor.

[0052] In some implementations, graphics processor 210 may be coupled to NB / MCH 202 via an accelerated graphics port (AGP).

[0053] In the depicted example, a local area network (LAN) adapter 212 is coupled to the south bridge and I / O controller hub (SB / ICH) 204. An audio adapter 216, a keyboard and mouse adapter 220, a modem 222, a read-only memory (ROM) 224, a universal serial bus (USB) and other ports 232, and a PCI / PCIe device 234 are coupled to the south bridge and I / O controller hub 204 via a bus 238. A hard disk drive (HDD) or solid-state drive (SSD) 226 and a CD-ROM 230 are coupled to the south bridge and I / O controller hub 204 via a bus 240. The PCI / PCIe devices 234 may include, for example, Ethernet adapters, add-in cards, and PC cards for notebook computers. PCI uses a card bus controller, while PCIe does not. ROM 224 may be, for example, a flash binary input / output system (BIOS). Hard disk drive 226 and CD-ROM 230 may use, for example, an integrated drive electronics (IDE), a serial advanced technology attachment (SATA) interface, or variations such as external SATA (eSATA) and micro SATA (mSATA). Super I / O (SIO) device 236 may be coupled to south bridge and I / O controller hub (SB / ICH) 204 via bus 238.

[0054] Memories such as main memory 208, ROM 224, or flash memory (not shown) are some examples of computer usable storage devices. Hard disk drives or solid state drives 226, CD-ROM 230, and other similarly available devices are some examples of computer usable storage devices, including computer usable storage media.

[0055] An operating system runs on processing unit 206. The operating system coordinates and provides Figure 2 The operating system may be a commercially available operating system for any type of computing platform, including but not limited to server systems, personal computers, and mobile devices. Object-oriented or other types of programming systems may operate in conjunction with the operating system and provide calls to the operating system from programs or applications executing on data processing system 200.

[0056] Instructions for operating systems, object-oriented programming systems, and applications or programs, such as Figure 1206, and may be loaded into at least one of one or more memories, such as main memory 208, for execution by processing unit 206. The processes of the illustrative embodiments may be performed by processing unit 206 using computer-implemented instructions, which may be located in a memory, such as main memory 208, read-only memory 224, or one or more peripheral devices.

[0057] Furthermore, in one case, code 226A may be downloaded from remote system 201B via network 201A, where similar code 201C is stored on storage device 201D. In another case, code 226A may be downloaded to remote system 201B via network 201A, where downloaded code 201C is stored on storage device 201D.

[0058] Figure 1-2 The hardware in may vary depending on the implementation. Figure 1-2 In addition to or in lieu of the hardware depicted Figure 1-2 In addition to the hardware depicted in the drawings, other internal hardware or peripheral devices may be used, such as flash memory, equivalent non-volatile memory, or optical disk drives, etc. In addition, the processes of the illustrative embodiments may be applied to a multi-processor data processing system.

[0059] In some illustrative examples, data processing system 200 may be a personal digital assistant (PDA), which is typically configured with flash memory to provide non-volatile memory for storing operating system files and / or user-generated data. The bus system may include one or more buses, such as a system bus, an I / O bus, and a PCI bus. Of course, the bus system may be implemented using any type of communication structure or architecture that provides data transfer between different components or devices attached to the structure or architecture.

[0060] The communications unit may include one or more devices for sending and receiving data, such as a modem or a network adapter. A memory may be, for example, main memory 208 or a cache, such as that found in north bridge and memory controller hub 202. A processing unit may include one or more processors or CPUs.

[0061] Figure 1-2 The depicted examples and above-described examples are not meant to imply architectural limitations. For example, data processing system 200 may be a tablet computer, laptop computer, or telephone device in addition to taking the form of a mobile or wearable device.

[0062] Where a computer or data processing system is depicted as a virtual machine, virtual device, or virtual component, the virtual machine, virtual device, or virtual component operates in the manner of data processing system 200 using virtualized representations of some or all of the components depicted in data processing system 200. For example, in the virtual machine, virtual device, or virtual component, processing unit 206 appears as a virtualized instance of all or some number of hardware processing units 206 available in a host data processing system, main memory 208 appears as a virtualized instance of all or some portion of main memory 208 available in the host data processing system, and disk 226 appears as a virtualized instance of all or some portion of disk 226 available in the host data processing system. In this case, the host data processing system is represented by data processing system 200.

[0063] See also Figure 3 , which depicts a block diagram of an example configuration 300 for incremental generation of quantum circuits according to an illustrative embodiment. The example embodiment includes an application 302. In a particular embodiment, the application 302 is Figure 1 An instance of application 105 or application 107.

[0064] Application 302 receives quantum algorithm 318. Quantum algorithm 318 includes a set of instructions to be executed by a quantum computer. Application 302 includes a map generation component 304. Map generation component 304 generates an index 306 of an uncompiled quantum circuit of quantum algorithm 318. In an embodiment, component 304 generates an index for the uncompiled quantum circuit for each iteration of the quantum algorithm. Index 306 includes a set of gate types 308 and a set of associated qubits 310 for each quantum gate in the uncompiled quantum circuit.

[0065] Component 304 generates a second index of compiled quantum circuits stored in database 312. Component 304 executes mapping commands 320 to generate a second index 322 of previously compiled quantum circuits. The second index 322 includes a set of gate types and a set of associated qubits for each quantum gate in the previously compiled quantum circuit. Component 304 executes additional mapping commands 324 to generate additional indexes 326 for other previously compiled quantum circuits. Database 312 includes gate parameters 314 and qubit parameters 316.

[0066] See also Figure 4 , which depicts a block diagram of an example configuration 400 for incremental generation of quantum circuits according to an illustrative embodiment. The example embodiment includes an application 402. In a particular embodiment, the application 402 is Figure 1 An instance of application 105 or application 107.

[0067] Application 402 receives quantum algorithm 412. Quantum algorithm 412 includes a set of instructions to be executed by a quantum computer. Application 402 includes compiler component 404 and comparison component 410. Compiler component 404 includes circuit transformation component 406 and quantum circuit parameter analysis component 408. Circuit transformation component 406 generates a quantum circuit from a subset of the instruction set of quantum algorithm 412. In an embodiment, compiler component 404 compiles first quantum circuit 418. Application 402 stores compiled quantum circuit 428 in database 414. Database 414 is Figure 1 An example of database 109 in FIG.

[0068] The quantum circuit analysis component 408 generates an index of quantum circuits of a quantum algorithm. In an embodiment, the component 408 generates an index for a subset of the set 416 of previously compiled quantum circuits.

[0069] Comparison component 410 determines structural similarity between an uncompiled quantum circuit of quantum algorithm 412 and a previously compiled quantum circuit stored in database 414. In an embodiment, circuit comparison component 426 executes index command 422 to generate an index 424 of a set of quantum gates and associated qubits for a subset of the set of previously compiled quantum circuits 416. In an embodiment, component 426 compares a first index of an uncompiled quantum circuit with a second index of a previously compiled quantum circuit. For example, component 426 compares the number of quantum gates of a particular type in the first index with the number of quantum gates of the same type in the second index. In response to determining structural equivalence of the uncompiled quantum circuit with the previously compiled quantum circuit, component 420 parameters the previously compiled quantum circuit with a set from the uncompiled quantum circuit. In response to determining that the structures of the uncompiled quantum circuit and the previously compiled quantum circuit are not equivalent, component 404 compiles the uncompiled quantum circuit.

[0070] See also Figure 5 , which depicts a flow chart of an exemplary method 500 for incremental generation of quantum circuits according to an illustrative embodiment. The exemplary method 500 may be Figure 4 Application 402 is executed in.

[0071] In box 502, application 402 compiles a first quantum circuit from a quantum algorithm. In box 504, application 402 stores the compiled quantum circuit in a database. In box 506, application 402 generates a gate index for an uncompiled second quantum circuit from the quantum algorithm. In an embodiment, application 402 detects that the second quantum circuit is submitted for compilation. In an embodiment, application 402 generates a first gate index including a set of quantum gates of the previously compiled first quantum circuit, each quantum gate including a corresponding subset of a set of qubits acted upon by the quantum gate. In an embodiment, application 402 generates a second gate index including a set of quantum gates of the uncompiled second quantum circuit, each quantum gate including a corresponding subset of a set of qubits acted upon by the quantum gate.

[0072] In an embodiment, the application 402 compares the first gate index and the second gate index to determine structural similarity between the first quantum circuit and the second quantum circuit. In response to determining that the first quantum circuit and the second quantum circuit are not structurally similar, the application 402 compiles the second quantum circuit. In block 508, in response to determining that the first quantum circuit and the second quantum circuit are structurally equivalent, the application 402 maps a first set of parameters of the second quantum circuit to the first quantum circuit.

[0073] Various embodiments of the present invention are described herein with reference to the relevant drawings. Alternative embodiments may be designed without departing from the scope of the present invention. For example, additional variational algorithms for quantum computing may be included in method 500 without departing from the scope of the present invention.

[0074] The following definitions and abbreviations are used to interpret the claims and specification. As used herein, the terms "comprises," "comprising," "including," "comprising," "having," "containing," or "having" or any other variation thereof are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that includes a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0075] Additionally, the term "illustrative" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "illustrative" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" should be understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "plurality" should be understood to include any integer greater than or equal to 2, i.e., two, three, four, five, etc. The term "connected" may include both indirect "connected" and direct "connected."

[0076] References in the specification to "one embodiment," "an embodiment," "an example embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment may or may not include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is considered to be within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0077] The terms "about", "substantially", "approximately" and variations thereof are intended to include the degree of error associated with the measurement of a particular quantity based on the equipment available at the time of filing this application. For example, "about" may include a range of ±8% or 5%, or 2% of a given value.

[0078] The description of different embodiments of the present invention has been presented for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments described herein.

Claims

1. A method for incremental generation of quantum circuits, comprising: detecting submission of a first quantum circuit for compilation, the first quantum circuit comprising a first set of quantum logic gates; generating a first gate index for the first quantum circuit, the first gate index comprising a first set of quantum logic gates, each quantum logic gate in the first set of quantum logic gates comprising a corresponding set of qubits acted upon by the quantum logic gate; comparing the first gate index to a second gate index of a second quantum circuit to determine structural equivalence of the first quantum circuit and the second quantum circuit; and In response to determining that the first quantum circuit is structurally identical to the second quantum circuit, parameterizing a first set of parameters of a second set of quantum logic gates of the second quantum circuit with a second set of parameters of the first set of quantum logic gates, wherein the second quantum circuit is a previously compiled quantum circuit stored in a database; and Wherein, the comparison of the first gate index with the second gate index comprises comparing the number of quantum logic gates of a specific type of the first gate index with the number of quantum logic gates of a specific type of the second gate index.

2. The method of claim 1, further comprising: In response to determining that a structure of the first quantum circuit and the second quantum circuit are not identical, the first quantum circuit is compiled.

3. The method of claim 2, wherein: The structurally non-identical includes a number of quantum logic gates of a specific type in the first set of quantum logic gates that is different from a number of quantum logic gates of a specific type in the second set of quantum logic gates.

4. The method of claim 1, further comprising: A set of previously compiled quantum circuits is stored in a database.

5. The method of claim 1, wherein the structural equivalence comprises the number of quantum logic gates of each specific type of the first set of quantum logic gates being equal to the number of quantum logic gates of the same specific type of the second set of quantum logic gates.

6. A computer usable program product comprising a computer readable storage device and program instructions stored on the storage device, the stored program instructions comprising: program instructions for detecting submission of a first quantum circuit for compilation, the first quantum circuit comprising a first set of quantum logic gates; program instructions for generating a first gate index for the first quantum circuit, the first gate index comprising a first set of quantum logic gates, each quantum logic gate in the first set of quantum logic gates comprising a corresponding set of qubits acted upon by the quantum logic gate; program instructions for comparing the first gate index to a second gate index of a second quantum circuit to determine structural similarity of the first quantum circuit and the second quantum circuit; as well as program instructions for, in response to determining structural equivalence of the first quantum circuit and the second quantum circuit, parameterizing a first set of parameters of a second set of quantum logic gates of the second quantum circuit with a second set of parameters of the first set of quantum logic gates, wherein the second quantum circuit is a previously compiled quantum circuit stored in a database; and Wherein, the comparison of the first gate index with the second gate index comprises comparing the number of quantum logic gates of a specific type of the first gate index with the number of quantum logic gates of a specific type of the second gate index.

7. The computer usable program product of claim 6, wherein the program instructions are stored in a computer readable storage device in a data processing system, and wherein the program instructions are transmitted from a remote data processing system over a network.

8. A computer usable program product as claimed in claim 7, wherein the program instructions are stored in a computer readable storage device in a server data processing system, and wherein the program instructions are downloaded to a remote data processing system over a network for use in a computer readable storage device associated with the remote data processing system.

9. The computer usable program product of claim 6, said stored program instructions further comprising: Program instructions compiled in response to determining that the structures of the first quantum circuit and the second quantum circuit are not identical to the first quantum circuit.

10. The computer usable program product of claim 9, wherein: The structurally non-identical includes a number of quantum logic gates of a specific type in the first set of quantum logic gates that is different from a number of quantum logic gates of a specific type in the second set of quantum logic gates.

11. The computer usable program product of claim 6, wherein the stored program instructions include: Program instructions for storing a set of previously compiled quantum circuits in a database.

12. The computer usable program product of claim 6, wherein the structural equality comprises the number of quantum logic gates of each particular type of the first set of quantum logic gates being equal to the number of quantum logic gates of the same particular type of the second set of quantum logic gates.

13. A computer system comprising a processor, a computer-readable memory and a computer-readable storage device, and program instructions stored on the storage device for execution by the processor via the memory, the stored program instructions comprising: program instructions for detecting submission of a first quantum circuit for compilation, the first quantum circuit comprising a first set of quantum logic gates; program instructions for generating a first gate index for the first quantum circuit, the first gate index comprising a first set of quantum logic gates, each quantum logic gate in the first set of quantum logic gates comprising a corresponding set of qubits acted upon by the quantum logic gate; program instructions for comparing the first gate index to a second gate index of a second quantum circuit to determine structural similarity of the first quantum circuit and the second quantum circuit; and program instructions for, in response to determining structural equivalence of the first quantum circuit and the second quantum circuit, parameterizing a first set of parameters of a second set of quantum logic gates of the second quantum circuit with a second set of parameters of the first set of quantum logic gates, wherein the second quantum circuit is a previously compiled quantum circuit stored in a database; and The comparison of the first gate index with the second gate index comprises comparing the number of quantum logic gates of a specific type indexed by the first gate index with the number of quantum logic gates of a specific type indexed by the second gate index.

14. The computer system of claim 13, wherein the stored program instructions further include: Program instructions for compiling the first quantum circuit are responsive to determining that the structures of the first quantum circuit and the second quantum circuit are not identical.

15. The computer system of claim 14, wherein the number of quantum logic gates of a particular type that are not structurally identical comprising the first set of quantum logic gates is different from the number of quantum logic gates of the particular type that are structurally identical comprising the second set of quantum logic gates.

16. The computer system of claim 13, wherein the stored program instructions further comprise: Program instructions for storing a set of previously compiled quantum circuits in a database.

17. The computer system of claim 13, wherein the structural equality comprises a number of quantum logic gates of each particular type of the first set of quantum logic gates being equal to a number of quantum logic gates of the same particular type of the second set of quantum logic gates.

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