Semiconductor device manufacturing method and semiconductor device

Abstract

This invention provides a method for manufacturing a semiconductor device that reduces manufacturing costs and improves performance, as well as the semiconductor device itself. First and second semiconductor chips (21a, 21b) are disposed on the front side of the wafer pad portion (41a1) of a main current lead frame (41a) and wiring is performed. Next, the main current lead frame (41a) and the first and second semiconductor chips (21a, 21b) are sealed with a semi-cured sealing material such that the terminal portion (41a3) of the main current lead frame (41a) protrudes, exposing the back side of the wafer pad portion (41a1), to form a semi-cured unit. Furthermore, the front side of an insulating sheet (70) is pressed against the back side of the semi-cured unit, covering the back side of the wafer pad portion (41a1) of the main current lead frame (41a). In this manufacturing method, the insulating sheet (70) does not warp, and the insulating sheet (70) can be installed regardless of the specifications of the molding die.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a semiconductor device and the semiconductor device itself. Background Technology

[0002] The semiconductor device includes a power semiconductor chip and a control IC (Integrated Circuit), wafer pads on which the semiconductor chip and control IC are disposed, and an insulating sheet disposed on the back of the wafer pads, and the semiconductor device is sealed by a sealing component. The power semiconductor chip uses switching elements of a power device. These switching elements are, for example, IGBTs (Insulated Gate Bipolar Transistors) and power MOSFETs (Metal-Oxide Semiconductor Field Effect Transistors). The control IC performs drive control of the power semiconductor chip. In this semiconductor device, heat emitted from the power semiconductor chip and control IC is dissipated from the insulating sheet via the wafer pads.

[0003] Such a semiconductor device is manufactured through the following steps. First, a power semiconductor chip and electronic components are placed on a wafer pad, which is then placed on an insulating sheet pre-assembled into a mold. While pressing the wafer pad towards the insulating sheet using a pin, sealant is filled into the mold, and the pin is then removed, allowing the sealant to cure within the mold. Removing the mold yields the semiconductor device (see, for example, Patent Document 1).

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2005-123495 Summary of the Invention

[0007] Technical issues

[0008] However, in the aforementioned semiconductor device manufacturing method, because the die pads are pressed against the insulating sheet using pins, lifting occurs between the die pads and the insulating sheet as the pins are removed. A semiconductor device sealed in this state may experience reduced heat dissipation, leading to decreased reliability. Furthermore, the insulating sheet assembled within the mold must have its shape and size modified according to the mold specifications. Therefore, the specifications of the insulating sheet must be modified for each mold. In addition, the conveying mechanism used to assemble the insulating sheet into the mold is complex and expensive. This results in increased manufacturing costs for semiconductor devices.

[0009] The present invention was made in view of this, and its object is to provide a method for manufacturing a semiconductor device and a semiconductor device that prevents a decrease in heat dissipation while suppressing an increase in manufacturing costs.

[0010] Technical solution

[0011] According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising: a preparation step, preparing a power semiconductor chip, a lead frame, and a semi-cured insulating sheet, the lead frame including a wafer pad portion and a terminal portion integrally connected to the wafer pad portion; a mounting step, configuring the power semiconductor chip on the front side of the wafer pad portion and performing wiring; a sealing step, sealing the lead frame and the power semiconductor chip using a semi-cured sealing material such that the terminal portion protrudes and exposes the back side of the wafer pad portion to form a semi-cured unit; a pressing step, pressing the front side of the insulating sheet against the back side of the semi-cured unit to cover the back side of the wafer pad portion; and a curing step, heating the semi-cured unit and the insulating sheet to cure them.

[0012] Additionally, according to one aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising: a lead frame including a wafer pad portion and a terminal portion integrally connected to the wafer pad portion; a power semiconductor chip disposed on the front side of the wafer pad portion; a sealing member sealing the lead frame and the power semiconductor chip in such a manner that the terminal portion protrudes and exposes the back side of the wafer pad portion; and an insulating sheet configured to cover the back side of the wafer pad portion exposed from the back side of the sealing member, and forming a height difference relative to the back side of the sealing member.

[0013] Technical effect

[0014] According to the disclosed technology, while suppressing the increase in manufacturing costs, it is possible to prevent the reduction in heat dissipation and suppress the reduction in the reliability of semiconductor devices. Attached Figure Description

[0015] Figure 1 This is an external view of the semiconductor device according to the first embodiment.

[0016] Figure 2 This is a cross-sectional view of the semiconductor device according to the first embodiment.

[0017] Figure 3 This is a longitudinal cross-sectional view of the semiconductor device according to the first embodiment.

[0018] Figure 4 This is a flowchart illustrating a method for manufacturing a semiconductor device according to a first embodiment.

[0019] Figure 5 This is a diagram illustrating the mounting process of a semiconductor chip and electronic components included in the manufacturing method of the semiconductor device according to the first embodiment.

[0020] Figure 6 This is a diagram illustrating the sealing process included in the manufacturing method of the semiconductor device according to the first embodiment.

[0021] Figure 7 This is a longitudinal cross-sectional view of a semi-cured unit generated after sealing in the semiconductor device manufacturing method of the first embodiment.

[0022] Figure 8 This is a diagram showing the pressing of a prepreg unit relative to an insulating sheet in the manufacturing method of a semiconductor device according to the first embodiment.

[0023] Figure 9 This is a top view of a semiconductor device with a heat sink installed according to the first embodiment.

[0024] Figure 10 This is a longitudinal cross-sectional view (one) of a semiconductor device with a heat sink installed according to the first embodiment.

[0025] Figure 11 This is a longitudinal cross-sectional view (second one) of a semiconductor device with a heat sink installed according to the first embodiment.

[0026] Figure 12 This is a longitudinal cross-sectional view of the semiconductor device according to the second embodiment.

[0027] Figure 13 This is a longitudinal cross-sectional view of the semiconductor device and heat sink according to the second embodiment.

[0028] Figure 14 This is a longitudinal cross-sectional view of the semiconductor device according to the third embodiment.

[0029] Symbol Explanation

[0030] 10, 10a, 10b Semiconductor devices

[0031] 11 Semi-cured units

[0032] 21a First Semiconductor Chip

[0033] 21b Second Semiconductor Chip

[0034] 22 bond wires

[0035] 30, 31, 32, 33, 34 Control lead frames

[0036] 34a1 Control chip pad section

[0037] 34a2 Control Wiring Section

[0038] 34a3 Control Terminal Section

[0039] 40, 41a, 41b, 41c, 41d Main current lead frame

[0040] 41a1 Wafer Pad Section

[0041] 41a2 Connecting part

[0042] 41a3 Terminal part

[0043] 50 Control IC

[0044] 60 Sealing components

[0045] 60a mounting hole

[0046] 60b recess

[0047] 61 Semi-cured resin

[0048] 70 Insulating sheet

[0049] 80 forming mold

[0050] 81 Upper mold

[0051] 82 Lower mold

[0052] 83 flow path

[0053] 84-type cavity

[0054] 85a, 85b press needles

[0055] 90 radiator

[0056] 91 Heatsink

[0057] 91a Bolt hole

[0058] 92 Heatsink Section

[0059] 93 bolts Detailed Implementation

[0060] Hereinafter, the embodiments will be described with reference to the accompanying drawings. It should be noted that in the following description, "front" and "top surface" refer to the... Figure 1 and Figure 3 In the semiconductor device 10, the surface facing upwards. Similarly, "upper" indicates that... Figure 1 and Figure 3 In the semiconductor device 10, the upper side is the orientation. "Back side" and "lower surface" are used to indicate the direction of the semiconductor device. Figure 1 and Figure 3In the semiconductor device 10, the surface facing downwards. Similarly, "downwards" indicates that... Figure 1 and Figure 3 In the semiconductor device 10, the direction is shown on the lower side. The same orientation is indicated in other figures as needed. The terms "front," "upper surface," "upper," "back side," "lower surface," "lower," and "side" are merely convenient expressions for determining relative positional relationships and do not limit the technical concept of the invention. For example, "upper" and "lower" do not necessarily indicate the vertical direction relative to the ground. That is, the directions of "upper" and "lower" are not limited to the direction of gravity. Furthermore, in the following description, "main component" indicates a content of 80 vol% or more.

[0061] [First Implementation Method]

[0062] use Figures 1-3 The semiconductor device 10 of the first embodiment will be described. Figure 1 This is an external view of the semiconductor device according to the first embodiment. It should be noted that... Figure 1 (A) is the semiconductor device 10 (from Figure 1 (B) Side view viewed from the top or bottom. Figure 1 (B) is a top view of semiconductor device 10. Figure 2 This is a cross-sectional view of the semiconductor device according to the first embodiment. Figure 3 This is a longitudinal cross-sectional view of the semiconductor device according to the first embodiment. It should be noted that... Figure 2 yes Figure 1 A cross-sectional view of the single-dash line YY of (A). Figure 3 yes Figure 2 A cross-sectional view of the single-dash line XX.

[0063] First, such as Figure 1 As shown, the entire semiconductor device 10 is sealed by a sealing member 60 to form a three-dimensional shape. It should be noted that the sealing member 60 of the semiconductor device 10 is cubical and may have curvature at its corners. The front side of the semiconductor device 10 is covered by the sealing member 60, and the back side is covered by the sealing member 60 and an insulating sheet 70. It should be noted that in... Figure 2In the diagram, dashed lines indicate the placement of the insulating sheet 70 on the back side of the sealing member 60. Furthermore, the semiconductor device 10 extends multiple control lead frames 30 and multiple main current lead frames 40 from both sides of the long side of the sealing member 60. It should be noted that in this embodiment, the control lead frames and main current lead frames are described as control lead frames 30 and main current lead frames 40 without particularly distinguishing between them. Additionally, the semiconductor device 10 has mounting holes 60a formed at both ends of the sealing member 60 along its length. The mounting holes 60a can be parallel to the length of the sealing member 60 and can be located at both ends along the centerline of the central portion. The mounting holes 60a have a diameter for bolts (described later) to pass through. The mounting holes 60a penetrate between the front and back sides of the sealing member 60. The mounting holes 60a are formed on the outer side of the insulating sheet 70 when viewed from above. By inserting bolts through the mounting holes 60a, the semiconductor device 10 can be mounted to a cooling unit such as a heat sink.

[0064] For such a semiconductor device 10, Figure 2 and Figure 3 The components shown are sealed by sealing component 60. That is, the semiconductor device 10 includes six sets of first semiconductor chips 21a and second semiconductor chips 21b, a control lead frame 30 (including control lead frames 31-34), a main current lead frame 40 (including main current lead frames 41a-41d), and a control IC 50. Furthermore, in the semiconductor device 10, the control lead frame 30, the control IC 50, the first semiconductor chips 21a, the second semiconductor chips 21b, and the main current lead frame 40 are appropriately electrically connected by bonding wires 22. It should be noted that in... Figure 2 The bonding wire 22 connected to the control IC 50 is omitted from the diagram. Furthermore, components such as the semiconductor device 10 are sealed by the sealing component 60. The wafer pad portion of the main current lead frame 40 (described later) Figure 2 The back side of the wafer pad portion 41a1) is exposed from the sealing member 60 and forms the same plane as the back side of the sealing member 60. In the semiconductor device 10, an insulating sheet 70 is mounted to cover the exposed wafer pad portion on the back side of the sealing member 60.

[0065] The first and second semiconductor chips 21a and 21b are power semiconductor chips made of silicon, silicon carbide, or gallium nitride. The first semiconductor chip 21a includes a switching element, such as a power MOSFET or IGBT. This first semiconductor chip 21a has, for example, a drain electrode (positive electrode, or collector electrode in an IGBT) as the main electrode on the back side, a gate electrode (control electrode) as the control electrode on the front side, and a source electrode (negative electrode, or emitter electrode in an IGBT) as the main electrode. The second semiconductor chip 21b also includes a switching element. The diode element is an SBD (Schottky Barrier Diode), a PiN (P-intrinsic-N) diode, or a FWD (Free Wheeling Diode). This second semiconductor chip 21b has a cathode electrode as the main electrode on the back side and a anode electrode as the main electrode on the front side. The thickness of the first and second semiconductor chips 21a and 21b is, for example, 180 μm or more and 220 μm or less, with an average thickness of about 200 μm. Furthermore, in... Figure 2 This example only shows the case where six sets of first and second semiconductor chips 21a and 21b are provided. However, it is not limited to six sets, and the number of sets can be set to correspond to the specifications of the semiconductor device 10. Alternatively, a semiconductor chip including an RC (Reverse-Conducting)-IGBT switching element comprising an IGBT and a FWD in one chip can be used instead of the first and second semiconductor chips 21a and 21b.

[0066] The back sides of the first and second semiconductor chips 21a and 21b are bonded to a predetermined main current lead frame 40 by solder (not shown). It should be noted that the solder is a lead-free solder with a predetermined alloy as its main component. The predetermined alloy is, for example, at least one of an alloy composed of tin-silver, an alloy composed of tin-zinc, and an alloy composed of tin-antimony. Additives such as copper, bismuth, indium, nickel, germanium, cobalt, or silicon may be included in the solder. It should be noted that, instead of solder, bonding can also be achieved by sintering a sintering material. In this case, the sintering material is, for example, powder of silver, gold, or copper.

[0067] For the first and second semiconductor chips 21a and 21b, their front-side main electrodes are electrically connected to the terminal portion (described later) of the main current lead frame 40 via bonding wires 22. Additionally, for the first and second semiconductor chips 21a and 21b, their front-side control electrodes are electrically connected to the control IC 50 via bonding wires (not shown). It should be noted that the bonding wires 22 are made of a material with excellent conductivity. Such material may be, for example, gold, silver, copper, aluminum, or an alloy including at least one of these. Furthermore, the diameter of the bonding wires 22 is, for example, 100 μm or more and 1.0 mm or less.

[0068] Multiple main current lead frames 40 are disposed in the semiconductor device 10 Figure 2 On the right side, the other end of the multiple main current lead frames 40 extends from the semiconductor device 10. Figure 2 The right-side side extends outward. The main current lead frames 41b, 41a, 41c, and 41d of the plurality of main current lead frames 40 are sealed by the sealing member 60 such that the back side of their wafer pad portions is exposed. Furthermore, the main current lead frame 41a includes a wafer pad portion 41a1, a connecting portion 41a2, and a terminal portion 41a3. The back side of the wafer pad portion 41a1 is exposed from the back side of the sealing member 60 and forms the same plane as the back side of the sealing member 60. Alternatively, the back side of the wafer pad portion 41a1 and the back side of the sealing member 60 may be the same plane. Additionally, as described above, the first and second semiconductor chips 21a and 21b are disposed on the front side of the wafer pad portion 41a1. The connecting portion 41a2 is inclined and integrally connects the wafer pad portion 41a1 and the terminal portion 41a3. The connecting portion 41a2 is sealed around the sealing member 60. Terminal portion 41a3 separates from the front side of wafer pad portion 41a1 and laterally as the connecting portion 41a2 tilts. One end of terminal portion 41a3 is integrally connected to wafer pad portion 41a1 via connecting portion 41a2. A bonding wire 22 is connected to the portion of terminal portion 41a3 sealed around the sealing member 60, and this bonding wire 22 is connected to the first and second semiconductor chips 21a and 21b. The other end of terminal portion 41a3 extends outward from sealing member 60. Terminal portion 41a3 can extend parallel to the front side of wafer pad portion 41a1 from the side of sealing member 60. It should be noted that, although not shown in the figure, the main current lead frames 41b, 41c, and 41d also include wafer pad portion, connecting portion, and terminal portion in the same way as main current lead frame 41a.

[0069] Multiple control lead frames 30 (including control lead frames 31, 32, 33, and 34) are disposed on the sealing member 60. Figure 2 On the left side of the middle section. The multiple control lead frames 30 are positioned higher than the wafer pad portion 40 of the main current lead frame 40, and at the same height as the terminal portion of the main current lead frame 40. The control lead frames 30 are located from the semiconductor device 10... Figure 2The left side extends outward. Among the multiple control lead frames 30, the control lead frame 34 includes a control chip pad portion 34a1, a control wiring portion 34a2, and a control terminal portion 34a3. The control chip pad portion 34a1 extends along the length of the semiconductor device 10, and a control IC 50 is disposed on the control chip pad portion 34a1 via solder (not shown). The control wiring portion 34a2 integrally connects the control chip pad portion 34a1 and the control terminal portion 34a3. The control chip pad portion 34a1 and the control wiring portion 34a2 are sealed around by a sealing member 60. One end of the control terminal portion 34a3 is integrally connected to the control wiring portion 34a2 and is sealed around by the sealing member 60. Bonding wires (not shown) connected to the control IC 50, etc., are connected to the sealed portion of the control wiring portion 34a2. The other end of the control terminal portion 34a3 extends outward from the sealing member 60. The control terminal portion 34a3 can extend from the side of the sealing member 60 parallel to the front of the wafer pad portion 41a1.

[0070] The multiple main current lead frames 40 and multiple control lead frames 30 are made of a material with excellent conductivity. Such materials include, for example, copper, aluminum, or an alloy comprising at least one of these. The thickness of the multiple main current lead frames 40 and multiple control lead frames 30 is preferably 0.10 mm or more and 1.00 mm or less, more preferably 0.20 mm or more and 0.50 mm or less. Alternatively, the multiple main current lead frames 40 and multiple control lead frames 30 can be electroplated using a material with excellent corrosion resistance. Such materials include, for example, nickel, gold, or an alloy comprising at least one of these.

[0071] The control IC 50 is electrically connected to the gate electrode of the first semiconductor chip 21a via bonding wires (not shown). The control IC 50 applies a control voltage to the first semiconductor chip 21a at a predetermined time. It should be noted that in the semiconductor device 10, in order to achieve the desired function, electronic components such as thermistors, capacitors, resistors, current sensors, and temperature sensors may be configured instead of the control IC 50, or the thermistors, capacitors, resistors, current sensors, and temperature sensors may be configured together with the control IC 50.

[0072] The sealing component 60 includes a thermosetting resin and an inorganic filler contained in the thermosetting resin. The thermosetting resin has at least one main component selected from the group consisting of, for example, epoxy resin, phenolic resin, and melamine resin. Preferably, the thermosetting resin has an epoxy resin as its main component. Furthermore, an inorganic material with silica as its main component is used in the inorganic filler. By using silica, the inorganic filler also functions as a release agent. In addition, the inorganic filler can maintain high flame retardancy without the addition of halogenated, antimony-based, or metal hydroxide-based flame retardants. The inorganic filler constitutes 70 vol% to 90 vol% of the total sealing material.

[0073] In addition, the insulating sheet 70 also includes a thermosetting resin and an inorganic filler contained in the resin. The thermosetting resin has at least one component selected from the group consisting of, for example, epoxy resin, phenolic resin, melamine resin, and polyimide resin. Preferably, the thermosetting resin has epoxy resin as the main component. The inorganic filler uses an inorganic material with at least one component selected from the group consisting of highly insulating and highly thermally conductive alumina, aluminum nitride, silicon nitride, and boron nitride. Furthermore, the sealing member 60 and the insulating sheet 70 preferably have the same thermosetting resin as the main component. More preferably, the thermosetting resins of both the sealing member 60 and the insulating sheet 70 have epoxy resin as the main component.

[0074] The insulating sheet 70 is, for example, rectangular in top view. The thickness of the insulating sheet 70 is 50 μm or more and 1.0 mm or less. The insulating sheet 70 is formed by covering the back side of the exposed wafer pad portion of the main current lead frame 40 on the back side of the sealing member 60. The insulating sheet 70 may cover the wafer pad portion of the main current lead frame 40 (in... Figure 3 The back side of the wafer pad portion 41a1 is covered, and the back side of the sealing member 60 surrounding the wafer pad portion may also be covered. That is, the back side of the insulating sheet 70 forms a height difference with respect to the back side of the sealing member 60. By covering the wafer pad portion (in... Figure 3 The back side of the chip pad portion 41a1 is covered, thereby ensuring insulation between the chip pad portion and the outside. In addition, since the back side of the sealing member 60 around the chip pad portion is also covered, insulation can be more reliably ensured even if the semiconductor device 10 is deformed.

[0075] Next, using Figures 4-8 The manufacturing method of such a semiconductor device 10 will be described. Figure 4 This is a flowchart illustrating a method for manufacturing a semiconductor device according to a first embodiment. Figure 5 This is a diagram illustrating the mounting process of a semiconductor chip and electronic components included in the manufacturing method of the semiconductor device according to the first embodiment. Figure 6This is a diagram illustrating the sealing process included in the manufacturing method of the semiconductor device according to the first embodiment. Figure 7 This is a longitudinal cross-sectional view of a semi-cured unit generated after sealing in the semiconductor device manufacturing method of the first embodiment. Figure 8 This diagram illustrates the pressing of a prepreg unit relative to an insulating sheet in the manufacturing method of the semiconductor device according to the first embodiment. It should be noted that... Figures 5-8 Is with Figure 2 The cross-sectional view corresponding to the cross-sectional position of the single-dash line XX.

[0076] First, a preparation process for the constituent components of the semiconductor device 10 is performed. Figure 4 Step S1). The components of the semiconductor device 10 include a first semiconductor chip 21a, a second semiconductor chip 21b, a main current lead frame 40, a control lead frame 30, a semi-cured insulating sheet, and sealing materials, etc.

[0077] The main current lead frame 40 and the control lead frame 30 are metal plates having a wiring pattern integrally formed by tie rods or the like. For such a metal plate, the main current lead frame 40 and the control lead frame 30 are formed from a single metal plate by, for example, etching or punching. Furthermore, a height difference processing is performed using a die for stamping. Thus, a metal plate with a wiring pattern is obtained, which is a wiring pattern integrally formed by the main current lead frame 40 and the control lead frame 30 by tie rods or the like.

[0078] The insulating sheet is a sheet comprising a semi-cured (Grade B) thermosetting resin and an inorganic filler. For example, it is manufactured as follows: First, a liquid resin (Grade A) is prepared as the thermosetting resin, and an inorganic filler is mixed with the liquid resin. The resin used here has at least one main component selected from the group consisting of epoxy resin, phenolic resin, melamine resin, and polyimide resin. Preferably, epoxy resin is used as the main component. Additionally, an inorganic material with at least one main component selected from the group consisting of alumina, aluminum nitride, silicon nitride, and boron nitride is used as the inorganic filler. Next, the liquid (Grade A) thermosetting resin and the inorganic filler are mixed, coated into a sheet, and heated to semi-cur (Grade B) for manufacturing. Alternatively, the liquid (Grade A) thermosetting resin mixed with the inorganic filler can be heated and semi-cured (Grade B) before being formed into a sheet for manufacturing. It should be noted that the heating time is appropriately set according to the cycle time and depends on the type of catalyst in the resin. For example, the heating temperature is above 100°C and below 200°C.

[0079] The sealing material is a powder or tablet comprising a semi-cured (Grade B) thermosetting resin and an inorganic filler. For example, it is manufactured as follows: First, a liquid resin (Grade A) is prepared as the thermosetting resin, and an inorganic filler is mixed with the liquid resin. The resin used here has at least one main component selected from the group consisting of epoxy resin, phenolic resin, and melamine resin. Preferably, epoxy resin is the main component. Furthermore, an inorganic material with silica as the main component is used as the inorganic filler. Next, the inorganic filler is mixed with the liquid resin. The liquid resin (Grade A) mixed with the inorganic filler is heated to generate a semi-cured material (Grade B). It should be noted that the heating time is appropriately set according to the cycle time and depends on the type of catalyst in the resin. For example, the heating temperature is 100°C or higher and 200°C or lower. The material after the semi-cured material in the semi-cured state is pulverized is formed into, for example, a sheet to generate the sealing material.

[0080] Next, an installation process is performed in which semiconductor chips 21a, 21b and control IC 50 are arranged and wired on the main current lead frame 40 and control lead frame 30 included in the metal plate. Figure 4 Step S2). Here, as Figure 5 As shown, firstly, the first and second semiconductor chips 21a and 21b are soldered to the wafer pads of the main current lead frame 40, and the control IC 50 is soldered to the control wafer pads of the control lead frame 30. For example, the first and second semiconductor chips 21a and 21b are soldered to the front side of the wafer pad 41a1 of the main current lead frame 41a. Additionally, the control IC 50 is soldered to the control wafer pad 34a1 of the control lead frame 34. Next, they are transported to a predetermined bonding apparatus for wire bonding, and wire routing is performed. For example, wire routing is performed by appropriately using bonding wires 22 to electrically connect the main current lead frame 40, on which the first and second semiconductor chips 21a and 21b are disposed, and the control lead frame 30, on which the control IC 50 is disposed.

[0081] Next, a sealing process is performed to form the semi-cured unit 11. Figure 4 Step S3). The semi-cured unit 11 is a unit formed by using a semi-cured sealing material to seal the control chip pad portion of the control lead frame 30, the control wiring portion, the connection portion of the main current lead frame 40, and the units of the first and second semiconductor chips 21a and 21b in such a way that the terminal portion of the main current lead frame 40 and the control terminal portion of the control lead frame 30 protrude and expose the back side of the chip pad portion of the main current lead frame 40.

[0082] In the sealing process ( Figure 4 In step S3), firstly, as Figure 6As shown, the main current lead frame 40 and the control lead frame 30, on which the first and second semiconductor chips 21a and 21b and the control IC 50 are mounted, are assembled into the molding die 80. First, the main current lead frame 40 and the control lead frame 30 are transferred to a sealing device for sealing and placed in the lower mold 82 of the sealing device. Next, in the sealing device, the main current lead frame 40 and the control lead frame 30 are clamped by the upper mold 81 and the lower mold 82 of the molding die 80. At this time, a flow path 83 and a cavity 84 are formed in the molding die 80. Thus, multiple main current lead frames 40 are assembled in the cavity 84 formed by the upper mold 81 and the lower mold 82. Figure 6 In the middle, there is the main current lead frame 41a) and multiple control lead frames 30 (in Figure 6 In the middle, for controlling the lead frame 34).

[0083] Next, as Figure 6 , Figure 7 As shown, a sealing material is filled into the cavity 84 formed by the molding die 80 to form a semi-cured unit 11. First, as... Figure 6 As shown, the chip pad portion of the main current lead frame 40 is adjusted by pressing pins 85a and 85b. Figure 6 The back side of the wafer pad portion 41a1 (located in the middle) contacts the surface of the lower mold 82, and the front side of the wafer pad portion 41a1 is pressed against the lower mold 82 and held in this state. It should be noted that the pins 85a and 85b can be provided in the upper mold 81 of the forming mold 80 and press vertically against the surface of the lower mold 82. The pins 85a and 85b can press the wafer pad portion (located in the middle) mounted on the main current lead frame 40 of the forming mold 80. Figure 6 The middle part is the area in the wafer pad section 41a1 where the first and second semiconductor chips 21a and 21b are not configured.

[0084] Next, the sheet-like semi-cured (Grade B) sealant is assembled into the canister of the sealing device and heated to soften it. The softened semi-cured sealant is pressurized and forced from flow path 83 into cavity 84. Upper mold 81 and lower mold 82 are preheated, and the softened semi-cured sealant is filled into cavity 84. Then, during the stage where the semi-cured sealant is filled into cavity 84, the push pins 85a and 85b are moved upwards towards forming mold 80, releasing pressure on the wafer pad portion (in... Figure 6 The middle part is the chip pad 41a1). At this time, the semi-cured sealing material is also pressed in by applying pressure from the flow path 83, so that the part that has been pressed by the pins 85a and 85b is filled by the semi-cured sealing material.

[0085] Then, stop filling the semi-cured sealing material from the flow path 83, separate the molding die, and remove the semi-cured unit 11 from the molding die 80. Thus, as Figure 7 As shown, a semi-cured unit 11 is formed by sealing the first and second semiconductor chips 21a and 21b, the main current lead frame 40, and the control lead frame 30 with a semi-cured sealing component (semi-cured resin 61). At this time, although... Figure 7 The diagram is omitted, but on the back of the pre-cured unit 11, the wafer pad portion of the main current lead frame 40 (in...) Figure 7 In the middle, the back side of the chip pad portion 41a1 is exposed in a manner that is flush with the back side of the pre-cured unit 11. Furthermore, since the pins 85a and 85b are pulled upwards, a recess is formed on the front side of the pre-cured resin 61 at the location where the pins 85a and 85b passed. It should be noted that the location on the front side of the pre-cured resin 61 where the pins 85a and 85b passed can also be a protrusion.

[0086] Next, a pressing process is performed to press the semi-cured insulating sheet 70 to the semi-cured unit 11. Figure 4 Step S4). First, as Figure 8 As shown, the semi-cured insulating sheet 70 and the semi-cured unit 11 are transported to a crimping device. Next, the front side of the semi-cured insulating sheet 70 is positioned to cover the exposed wafer pads on the back side of the semi-cured unit 11, and then crimped using the crimping device. A press can be used as the crimping device. It should be noted that, at this time, heating can also be used for crimping. Such a crimping device can be a heated press. By heating the semi-cured insulating sheet 70 and crimping it in a softened state, it can be tightly fitted. Then, it is removed from the crimping device, forming the semi-cured unit 11 with the semi-cured insulating sheet 70 crimped on.

[0087] Next, the curing process is carried out. Figure 4 Step S5). First, the semi-cured unit 11 with the semi-cured insulating sheet 70 pressed onto it is transferred to a heating device. Then, the semi-cured unit 11 with the semi-cured insulating sheet 70 pressed onto it is heated to a predetermined temperature in the heating device. It should be noted that the heating temperature at this time is above 120°C and below 180°C. In addition, during heating, the semi-cured unit 11 with the semi-cured insulating sheet 70 pressed onto it is in a non-pressurized state without any applied pressure. In this way, the semi-cured insulating sheet 70 and the semi-cured unit 11 are cured, thereby manufacturing a semiconductor device 10 including the cured sealing member 60 and the insulating sheet 70. It should be noted that the curing process ( Figure 4Before or after step S5), unwanted parts such as pull rods are removed from the metal plate. Furthermore, bending processing can be performed on the terminal portions of the main current lead frame 40 and the control terminal portions of the control lead frame 30.

[0088] By pressing the semi-cured insulating sheet 70 against the back of the semi-cured unit 11 and then curing it, the sealing member 60 and the semi-cured insulating sheet 70 are simultaneously cured from their semi-cured states. Therefore, they are tightly bonded to each other. Furthermore, by using the same main component resin for both the sealing member 60 and the semi-cured insulating sheet 70, a more secure bond can be achieved. Preferably, both the sealing member 60 and the insulating sheet 70 are thermosetting resins with epoxy resin as the main component. Moreover, by pressing the semi-cured insulating sheet 70 against the back of the semi-cured unit 11 and then performing a curing process using other devices, the semiconductor device 10 including the insulating sheet 70 can be easily manufactured without increasing manufacturing costs.

[0089] Next, using Figures 9-11 An example of a semiconductor device 10 being equipped with a heat sink as a cooling unit will be described. Figure 9 This is a top view of the semiconductor device with a heat sink installed according to the first embodiment. Figure 10 and Figure 11 This is a longitudinal cross-sectional view of the semiconductor device with a heat sink installed according to the first embodiment. It should be noted that... Figure 10 It means Figure 9 A cross-sectional view of the single-dotted dashed line XX. Figure 11 It means Figure 9 A cross-sectional view of the single-dash line YY. Additionally, Figure 9 The single-dot dash XX corresponds to Figure 2 The position of the single-dot dashed line XX. Additionally... Figure 10 and Figure 11 It is also a diagram that omits the symbols for the components.

[0090] A heat sink 90 is mounted on the back of the semiconductor device 10 by bolts 93. The heat sink 90 is an example of a cooling unit and is made of a metal with excellent thermal conductivity. Such metals include, for example, aluminum, iron, silver, copper, or alloys comprising at least one of these. The heat sink 90 includes a heat sink plate 91 and a heat sink portion 92 comprising one or more heat sink fins formed on the back of the heat sink plate 91. Furthermore, the heat sink plate 91, when viewed from above, is a rectangle with an area larger than that of the semiconductor device 10, and has bolt holes 91a formed on its front side for the bolts 93 to engage. When the heat sink 90 is mounted to the back of the semiconductor device 10, these bolt holes 91a correspond to the mounting holes 60a of the semiconductor device 10. To improve corrosion resistance, materials such as nickel can be formed on the surface of such a heat sink 90 through electroplating or similar processes. Other materials besides nickel include nickel-phosphorus alloys and nickel-boron alloys. It should be noted that, as another example of a cooling unit, a water-based cooling device can also be applied. In this case, the cooling device also has bolt holes corresponding to the mounting holes 60a of the semiconductor device 10.

[0091] The back of the semiconductor device 10 is disposed on the front side of such a heat sink 90 (heat sink 91), and a bolt 93 is inserted through the mounting hole 60a and screwed into the bolt hole 91a of the heat sink 90's heat sink 91. This allows the heat sink 90 to be mounted on the semiconductor device 10. In the semiconductor device 10, the insulating sheet 70 is mounted with a height difference relative to the sealing member 60. Therefore, only the insulating sheet 70 contacts the front side of the heat sink 91 of the heat sink 90. ​​Thus, the force of tightening the bolt 93 becomes the adhesion force between the heat sink 90 and the insulating sheet 70, improving the heat dissipation of the semiconductor device 10. It should be noted that a heat-dissipating compound is coated between the insulating sheet 70 and the heat sink 90. ​​By increasing the adhesion force between the heat sink 90 and the insulating sheet 70, the heat-dissipating compound is also thinly and uniformly diffused throughout the space between the insulating sheet 70 and the heat sink 90.

[0092] The aforementioned semiconductor device 10 has first and second semiconductor chips 21a and 21b disposed on the front side of the wafer pad portion 41a1 of the main current lead frame 41a, and wiring is performed thereon. Next, by making the terminal portion 41a3 of the main current lead frame 41a protrude and exposing the back side of the wafer pad portion 41a1, a semi-cured unit 11 is formed by sealing the main current lead frame 41a and the first and second semiconductor chips 21a and 21b using a semi-cured sealing material. Furthermore, the front side of the insulating sheet 70 is pressed against the back side of the semi-cured unit 11 to cover the back side of the wafer pad portion 41a1 of the main current lead frame 41a. In this manufacturing method, the insulating sheet 70 does not warp, and the insulating sheet 70 can be installed regardless of the specifications of the forming mold 80. There is also no need for a conveying mechanism for transporting the insulating sheet 70 to the forming mold 80, enabling easy and reliable manufacturing of the semiconductor device 10 including the insulating sheet 70 while suppressing manufacturing costs.

[0093] The sealing component 60 and insulating sheet 70 of the semiconductor device 10 thus manufactured include a thermosetting resin and an inorganic filler. Preferably, the thermosetting resin of the sealing component 60 and the insulating sheet 70 is mainly composed of the same thermosetting resin. More preferably, the thermosetting resin of both the sealing component 60 and the insulating sheet 70 is mainly composed of epoxy resin.

[0094] Furthermore, the semiconductor device 10 manufactured in this way mounts the insulating sheet 70 with a height difference relative to the back side of the sealing member 60. Therefore, if the heat sink 90 is mounted on the back side of the semiconductor device 10, the heat sink 90 only contacts the insulating sheet 70. Thus, the force of tightening the bolt 93 becomes the adhesion force between the heat sink 90 and the insulating sheet 70, and the heat dissipation compound also diffuses thinly between the insulating sheet 70 and the heat sink 90, thereby improving the heat dissipation performance of the semiconductor device 10.

[0095] [Second Implementation]

[0096] use Figure 12 The semiconductor device of the second embodiment will be described. Figure 12 This is a longitudinal cross-sectional view of the semiconductor device according to the second embodiment. It should be noted that in semiconductor device 10a, the same symbols are used for components identical to those in semiconductor device 10, and their descriptions are omitted or simplified. In semiconductor device 10a, a recess 60b is provided on the back side of the sealing member 60. The wafer pad portion of the main current lead frame 40 is exposed within this recess 60b. Figure 12The back side of the wafer pad portion 41a1 is located in the middle. Therefore, the back side surrounding the recess 60b of the sealing member 60 is located lower than the back side of the wafer pad portion 41a1. It should be noted that in the manufacture of such a semiconductor device 10a, a forming mold is used, which provides a protrusion forming the recess 60b on the sealing member 60. The other manufacturing processes are the same as in the first embodiment.

[0097] Next, using Figure 13 The case where a heat sink 90 is installed on such a semiconductor device 10a will be described. Figure 13 This is a longitudinal cross-sectional view of the semiconductor device and heat sink according to the second embodiment. It should be noted that... Figure 13 Corresponding to Figure 11 The cross-section of the semiconductor device 10a. When mounting the heat sink 90 to the semiconductor device 10a, firstly, a heat-dissipating compound is coated inside the recess 60b of the semiconductor device 10a. Then, similarly to the first embodiment, the heat sink 90 is mounted on the back side of the semiconductor device 10a and the bolt 93 is tightened. If the back side of the semiconductor device 10a and the front side of the heat sink 90 are brought into close contact as the bolt 93 is tightened, the thickness of the heat-dissipating compound between the back side of the insulating sheet 70 and the front side of the heat sink 90 can be made uniform. Therefore, the thermal conductivity from the insulating sheet 70 to the heat sink 90 is improved. To improve this thermal conductivity, it is desirable that the heat-dissipating compound is uniform and thin. Therefore, the depth of the recess 60b is preferably such that the height of the back side of the insulating sheet 70 is the same as the height of the back side surrounding the recess 60b of the semiconductor device 10a. Alternatively, the depth of the recess 60b is preferably 10 μm or more and 100 μm or less.

[0098] [Third Implementation Method]

[0099] use Figure 14 The semiconductor device of the third embodiment will be described. Figure 14 This is a longitudinal cross-sectional view of the semiconductor device according to the third embodiment. It should be noted that the semiconductor device 10b uses the same symbols for components identical to those in the semiconductor device 10, and their descriptions are omitted or simplified. The semiconductor device 10b includes the wafer pad portion of the main current lead frame 40 (in... Figure 14 The thickness of the wafer pad portion 41a1 is greater than that in the first embodiment. Therefore, the thickness of the wafer pad portion 41a1 is greater than the thickness of the connection portion 41a2 and the terminal portion 41a3. This increases the heat capacity of the main current lead frame 40, suppressing transient increases in thermal resistance. Furthermore, by making the wafer pad portion (in...)... Figure 14 The thickness of the wafer pad portion 41a1 is increased, thereby generating heat diffusion and reducing thermal resistance compared to the first embodiment. Therefore, semiconductor device 10b is more capable of achieving improved heat dissipation than semiconductor device 10. Furthermore, the third embodiment is not limited to... Figure 14 In some cases, the wafer pad portion of the main current lead frame 40 in the second embodiment may be thicker than that in the second embodiment.

Claims

1. A method of manufacturing a semiconductor device, characterized by, including: a preparation step of preparing a power semiconductor chip, a lead frame including a wafer pad portion and a terminal portion integrally connected to the wafer pad portion, a semi-cured state insulating sheet, and a semi-cured state sealing material; a mounting step of arranging the power semiconductor chip on a front surface of the wafer pad portion and performing wiring; a sealing step of sealing the lead frame and the power semiconductor chip with the semi-cured state sealing material in a manner that the terminal portion protrudes and exposes a back surface of the wafer pad portion to form a semi-cured unit; a press bonding step of press-bonding a front surface of the semi-cured state insulating sheet to a back surface of the semi-cured unit to cover the back surface of the wafer pad portion; and a curing step of curing the semi-cured unit and the semi-cured state insulating sheet by heating.

2. The method of manufacturing a semiconductor device according to claim 1, wherein after the press bonding step is performed, the semi-cured unit to which the insulating sheet is press-bonding is conveyed to a heating device, and the curing step is performed by the heating device.

3. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the press bonding step press-bonds the semi-cured unit to the insulating sheet in a heated state.

4. The method of manufacturing a semiconductor device according to claim 1, wherein the curing step heats the semi-cured unit to which the insulating sheet is press-bonding without pressure.

5. The method of manufacturing a semiconductor device according to claim 1, wherein the sealing material and the insulating sheet include a semi-cured state thermosetting resin and an inorganic filler.

6. The method of manufacturing a semiconductor device according to claim 5, wherein the thermosetting resin of the sealing material and the thermosetting resin of the insulating sheet both include an epoxy resin as a main component.

7. The method of manufacturing a semiconductor device according to claim 5, wherein the inorganic filler of the sealing material includes silicon oxide as a main component, and the inorganic filler of the insulating sheet includes at least one selected from the group consisting of aluminum oxide, aluminum nitride, silicon nitride, and boron nitride as a main component. having:

8. A semiconductor device, characterized by comprising: a lead frame including a wafer pad portion and a terminal portion integrally connected to the wafer pad portion; a power semiconductor chip arranged on a front surface of the wafer pad portion; a sealing member provided with a recess on a back surface to seal the lead frame and the power semiconductor chip in a manner that the terminal portion protrudes and the back surface of the wafer pad portion is exposed in the recess, wherein a back surface around the recess of the sealing member is located at a position lower than a back surface of the wafer pad portion; ​ an insulating sheet provided in the recess of the sealing member to cover a back surface of the wafer pad portion exposed by the recess of the sealing member, and constituting a height difference with respect to a back surface of the recess of the sealing member, wherein the back surface of the recess of the sealing member projects more outward than the back surface of the insulating sheet, the area of the back surface of the insulating sheet is smaller than the opening area of the recess of the sealing member, and larger than the area of the back surface of the wafer pad portion; a heat sink provided to the back surface of the recess of the sealing member; and a heat dissipation composite provided in a space surrounded by the sealing member, the insulating sheet, and the heat sink.

9. The semiconductor device according to claim 8, wherein the sealing member and the insulating sheet include a thermosetting resin and an inorganic filler.

10. The semiconductor device according to claim 9, wherein the thermosetting resin of the sealing member and the thermosetting resin of the insulating sheet both include an epoxy resin as a main component.

11. The semiconductor device according to claim 9, wherein the inorganic filler of the sealing member includes silicon oxide as a main component, and the inorganic filler of the insulating sheet includes at least one selected from the group consisting of aluminum oxide, aluminum nitride, silicon nitride, and boron nitride as a main component.

12. The semiconductor device according to claim 8, wherein the thickness of the wafer pad portion is thicker than the thickness of the terminal portion.

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