Circuit and method of forming the same

Abstract

A circuit and a method for forming the circuit, the circuit being an electrostatic discharge protection circuit, comprising: an electrostatic discharge clamp located between a first track and a second track; a trigger device configured to activate the electrostatic discharge clamp in response to an electrostatic discharge event; and a charge dissipation element located between the first track and the second track for dissipating a residual charge at an input of the trigger device.

Description

Technical Field

[0001] The present disclosure relates generally to integrated circuits, and more particularly to protecting integrated circuits from electrostatic discharge (ESD). Background Art

[0002] Integrated circuits are widely used in a variety of applications. The reliability of such integrated circuits can be affected by a variety of factors. One such factor may be an electrostatic discharge (ESD) event. An ESD event may cause a brief charge surge within the integrated circuit, which may ultimately cause the integrated circuit to fail. Because ESD events may occur under a variety of conditions, such as during manufacturing, assembly, testing, field operation, etc., protection against ESD events is critical to the proper operation of the integrated circuit. In order to protect the integrated circuit from such ESD events, ESD protection may be used within the integrated circuit. However, current ESD protection mechanisms have limitations in how they are configured and how they operate. Summary of the invention

[0003] Some aspects of the present disclosure provide a circuit including an electrostatic discharge clamp, a trigger device, and a charge dissipation element. The electrostatic discharge clamp is located between a first rail and a second rail. The trigger device is configured to activate the electrostatic discharge clamp in response to an electrostatic discharge event. The charge dissipation element is located between the first rail and the second rail and is used to dissipate residual charge at the input of the trigger device.

[0004] Other aspects of the present disclosure provide a circuit including a first virtual power rail, a second virtual power rail, an electrostatic discharge clamp, a trigger device, and a charge dissipation element. The first virtual power rail is connected to the first rail. The second virtual power rail is connected to the first rail. The electrostatic discharge clamp is connected between the first virtual power rail and the second rail. The trigger device is connected to the electrostatic discharge clamp and is configured to activate the electrostatic discharge clamp in an electrostatic discharge event based on the voltage level of the second virtual power rail and the voltage level of the trigger signal. The charge dissipation element is connected between the second rail and at least one of the second virtual power rail or the trigger signal to dissipate residual charge from at least one of the second virtual power rail or the trigger signal.

[0005] Still other aspects of the present disclosure provide a method of forming a circuit. The method includes: connecting an ESD clamp between a first track and a second track; connecting a trigger device to the ESD clamp; connecting a charge dissipation element between an input of the trigger device and the second track; dissipating residual charge from the input of the trigger device to the second track through the charge dissipation element; changing an output of the trigger device in response to an ESD event to activate the ESD clamp; and in response to the activation, transferring an ESD current from the first track to the second track through the ESD clamp. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the sizes of various features are arbitrarily expanded or reduced for clarity of discussion.

[0007] Figure 1 is an example circuit diagram of an ESD protection circuit according to some embodiments;

[0008] Figure 2 According to some embodiments Figure 1 An example circuit diagram of an exemplary implementation of an ESD protection circuit;

[0009] Figure 3 is another example circuit diagram of an ESD protection circuit according to some embodiments;

[0010] 4A to 4D For example, according to some embodiments Figures 1 to 3 Examples of charge dissipating components used in ESD protection circuits;

[0011] Figure 5 To illustrate a device having a charge dissipation element according to some embodiments Figures 1 to 3 ESD protection circuit, example curve graph of exemplary simulation;

[0012] Figure 6 To summarize some embodiments Figures 1 to 3 An example flow chart of the operation of an ESD protection circuit.

[0013]

Explanation of symbols

[0014] 100: Electrostatic discharge protection circuit

[0015] 105: Electrostatic Discharge Clamp

[0016] 110: First track

[0017] 115: The First Virtual Power Rail

[0018] 120: Second track

[0019] 125: First diode

[0020] 130: Second diode

[0021] 135: Second virtual power rail

[0022] 140: Trigger device

[0023] 145: Trigger signal

[0024] 150: Resistor-Capacitor Filter

[0025] 155: Resistor

[0026] 160:Capacitor

[0027] 165: First Node

[0028] 170: Second Node

[0029] 175: Start signal

[0030] 180: Charge dissipation element

[0031] 185:NMOS transistor

[0032] 190: First terminal

[0033] 195: Second terminal

[0034] 200: Third terminal

[0035] 205: Body terminal

[0036] 210: Buffered Inverter

[0037] 215:PMOS transistor

[0038] 220:NMOS transistor

[0039] 225: First terminal

[0040] 230: Second terminal

[0041] 235: First terminal

[0042] 240: Second terminal

[0043] 245: Third terminal

[0044] 250: Third terminal

[0045] 255: Electrostatic discharge protection circuit

[0046] 260: First track

[0047] 265: Second Track

[0048] 270: First Virtual Power Rail

[0049] 275: Second Virtual Power Rail

[0050] 280: First diode

[0051] 285: Second diode

[0052] 290: ESD Clamp

[0053] 295: Trigger Device

[0054] 300: Resistor-Capacitor Filter

[0055] 305: Resistor

[0056] 310: Capacitor

[0057] 315: Trigger signal

[0058] 320: First Node

[0059] 325: Second Node

[0060] 330: Charge dissipation element

[0061] 335: Reverse diode

[0062] 340: Cathode terminal

[0063] 345: Anode terminal

[0064] 350: Series diode

[0065] 355: Anode terminal

[0066] 360: Cathode terminal

[0067] 365: cathode terminal

[0068] 370:NMOS diode

[0069] 375: First terminal

[0070] 380: Second terminal

[0071] 385: Third terminal

[0072] 390:PMOS diode

[0073] 395: First terminal

[0074] 400: Second terminal

[0075] 405: The third terminal

[0076] 410: Graph

[0077] 420: Process

[0078] 425: Operation

[0079] 430: Operation

[0080] 435: Operation

[0081] 440: Operation

[0082] 445: Operation

[0083] 450: Operation

[0084] 455: Operation

[0085] 460: Operation DETAILED DESCRIPTION

[0086] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or on a second feature in the following description may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0087] Additionally, for ease of description, spatially relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature, as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0088] Reference now Figure 1, an example circuit diagram of an electrostatic discharge (“Electrostatic Discharge, ESD”) protection circuit 100 is shown according to some embodiments of the present disclosure. The ESD protection circuit 100 can be used to protect an integrated circuit from an ESD event. An “integrated circuit” can be an interconnection of electrical components such as resistors, transistors, switches, batteries, inductors, or other types of semiconductor devices configured to achieve desired functionality. An “ESD event” can be any condition that causes or may cause an electrostatic surge or excess charge flow that can potentially damage the integrated circuit in some way. The ESD protection circuit 100 can be configured to protect the integrated circuit from such damaging ESD events.

[0089] Thus, the ESD protection circuit 100 includes an electrostatic discharge (ESD) clamp 105 connected between a first rail 110 and a second rail 120, and specifically between a first virtual power rail 115 of the first rail and the second rail 120. In some embodiments, the first rail 110 may be a voltage bus connected to one or more input / output signals. In some embodiments, the second rail 120 may be a voltage bus connected to a reference voltage such as ground. Thus, in some embodiments, the first rail 110 may be at a higher potential or voltage level relative to the second rail 120. In some embodiments, the first virtual power rail 115 may be a voltage bus connected to the first rail 110 via a first diode 125. The first diode 125 may ensure that current flows in a single direction from the first rail 110 toward the first virtual power rail 115 and ultimately to the protected integrated circuit. Thus, in some embodiments, the integrated circuit that the ESD protection circuit 100 is configured to protect may be connected to at least the first virtual power rail 115 to supply power to the integrated circuit. In some embodiments, the protected integrated circuit may also be connected to the second rail 120.

[0090] In addition, in some embodiments, the ESD protection circuit 100 may also include a second diode 130 connected between the first rail 110 and the second virtual power rail 135. The second diode 130 can ensure that the current flows in a single direction from the first rail 110 toward the second virtual power rail 135 and finally reaches the protected integrated circuit. Therefore, in some embodiments, the second virtual power rail 135 can be connected to the protected integrated circuit in addition or through other connections to provide power supply to the integrated circuit. Similar to the first virtual power rail 115, the second virtual power rail 135 can be a voltage bus bar.

[0091] In order to protect the integrated circuit from the ESD event, the ESD clamp 105 can be configured to transfer excess charge (e.g., ESD current) between the first virtual power rail 115 and the second rail 120 during the ESD event. For example, in some embodiments, the ESD clamp 105 can be configured to transfer the ESD current from the first virtual power rail 115 to the second rail 120. Under normal operating conditions (e.g., when there is no ESD event), the ESD clamp 105 can remain in an unactivated, deactivated, or cut-off state. When the ESD protection circuit 100 detects an ESD event, the ESD clamp 105 can be activated or turned on to transfer the ESD current between the first virtual power rail 115 and the second rail 120. In some embodiments, the activation and deactivation of the ESD clamp 105 can be controlled by the trigger device 140.

[0092] The trigger device 140 may be connected to the ESD clamp 105. Specifically, the output of the trigger device 140 may be input into the ESD clamp 105 to activate and deactivate the ESD clamp. By changing the output of the trigger device 140, the ESD clamp 105 may be turned on or off. In order to change the output of the trigger device 140, the trigger device may be connected to the second virtual power rail 135 and the trigger signal 145. Based on the voltage level of the second virtual power rail 135 and the voltage level of the trigger signal 145, the voltage level at the output of the trigger device 140 may be changed to activate and deactivate the ESD clamp 105. For example, in some embodiments, the output of the trigger device 140 may become a high voltage level. If the voltage level is at or above a predetermined threshold value, the voltage level may be considered a "high voltage level", and if this voltage level is below the predetermined threshold value, the voltage level may be considered a "low voltage level". In some embodiments, the high voltage level at the output of the trigger device 140 may be configured to activate the ESD clamp 105. Thus, in some embodiments, the trigger device 140 may be controlled based on the second virtual power rail 135 and the trigger signal 145 to generate a high voltage level at the output of the trigger device to activate the ESD clamp 105 during an ESD event.

[0093] In other embodiments, the ESD clamp 105 may be configured to activate when the trigger device 140 is at a low voltage level. In such embodiments, the second virtual power rail 135 and the trigger signal 145 may be configured to generate a low voltage level at the output of the trigger device 140 during an ESD event to activate the ESD clamp 105. Furthermore, in some embodiments, the low voltage level at the output of the trigger device 140 may be configured to deactivate the ESD clamp 105. Thus, in some embodiments, when there is no ESD event, the second virtual power rail 135 and the trigger signal 145 may be configured to generate a low voltage level at the output of the trigger device to deactivate the ESD clamp 105 or keep the ESD clamp 105 from being activated. In some embodiments, when there is no ESD event, the ESD clamp 105 may be configured not to be activated when the output of the trigger device 140 is at a high voltage level. In such embodiments, the second virtual power rail 135 and the trigger signal 145 may be configured to generate a high voltage level at the output of the trigger device to deactivate the ESD clamp 105.

[0094] In some embodiments, the trigger device 140 may be a buffer device, a buffered inverter device, etc. In other embodiments, the trigger device 140 may be another type of suitable device configured to change the output of the trigger device based on the occurrence of an ESD event. In addition, in some embodiments, the ESD clamp 105 may be an n-type Metal-Oxide-Semiconductor Field-Effect Transistor (NMOS) transistor or a p-type Metal-Oxide-Semiconductor Field-Effect Transistor (PMOS) transistor. In other embodiments, another type of suitable device that can be selectively turned on and off and can divert ESD current from the first virtual power rail 115 to the second rail 120 during an ESD event may be used.

[0095] The voltage level of the trigger signal 145 can be changed based on the resistor-capacitor filter 150 having the resistor 155 and the capacitor 160. The distributed resistor-capacitor filter 150 can be configured to provide a valid transient trigger signal (e.g., the trigger signal 145) to the trigger device 140 during an ESD event. In some embodiments, the resistor-capacitor filter 150 can act as a low-pass filter driven by the voltage or current from the first rail 110 and the second rail 120. The resistor-capacitor filter 150 can establish a voltage drop across the first node 165 based on the voltage level at the second node 170 to set the voltage level of the trigger signal 145 to provide a valid transient trigger signal to the trigger device 140.

[0096] During normal operation (e.g., when there is no ESD event), the voltage level applied at the first rail 110 may cause the voltage level at the second node 170 to remain at a high voltage level. With the second node 170 at a high voltage level, the voltage level at the first node 165 is also at a high voltage level, and thus the trigger signal 145 is also at a high voltage level. In some embodiments, the trigger device 140 may be a buffered inverter device. In such embodiments, the high voltage level of the trigger signal 145 may cause the buffered inverter of the trigger device 140 to generate a low voltage level at the output as the enable signal 175. Thus, the trigger device 140 receives the trigger signal 145 as an input and generates the enable signal 175 as an output. In some embodiments, when the enable signal 175 is at a low voltage level, the ESD clamp 105 may be in a cut-off state.

[0097] However, during an ESD event, the trigger device 140 is configured to detect the ESD event and generate a high voltage level at the activation signal 175 to activate the ESD clamp 105. For example, during an ESD event, the first rail 110 receives an ESD current surge, which increases the voltage levels of the first virtual power rail 115 and the second virtual power rail 135. The increased voltage level at the second node 170 causes the voltage level at the first node 165 to become a low voltage level. Specifically, the resistor 155 of the resistor-capacitor filter 150 prevents the voltage surge from passing through, thereby causing the first node 165 to become a low voltage level. When the trigger device 140 is a buffered inverter, the low voltage level at the trigger signal 145 causes the buffered inverter to generate a high voltage level signal at the activation signal 175, thereby turning on the ESD clamp 105. When the ESD clamp 105 is turned on, the ESD current can be corrected or transferred from the first virtual power rail 115 to the second rail 120 via the ESD clamp, thereby effectively preventing the ESD current from being transmitted to the integrated circuit protected by the ESD protection circuit 100 .

[0098] Thus, the operation of the trigger device 140 is based on the voltage levels at the first node 165 (e.g., the trigger signal 145) and the second node 170 (e.g., the second virtual power rail 135). In some embodiments, the resistor-capacitor filter 150 can store charge. The stored charge can be residual charge from one or more previous cycles (e.g., normal events or ESD events). In some embodiments, this residual charge can be stored at the first node 165 and / or the second virtual power rail 135. In some embodiments, the residual charge at the first node 165 can be attributed to the residual charge stored at the second node 170. The residual charge at the first node 165 and / or the second node 170 can affect the correct operation of the trigger device 140. For example, in some embodiments, after the ESD event has passed, the potential or voltage level at the first node 165 and / or the second node 170 may not return to the zero charge level so that the residual charge remains stored at those nodes. When the next ESD event occurs, instead of being at a low voltage level, the residual charge causes the first node 165 to be at a high voltage level, so that the transient voltage at the first node is at a relatively higher voltage level than the second virtual power rail 135. The high voltage level at the first node 165 can then cause the trigger device 140 to generate a low voltage level signal at the enable signal 175, thereby keeping the ESD clamp 105 off and unable to divert the ESD current. In the case where the ESD current cannot be diverted, the integrated circuit protected by the ESD protection circuit 100 is damaged.

[0099] Similarly, in some embodiments, the transient response voltage level at the first node may be a low voltage level during a normal operation cycle due to residual charge at the first node 165 and / or the second node 170. The low voltage level at the first node 165 may cause the trigger device 140 to generate a high voltage level signal at the activation signal 175, thereby causing the ESD clamp 105 to activate and transfer current from the first virtual power rail 115 to the second rail 120. By being turned on during normal operation, the ESD clamp 105 may hinder normal operation of the integrated circuit protected by the ESD protection circuit 100.

[0100] To ensure proper operation of the ESD protection circuit 100, such that the ESD clamp 105 is always activated during an ESD event and is activated only during an ESD event, the present disclosure provides a mechanism to discharge any residual charge stored at the first node 165 and / or the second node 170. For example and as Figure 1As shown, in some embodiments, a charge dissipation element 180 may be disposed between the first node 165 and the second rail 120 to discharge the potential or residual charge stored at the first node. Thus, the charge dissipation element 180 provides a charge dissipation path for the residual charge from the first node 165 through the second rail 120 to ground, thereby allowing the first node to be maintained at a potential of approximately zero voltage level or close to the potential of the second rail 120. By allowing the residual charge at the first node 165 to discharge, the present disclosure provides a mechanism to ensure that the trigger device 140 is properly activated, and in turn, the ESD clamp 105 is properly activated.

[0101] Go to Figure 2 , examples of an ESD clamp 105 and a trigger device 140 that may be used in an ESD protection circuit 100 are shown according to some embodiments of the present disclosure. In some embodiments, the ESD clamp 105 may include an NMOS transistor 185. A first terminal (e.g., a drain terminal) 190 of the NMOS transistor 185 may be connected to the first virtual power rail 115, and a second terminal (e.g., a source terminal) 195 of the NMOS transistor may be connected to the second rail 120. A third terminal (e.g., a gate terminal) 200 of the NMOS transistor may be connected to the enable signal 175, and a body terminal 205 of the NMOS transistor may be connected to the second rail 120. In other embodiments, instead of the NMOS transistor 185, a PMOS transistor or another suitable device may be used for the ESD clamp 105.

[0102] Furthermore, in some embodiments, the trigger device 140 may be a buffered inverter 210 having a p-type metal oxide semiconductor field effect transistor (PMOS) transistor 215 and an n-type metal oxide semiconductor field effect transistor (NMOS) transistor 220. A first terminal (e.g., drain terminal) 225 of the PMOS transistor 215 may be connected to the second virtual power rail 135, and a second terminal (e.g., source terminal) 230 of the PMOS transistor may be connected to a first terminal (e.g., drain terminal) 235 of the NMOS transistor 220. A second terminal (e.g., source terminal) 240 of the NMOS transistor 220 may be connected to the second rail 120. Furthermore, in some embodiments, a third terminal (e.g., gate terminal) 245 of the PMOS transistor 215 and a third terminal (e.g., gate terminal) 250 of the NMOS transistor 220 may be connected to the trigger signal 145. Although the buffered inverter 210 is shown as being used as the trigger device 140, in some embodiments, other types of suitable trigger devices may be used.

[0103] During an ESD event, the first rail 110 receives an ESD current, which causes the voltage level of the first virtual power rail 115 to increase, which in turn increases the voltage level at the first terminal 190 of the NMOS transistor 185. The ESD current also increases the voltage level of the second virtual power rail 135 and the second node 170. Due to the resistance provided by the resistor 155 of the resistor-capacitor filter 150, the voltage level at the second node 170 produces a low voltage level at the first node 165, which is then applied to the buffer inverter 210 via the third terminal 245 of the PMOS transistor 215 and the third terminal 250 of the NMOS transistor 220 connected to the trigger signal 145. Due to receiving the low voltage level signal as an input, the buffer inverter 210 produces a high voltage level at the enable signal 175 to turn on the NMOS transistor 185. After being turned on, the NMOS transistor 185 creates a path for passing the ESD current from the first virtual power rail 115 to the second rail 120. Furthermore, due to the presence of charge dissipation element 180, any residual charge remaining at first node 165 after an ESD event is dissipated to regulate proper activation of buffer inverter 210 and NMOS transistor 185 during normal operation and during the next ESD event.

[0104] The charge dissipation element 180 may be used to dissipate any pre-existing charge on the second virtual power rail 135 (as discussed below) and / or the first node 165, regardless of the cause of the pre-existing charge (e.g., residual charge) at the second virtual power rail and / or the first node. For example, as described above, in some embodiments, the charge dissipation element 180 may be used to dissipate any residual charge from the first node 165 (and / or the second virtual power rail 135, as discussed below) after an ESD event. In other embodiments, the charge dissipation element 180 may be used to eliminate pre-existing (e.g., residual charge) from the second virtual power rail 135 and / or the first node 165 that occurs due to a power on or off operation, any intentional or accidental pre-biasing action that causes a potential at the second virtual power rail and / or the first node prior to the ESD event, or any other event that causes a potential at those nodes. As pre-existing (e.g., residual) charges are dissipated from the second virtual power rail 135 and / or the first node 165, the charge dissipation element 180 ensures that the second virtual power rail and / or the first node are maintained at a potential close to the potential of the second rail 120. By maintaining the potential of the second virtual power rail 135 and / or the first node 165 close to the potential of the second rail 120, when an ESD event occurs, the trigger device 140 is properly actuated to enable the ESD clamp 105.

[0105] refer to Figure 3, another example of an ESD protection circuit 255 is shown according to some embodiments of the present disclosure. The ESD protection circuit 255 is similar to the ESD protection circuit 100 except for the location of the charge dissipation elements. Thus, similar to the ESD protection circuit 100, the ESD protection circuit 255 includes a first rail 260, a second rail 265, a first virtual power rail 270, and a second virtual power rail 275, each of which is similar to the first rail 110, the second rail 120, the first virtual power rail 115, and the second virtual power rail 135, respectively. A first diode 280, similar to the first diode 125, is disposed between the first rail 260 and the first virtual power rail 270. A second diode 285, similar to the second diode 130, is disposed between the first rail 260 and the second virtual power rail 275. The ESD protection circuit 255 also includes an ESD clamp 290, similar to the ESD clamp 105, and a trigger device 295, similar to the trigger device 140.

[0106] The resistor-capacitor filter 300 having a resistor 305 and a capacitor 310 provides a trigger signal 315 to the trigger device 295 at a first node 320. The resistor-capacitor filter 300, the resistor 305, and the capacitor 310 are similar to the resistor-capacitor filter 150, the resistor 155, and the capacitor 160, respectively. The size of the resistor 155, the resistor 305, the capacitor 160, and the capacitor 310 can vary from one embodiment to another depending on the current level that needs to be corrected during the ESD event. The voltage level at the first node 320 can be changed based on the voltage level at the second node 325, as discussed above. The operation of the ESD protection circuit 255 is similar to the operation of the ESD protection circuit 100, and therefore will not be described again.

[0107] The ESD protection circuit 255 also includes a charge dissipation element 325 similar to the charge dissipation circuit 180. However, in contrast to the charge dissipation circuit 180, which may be connected between the first node 165 and the second rail 120, the charge dissipation element 330 may be connected between the second node 325 and the second rail 265. The charge dissipation element 330 may thus provide a path to dissipate residual charge from the second virtual power rail 275 via the second node 325. As discussed above, in some embodiments, the voltage level at the first node 320 may be affected by the residual charge at the second node 325. By dissipating the residual charge from the second node 325, the residual charge of the second node no longer affects the voltage level at the first node 320.

[0108] Thus, in some embodiments, a charge dissipation element (e.g., charge dissipation element 180) may be connected to dissipate residual charge from a first node (e.g., first node 165, 320), while in other embodiments, a charge dissipation element (e.g., charge dissipation element 330) may be connected to dissipate residual charge from a second node (e.g., second node 170, 325). In some embodiments, the charge dissipation element may be connected to the first node (e.g., first node 165, 320) or the second node (e.g., second node 170, 325). In other embodiments, the charge dissipation element may be connected to both the first node (e.g., first node 165, 320) and the second node (e.g., second node 170, 325). Thus, in some embodiments, the charge dissipation element may be additionally connected at Figure 1 Likewise, in some embodiments, the charge dissipation element may be additionally connected between the second node 170 and the second rail 120. Figure 3 between the first node 320 and the second track 265 .

[0109] Now go to 4A to 4D , according to some embodiments of the present disclosure, example configurations that may be used for charge dissipation element 180 and / or charge dissipation element 330 are shown. In some embodiments and as Figure 4A As shown, the charge dissipation element 180 and / or the charge dissipation element 330 can be configured as a reverse diode 335, wherein the cathode terminal 340 is connected to the first node or the second node, and the anode terminal 345 is connected to the second rail (e.g., the second rail 120, 265). For example, in some embodiments, the charge dissipation element 180 can be configured as a reverse diode 335, such that the cathode terminal 340 of the reverse diode 335 is connected to the first node 165 and the anode terminal 345 of the reverse diode is connected to the second rail 120. Similarly, in some embodiments, the charge dissipation element 330 can be configured as a reverse diode 335, such that the cathode terminal 340 is connected to the second node 325 and the anode terminal 345 is connected to the second rail 265.

[0110] In some embodiments, and as Figure 4BAs shown, the charge dissipation element 180 and / or the charge dissipation element 330 can be configured as a series of diodes 350. The number of diodes in the series of diodes 350 can vary from one embodiment to another. In some embodiments, the number of diodes in the series of diodes 350 can depend on the amount of residual charge that needs to be dissipated. In addition, in some embodiments, the series of diodes 350 can be connected so that the anode terminal 355 of the first diode in the series of diodes 350 is connected to the first node (e.g., the first node 165, 320) or the second node (e.g., the second node 170, 325), and the cathode terminal 360 of the first diode is connected to the anode terminal of the next diode in the sequence (e.g., the second diode). The cathode terminal of the second diode can be connected to the anode of the third diode in the sequence, and so on. The cathode terminal 365 of the last series of diodes 350 in the series can be connected to the second rail (e.g., the second rail 120, 265).

[0111] In some embodiments, and as Figure 4C As shown, the charge dissipation element 180 and / or the charge dissipation element 330 can be configured as an NMOS diode 370. A first terminal (e.g., drain terminal) 375 of the NMOS diode 370 can be connected to a first node (e.g., first node 165, 320) or a second node (e.g., second node 170, 325), and a second terminal (e.g., source terminal) 380 of the NMOS diode can be connected to a second rail (e.g., second rail 120, 265). A third terminal (e.g., gate terminal) 385 of the NMOS diode 370 can be connected to the second terminal 380. In other embodiments, and as Figure 4D As shown, the charge dissipation element 180 and / or the charge dissipation element 330 can be configured as a PMOS diode 390. A first terminal (e.g., drain terminal) 395 of the PMOS diode 390 can be connected to a first node (e.g., first node 165, 320) or a second node (e.g., second node 170, 325), and a second terminal (e.g., source terminal) 400 of the PMOS diode can be connected to a second rail (e.g., second rail 120, 265). A third terminal (e.g., gate terminal) 405 of the PMOS diode 390 can be connected to the first terminal 395.

[0112] In other embodiments, other types of devices may be used for charge dissipation element 180 and / or charge dissipation element 330 for draining residual charge. In some embodiments, and particularly in those embodiments where a first charge dissipation element is used to drain residual charge from a first node (e.g., first node 165, 320) and a second charge dissipation element is used to drain residual charge from a second node (e.g., second node 170, 325), both the first and second charge dissipation elements may be of the same type. In other embodiments, the first charge dissipation element and the second charge dissipation element may be of different types. By connecting such charge dissipation element(s) between a first node (e.g., first node 165, 320) and / or a second node (e.g., second node 170, 325), any residual charge from those nodes may be drained to a second rail (e.g., second rail 120, 265).

[0113] refer to Figure 5 , an example graph 410 is shown according to some embodiments of the present disclosure. In some embodiments, ESD testing may be performed to monitor or test the effectiveness of the ESD protection circuit. Example tests may include human body model (HBM) testing, charge device model (CDM) testing, machine model (MM) testing, etc. HBM testing may be based on an ESD event caused by a charged person discharging a charge surge into an ESD protection circuit (e.g., ESD protection circuit 100, 255). CDM testing may be based on an ESD event in which the ESD protection circuit (e.g., ESD protection circuit 100, 255) is self-charged during a manufacturing process. MM testing may be based on a charge surge from a charged device (e.g., a machine, a tool, etc.). Such ESD tests may be used to provide feedback on whether the ESD protection circuit (e.g., ESD protection circuit 100, 255) is operating correctly. However, if the ESD protection circuit (eg, ESD protection circuits 100 , 255 ) does not operate properly, such testing may damage the integrated circuit to which the ESD protection circuit is connected.

[0114] Therefore, in some embodiments, a transmission line pulsing (TLP) test may be used. The TLP test may be used to test and characterize the performance properties of an ESD protection circuit (e.g., ESD protection circuit 100, 255) without damaging the connected integrated circuit. The TLP test may simulate an ESD event and measure the response of the ESD protection circuit (e.g., ESD protection circuit 100, 255). Graph 410 shows an exemplary ESD test simulation of an ESD protection circuit (e.g., ESD protection circuit 100, 255) having a charge dissipation element (e.g., charge dissipation element 180, 330). Graph 410 plots the TLP voltage on the X-axis versus the TLP current on the Y-axis. In addition, graph 410 shows three curves. The curves of graph 410 have lower clamping voltages than similar curves (not shown) simulated without a charge dissipation element (e.g., charge dissipation element 180, 330). By using charge dissipating elements such as charge dissipating elements 180 or 330 , a lower clamping voltage may be delivered to an integrated circuit that an ESD protection circuit (eg, ESD protection circuits 100 , 255 ) is configured to protect, compared to an ESD protection circuit without the charge dissipating elements.

[0115] Reference now Figure 6 , an example flow chart outlining operations of a process 420 for operating an ESD protection circuit (e.g., ESD protection circuit 100, 255) is shown according to some embodiments of the present disclosure. According to embodiments, process 420 may include other or additional operations. To protect an integrated circuit from an ESD event, an ESD protection circuit (e.g., ESD protection circuit 100, 255) may be connected to the integrated circuit. To connect the ESD protection circuit to the integrated circuit, after starting at operation 425, an ESD clamp (e.g., ESD clamp 105, 290) may be connected between a first rail (e.g., first rail 110, 260) and a second rail (e.g., second rail 120, 265) at operation 430. More specifically, the ESD clamp may be connected between a first virtual power rail (e.g., first virtual power rail 115, 270) and a second rail. In some embodiments, the ESD clamp may include an NMOS transistor, a first terminal of the NMOS transistor may be connected to a first virtual power rail, a second terminal of the NMOS transistor may be connected to a second rail, and a third terminal of the NMOS transistor may be connected to a trigger device (e.g., trigger device 140, 295).

[0116] At operation 435, a trigger device (e.g., trigger device 140, 295) is connected to an ESD clamp (e.g., ESD clamp 105, 290) so that the ESD clamp can be activated or deactivated by changing the voltage level at the output of the trigger device. In addition, to ensure that the trigger device itself correctly changes the voltage level at the output of the trigger device, a charge dissipation element (e.g., charge dissipation element 180, 330) is connected to the trigger device at operation 440. As discussed above, in some embodiments, the charge dissipation element (e.g., charge dissipation element 180) can be connected between a first node (e.g., first node 165, 320) and a second rail (e.g., second rail 120, 265). In other embodiments, the charge dissipation element (e.g., charge dissipation element 330) can be additionally or otherwise connected between a second node (e.g., second node 170, 325) and the second rail. In addition, a resistor-capacitor filter (e.g., resistor-capacitor filter 150, 330) can be connected as discussed above.

[0117] After connecting the various elements of the ESD protection circuit, at operation 445, the charge dissipation element (e.g., charge dissipation element 180, 330) transfers any residual charge that may have accumulated at a first node (e.g., first node 165, 320) or a second node (e.g., second node 170, 325) to which the charge dissipation element may be connected. By dissipating the residual charge, the charge dissipation element ensures that the ESD clamp (e.g., ESD clamp 105, 290) does not accidentally turn on during normal operation and is always turned on during an ESD event. At operation 450, the process 420 waits for an ESD event. After detecting an ESD event, process 420 proceeds to operation 455, where the trigger device (e.g., trigger device 140, 295) changes the output of the trigger device to activate the ESD clamp (e.g., ESD clamp 105, 290). The activation of the ESD clamp (e.g., ESD clamp 105, 290) causes the ESD clamp (e.g., ESD clamp 105, 290) to cause the ESD current to be transferred from the first rail (e.g., first rail 110, 260) to the second rail (e.g., second rail 120, 265), thereby reducing the clamping voltage that would otherwise be delivered to the protected integrated circuit.

[0118] On the other hand, if no ESD event is detected at operation 450 and only normal operating voltage is detected, the ESD clamp (e.g., ESD clamp 105, 290) is maintained in the de-activated state by the trigger device (e.g., trigger device 140, 295) at operation 460, as discussed above. Both operations 455 and 460 lead back to operation 445, where any residual charge from the first node (e.g., first node 165, 320) and / or the second node (e.g., second node 170, 325) continues to be discharged to maintain the ESD clamp (e.g., ESD clamp 105, 290) in optimal operating conditions.

[0119] Thus, the present disclosure provides an ESD protection circuit that effectively provides protection to an integrated circuit against ESD events. A charge dissipation element prevents the ESD clamp from accidentally turning on during normal operation by dissipating any residual charge that may have been stored at the input of the trigger device after an ESD event, or between two normal operation cycles. The charge dissipation element also ensures that the ESD clamp does not actually turn on during normal operation by dissipating any residual charge from the input of the trigger device before an ESD event. Thus, the charge dissipation element results in a lower clamping voltage and increased efficiency of the ESD protection circuit.

[0120] According to some aspects of the present disclosure, a circuit is disclosed, comprising: an ESD clamp located between a first rail and a second rail; a trigger device configured to activate the ESD clamp in response to an ESD event; and a charge dissipation element located between the first rail and the second rail for dissipating residual charge at an input of the trigger device.

[0121] In some embodiments, the charge dissipation element is connected between the input of the trigger device and the second rail. In some embodiments, the input of the trigger device includes a trigger signal connected to the first node and a virtual power rail connected to the second node, and wherein the charge dissipation element is connected between the first node and the second rail. In some embodiments, the input of the trigger device includes a trigger signal connected to the first node and a virtual power rail connected to the second node, and wherein the charge dissipation element is connected between the second node and the second rail. In some embodiments, the trigger device is a buffered inverter. In some embodiments, the charge dissipation element is a reverse diode. In some embodiments, the charge dissipation element is a diode string. In some embodiments, the charge dissipation element is a p-type metal oxide semiconductor field effect transistor diode. In some embodiments, the charge dissipation element is an n-type metal oxide semiconductor field effect transistor diode. In some embodiments, the electrostatic discharge clamp is a transistor, and the transistor includes a first terminal connected to the virtual power rail of the first rail, a second terminal connected to the second rail, and a third terminal connected to the trigger device. In some implementations, the circuit further includes a resistor-capacitor filter located between the first rail and the second rail, and wherein the resistor-capacitor filter is configured to change a voltage level at an input of the trigger device during an electrostatic discharge event to activate the electrostatic discharge clamp.

[0122] According to some other aspects of the present disclosure, another circuit is disclosed. The circuit includes: a first virtual power rail connected to the first rail; a second virtual power rail connected to the first rail; an electrostatic discharge clamp connected between the first virtual power rail and the second rail; and a trigger device connected to the electrostatic discharge clamp and configured to activate the electrostatic discharge clamp in an electrostatic discharge event based on the voltage level of the second virtual power rail and the voltage level of the trigger signal. The circuit also includes a charge dissipation element connected between the second rail and at least one of the second virtual power rail or the trigger signal, for dissipating residual charge from at least one of the second virtual power rail or the trigger signal.

[0123] In some embodiments, the circuit further includes a first diode between the first track and the first virtual power track, and a second diode between the first track and the second virtual power track. In some embodiments, the circuit further includes a resistor-capacitor filter, wherein the resistor of the resistor-capacitor filter is connected to the second diode, wherein the second virtual power track is connected to a second node between the second diode and the resistor, and wherein the trigger signal is connected to a first node between the resistor and the capacitor of the resistor-capacitor filter, and the capacitor is connected to the second track. In some embodiments, the charge dissipation element is connected between the first node and the second track. In some embodiments, the charge dissipation element is connected between the second node and the second track. In some embodiments, the charge dissipation element is one of a reverse diode, a series diode, a p-type metal oxide semiconductor field effect transistor diode, or an n-type metal oxide semiconductor field effect transistor diode. In some embodiments, the trigger device is a buffer inverter and the electrostatic discharge clamp is an n-type metal oxide semiconductor field effect transistor diode.

[0124] According to yet another aspect of the present disclosure, a method of forming a circuit is disclosed. The method includes: connecting an electrostatic discharge clamp between a first track and a second track; connecting a trigger device to the electrostatic discharge clamp; connecting a charge dissipation element between an input of the trigger device and the second track; and dissipating residual charge from the input of the trigger device to the second track through the charge dissipation element. The method also includes: changing the output of the trigger device in response to an electrostatic discharge event to activate the electrostatic discharge clamp; and in response to the activation, transferring the electrostatic discharge current from the first track to the second track through the electrostatic discharge clamp.

[0125] In some embodiments, the method further includes: changing the output of the trigger device to deactivate the ESD clamp after the ESD event until the next ESD event; and continuing to dissipate residual charge from the input of the trigger device to the second rail through the charge dissipation element.

[0126] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A circuit, characterized in that: Include: an electrostatic discharge clamp located between a first track and a second track; a first virtual power rail connected to the first rail and the ESD clamp; a trigger device configured to activate the ESD clamp in response to an ESD event, wherein an input of the trigger device includes a trigger signal connected to a first node and a second virtual power rail connected to a second node, and based on the voltage level of the second virtual power rail and the voltage level of the trigger signal, the voltage level at the output of the trigger device is changed to activate the ESD clamp; a charge dissipation element, located between the first track and the second track, for dissipating a residual charge at the input of the trigger device; and A first diode, located between the first rail and the first virtual power rail, is configured to ensure that current flows in a single direction from the first rail toward the first virtual power rail and ultimately to the protected integrated circuit.

2. The circuit according to claim 1, characterized in that The charge dissipation element is connected between the input of the trigger device and the second rail.

3. The circuit according to claim 1, characterized in that The charge dissipation element is connected between the first node and the second rail.

4. The circuit according to claim 1, characterized in that The charge dissipation element is connected between the second node and the second rail.

5. The circuit according to claim 1, characterized in that The trigger device is a buffer inverter.

6. The circuit according to claim 1, characterized in that The charge dissipation element is a reverse diode.

7. The circuit according to claim 1, characterized in that The charge dissipation element is a diode string.

8. The circuit according to claim 1, characterized in that The charge dissipation element is a p-type metal oxide semiconductor field effect transistor diode.

9. The circuit according to claim 1, characterized in that The charge dissipation element is an n-type metal oxide semiconductor field effect transistor diode.

10. The circuit according to claim 1, characterized in that The electrostatic discharge clamp is a transistor including a first terminal connected to the first virtual power rail, a second terminal connected to the second rail, and a third terminal connected to the trigger device.

11. The circuit according to claim 1, characterized in that Further included is a resistor-capacitor filter located between the first rail and the second rail, and wherein the resistor-capacitor filter is configured to change a voltage level at the input of the trigger device during the electrostatic discharge event to activate the electrostatic discharge clamp.

12. A circuit, characterized in that: Include: a first virtual power rail connected to a first rail and an ESD clamp; a first diode, located between the first rail and the first virtual power rail, configured to ensure that current flows in a single direction from the first rail toward the first virtual power rail and ultimately to the protected integrated circuit; a second virtual power rail connected to a second node; The electrostatic discharge clamp is connected between the first virtual power rail and a second rail; a trigger device connected to the ESD clamp and configured to activate the ESD clamp in an ESD event based on a voltage level of the second virtual power rail and the voltage level of a trigger signal, wherein an input of the trigger device includes a trigger signal and the second virtual power rail, and the trigger signal is connected to a first node; and A charge dissipation element is connected between the second rail and at least one of the second virtual power rail or the trigger signal, for dissipating residual charge from the at least one of the second virtual power rail or the trigger signal.

13. The circuit according to claim 12, characterized in that Further included is a second diode located between the first rail and the second virtual power rail.

14. The circuit according to claim 13, characterized in that Further comprising a resistor-capacitor filter, wherein a resistor of the resistor-capacitor filter is connected to the second diode, wherein the second virtual power rail is connected to the second node between the second diode and the resistor, and wherein the trigger signal is connected to the first node between the resistor and a capacitor of the resistor-capacitor filter, the capacitor being connected to the second rail.

15. The circuit according to claim 14, characterized in that The charge dissipation element is connected between the first node and the second rail.

16. The circuit according to claim 14, characterized in that The charge dissipation element is connected between the second node and the second rail.

17. The circuit according to claim 12, characterized in that The charge dissipation element is one of a reverse diode, a series diode, a p-type metal oxide semiconductor field effect transistor diode or an n-type metal oxide semiconductor field effect transistor diode.

18. The circuit according to claim 12, characterized in that The trigger device is a buffer inverter and the ESD clamp is an n-type metal oxide semiconductor field effect transistor diode.

19. A method of forming a circuit, characterized in that: Include: connecting an ESD clamp between a first rail and a second rail, connecting a first dummy power rail to the first rail and the ESD clamp, and providing a first diode between the first rail and the first dummy power rail, the first diode being configured to ensure that current flows in a single direction from the first rail toward the first dummy power rail and ultimately to the protected integrated circuit; connecting a trigger device to the electrostatic discharge clamp; Connecting a charge dissipation element between an input of the trigger device and the second rail, the input of the trigger device including a trigger signal connected to a first node and a second virtual power rail connected to a second node; dissipating a residual charge from the input of the trigger device to the second rail through the charge dissipation element; In response to an ESD event, changing an output of the trigger device based on the voltage level of the second virtual power rail and the voltage level of the trigger signal to activate the ESD clamp; and In response to the activation, the ESD current is transferred from the first track to the second track through the ESD clamp.

20. The method of claim 19, wherein: Further including: changing the output of the trigger device after the ESD event to deactivate the ESD clamp until the next ESD event; and The residual charge continues to be dissipated from the input of the trigger device to the second rail through the charge dissipation element.

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