Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the structure comprises: a substrate, a gate structure on the substrate surface, first sidewalls on both sides of the gate structure; source and drain openings in the substrate on both sides of the gate structure; a first stress layer on the sidewall surfaces of the source and drain openings; a second stress layer in the source and drain openings and covering the sidewall surfaces of the first stress layer, the second stress layer filling the source and drain openings. The semiconductor structure has good performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in the integrated circuit is continuously reduced, so that the operating speed of the entire integrated circuit can be effectively improved.

[0003] In a very large scale integrated circuit, stress is usually formed on a transistor to increase the carrier mobility of the transistor and thus increase the driving current of the transistor.

[0004] However, the performance of semiconductor devices formed by the prior art needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of semiconductor devices.

[0006] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate, a gate structure on the surface of the substrate, and first side walls on both sides of the gate structure; source and drain openings in the substrate on both sides of the gate structure; a first stress layer located on the side wall surfaces of the source and drain openings; a second stress layer located in the source and drain openings and covering the side wall surfaces of the first stress layer, wherein the second stress layer fills the source and drain openings.

[0007] Optionally, the material of the first stress layer includes: germanium silicon, and the germanium in the germanium silicon material of the first stress layer has a first concentration; the material of the second stress layer includes: germanium silicon, and the germanium in the germanium silicon material of the second stress layer has a second concentration, and the second concentration is greater than the first concentration; the first concentration is in the range of 0.1 to 0.5; the second concentration is in the range of 0.4 to 0.8.

[0008] Optionally, the first sidewall spacer has a second thickness; the second thickness ranges from 3 nanometers to 7 nanometers.

[0009] Optionally, it also includes: a doping layer located between the top surface of the substrate and the bottom of the second stress layer.

[0010] Optionally, when the distance between the first stress layers in the source and drain openings on both sides of the gate structure is less than a preset value, the doping layer is doped with second conductive type ions, and the second conductive type ions and the first conductive type ions have opposite conductive types.

[0011] Optionally, when the distance between the first stress layers in the source and drain openings on both sides of the gate structure is greater than a preset value, the doping layer is doped with first conductive type ions.

[0012] Optionally, the source drain opening includes: the source drain opening includes: a first region and a second region located on the first region, the source drain opening in the first region has a first distance in the extension direction of the fin, the source drain opening in the second region has a second distance in the extension direction of the fin, and the second distance is smaller than the first distance.

[0013] Optionally, it also includes: a second side wall located on the side wall surface of the first side wall.

[0014] Optionally, the base includes a substrate and a fin located on a surface of the substrate, the gate structure covers a portion of the top surface and sidewall surface of the fin; and the source and drain openings are located in the fin on both sides of the gate structure.

[0015] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, wherein the surface of the substrate has a gate structure, and both sides of the gate structure have initial first side walls; using the initial first side walls and the gate structure as a mask, etching the substrate on both sides of the gate structure to form source and drain openings in the substrate; forming an initial first stress layer on the side wall surfaces and bottom surfaces of the source and drain openings; thinning the initial first side walls to form a first side wall; using the first side walls as a mask, etching the initial first stress layer until the bottom surface of the source and drain openings is exposed, and forming a first stress layer on the side wall surfaces of the source and drain openings; forming a second stress layer covering the side wall surfaces of the first stress layer in the source and drain openings, and the second stress layer fills the source and drain openings.

[0016] Optionally, the initial first sidewall spacer has a first thickness, the first sidewall spacer has a second thickness, and the second thickness is less than the first thickness; the first thickness ranges from 7 nanometers to 12 nanometers; and the second thickness ranges from 3 nanometers to 7 nanometers.

[0017] Optionally, the initial first stress layer located on the side wall surface portion of the source and drain openings has a first size, the first stress layer located on the side wall surface portion of the source and drain openings has a second size, and the second size is smaller than the first size; the first size ranges from 6 nanometers to 10 nanometers; the second size ranges from 3 nanometers to 6 nanometers.

[0018] Optionally, the material of the first stress layer includes: germanium silicon, and the germanium in the germanium silicon material of the first stress layer has a first concentration; the material of the second stress layer includes: germanium silicon, and the germanium in the germanium silicon material of the second stress layer has a second concentration, and the second concentration is greater than the first concentration.

[0019] Optionally, the first concentration range is 0.1 to 0.5; the second concentration range is 0.4 to 0.8.

[0020] Optionally, it also includes: after forming the first stress layer and before forming the second stress layer, performing an ion implantation process on the substrate exposed at the bottom of the source and drain openings to form an initial doping layer on a portion of the substrate at the bottom of the source and drain openings; and annealing the initial doping layer to form a doping layer.

[0021] Optionally, when the distance between the first stress layers in the source and drain openings on both sides of the gate structure is less than a preset value, the doping layer is doped with second conductive type ions, and the second conductive type ions and the first conductive type ions have opposite conductive types.

[0022] Optionally, when the distance between the first stress layers in the source and drain openings on both sides of the gate structure is greater than a preset value, the doping layer is doped with first conductive type ions.

[0023] Optionally, the method further includes: after forming the first stress layer, forming a second sidewall spacer on the sidewall surface of the first sidewall spacer.

[0024] Optionally, the method for forming the source and drain openings includes: using the initial first side wall as a mask to form initial source and drain openings in the substrate on both sides of the gate structure; performing a first amorphization treatment on the substrate exposed at the bottom of the initial source and drain openings to form a first amorphized layer (not shown in the figure) on the substrate exposed at the bottom of the initial source and drain openings; removing the first amorphized layer to form the initial source and drain openings into the source and drain openings; removing the first amorphized layer to form the initial source and drain openings into the source and drain openings.

[0025] Optionally, it also includes: after forming the initial first stress layer and before etching the initial first stress layer, performing a second amorphization treatment on the initial first stress layer exposed at the bottom of the source and drain openings; after the second amorphization treatment, etching the initial first stress layer using the first side wall as a mask; the second amorphization layer treatment includes: an ion implantation process; the parameters of the ion implantation process include: an implantation angle of 5 degrees to 20 degrees, the implantation angle being the angle between the direction of ion implantation and a reference plane, the reference plane being a plane perpendicular to the substrate surface and parallel to the channel width direction.

[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0027] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the thickness of the first sidewall formed by thinning the initial first sidewall is relatively thin. Then, the initial first stress layer is etched using the first sidewall with a relatively thin thickness as a mask, and the portion of the initial first stress layer exposed relative to the first sidewall is etched away, so that the initial first stress layer located on the bottom surface of the source and drain opening is removed, and at the same time, the thickness of the initial first stress layer located on the sidewall surface of the source and drain opening is also thinned to form the first stress layer, and then the space for subsequently forming the second stress layer is correspondingly increased. Since the stress of the second stress layer is greater than that of the first stress layer, increasing the space of the second stress layer is conducive to increasing the stress on the channel, thereby improving the driving current of the formed semiconductor structure.

[0028] Furthermore, a channel is formed in the substrate between adjacent source and drain openings and at the bottom of the gate structure, and when the distance between the first stress layers in the source and drain openings on both sides of the gate structure is less than a preset value, that is, the channel length is small. By doping the doped layer with second conductive type ions, and the second conductive type ions and the first conductive type ions have opposite conductive types, the second conductive type ions can neutralize the first conductive type ions in the first stress layer and the second stress layer, thereby reducing the impact on the channel, which is beneficial to reducing the short channel effect, so that the performance of the formed semiconductor structure is better.

[0029] Furthermore, a channel is formed in the substrate between adjacent source and drain openings and at the bottom of the gate structure. When the distance between the first stress layers in the source and drain openings on both sides of the gate structure is greater than a preset value, the doping layer is doped with first conductive type ions, and the conductive types of the doping layer, the first stress layer, and the second stress layer are the same, which is beneficial to increase the concentration of the first conductive type ions in the first stress layer and the second stress layer, thereby improving the driving current of the semiconductor structure, so that the performance of the formed semiconductor structure is better.

[0030] Furthermore, after the initial first stress layer is formed, the initial first stress layer exposed at the bottom of the source and drain openings is subjected to a second amorphization treatment, so that the material properties of the initial first stress layer located at the bottom surface of the source and drain openings are changed, which is beneficial to the subsequent use of the first sidewall as a mask to etch the initial first stress layer. In the process, the etching rate of the initial first stress layer after the second amorphization treatment is increased. On the one hand, it is more conducive to etching and removing the initial first stress layer located at the bottom surface of the source and drain openings; on the other hand, the second crystallization treatment is an ion implantation with a certain inclination angle. The second amorphization treatment can also change the material properties of the initial first stress layer located at the groove at the bottom of the source and drain openings, that is, the initial first stress layer located at the groove of the source and drain openings is also easily removed, thereby increasing the space for the subsequent formation of the second stress layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figures 1 to 3 It is a structural schematic diagram of each step of a method for forming a semiconductor structure;

[0032] Figures 4 to 13 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0033] As described in the background art, the performance of semiconductor devices formed by the prior art needs to be improved.

[0034] Figures 1 to 3 The present invention is a structural schematic diagram of each step of a method for forming a semiconductor structure.

[0035] Please refer to Figure 1 , providing a substrate 100; forming a gate structure 110 on the surface of the substrate 100; etching a portion of the substrate 100 on both sides of the gate structure 110 to form an opening 120 in the substrate 10, and the surface of the substrate 100 exposes the opening 120.

[0036] Please refer to Figure 2 A first stress layer 130 is formed on the sidewall surface and the bottom surface of the opening 120 .

[0037] Please refer to Figure 3 After forming the first stress layer 130 , a second stress layer 140 is formed in the opening 120 , and the first stress layer 130 and the second stress layer 140 constitute a source-drain doping layer, thereby forming a transistor device.

[0038] In the above method, the semiconductor structure is a PMOS transistor, and the first stress layer 130 and the second stress layer 140 are formed by an epitaxial growth process. The material of the first stress layer 130 includes: germanium silicon, and the germanium in the germanium silicon material has a first concentration; the material of the second stress layer 140 includes: germanium silicon, and the germanium in the germanium silicon material has a second concentration, and the first concentration is less than the second concentration. The first stress layer 130 with a smaller concentration is conducive to making the interface defects between the first stress layer 130 and the substrate 100 smaller, so as to serve as a buffer layer between the substrate 100 and the second stress layer 140, which is conducive to improving the interface reliability. The second stress layer 140 with a larger concentration has a larger stress, which is conducive to improving the driving current of the device.

[0039] However, since the first stress layer 130 occupies a certain space of the source-drain opening 120, the space used to form the second stress layer 140 is smaller, so that the stress generated by the source-drain doping layer composed of the first stress layer 130 and the second stress layer 140 on the channel is still small, resulting in a smaller driving current of the transistor device, thereby deteriorating the performance of the semiconductor structure.

[0040] To solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate surface having a gate structure, and the gate structure having initial first sidewalls on both sides; using the initial first sidewall as a mask, etching the substrate on both sides of the gate structure to form source and drain openings in the substrate; forming an initial first stress layer on the sidewall surface and bottom surface of the source and drain openings; after forming the initial first stress layer, thinning the initial first sidewall to form a first sidewall; using the first sidewall as a mask, etching the initial first stress layer until the bottom surface of the source and drain openings is exposed, forming a first stress layer on the sidewall surface of the source and drain openings; forming a second stress layer covering the sidewall surface of the first stress layer in the source and drain openings, and the second stress layer fills the source and drain openings. The semiconductor structure formed by the method has good performance.

[0041] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0042] Figures 4 to 13 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0043] Please refer to Figure 4 , providing a substrate 200 , wherein a gate structure 210 is provided on a surface of the substrate 200 , and initial first spacers 220 are provided on both sides of the gate structure 210 .

[0044] In this embodiment, the base 200 includes a substrate 201 and a fin 202 located on a surface of the substrate 201 , and the gate structure 210 covers a portion of a top surface and a sidewall surface of the fin 202 .

[0045] In other embodiments, the substrate has no fins thereon.

[0046] In this embodiment, the method for forming the base 200 includes: providing an initial substrate (not shown); the initial substrate has a first patterned layer, and the first patterned layer exposes a portion of the surface of the initial substrate; using the first patterned layer as a mask, etching the initial substrate to form the substrate 201 and the fin 202 located on the surface of the substrate 201.

[0047] In this embodiment, the material of the initial substrate is silicon. Accordingly, the material of the substrate 201 and the fin 202 is silicon.

[0048] In other embodiments, the material of the initial substrate includes: germanium, silicon germanium, silicon on insulator or germanium on insulator. Correspondingly, the material of the substrate includes: germanium, silicon germanium, silicon on insulator or germanium on insulator. The material of the fin includes: germanium, silicon germanium, silicon on insulator or germanium on insulator.

[0049] In this embodiment, the gate structure 210 includes a gate dielectric layer 211 and a gate electrode layer 212 located on the surface of the gate dielectric layer 211 .

[0050] In this embodiment, the process of forming the gate dielectric layer 211 includes: a deposition process; the material of the gate dielectric layer 211 is silicon oxide.

[0051] In another embodiment, the material of the gate dielectric layer includes a material with a K value greater than 3.9, such as titanium oxide, aluminum oxide, hafnium oxide, tantalum oxide or lanthanum oxide.

[0052] In this embodiment, the material of the gate electrode layer 212 includes polysilicon.

[0053] In another embodiment, the material of the gate electrode layer includes a metal material, such as a combination of one or more of tungsten, cobalt, copper, nickel, titanium and titanium nitride.

[0054] In this embodiment, the gate structure 210 further includes: a barrier layer 213 located on the top surface of the gate electrode layer 212. The barrier layer 213 is used to protect the gate structure 210 from being affected by the subsequent processes, so as to maintain a good morphology.

[0055] The initial first sidewall 220 is used in subsequent process steps to, on the one hand, protect the gate structure 210 from being affected by the process so as to maintain a good morphology; on the other hand, serve as a mask for subsequent formation of source and drain openings so as to define the position and size of the source and drain openings.

[0056] The material of the initial first spacer 220 includes: one or a combination of silicon oxide, silicon nitride, silicon oxynitride, titanium dioxide or titanium nitride.

[0057] The initial first sidewall spacer 220 has a first thickness W1.

[0058] The first thickness W1 ranges from 7 nanometers to 12 nanometers.

[0059] Next, the initial first sidewall 220 and the gate structure 210 are used as masks to etch the substrate 200 on both sides of the initial first sidewall 220 and the gate structure 210 to form source and drain openings in the substrate 200. For the specific process of forming the source and drain openings, please refer to Figure 5 to Figure 6 .

[0060] Please refer to Figure 5 Initial source and drain openings 230 are formed in the substrate 200 on both sides of the initial first spacer 220 and the gate structure 210 .

[0061] Specifically, the initial first spacer 220 and the gate structure 210 are used as masks to etch the fins 202 on both sides of the initial first spacer 220 and the gate structure 210 until the surface of the substrate 201 is exposed, and initial source and drain openings 230 are formed in the fins 202 .

[0062] The process of etching the fin 202 using the initial first spacer 220 and the gate structure 210 as masks includes: an anisotropic dry etching process.

[0063] Please refer to Figure 6 , perform a first amorphization treatment on the substrate 200 exposed at the bottom of the initial source and drain opening 230, so that the substrate 200 exposed at the bottom of the initial source and drain opening 230 forms a first amorphization layer (not shown in the figure); remove the first amorphization layer, so that the initial source and drain opening 230 forms the source and drain opening 240.

[0064] It should be noted that by removing the first amorphous layer, the initial source opening 230 forms a source-drain opening 240, and the source-drain opening 240 includes: a first region I and a second region II located on the first region I, the first region I is the region of the source-drain opening 240 corresponding to the initial source-drain opening 230 after the first amorphous layer is removed, and the second region II is the region on the first region I of the source-drain opening 240.

[0065] In this embodiment, the source / drain openings 240 in the first region I have a first distance in the fin extension direction, and the source / drain openings 240 in the second region II have a second distance in the fin extension direction, and the second distance is smaller than the first distance.

[0066] Due to the different properties of the materials of the first amorphized layer and the fin 202, the etching process used for the subsequent removal of the first amorphized layer can have different etching rates for the first amorphized layer and the fin 202, so that the first amorphized layer is removed to increase the size of the initial source and drain opening 230 at the bottom along the extension direction of the fin 202, that is, the size of the first region I of the source and drain opening 240 along the extension direction of the fin 202 is increased, and the initial source and drain opening 230 of the second region II will not be etched. Then, a source and drain doping layer is subsequently formed in the source and drain opening 240, and the size of the source and drain doping layer of the second region II along the extension direction of the fin 202 remains unchanged, ensuring that the effective length of the channel located below the gate structure 210 is longer, thereby reducing the short channel effect. At the same time, the size of the first region I of the source and drain opening 240 is increased, so that the space of the source and drain opening 240 is increased, which is conducive to increasing the stress of the source and drain doping layer, thereby improving the driving current of the formed device. In summary, the performance of the semiconductor structure is relatively high.

[0067] In other embodiments, the first amorphization treatment may not be performed, and the substrate on both sides of the initial first spacer and gate structure may be etched using the initial first spacer and gate structure as a mask to form the source and drain openings in the substrate.

[0068] It should be noted that, in the present embodiment, the source-drain opening 240 is formed with a groove (not shown in the figure) at the bottom, and an angle a is formed between the sidewall of the groove and the bottom of the source-drain opening 240 .

[0069] Please refer to Figure 7 An initial first stress layer 250 is formed on the sidewall surface and the bottom surface of the source / drain opening 240 .

[0070] The initial first stress layer 250 provides material for subsequently forming a first stress layer.

[0071] The initial first stress layer 250 located on the sidewall surface of the source / drain opening 240 has a first size H1.

[0072] The first size H1 ranges from 6 nanometers to 10 nanometers.

[0073] The material of the initial first stress layer 240 includes silicon germanium, silicon phosphide or silicon carbide.

[0074] In this embodiment, the material of the initial first stress layer 250 is germanium silicon, and the germanium in the germanium silicon material of the initial first stress layer 250 has a first concentration.

[0075] The first concentration ranges from 0.1 to 0.5.

[0076] It should be noted that the germanium in the germanium silicon material has a first concentration, which refers to the ratio of the amount of germanium to the amount of silicon.

[0077] Please refer to Figure 8 , a second amorphization treatment is performed on the initial first stress layer 250 exposed at the bottom of the source / drain opening 240 .

[0078] The second amorphous layer processing includes: an ion implantation process; the parameters of the ion implantation process include: an implantation angle of 5 degrees to 20 degrees, the implantation angle is the angle between the ion implantation direction and a reference plane, and the reference plane is a plane perpendicular to the surface of the substrate 200 and parallel to the channel width direction.

[0079] After the initial first stress layer 250 is formed, the initial first stress layer 250 exposed at the bottom of the source and drain openings 240 is subjected to a second amorphization treatment, so that the material properties of the initial first stress layer 250 located at the bottom surface of the source and drain openings 240 are changed, which is beneficial to increase the etching rate of the initial first stress layer 250 after the second amorphization treatment in the subsequent process of etching the initial first stress layer 250 using the first sidewall as a mask. On the one hand, it is more conducive to etching and removing the initial first stress layer 250 located at the bottom surface of the source and drain openings 240; on the other hand, the second crystallization treatment is an ion implantation with a certain tilt angle, and the second amorphization treatment can also change the material properties of the initial first stress layer 250 located in the groove at the bottom of the source and drain openings 240, that is, the initial first stress layer 250 located in the groove of the source and drain openings 240 is also easily removed, thereby increasing the space for the subsequent formation of the second stress layer.

[0080] In other embodiments, the initial first stress layer exposed at the bottom of the source / drain opening may not be subjected to the second amorphization treatment.

[0081] Please refer to Fig. 9 , thinning the initial first sidewall 220 to form a first sidewall 221.

[0082] Specifically, in this embodiment, after the initial first stress layer 250 is subjected to the second amorphization treatment, the initial first sidewall spacer 220 is thinned to form the first sidewall spacer 221 .

[0083] The initial first sidewall 220 has a first thickness W1 , the first sidewall 221 has a second thickness W2 , and the second thickness W2 is smaller than the first thickness W1 .

[0084] The first thickness W1 ranges from 7 nanometers to 12 nanometers; the second thickness W2 ranges from 3 nanometers to 7 nanometers.

[0085] In this embodiment, after the initial first stress layer 250 is formed, the initial first sidewall spacer 220 is thinned to form a first sidewall spacer 221 , and then the initial first stress layer 250 is etched using the first sidewall spacer 221 as a mask.

[0086] In other embodiments, the initial first side wall may be thinned, and after forming the first side wall, an initial first stress layer is formed on the side wall surface and bottom surface of the source / drain opening, and then the initial first stress layer is etched using the first side wall as a mask.

[0087] Please refer to Fig.10 , using the first sidewall 221 as a mask, etching the initial first stress layer 250 until the bottom surface of the source-drain opening 240 is exposed, and forming a first stress layer 260 on the sidewall surface of the source-drain opening 240 .

[0088] The first stress layer 260 located on the sidewall surface of the source / drain opening 240 has a second size H2 , and the second size H2 is smaller than the first size H1 .

[0089] In this embodiment, the second size H2 is in the range of 3 nanometers to 6 nanometers.

[0090] Since the first stress layer 260 is formed by etching the initial first stress layer 250, the material of the initial first stress layer 250 is germanium silicon, and the germanium in the germanium silicon material of the initial first stress layer 250 has a first concentration, correspondingly, the material of the first stress layer 260 is germanium silicon, and the germanium in the germanium silicon material of the first stress layer 260 has a first concentration.

[0091] By thinning the initial first sidewall 220, the thickness of the first sidewall 221 formed is relatively thin. Then, the initial first stress layer 250 is etched using the first sidewall 221 with a relatively thin thickness as a mask, and the portion of the initial first stress layer 250 exposed relative to the first sidewall is etched away, so that the initial first stress layer 250 located on the bottom surface of the source-drain opening 240 is removed, and at the same time, the thickness of the initial first stress layer 250 located on the sidewall surface of the source-drain opening 210 is also thinned to form the first stress layer 260, and the space for the subsequent formation of the second stress layer is correspondingly increased. Since the stress of the second stress layer is greater than that of the first stress layer, increasing the space of the second stress layer is conducive to increasing the stress on the channel, thereby improving the driving current of the formed semiconductor structure.

[0092] Please refer to Fig.11, an ion implantation process is performed on the substrate 200 exposed at the bottom of the source / drain opening 240 to form an initial doping layer (not shown in the figure) on a portion of the substrate 200 at the bottom of the source / drain opening 240; and the initial doping layer is annealed to form a doping layer 270.

[0093] The distance between the first stress layers 260 in the source-drain openings 240 on both sides of the gate structure 210 is smaller than a preset value, and the doping layer 270 is doped with second conductive type ions, and the second conductive type ions and the first conductive type ions have opposite conductive types.

[0094] Since a channel is formed in the substrate 200 between adjacent source and drain openings 240 and at the bottom of the gate structure 210, when the distance between the first stress layers 260 in the source and drain openings 240 on both sides of the gate structure 210 is less than a preset value, that is, the channel length is small. By doping the doping layer 270 with second conductive type ions, and the second conductive type ions and the first conductive type ions have opposite conductive types, the second conductive type ions can neutralize the first conductive type ions in the first stress layer 260 and the second stress layer 280, thereby reducing the impact on the channel, which is beneficial to reducing the short channel effect, so that the performance of the formed semiconductor structure is better.

[0095] In another embodiment, when the distance between the first stress layers in the source-drain openings on both sides of the gate structure is greater than a preset value, the doping layer is doped with first conductive type ions.

[0096] Since a channel is formed between adjacent source and drain openings and in the substrate at the bottom of the gate structure, when the distance between the first stress layers in the source and drain openings on both sides of the gate structure is greater than a preset value, the doping layer is doped with first conductive type ions, and the conductive types of the doping layer, the first stress layer, and the second stress layer are the same, which is beneficial to increase the concentration of the first conductive type ions in the first stress layer and the second stress layer 280, thereby improving the driving current of the semiconductor structure, so that the performance of the formed semiconductor structure is better.

[0097] In other embodiments, the doping layer may not be formed.

[0098] Please refer to Fig.12 A second stress layer 280 is formed in the source / drain opening 240 to cover the sidewall surface of the first stress layer 260 , and the second stress layer 280 completely fills the source / drain opening 240 .

[0099] In this embodiment, the second stress layer 280 also covers the surface of the doping layer 270 .

[0100] The material of the second stress layer 280 includes germanium silicon. The germanium in the germanium silicon material of the second stress layer 270 has a second concentration, and the second concentration is greater than the first concentration.

[0101] The second concentration range is 0.4-0.8.

[0102] The germanium in the germanium silicon material of the first stress layer 260 has a first concentration; the germanium in the germanium silicon material of the second stress layer 280 has a second concentration, and the first concentration is less than the second concentration. On the one hand, the first stress layer 260 with a smaller concentration is conducive to making the interface defects between the first stress layer 260 and the substrate 200 smaller, so as to serve as a buffer layer between the substrate 200 and the second stress layer 280, which is conducive to improving the interface reliability. The second stress layer 280 with a larger concentration has a larger stress, which is conducive to improving the driving current of the device, and increasing the space of the second stress layer 280 is conducive to improving the driving current of the device.

[0103] Please refer to Fig.13 After forming the second stress layer 280 , a second sidewall 222 is formed on the sidewall surface of the first sidewall 221 .

[0104] The first side wall 221 and the second side wall 222 together serve as the side wall structure of the gate structure 210 (not shown in the figure). The side wall structure has the following functions: on the one hand, to protect the side wall surface of the gate structure 210 and reduce the impact of subsequent processes; on the other hand, to prevent the distance between the subsequently formed conductive plug and the gate structure 210 from being too close, which would lead to the generation of leakage current.

[0105] In this embodiment, the method for forming the semiconductor structure further includes: after forming the second sidewall 222 , forming a dielectric layer (not shown) on the substrate 200 ; and forming a conductive plug electrically connected to the second stress layer 280 in the dielectric layer.

[0106] Accordingly, the embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Fig.13 , including: a substrate 200, wherein the surface of the substrate 200 has a gate structure 210, and the gate structure 210 has first sidewalls 221 on both sides; source and drain openings 240 in the substrate 200 located on both sides of the gate structure 210; a first stress layer 260 located on the side wall surfaces of the source and drain openings 240; a second stress layer 280 located in the source and drain openings 240 and covering the side wall surfaces of the first stress layer 260, and the second stress layer 280 fills the source and drain openings 240.

[0107] The following is a detailed description with reference to the accompanying drawings.

[0108] The base 200 includes a substrate 201 and a fin 202 located on the surface of the substrate 201 . The gate structure 210 covers a portion of the top surface and sidewall surface of the fin 202 . The source and drain openings 240 are located in the fin 202 on both sides of the gate structure 210 .

[0109] The material of the first stress layer 260 includes: germanium silicon, and the germanium in the germanium silicon material of the first stress layer 260 has a first concentration; the material of the second stress layer 280 includes: germanium silicon, and the germanium in the germanium silicon material of the second stress layer 280 has a second concentration, and the second concentration is greater than the first concentration; the first concentration ranges from 0.1 to 0.5; the second concentration ranges from 0.4 to 0.8.

[0110] The first sidewall spacer 222 has a second thickness; the second thickness ranges from 3 nanometers to 7 nanometers.

[0111] In this embodiment, the semiconductor structure further includes: a doping layer 270 located between the top surface of the substrate 200 and the bottom of the second stress layer 280 .

[0112] In this embodiment, the distance between the first stress layers 260 in the source-drain openings 240 on both sides of the gate structure 210 is less than a preset value, and the doping layer 270 is doped with second conductive type ions, and the second conductive type ions and the first conductive type ions have opposite conductive types.

[0113] In other embodiments, when the distance between the first stress layers 260 in the source-drain openings 240 at both sides of the gate structure 210 is greater than a preset value, the doping layer 270 is doped with first conductive type ions.

[0114] The source-drain opening 240 includes: a first region I and a second region II located on the first region I, the source-drain opening 240 of the first region I has a first distance in the extension direction of the fin 202, the source-drain opening 240 of the second region II has a second distance in the extension direction of the fin 202, and the second distance is smaller than the first distance.

[0115] In this embodiment, the semiconductor structure further includes: a second sidewall spacer 222 located on the sidewall surface of the first sidewall spacer 221 .

[0116] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, It is characterized in that include: A substrate, wherein a gate structure is provided on a surface of the substrate, and first sidewalls are provided on both sides of the gate structure; source and drain openings in the substrate on both sides of the gate structure; A first stress layer located on the sidewall surface of the source / drain opening; A second stress layer located in the source / drain opening and covering the sidewall surface of the first stress layer, wherein the second stress layer completely fills the source / drain opening; The first stress layer is formed by thinning the thickness of the initial first stress layer located on the sidewall surface of the source and drain openings, the initial first stress layer located on the sidewall surface of the source and drain openings has a first size, and the first stress layer located on the sidewall surface of the source and drain openings has a second size, and the second size is smaller than the first size; The source-drain opening comprises: a first region perpendicular to the extension direction of the fin and a second region located on the first region, the source-drain opening of the first region has a first distance in the extension direction of the fin, the source-drain opening of the second region has a second distance in the extension direction of the fin, and the second distance is smaller than the first distance; the source-drain opening has a groove at the bottom, and the angle between the side wall of the groove and the source-drain opening is an acute angle.

2. The semiconductor structure according to claim 1, It is characterized in that The material of the first stress layer includes: germanium silicon, and the germanium in the germanium silicon material of the first stress layer has a first concentration; the material of the second stress layer includes: germanium silicon, and the germanium in the germanium silicon material of the second stress layer has a second concentration, and the second concentration is greater than the first concentration; the first concentration ranges from 0.1 to 0.5; the second concentration ranges from 0.4 to 0.

8.

3. The semiconductor structure according to claim 1, It is characterized in that The first sidewall spacer has a second thickness; the second thickness ranges from 3 nanometers to 7 nanometers.

4. The semiconductor structure according to claim 1, It is characterized in that Also includes: A doped layer is located between the top surface of the substrate and the bottom of the second stressor layer.

5. The semiconductor structure according to claim 4, It is characterized in that When the distance between the first stress layers in the source and drain openings on both sides of the gate structure is less than a preset value, the doping layer is doped with second conductive type ions, and the second conductive type ions and the first conductive type ions have opposite conductive types.

6. The semiconductor structure according to claim 4, It is characterized in that When the distance between the first stress layers in the source-drain openings at both sides of the gate structure is greater than a preset value, the doping layer is doped with first conductive type ions.

7. The semiconductor structure according to claim 1, It is characterized in that Also includes: A second side wall is located on the side wall surface of the first side wall.

8. The semiconductor structure according to claim 1, It is characterized in that The base comprises a substrate and a fin located on a surface of the substrate, and the gate structure covers a portion of the top surface and sidewall surface of the fin; The source and drain openings are located in the fins on both sides of the gate structure.

9. A method for forming a semiconductor structure, It is characterized in that include: Providing a substrate, wherein a gate structure is provided on a surface of the substrate, and initial first spacers are provided on both sides of the gate structure; Using the initial first spacer and the gate structure as masks, etching the substrate on both sides of the gate structure to form source and drain openings in the substrate; Forming an initial first stress layer on the sidewall surface and bottom surface of the source / drain opening; Thinning the initial first sidewall to form a first sidewall; Using the first sidewall as a mask, etching the initial first stress layer until the bottom surface of the source and drain openings is exposed, and forming a first stress layer on the sidewall surface of the source and drain openings; forming a second stress layer in the source / drain opening covering the sidewall surface of the first stress layer, wherein the second stress layer completely fills the source / drain opening; The initial first stress layer located on the sidewall surface of the source / drain opening has a first size, and the first stress layer located on the sidewall surface of the source / drain opening has a second size, and the second size is smaller than the first size; The source-drain opening comprises: a first region perpendicular to the extension direction of the fin and a second region located on the first region, the source-drain opening of the first region has a first distance in the extension direction of the fin, the source-drain opening of the second region has a second distance in the extension direction of the fin, and the second distance is smaller than the first distance; the source-drain opening has a groove at the bottom, and the angle between the side wall of the groove and the source-drain opening is an acute angle.

10. The method for forming a semiconductor structure according to claim 9, It is characterized in that The initial first sidewall spacer has a first thickness, the first sidewall spacer has a second thickness, and the second thickness is smaller than the first thickness; the first thickness ranges from 7 nanometers to 12 nanometers; and the second thickness ranges from 3 nanometers to 7 nanometers.

11. The method for forming a semiconductor structure according to claim 9, It is characterized in that The first size ranges from 6 nanometers to 10 nanometers; the second size ranges from 3 nanometers to 6 nanometers.

12. The method for forming a semiconductor structure according to claim 9, It is characterized in that The material of the first stress layer includes germanium silicon, in which germanium has a first concentration; the material of the second stress layer includes germanium silicon, in which germanium has a second concentration greater than the first concentration.

13. The method for forming a semiconductor structure according to claim 12, It is characterized in that The first concentration range is 0.1-0.5; the second concentration range is 0.4-0.

8.

14. The method for forming a semiconductor structure according to claim 9, It is characterized in that Also includes: After forming the first stress layer and before forming the second stress layer, performing an ion implantation process on the substrate exposed at the bottom of the source / drain openings, so that a portion of the substrate at the bottom of the source / drain openings forms an initial doping layer; The initial doping layer is annealed to form a doping layer.

15. The method for forming a semiconductor structure according to claim 14, It is characterized in that When the distance between the first stress layers in the source and drain openings on both sides of the gate structure is less than a preset value, the doping layer is doped with second conductive type ions, and the second conductive type ions and the first conductive type ions have opposite conductive types.

16. The method for forming a semiconductor structure according to claim 14, It is characterized in that When the distance between the first stress layers in the source-drain openings at both sides of the gate structure is greater than a preset value, the doping layer is doped with first conductive type ions.

17. The method for forming a semiconductor structure according to claim 9, It is characterized in that Also includes: After forming the first stress layer, a second sidewall spacer is formed on the sidewall surface of the first sidewall spacer.

18. The method for forming a semiconductor structure according to claim 9, It is characterized in that The method for forming the source-drain openings includes: using the initial first side wall as a mask to form initial source-drain openings in the substrate on both sides of the gate structure; performing a first amorphization treatment on the substrate exposed at the bottom of the initial source-drain openings to form a first amorphized layer on the substrate exposed at the bottom of the initial source-drain openings; removing the first amorphized layer to form the initial source-drain openings into the source-drain openings; removing the first amorphized layer to form the initial source-drain openings into the source-drain openings.

19. The method for forming a semiconductor structure according to claim 9, It is characterized in that Also includes: After forming the initial first stress layer and before etching the initial first stress layer, performing a second amorphization treatment on the initial first stress layer exposed at the bottom of the source / drain opening; After the second amorphization treatment, the initial first stress layer is etched using the first sidewall as a mask; The second amorphization treatment includes: an ion implantation process; the parameters of the ion implantation process include: an implantation angle of 5 degrees to 20 degrees, the implantation angle being the angle between the ion implantation direction and a reference plane, the reference plane being a plane perpendicular to the substrate surface and parallel to the channel width direction.

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